WO2021196039A1 - 安全芯片、安全芯片的制造方法和电子设备 - Google Patents

安全芯片、安全芯片的制造方法和电子设备 Download PDF

Info

Publication number
WO2021196039A1
WO2021196039A1 PCT/CN2020/082609 CN2020082609W WO2021196039A1 WO 2021196039 A1 WO2021196039 A1 WO 2021196039A1 CN 2020082609 W CN2020082609 W CN 2020082609W WO 2021196039 A1 WO2021196039 A1 WO 2021196039A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
layer
wafer
optically
medium layer
Prior art date
Application number
PCT/CN2020/082609
Other languages
English (en)
French (fr)
Inventor
陆斌
沈健
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2020/082609 priority Critical patent/WO2021196039A1/zh
Publication of WO2021196039A1 publication Critical patent/WO2021196039A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

Definitions

  • This application relates to the field of chips, and more specifically, to a security chip, a method for manufacturing a security chip, and an electronic device.
  • the security chip is a device that can independently generate, encrypt and decrypt keys. It has independent logic modules and storage modules inside, which can store keys and characteristic data, and provide encryption and security authentication services for computers or mobile terminals.
  • the security chip is used for encryption, and the key and encrypted data are stored. The stolen data cannot be decrypted, thereby protecting business privacy and data security.
  • the manufacturing cost of the security chip is relatively high, and there are many methods to attack the security chip.
  • one of the most important attack methods to crack the security chip is laser fault injection.
  • the attacker uses an infrared band laser to illuminate a specific area of the chip's logic module through the back of the chip.
  • the photocurrent generated by the interaction between the laser and the silicon is used to make the chip output wrong results.
  • the attacker can obtain the key and crack the encrypted information stored in the chip by collecting the error with a certain characteristic that occurred at a specific time and at a specific location, and comparing and analyzing with the correct encryption result.
  • the embodiments of the present application provide a security chip, a method for manufacturing a security chip, and an electronic device, which can improve the security level of the security chip, reduce the cost, and improve the comprehensive performance of the security chip.
  • a security chip including: a first chip, a second chip, and a first light blocking layer; the first chip and the second chip are stacked on top of each other and electrically connected to each other; the first light blocking layer The circuit area close to the first chip is used for total reflection and/or scattering of the first light signal irradiated from the outside and directed toward the circuit area in the first chip.
  • the first chip and the second chip are manufactured independently, without the need to integrate the functional circuits of the first chip and the second chip into the same chip, so that the first chip and the second chip are manufactured
  • Process decoupling reduces the manufacturing cost of the first chip and the second chip, and the first chip and the second chip are stacked to form a security chip, thereby reducing the surface area of the security chip.
  • the newly added light barrier layer in the security chip performs total reflection and/or scattering of the optical signal, which reduces the manufacturing cost while preventing laser injection attacks and improving the security performance of the chip.
  • the light barrier layer is close to the chip In the circuit area, it is not easy for an attacker to remove the light blocking layer without damaging the circuit area, so that the light blocking layer can well block the light signal from entering the circuit area of the chip.
  • the thickness of the first chip is less than 30 ⁇ m; and/or the thickness of the second chip is less than 30 ⁇ m.
  • the surface area of the first chip is not equal to the surface area of the second chip;
  • the security chip further includes: a carrier, the carrier includes a receiving structure, the receiving structure is a through hole or Groove; the first chip and the chip with the smaller surface area of the second chip are arranged in the accommodating structure, and the carrier and the chip with the larger surface area of the first chip and the second chip are stacked up and down in alignment.
  • the small area chip is not directly on the wafer, and is bonded to the wafer where the large area chip is located by wafer-level bonding, but a single chip is placed in the housing structure of the carrier. Before stacking the two chips, test the two chips to screen out the chips with good performance, remove the chips with poor performance, improve the yield of the overall security chip, and further reduce the overall manufacturing cost.
  • the security chip further includes: a first interconnection layer and a second interconnection layer, the first interconnection layer and the second interconnection layer are disposed between the first chip and the second chip; The first chip and the second chip are electrically connected through the first interconnection layer and the second interconnection layer.
  • the surface area of the first interconnection layer is equal to the surface area of the second interconnection layer, and the first chip and the second chip pass through the first interconnection layer and the second interconnection layer.
  • the interconnection layer performs wafer-level bonding to form electrical connections.
  • At least one first bonding pad is formed on the lower surface of the first interconnection layer, and at least one second bonding pad is formed on the upper surface of the second interconnection layer; the at least one The first bonding pad and the at least one second bonding pad are in one-to-one correspondence, and one of the at least one first bonding pad is bonded to its corresponding second bonding pad An electrical connection is formed on the pad.
  • the electrical connection device between the stacked first chip and the second chip that is, the bonding pad in the interconnection layer, is hidden inside the security chip, and cannot be read from the outside through the electrical connection device.
  • the data in the first chip and the second chip and related information of the chip are obtained, thereby improving the security performance and reliability of the security chip.
  • the surface area of the first interconnection layer and the surface area of the second interconnection layer are both equal to the surface area of the chip with the larger surface area of the first chip and the second chip.
  • the first light blocking layer includes: a first light thinner medium layer and a first light dense medium layer; the first light dense medium layer is connected to the first light thinner medium layer; wherein, The first optically dense medium layer is used to receive the first optical signal and transmit the first optical signal to the first interface between the first optically dense medium layer and the first optically thinner medium layer; the first The interface is a rough surface with a roughness greater than a preset threshold, and is used to totally reflect and/or scatter the first light signal irradiated from the outside and toward the circuit area in the first chip to prevent the first light signal from entering the first chip.
  • the circuit area in a chip is used to totally reflect and/or scatter the first light signal irradiated from the outside and toward the circuit area in the first chip to prevent the first light signal from entering the first chip.
  • the light incident from the first optically denser medium layer can be totally reflected and/or scattered, thereby reducing the optical signal reaching the first chip In order to achieve the purpose of resisting laser attack.
  • the roughness of the first interface is greater than 20 nm.
  • a spike-like structure or a hole-like structure is formed on the first interface, and the spike-like structure is formed by a pyramid-shaped protrusion or an inverted pyramid-shaped pit.
  • the first optically thin dielectric layer is connected to the surface of the substrate of the first chip.
  • the shape of the first interface is substantially the same as the shape of the substrate surface of the first chip.
  • the roughness of the first interface is greater than the roughness of the substrate surface of the first chip.
  • the security chip further includes: a first intermediate layer; the first intermediate layer is connected to the surface of the substrate of the first chip, and the first optically thin dielectric layer is connected to the first intermediate layer
  • the morphology of the connection surface between the first optically thin medium layer and the first intermediate layer is basically the same as the morphology of the first interface.
  • the first optically thinner medium layer and the first optically denser medium layer are located in the substrate of the first chip, and the first optically thinner medium layer is close to the one in the first chip. Circuit area.
  • the material of the first optically dense medium layer is silicon, and the material of the first optically thinner medium layer is silicon dioxide; or, the material of the first optically dense medium layer is metal, and
  • the material of the first optically thin dielectric layer is any one of silicon nitride, silicon oxynitride, and silicon carbonitride.
  • the security chip further includes: a second light blocking layer, the second light blocking layer is close to the circuit area in the second chip, and is used to remove the light from the outside and toward the second chip.
  • the second light signal irradiated by the circuit area of the second chip is totally reflected and/or scattered to prevent the second light signal from entering the circuit area of the second chip.
  • the second light blocking layer includes: a second light thinner medium layer and a second light dense medium layer; the second light dense medium layer is connected to the second light thinner medium layer; wherein, The second optically dense medium layer is used to receive the second optical signal and transmit the second optical signal to a second interface between the second optically dense medium layer and the second optically thinner medium layer; the second The interface is a rough surface with a roughness greater than a preset threshold, and is used to perform total reflection and/or scattering of the second light signal irradiated from the outside toward the circuit area in the second chip to prevent the second light signal from entering the The circuit area in the second chip.
  • the roughness of the second interface is greater than 20 nm.
  • a spike-like structure or a hole-like structure is formed on the second interface, and the spike-like structure is formed by a pyramid-shaped protrusion or an inverted pyramid-shaped pit.
  • the second optically thinner dielectric layer is connected to the surface of the substrate of the second chip.
  • the shape of the second interface is substantially the same as the shape of the substrate surface of the second chip.
  • the roughness of the second interface is greater than the roughness of the substrate surface of the second chip.
  • the security chip further includes: a second intermediate layer; the second intermediate layer is connected to the surface of the substrate of the second chip, and the second optically thin dielectric layer is connected to the second intermediate layer
  • the morphology of the connecting surface of the second optically thin medium layer and the second intermediate layer is basically the same as the morphology of the second interface.
  • the second optically thinner medium layer and the second optically denser medium layer are located in the substrate of the second chip, and the second optically thinner medium layer is close to the Circuit area.
  • the material of the second optically dense medium layer is silicon, and the material of the second optically thinner medium layer is silicon dioxide; or, the material of the second optically dense medium layer is metal, and
  • the material of the second optically thin dielectric layer is any one of silicon nitride, silicon oxynitride, and silicon carbonitride.
  • the security chip further includes: a pad; the pad is located on a side of the security chip, is close to the first chip, and is electrically connected to the first chip; or, the pad is located at The other side of the security chip is close to the second chip and is electrically connected to the second chip.
  • the first chip and the second chip are a logic chip and a memory chip, respectively.
  • a method for manufacturing a security chip including: preparing a first chip, where the first chip is located in a first wafer; preparing a second chip, where the second chip is located in a second wafer; The circle-level bonding process bonds the first wafer and the second wafer, so that the first chip and the corresponding second chip are stacked up and down, and are electrically connected to each other, wherein, close to the first chip
  • the circuit area of the first chip is provided with a first light blocking layer, and the first light blocking layer is used to totally reflect and/or scatter the first light signal irradiated from the outside and toward the circuit area in the first chip; A wafer and a second wafer are cut to obtain a first security chip.
  • the first security chip includes the first chip, the second chip, and the first light blocking layer.
  • the preparing the first chip includes: preparing and dividing the first chip in a third wafer; and preparing a housing structure in the first wafer, and the housing structure is connected Hole or groove; the first chip is fixedly placed in the accommodating structure.
  • the preparing the first chip includes: preparing the first chip in the first wafer.
  • the preparing the second chip includes: preparing and dividing the second chip in a fourth wafer; fabricating a housing structure on the second wafer, and the housing structure is connected Hole or groove; the second chip is fixedly placed in the accommodating structure.
  • the preparing the second chip includes: preparing the second chip in the second wafer.
  • the manufacturing method before the first wafer and the second wafer are bonded by a wafer-level bonding process, the manufacturing method further includes: preparing a first interconnection on the upper surface of the first chip. Layer, the first interconnection layer is electrically connected with the first chip; a second interconnection layer is prepared on the upper surface of the second chip, and the second interconnection layer is electrically connected with the second chip.
  • the first wafer and the second wafer are bonded by a wafer-level bonding process, so that the first chip and its corresponding second chip are stacked on top of each other and are mutually stacked.
  • the electrical connection includes: flipping the first wafer or the second wafer upside down; bonding the first interconnection layer and the second interconnection layer using a wafer-level bonding process, so that the first chip and its corresponding The second chip is stacked on top of each other and electrically connected to each other.
  • the bonding of the first interconnection layer and the second interconnection layer by using a wafer-level bonding process includes: bonding the upper surface of the first interconnection layer by a wafer-level bonding process At least one first bonding pad and at least one second bonding pad on the lower surface of the second interconnection layer to form an electrical connection between the first interconnection layer and the second interconnection layer; wherein the at least one first interconnection layer The bonding pads and the at least one second bonding pad are in one-to-one correspondence.
  • the manufacturing method further includes: preparing the first wafer on the substrate surface of the first wafer The first light blocking layer.
  • the preparing the first light blocking layer on the surface of the substrate of the first wafer includes: preparing a first light barrier layer on the surface of the substrate of the first wafer; A first optically dense medium layer is prepared on the surface of the first optically thinner medium layer, and the surface of the first optically thinner medium layer is a rough surface with a roughness greater than a preset threshold.
  • the preparing the first optical thinning medium layer on the substrate surface of the first wafer includes: performing a thinning process on the substrate surface of the first wafer to make the first
  • the substrate surface of the wafer is a rough surface with a roughness greater than a preset threshold; the first optical thinning medium layer is prepared on the substrate surface of the first wafer, and the surface form of the first optical thinning medium layer is the same as that of the first optical thinning medium layer.
  • the morphology of the substrate surface of a wafer is basically the same.
  • the preparing a first photophobic medium layer on the surface of the substrate of the first wafer includes: preparing the first photophobic medium layer on the surface of the substrate of the first wafer; The surface of the first optical thinning medium layer is roughened, so that the surface of the first optical thinning medium layer is a rough surface with a roughness greater than a preset threshold.
  • the preparing a first light blocking layer on the surface of the substrate of the first wafer includes: preparing a first intermediate layer on the surface of the substrate of the first wafer; The surface of the layer is roughened, so that the surface of the first intermediate layer is a rough surface with a roughness greater than a preset threshold; a first photophobic medium layer is prepared on the surface of the first intermediate layer, and the first photophobic medium layer
  • the morphology of the surface is basically consistent with the surface morphology of the first intermediate layer.
  • the manufacturing method before preparing the first optical thinner dielectric layer on the first wafer, the manufacturing method further includes: performing a thinning process on the substrate surface of the first wafer.
  • the performing a thinning process on the surface of the substrate of the first wafer includes: reducing the thickness of the first wafer to 30 ⁇ m or less.
  • the surface roughness of the first optically thin dielectric layer is greater than 20 nm.
  • a spike-like structure or a hole-like structure is formed on the surface of the first optical thinning medium layer, and the spike-like structure is formed by pyramid-shaped protrusions or inverted pyramid-shaped pits.
  • the material of the first optically dense medium layer is silicon, and the material of the first optically thinner medium layer is silicon dioxide; or, the material of the first optically dense medium layer is metal, and
  • the material of the first optically thin dielectric layer is any one of silicon nitride, silicon oxynitride, and silicon carbonitride.
  • the preparing the first chip includes: preparing the first light blocking layer in the first wafer; preparing the first chip above the first light blocking layer.
  • the preparing the first light blocking layer in the first wafer includes: preparing a first light blocking layer in the first wafer; A first optically dense medium layer is correspondingly formed below; the first interface between the first optically dense medium layer and the first optically thinner medium layer is a rough surface with a roughness greater than a preset threshold.
  • the first optically dense dielectric layer is silicon
  • the first optically thinner dielectric layer is a buried silicon oxide BOX.
  • the manufacturing method further includes: preparing a second light under the second wafer. Barrier layer.
  • the preparing a second light blocking layer on the surface of the substrate of the second wafer includes: preparing a second light blocking layer on the surface of the substrate of the second wafer; A second optically dense medium layer is prepared on the surface of the second optically thinner medium layer, and the surface of the second optically thinner medium layer is a rough surface with a roughness greater than a preset threshold.
  • the preparing a second optical thinning medium layer on the substrate surface of the second wafer includes: performing a thinning process on the substrate surface of the second wafer to make the second wafer
  • the substrate surface of the wafer is a rough surface with a roughness greater than a preset threshold; the second optically thin dielectric layer is prepared on the substrate surface of the second wafer, and the morphology of the second optically thin dielectric layer is the same as that of the first
  • the substrate surface morphology of the two wafers is basically the same.
  • the preparing a second optical thinning medium layer under the second wafer includes: preparing the second optical thinning medium layer on the surface of the substrate of the second wafer; The surface of the second optical thinning medium layer is roughened, so that the surface of the second optical thinning medium layer is a rough surface with a roughness greater than a preset threshold.
  • the preparing a second light blocking layer on the substrate surface of the second wafer includes: preparing a second intermediate layer on the substrate surface of the second wafer; The surface of the layer is roughened, so that the surface of the second intermediate layer is a rough surface with a roughness greater than a preset threshold; the second optical thinning medium layer is prepared on the surface of the second intermediate layer, and the second optical thinning medium
  • the surface morphology of the layer is basically consistent with the surface morphology of the second intermediate layer.
  • the manufacturing method before preparing the second optically thin dielectric layer, the manufacturing method further includes: performing a thinning process on the surface of the substrate of the second wafer.
  • the thinning of the substrate surface of the second wafer includes: reducing the thickness of the second wafer to 30 ⁇ m or less.
  • the surface roughness of the second optically thinner medium layer is greater than 20 nm.
  • a spike-like structure or a hole-like structure is formed on the surface of the second optical thinning medium layer, and the spike-like structure is formed by pyramid-shaped protrusions or inverted pyramid-shaped pits.
  • the material of the second optically dense medium layer is silicon, and the material of the second optically thinner medium layer is silicon dioxide; or, the material of the second optically dense medium layer is metal, and
  • the material of the second optically thin dielectric layer is any one of silicon nitride, silicon oxynitride, and silicon carbonitride.
  • the preparing the first light blocking layer above the first wafer includes: arranging a carrier sheet under the second light blocking layer; using the carrier sheet as a support, in the The first light blocking layer is prepared on the first wafer.
  • the preparing the second chip includes: preparing a second light blocking layer in the second wafer; preparing the second chip above the second light blocking layer.
  • the preparing a second light blocking layer in the second wafer includes: preparing a second light blocking layer in the second wafer; below the second light blocking layer Correspondingly, a second optically dense medium layer is formed; the second interface between the second optically dense medium layer and the second optically thinner medium layer is a rough surface with a roughness greater than a preset threshold.
  • the second optically dense dielectric layer is silicon
  • the second optically thinner dielectric layer is a buried silicon oxide BOX.
  • the manufacturing method further includes: manufacturing a pad, the pad located on one side of the security chip, close to the first chip, and electrically connected to the first chip; or, the pad Located on the other side of the security chip, close to the second chip, and electrically connected to the second chip.
  • the first chip and the second chip are a logic chip and a memory chip, respectively.
  • a security chip including a security chip manufactured according to the second aspect and the manufacturing method described in any one of the possible implementation manners of the second aspect.
  • an electronic device including the first aspect and the security chip described in any one of the possible implementation manners of the first aspect.
  • Figure 1 is a schematic structural diagram of a security chip based on a system-on-chip architecture.
  • FIGS. 2 to 5 are schematic diagrams of the structure of several security chips according to the embodiments of the present application.
  • FIG. 6 is a schematic structural diagram of a security chip according to an embodiment of the present application, in which a schematic structural diagram of the first light blocking layer of the security chip is shown.
  • Fig. 7 is a perspective view of a surface structure of a first optical thinner medium layer according to an embodiment of the present application.
  • Fig. 8 is a cross-sectional view of a first optical thinner medium layer according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another security chip according to an embodiment of the present application, in which another schematic structural diagram of the first light blocking layer is shown.
  • FIG. 10 is a schematic structural diagram of another security chip according to an embodiment of the present application, in which another schematic structural diagram of the first light blocking layer is shown.
  • 11 to 13 are schematic diagrams of the structure of other security chips according to embodiments of the present application.
  • 16-22 show partial cross-sectional views of the first wafer and the second wafer after several process steps according to embodiments of the present application.
  • 23 to 25 are schematic flowcharts of other methods for manufacturing security chips according to embodiments of the present application.
  • 26 to 31 show partial cross-sectional views of the first wafer and the second wafer after several process steps according to an embodiment of the present application.
  • FIG. 32 is a schematic structural diagram of another security chip according to an embodiment of the present application.
  • FIG. 33 is a schematic flow chart of another method for manufacturing a security chip according to an embodiment of the present application.
  • the security chip may be an embedded security chip (embedded Security Element, eSE), a biochip (for example, a fingerprint sensor chip), a chip with a circuit (for example, a fingerprint sensor chip) and a near field communication (NFC) chip. Processor), various chips in the Internet of Things, and so on.
  • the security chip may include elements such as transistors, resistors, capacitors, and inductors, and wiring devices or components.
  • the security chip may be a miniature electronic device or component carrying an integrated circuit (IC). This application does not make specific restrictions on this.
  • the chip provided in the embodiments of this application can be applied to mobile terminals such as smart phones, tablets, wearable devices, smart homes, smart cars, or other electronic devices such as servers, supercomputers, security devices, etc. middle.
  • FIG. 1 shows a schematic structural diagram of a security chip 100 based on a System On Chip (SOC) architecture.
  • SOC System On Chip
  • the security chip 100 mainly includes a logic module 110 and a storage module 120.
  • the logic module 110 and the storage module 120 are integrated on the same chip, which can realize fast and safe communication between the logic module 110 and the storage module 120. Communication.
  • the foregoing logic module 110 may be a central processing unit (CPU), or may be other logic control and calculation modules, used to control the operation of various components in the security chip and the calculation and processing of data ,
  • the calculated data is transmitted to the storage module 120 for storage.
  • the logic module 110 includes, but is not limited to, a microcontroller (Microcontroller Unit, MCU), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (ASIC), a ready-made programmable gate array (Field Programmable Gate Array (FPGA) or other programmable logic devices (Programmable Logic Device, PLD), discrete gates or transistor logic devices, discrete hardware components.
  • MCU microcontroller Unit
  • DSP Digital Signal Processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • PLD Programmable Logic Device
  • the aforementioned storage module 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) circuit. It should be understood that the storage circuit may also be other types of storage circuits, such as other random access memory (RAM) circuits, read only memory circuits (Read Only Memory, ROM) circuits, and flash memory (Flash). The example does not make any restrictions on this.
  • DRAM Dynamic Random Access Memory
  • the storage circuit may also be other types of storage circuits, such as other random access memory (RAM) circuits, read only memory circuits (Read Only Memory, ROM) circuits, and flash memory (Flash). The example does not make any restrictions on this.
  • the security chip 100 may also include a data encryption engine (Data Encryption Engine) module 130, which is based on a specific encryption and decryption algorithm Encrypt and decrypt user data to ensure data security.
  • Data Encryption Engine Data Encryption Engine
  • the encrypted data and the key can be stored or cached in the storage module 120.
  • the data encryption engine can encrypt and decrypt user data based on any encryption algorithm in the prior art, and this application also does not specifically limit the specific encryption and decryption algorithm.
  • the aforementioned data encryption engine module 130 may be integrated with the logic module 110.
  • the logic module after the integrated encryption engine module 130 may be used to encrypt and decrypt data.
  • the attacker uses a laser fault injection method to attack, in some attack methods, the attacker uses an infrared band laser to illuminate a specific area of the logic module of the chip through the back of the chip. The photocurrent generated by the interaction between the laser and the silicon is used to make the chip output wrong results. Finally, the attacker can obtain the key and crack the encrypted information stored in the security chip by collecting errors with certain characteristics that occur at a specific time and at a specific location, and comparing and analyzing the results with the correct encryption results.
  • the security chip 100 further includes a photosensitive module 140 for detecting the light signal irradiated into the security chip.
  • the photosensitive module 140 detects the laser irradiation, the photosensitive module 140 issues an instruction to issue an alarm or erase the information stored in the chip, for example, to erase the encrypted information stored in the storage module 120 and so on.
  • the photosensitive module 130 may be a photoresistor, a photodiode, a phototransistor, or other components that can convert an optical signal into an electrical signal.
  • the embodiment of the present application does not specifically limit the type of a specific photosensitive module.
  • FIG. 1 only exemplarily shows part of the functional modules in the security chip.
  • the security chip may also include other functional modules and corresponding circuit structures.
  • the security chip 100 may also include an interface module to form a security chip. Data input and output channels with peripherals. This application does not specifically limit the specific functional composition of the security chip.
  • a photosensitive module 130 is added to the security chip 100.
  • adding a photosensitive module will cause Increasing the area of the entire security chip will also increase the manufacturing cost of the entire security chip.
  • the logic module 110, the storage module 120 and other modules are integrated on a chip in the form of SOC, etc., although fast and secure communication can be realized, different modules have different circuits and process systems. It is required to integrate different types of modules on the same chip, which will cause the overall manufacturing cost of the chip to be higher.
  • this application proposes a security chip that can still improve the security level of the security chip without using a photosensitive module, prevent laser fault injection attacks, reduce the area of the security chip, and reduce the cost of the security chip. manufacturing cost.
  • FIG. 2 shows a schematic diagram of the structure of a security chip 200.
  • the security chip 200 includes: a first chip 210, a second chip 220 and a first light blocking layer 230;
  • the first chip 210 and the second chip 220 are stacked up and down and electrically connected to each other;
  • the first light blocking layer 230 is close to the circuit area 211 in the first chip 210, and is used for total reflection and/or scattering of the first light signal irradiated from the outside and toward the circuit area 211 in the first chip 210.
  • the second chip 220 is stacked under the first chip 210, and the first light blocking layer 230 is disposed above the circuit area 211 in the first chip 210.
  • the area of the first light blocking layer 230 is not less than the area of the circuit area 211.
  • the first light blocking layer 230 may completely cover the circuit area 211. Or in other cases, the first light blocking layer 230 may also partially cover the circuit area 211, for example, only cover a partial circuit area in the circuit area 211, which is a core functional circuit area of the first chip.
  • the second chip 220 may also be stacked above the first chip 210, and the first light blocking layer 230 is disposed under the circuit area 211 in the first chip 210.
  • the first chip 210 and the second chip 220 are different types of chips and are used to implement different functions.
  • the first chip 210 may be a logic chip, and the logic chip includes a logic circuit that performs logic operations and operations on digital signals. Specifically, it may be a programmable logic device or other processor chips, such as the logic module 110 and data in FIG.
  • the encryption engine module 130 may be a logic chip, which is mainly used to implement the control function of the security chip 200 and logic operation functions such as data processing.
  • the second chip 220 may be a storage chip, for example, may include the storage module 120 in FIG. 1, and is mainly used to implement the storage of encrypted data.
  • the first chip 210 may also be a memory chip, and the second chip 220 corresponds to a logic chip.
  • the first chip 210 and the second chip 220 are both logic chips, or both are memory chips.
  • the first chip and the second chip include but are not limited to logic chips or memory chips, and they may also be any other types of chips used to perform specific functions in the security chip.
  • the implementation of this application The example does not limit the specific types of the first chip and the second chip.
  • the first chip 210 and the second chip 220 are two independently formed chip structures, which are stacked on top of each other through a three-dimensional (3D) packaging method, and are electrically connected to form a security chip.
  • the first chip 210 and the second chip 220 may be prepared and formed on two wafers respectively. For example, only logic chips are prepared on the logic wafer, and only memory chips are prepared on the storage wafer.
  • the process of making a logic chip can be optimized based on the structure of the logic chip, and the process of preparing a memory chip from a storage wafer can be optimized based on the structure of the memory chip, so that the process of the logic chip and the memory chip can be optimized.
  • the process is optimal. Compared with the integrated preparation of logic chips and memory chips on the same wafer, it is necessary to comprehensively consider the process requirements of logic chips and memory chips.
  • By adopting the method of the embodiments of this application under the premise of improving the respective performance of logic chips and memory chips, It can also reduce the manufacturing cost of logic chips and memory chips.
  • the circuit of the chip is formed on the wafer through complex semiconductor processes such as Photolithography, Ion implantation, Etch, Deposition, Epitaxy, etc. structure.
  • a substrate we can also call it a substrate.
  • the circuit area of the chip prepared by the semiconductor process is generally formed on the upper part of the substrate and the epitaxial layer above the substrate.
  • the circuit area 211 in the first chip 210 is located below the first chip 210, and the substrate 212 is located above the first chip 210, and is located on the first chip 210. 210 above the circuit area 211.
  • the first light blocking layer 230 may be formed in the substrate 212 of the first chip 210. In other embodiments, as shown in FIG. 2, the first light blocking layer 230 may also be formed in Above the substrate 212 of the first chip 210.
  • the light signal (for example, the first light signal) incident on the first light blocking layer 230 can be totally reflected and/or scattered by the first light blocking layer 230 to prevent the first light signal from entering into In the first chip 210, in particular, the first optical signal is prevented from entering the circuit area 211 of the first chip 210, thereby reducing or even eliminating the optical signal entering the circuit area 211 of the first chip 210, and avoiding the formation of laser light on the security chip. Inject attacks to improve the security performance of the security chip.
  • the area of the security chip is reduced, and the manufacturing cost of the security chip is also reduced.
  • the newly added light blocking layer performs total reflection and/or scattering of the light signal, avoiding the addition of a photosensitive module in the security chip to detect the attack light signal, and on the premise of improving the security performance of the security chip, further reducing the area and manufacturing of the security chip 200 cost.
  • the thicknesses of the first chip 210 and the second chip 220 are relatively small, and may be chips after a substrate thinning process, which can prevent attackers from disassembling the security chip, thereby improving the security performance of the security chip.
  • the thickness of the first chip 210 and/or the second chip 220 is less than a certain threshold.
  • the thickness of the first chip 210 and/or the second chip 220 is less than 30 ⁇ m.
  • the thickness of the two chips is less than 10 ⁇ m.
  • FIG. 3 shows a schematic structural diagram of another security chip 200.
  • the lower surface of the first chip 210 is further provided with a first interconnection layer 240
  • the upper surface of the second chip 220 is further provided with a second interconnection layer 250.
  • the first chip 210 and the second chip 220 are electrically connected through the first interconnection layer 240 and the second interconnection layer 250.
  • the components in the chip are formed on the wafer, for example, the process of forming a field effect transistor.
  • FEOL Front End Of Line
  • the area formed by the combination of components in the chip can be understood as the circuit area in the chip, such as the circuit area 211 in the first chip 210 above or the circuit area 212 in the second chip 220 below.
  • BEOL BackEnd Of Line
  • the first interconnection layer 240 on the lower surface of the first chip 210 and the second interconnection layer 250 on the upper surface of the second chip 220 can both be metal for connecting various components of the circuit prepared by a later process.
  • the first interconnection layer 240 is electrically connected to the first chip 210, specifically, is electrically connected to the circuit area 211 in the first chip 210
  • the second interconnection layer 250 is electrically connected to the second chip 220, specifically, The circuit area 221 in the second chip 220 is electrically connected.
  • the first interconnection layer 240 and the second interconnection layer 250 may include a re-distribution layer (RDL), which is used to input and output the first chip 210 and the second chip 220 (Input Output, IO) interface is re-arranged.
  • RDL re-distribution layer
  • the foregoing interconnection layer for example, the first interconnection layer 240 includes at least one metal circuit layer and an insulating dielectric layer between the metal circuit layers.
  • the material of the metal circuit layer includes but is not limited to one or more of the following materials: Titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), gold (Au), palladium (Pd), or titanium nitride (TiN), tantalum nitride (TaN), etc. Wait.
  • the insulating layer may include but is not limited to: silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide nitride (SiCN), polyimide (PI), polybenzoxazole (Polybenzoxazole, PBO) ) And one or more of benzocyclobutene (BCB).
  • the second interconnection layer 250 can also be made of the above-mentioned materials.
  • the surface areas of the first interconnection layer 240 and the second interconnection layer 250 are equal.
  • the surface area of the interconnection layer here refers to the upper surface area or the lower surface area, and generally speaking, the upper surface of the interconnection layer The area is equal to the area of the lower surface.
  • a wafer-level bonding process can be used.
  • W2W wafer to Wafer
  • the two layers of wafers There is a one-to-one correspondence between the upper chips (Die), where the first chip 210 on the upper wafer corresponds to the second chip 220 on the lower wafer, and the first chip 210 and the first interconnection layer 240 on the upper wafer correspond to each other. Stacked together with the second chip 220 and the second interconnection layer 250 on the lower wafer to achieve a stacked security chip structure.
  • At least one first bonding pad 241 is formed on the lower surface of the first interconnection layer 240, and at least one second bonding pad 251 is formed on the upper surface of the second interconnection layer 250
  • the at least one first bonding pad 241 and the at least one second bonding pad 251 are also formed of metal and can be used to transmit electrical signals.
  • the at least one first bonding pad 241 and the at least one second bonding pad 241 are also formed of metal.
  • the material of the pad 251 is the same as the material of the metal circuit layer in the interconnection layer described above.
  • the at least one first bonding pad 241 and the at least one second bonding pad 251 have a one-to-one correspondence, and each of the at least one first bonding pad 241 can pass crystals.
  • the circular-level bonding process is bonded to its corresponding second bonding pad 251 to form an electrical connection, thereby forming an electrical connection between the first interconnection layer 240 and the second interconnection layer 250, so that the first chip 210 and The second chip 220 is electrically connected through these two interconnection layers.
  • the electrical connection device between the stacked first chip 210 and the second chip 220 that is, the bonding pad in the interconnection layer, is hidden inside the security chip 200, and the electrical connection cannot be passed from the outside.
  • the connection device reads the data in the first chip 210 and the second chip 220 and related information of the chip, thereby improving the safety performance and reliability of the security chip 200.
  • the security chip 200 formed after the first chip 210 and the second chip 220 are stacked and connected has many advantages such as small size, high reliability, and low power consumption, and can improve the overall performance of the security chip. , So that it can be applied to more and more demanding application scenarios.
  • first chip 210 and the second chip 220 may adopt a chip-to-wafer (C2W) bonding process, in addition to using a wafer-level bonding process to achieve chip stacking and electrical connection, or
  • the chip-to-chip (C2C) bonding process realizes the stacking and electrical connection of the chips, and the embodiment of the present application does not specifically limit the specific stacking mode and electrical connection mode of the chip.
  • the security chip further includes a pad, which is used to communicate with other electronic components, transmit data signals generated by the security chip, or receive control signals transmitted by other devices, and so on.
  • the pad may be located on one side of the security chip, close to the first chip, and electrically connected to the first chip; or, the pad may also be located on the other side of the security chip, close to the second chip, and The second chip is electrically connected.
  • the bonding pad 280 is disposed above the first light blocking layer 230 and is electrically connected to the metal circuit layer in the first interconnection layer 240 to be electrically connected to the first chip 210.
  • a blind hole is formed between the metal circuit layer in the first interconnection layer 240 and the upper surface of the first light blocking layer 230, and the sidewall of the blind hole and the upper surface of the first light blocking layer 230 are formed There is an insulating dielectric layer 281, and the pad 280 is formed on the insulating dielectric layer 281, and is connected to the metal circuit layer in the first interconnection layer 240 through the metal structure in the blind hole.
  • the pad 280 may also be disposed under the second chip 220 to be electrically connected to the metal circuit layer in the second interconnection layer 250.
  • FIG. 3 only illustrates the structure of one pad of the security chip, and the security chip may also include multiple pads for transmitting signals of the security chip.
  • the surface area of the first chip 210 and the surface area of the second chip 220 are equal and stacked up and down in alignment. At this time, the surface area of the first chip 210, the surface area of the second chip 220, the surface area of the first interconnection layer 240, and the surface area of the second interconnection layer 250 are equal, and they are all aligned and stacked up and down.
  • the surface area of the first chip 210 may not be equal to the surface area of the second chip 220.
  • the surface area of the chip in this application is the upper surface area or the lower surface area of the chip, and generally speaking, the upper surface area and the lower surface area of the chip Approximately equal.
  • the projected area of the chip mounted on the PCB board can also be regarded as the surface area of the chip.
  • first chip 210 and the second chip 220 are different types of chips, they have their own circuit structures and therefore have their own process requirements, and the surface areas of the two are usually not equal.
  • one of the first chip 210 and the second chip 220 with the smaller surface area is placed in the carrier, and the surface area of the carrier is the same as the other surface area.
  • the surface area of the larger chip is equal, and the carrier is stacked up and down in alignment with another chip with a larger surface area.
  • FIG. 4 shows a schematic structural diagram of another security chip 200.
  • the surface area of the first chip 210 is smaller than the surface area of the second chip 220.
  • the security chip 200 further includes a carrier 260 whose surface area is equal to the surface area of the second chip 220.
  • a accommodating structure 261 is provided in the carrier 260, and the accommodating structure 261 is a through hole, and the first chip 210 is provided in the accommodating structure 261.
  • a filling layer 262 is further provided between the first chip 210 and the carrier 260 to stably fix the first chip 210 in the accommodating structure 261.
  • the filling layer 262 includes, but is not limited to, polymer organic materials, such as dry film (Dry Film) materials or other polymer materials with good fluidity.
  • the filling layer 262 can be a dry film material that can be photoetched, and can be filled between the first chip 210 and the accommodating structure 261 without voids under vacuum and heating conditions, and adopts The lithographic material can be used as the filling layer, while filling and fixing the gap between the groove and the first chip, it can also facilitate the process and save the manufacturing time of the chip.
  • the accommodating structure 261 may be a groove in addition to a through hole, and the groove is formed on the lower surface of the carrier 260.
  • the first chip 210 is disposed at the bottom of the groove through an adhesive layer to stably fix the first chip 210 in the groove.
  • the adhesive layer includes but is not limited to die attach film (DAF) .
  • the surface area of the first interconnection layer 240 is larger than the surface area of the first chip 210 and is equal to the surface area of the carrier 260.
  • the surface area of the second interconnection layer 250 is equal to the surface area of the second chip 220. Therefore, the surface area of the second interconnection layer 250 is also equal to the surface area of the carrier 260.
  • FIG. 5 shows a schematic structural diagram of another security chip 200.
  • the surface area of the second chip 220 is smaller than the surface area of the first chip 210.
  • the second chip 220 is disposed in the accommodating structure 261 in the carrier 260.
  • the accommodating structure 261 in the carrier 260 is a groove formed on the upper surface of the carrier 260, and the second chip 220 is fixed in the accommodating structure 261 through the adhesive layer 263 and/or the filling layer 262
  • the adhesive layer 263 includes but is not limited to DAF.
  • the accommodating structure 261 may also be a through hole.
  • the surface area of the second interconnection layer 250 is larger than the surface area of the second chip 220 and is equal to the surface area of the carrier 260.
  • the surface area of the first interconnection layer 240 is equal to the surface area of the first chip 210. Therefore, the surface area of the first interconnection layer 240 is also equal to the surface area of the carrier 260.
  • a chip with a smaller surface area is arranged in a carrier to realize stacking between two chips of different sizes.
  • the first interconnection layer 240 and the second interconnection layer 250 are respectively formed, and the first chip 210 and the second chip 220 are electrically connected by bonding between the first interconnection layer 240 and the second interconnection layer 250.
  • the accommodating structure in the carrier provides support and stability for the small-area chip, so that the large-area chip and the small-area chip are stacked together, so that the stacked chip structure can be realized while still It is possible to manufacture as many small-area chips as possible on the wafer, reducing the cost of a single chip, thereby reducing the overall manufacturing cost.
  • the small-area chip is not directly on the wafer, and is bonded to the wafer where the large-area chip is located by wafer-level bonding. Before stacking the two chips, test the two chips to screen out chips with good performance, remove chips with poor performance, improve the overall security chip yield, and further reduce overall manufacturing costs. It can be understood that although the embodiments describe a stack of two chips, one large and one small, a stack of one large chip and more small chips is also possible.
  • the carrier 260 includes but is not limited to silicon, glass, ceramic, and other wafer materials.
  • the embodiment of the present application does not specifically limit the specific carrier material.
  • one of the first chip 210 and the second chip 220 is arranged in the carrier, and the other chip is directly formed in the substrate.
  • the first chip 210 and the second chip 210 The two chips 220 may also be both arranged in the carrier, and then stacked and electrically connected through the interconnection layer.
  • the specific structure of the security chip can be referred to the above related description, which will not be repeated here.
  • FIG. 6 shows a schematic structural diagram of another security chip 200.
  • the first light blocking layer 230 is formed by a first optically dense medium layer 231 and a first optically thinner medium layer 232, and the first optically thinner medium layer 232 connects the first optically dense medium layer 231 and the first chip 210, or the first optically thinner medium layer 232 is interposed between the first optically denser medium layer 231 and the first chip 210.
  • the first optically dense medium layer 231 is a light receiving layer for receiving optical signals and transmitting the optical signals to the first interface formed between the first optically dense medium layer 231 and the first optically thinner medium layer 232.
  • the first optically dense medium layer 231 is an optically dense medium relative to the first optically thinner medium layer 232, in other words, the first optically dense medium layer 232 is relative to As for the optical thinning medium of the first optical dense medium layer 231, the optical thinning medium layer and the optical thinning medium layer in the embodiment of the present application are not absolute concepts, but relative concepts related to each other.
  • the refractive index of the first optically dense medium layer is greater than the refractive index of the first optically thinner medium layer 232.
  • the specific value of the refractive index is not specifically limited.
  • the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232 is a rough interface.
  • the rough interface is composed of multiple different directions. When the optical signal in the same direction is incident on the rough interface, the incident angle of the optical signal received by the small surface in different directions is different.
  • the roughness of the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232 is greater than or equal to a preset
  • the threshold value when the vertical light reaches the first interface, its angle of incidence is increased, so that its angle of incidence is greater than the critical angle, so as to meet the condition of total reflection;
  • the light can effectively reduce the intensity of the refracted light entering the first optically thin medium layer 232, so that most of the light cannot reach the first chip of the security chip, thereby achieving the purpose of resisting laser attacks.
  • the roughness of the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232 is greater than or equal to a preset
  • the threshold value is set, the light receiving area of the first optical thinning medium layer 232 for oblique light can be reduced, thereby reducing the amount of refracted light entering the first optical thinning medium layer 232, so as to achieve the purpose of resisting laser attack.
  • the propagation path of the oblique light in the first optical dense medium layer 231 is longer, which further increases the oblique light reaching the first optical dense medium layer.
  • the loss during the process of 231 and the first optical thinning medium layer 232 further reduces the intensity of light entering the first optical thinning medium layer 232 and ensures the security of the security chip.
  • the first interface whose roughness is greater than the preset threshold can be scattered, making the laser unable to Concentrating to a specific area further reduces the intensity of the refracted light entering the first optically thin medium layer 232.
  • the first interface between the rough first optically dense medium layer 231 and the first optically thinner medium layer 232 can totally reflect or scatter the light incident from the first optically dense medium layer 231 (for example, the first Optical signal), which can reduce the intensity of light reaching the first chip, especially the circuit area in the first chip, so as to achieve the purpose of resisting laser attack.
  • the first optically dense medium layer 231 for example, the first Optical signal
  • the roughness of the first interface is greater than 20 nm.
  • the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232 may be formed with periodically or randomly distributed spike-like structure or hole-like structure, or any other undulating shape. structure.
  • the spike-like structure is beneficial to increase the incident angle of the incident light perpendicular to the first optical dense medium layer 231, thereby causing total reflection, and the hole-like structure is beneficial to scattering the incident light.
  • FIG. 7 shows a surface structure diagram of the first optical thinning medium layer 232.
  • the above-mentioned spike-like structure may be composed of irregularly-sized pyramid-shaped protrusions or inverted pyramid-shaped pits. form.
  • FIG. 8 is a schematic cross-sectional view of the spike structure.
  • the inclined surface of the pyramidal protrusion and the plane where the chip is located form an included angle of 54.7 degrees.
  • the spike-like structure can also be formed by regular pyramid-shaped protrusions or inverted pyramid-shaped pits, and the angle between the slope of the pyramid-shaped protrusion and the plane where the chip is located can also be other values, such as 60 degrees, This application does not impose specific restrictions on this.
  • the pyramidal protrusions can have a regular or irregular sawtooth structure in cross section.
  • the material of the first optically dense medium layer 231 is silicon (Si), and the material of the first optically dense medium layer 232 is silicon dioxide (SiO 2 ); or, the material of the first optically dense medium layer 231 is Metal, the material of the second optically thin dielectric layer 232 is any one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).
  • the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232 to be a rough surface with a roughness greater than a preset threshold, it is possible to make incident on the first optically dense medium Most of the optical signals and even all of the optical signals in the 231 are reflected, which can reduce or eliminate the intensity of light reaching the first chip, thereby achieving the purpose of resisting laser attacks.
  • the process flow is relatively simple. Does not affect the processing method of the chip, which is convenient for mass production.
  • the first optically thinner dielectric layer 232 may be connected to the surface of the substrate of the first chip 210.
  • the first optical thinning medium layer 232 is directly disposed on the upper surface of the substrate of the first chip 210, wherein the upper surface of the substrate of the first chip 210 has a roughness greater than a preset value.
  • Threshold rough surface the shape of the rough surface is basically the same as the shape of the first interface between the first optically dense medium layer 231 and the first optically thinner medium layer 232, which may also be formed with spike-like structures or holes structure.
  • the thickness of the first photophobic medium layer 232 grown on the upper surface of the substrate of the first chip 210 is relatively small. Therefore, the upper surface of the first photophobic medium layer 231 and the first chip 210 have a small thickness.
  • the top surface of the substrate is similar in shape, all of which are rough planes.
  • FIG. 9 shows a schematic structural diagram of another security chip 200.
  • the first optically thin dielectric layer 232 is also directly disposed on the upper surface of the substrate of the first chip 210, wherein the upper surface of the substrate of the first chip 210 and the first optical The morphology of the upper surface of the sparse dielectric layer 232 is inconsistent, and the roughness of the upper surface of the first optical sparse dielectric layer 232 is greater than the roughness of the upper surface of the substrate of the first chip 210, that is, the first optical dense dielectric layer 231 and the first The roughness of the first interface between the optically thin dielectric layers 232 is greater than the roughness of the upper surface of the substrate of the first chip 210.
  • the first optically thin dielectric layer 232 may also be connected to the substrate surface of the first chip 210 through an intermediate layer.
  • FIG. 10 shows a schematic structural diagram of another security chip 200.
  • the upper surface of the substrate of the first chip 210 is further provided with a first intermediate layer 233, and the first optically thin dielectric layer 232 is provided on the upper surface of the first intermediate layer 233.
  • the upper surface of the first intermediate layer 233 is a rough surface, which is similar to the structure of the first optically thinner medium layer in FIG.
  • the shape of the lower surface is basically the same. It can also be said that the shape of the first interface between the first optically dense medium layer 231 and the first optically thinner layer 232 is basically the same as the shape of the upper surface of the first intermediate layer 233, both Rough plane.
  • the material of the first intermediate layer 233 includes but is not limited to silicon material, for example, it may be polysilicon, microcrystalline silicon or amorphous silicon, etc.
  • the material of the first intermediate layer 233 may be the same as the substrate material of the first chip 210. Same or different, the first intermediate layer 233 is intended to form a rough surface, so that the first optically thin dielectric layer above it also forms a rough interface.
  • the embodiment of the present application does not specifically limit the material of the first intermediate layer. .
  • the first light blocking layer 230 is formed above the substrate of the first chip 210, and the first light blocking layer 230 is The layer 230 can be implemented in the subsequent process of the chip. Therefore, the manufacturing process of the first light blocking layer 230 does not affect the manufacturing process of the previous process of the first chip 210, and therefore will not cause any influence on the main manufacturing process of the first chip 210. As a result, the design of the first chip 210 is more flexible, so that the security chip 200 can be applied in more scenarios.
  • first light blocking layer 230 may also be directly formed in the substrate of the first chip 210, that is, prepared in the previous process of the first chip 210.
  • the substrate of the first chip 210 is a silicon on insulator (SOI) structure
  • the substrate of the first chip 210 includes a top silicon layer and a buried silicon oxide layer.
  • the top silicon layer is used to prepare the circuit area 211 of the first chip 210
  • the buried silicon oxide layer is used to prepare the first light blocking layer 230.
  • the optically thin dielectric layer 232, and the bottom silicon layer is used to prepare the first optically dense dielectric layer 231.
  • the structure of the first light blocking layer 230 is the same as the structure of the first light blocking layer in FIG. 6, and the difference between the two mainly lies in the manufacturing process.
  • the first light blocking layer is provided near the circuit area of the first chip, which can prevent the first light signal from entering the circuit area of the first chip.
  • a second light blocking layer can also be provided near the circuit area of the second chip to prevent the second light signal from entering the circuit area of the second chip.
  • FIG. 11 shows a schematic structural diagram of another security chip 200.
  • the security chip 200 further includes: a second light blocking layer 270, which is close to the circuit area 221 in the second chip 220, and is used for total reflection and reflection of the second light signal. /Or scattering to prevent the second light signal from entering the circuit area 221 in the second chip 220.
  • a second light blocking layer 270 which is close to the circuit area 221 in the second chip 220, and is used for total reflection and reflection of the second light signal. /Or scattering to prevent the second light signal from entering the circuit area 221 in the second chip 220.
  • the second light blocking layer 270 may include a second light-sparse medium layer 272 and a second light-dense medium layer 271.
  • the second optically dense medium layer 271 is connected under the second optically thinner medium layer 272, and the second interface between the second optically denser medium layer 271 and the second optically thinner medium layer 272 has a roughness greater than a preset threshold. Rough surface. In some embodiments, the roughness of the second interface is greater than 20 nm.
  • a spike-like structure or a hole-like structure is formed on the second interface; the spike-like structure is formed by pyramid-shaped protrusions or inverted pyramid-shaped pits.
  • the second light blocking layer 270 is symmetrically formed under the second chip 220.
  • the second optically thin dielectric layer 272 is connected to the surface of the substrate of the second chip 220.
  • the second optical thinning medium layer 272 is disposed on the lower surface of the substrate of the second chip 220.
  • the bottom surface of the substrate of the second chip 220 is a rough surface with a roughness greater than a preset threshold.
  • the shape is basically the same, and it can also be formed with a spike-like structure or a hole-like structure.
  • the thickness of the second optically thin medium layer 272 is relatively small, and the upper surface and the lower surface thereof are rough surfaces with substantially the same shape.
  • the morphology of the bottom surface of the substrate is inconsistent with the bottom surface of the second optically thin dielectric layer 272, and the roughness of the upper surface of the second optically thin dielectric layer 272 is greater than the roughness of the bottom surface of the substrate of the second chip 220, namely The roughness of the second interface between the second optically dense medium layer 271 and the second optically thinner medium layer 272 is greater than the roughness of the lower surface of the substrate of the second chip 220.
  • the second optically thin dielectric layer 272 may also be connected to the substrate surface of the second chip 220 through an intermediate layer.
  • the lower surface of the second intermediate layer 273, the lower surface of the second intermediate layer 273 is a rough surface, which is similar to the structure of the second optically thinner layer in FIG. 11.
  • the second optically thinner The thickness of the layer 272 is relatively small, and the morphology of the upper surface and the lower surface thereof are basically the same.
  • the shape of the lower surface of 273 is basically the same, all of which are rough planes.
  • the material of the second intermediate layer 273 includes but is not limited to silicon material, for example, it can be polysilicon, microcrystalline silicon or amorphous silicon, etc.
  • the material of the second intermediate layer 273 can be the same as the material of the second intermediate layer 273.
  • the substrate materials of the two chips 220 are the same or different.
  • the second intermediate layer 273 is intended to form a rough surface, so that the second optically thin dielectric layer underneath also forms a rough interface.
  • the material of the layer is not specifically limited.
  • the material of the second optically dense medium layer 271 is silicon (Si), and the material of the second optically dense medium layer 272 is silicon dioxide (SiO 2 ); or, the material of the first optically dense medium layer 231 is Metal, the material of the second optically thin dielectric layer 232 is any one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).
  • the pad 280 is disposed above the first light blocking layer 230 and is connected to the first interconnection layer 240.
  • the pad 280 may also be disposed on the second The underside of the light blocking layer 230, such as under the second optically dense medium layer 271 in FIGS. 11 to 13, is connected to the second interconnection layer 250.
  • the light blocking layer is a highly reflective film, which can be a metal material or an all-dielectric material.
  • the embodiment of the present application does not specifically limit the structure of the specific light blocking layer.
  • both chips are protected against laser fault injection, which further enhances the security performance of the security chip.
  • the light blocking layer is realized by adopting a structure of a light thinning medium layer and a light dense medium layer, it can be prepared by directly preparing two dielectric layers on the semiconductor chip, which not only ensures that no additional In the case of chip area, laser attack is prevented, and the process flow is relatively simple, does not affect the processing method of the chip, is convenient for mass production and has low manufacturing cost.
  • the device embodiment of the security chip of the present application is described in detail above, and the following describes the embodiment of the method for manufacturing the security chip of the present application in detail with reference to FIG. 14 to FIG. 33. It should be understood that the device embodiment Corresponding to the method embodiments, and for similar descriptions, reference may be made to the device embodiments.
  • Fig. 14 is a schematic flow chart of a method for manufacturing a security chip.
  • the manufacturing method 20 of the security chip may include the following steps.
  • S220 Prepare a second chip, which is located in the second wafer.
  • the physical parameters such as the material and structure of the first wafer and the second wafer may be the same.
  • the number of chips prepared on the first wafer is equal to the number of chips prepared on the second wafer.
  • the first chip and the second chip are different types of chips and are used to implement different functions.
  • the first chip and the second chip are a logic chip and a memory chip, respectively.
  • first chip and the second chip please refer to the description of the first chip 210 and the second chip 220 in the above device embodiment. Related descriptions will not be repeated here.
  • S230 Use a wafer-level bonding process to bond the first wafer and the second wafer, so that the first chip and its corresponding second chip are stacked up and down, and are electrically connected to each other.
  • a wafer-level bonding process is used to stack the first wafer above the second wafer, so that the first chip is correspondingly stacked above the second chip and is electrically connected to the second chip.
  • the size of the first wafer and the second wafer are the same. After the first wafer and the second wafer are stacked, each chip in the first wafer corresponds to each chip in the second wafer on a one-to-one basis. , The centers of the corresponding two chips coincide in the vertical direction.
  • the first chip in the first wafer corresponds to the second chip in the second wafer
  • the centers of the first chip and the second chip overlap in the vertical direction
  • the first chip and the second chip are electrically connected to each other .
  • S240 Prepare a first light blocking layer on the surface of the substrate of the first wafer, and the first light blocking layer is used for total reflection and/or scattering of the first light signal to prevent the first light signal from entering the first chip Circuit area.
  • a first light blocking layer is prepared on the upper surface of the first wafer, and the first light blocking layer will be incident from above the security chip to the second wafer. At least part of the optical signal (such as the first optical signal) of a light blocking layer is totally reflected and/or scattered to prevent the first optical signal from entering the chip to form a laser fault attack.
  • the first wafer and the second wafer may be silicon wafers or other semiconductor material wafers.
  • a first light blocking layer is prepared on the lower surface of the first wafer, The first light signal incident on the first light blocking layer is totally reflected and/or scattered.
  • the first light blocking layer is prepared on the substrate surface of the first wafer.
  • the substrate surface of the first wafer is the first The upper surface of the wafer, if the first wafer is stacked under the second wafer, the substrate surface of the first wafer is the lower surface of the first wafer.
  • the circuit structure of the first chip is formed on the other surface, and this surface is the bonding surface.
  • the entire surface of the substrate of the first wafer can be covered and prepared with a light blocking layer, wherein, in the light blocking layer, a local area corresponding to the first chip is called The first light blocking layer.
  • S250 Cutting the stacked first wafer and second wafer to obtain a first security chip, where the first security chip includes a first chip, a second chip, and a first light blocking layer.
  • the stacked first wafer and second wafer are cut along the cutting path to obtain multiple stacked security chips, where each security chip has the same structure, and each security chip includes light blocking
  • the layer prevents laser injection attacks.
  • the first security chip manufactured in this step may be the security chip 200 in the device embodiment of FIG. 2 described above.
  • FIG. 15 is a schematic flowchart of another method for manufacturing a security chip.
  • the manufacturing method 30 of the security chip may include the following steps.
  • S311 Prepare a first chip in the first wafer.
  • This step is an implementation manner of the above step S210.
  • a semiconductor manufacturing process is used to prepare a first chip array in a first wafer.
  • Each chip in the first chip array has the same structure.
  • the first chip in this step is a chip in the first chip array. .
  • the circuit structure of each chip in the first chip array can be prepared in the first wafer through semiconductor processes such as photolithography, ion implantation, etching, deposition, and epitaxy, for example, field effect transistors and the like can be prepared.
  • This step and the following steps S340 and S350 are one implementation of the above step S230.
  • a post-process in the semiconductor process can be used to prepare a first interconnection layer to form the first chip on the first wafer.
  • the first interconnection layer includes a metal circuit layer and an insulating dielectric layer.
  • the first interconnection layer The metal circuit layer in the layer is electrically connected to the first chip.
  • the first interconnection layer may include a rewiring layer for re-layouting the input and output interfaces of the first chip.
  • At least one first bonding pad is formed on the upper surface of the first interconnection layer, and the at least one first bonding pad is formed of metal and can be used to transmit electrical signals of the first chip.
  • first interconnection layer for the first interconnection layer, reference may be made to the related description of the first interconnection layer 240 in the foregoing device embodiment, which will not be repeated here.
  • the upper surface of the first interconnection layer may also be planarized to form a smooth plane whose flatness and roughness both meet certain threshold requirements.
  • polishing the upper surface of the first interconnection layer includes, but is not limited to, a chemical mechanical polishing (CMP) process.
  • FIG. 16 shows a partial cross-sectional view of the first wafer after this step.
  • the circuit area 211 of the first chip 210 is formed in the first wafer 201
  • the first interconnection layer 240 is formed on the upper surface of the first chip
  • the first interconnection layer 240 includes a metal circuit layer
  • At least one first bonding pad 241 is formed on the surface of the first interconnection layer 240.
  • S331 Prepare a second chip in the second wafer.
  • This step is an implementation manner of the above step S220.
  • each chip in the second chip array has the same structure, and the second chip in this step is one chip in the second chip array.
  • each chip in the first wafer corresponds to each chip in the second wafer on a one-to-one basis, the surface areas of the corresponding two chips are equal, and the two chips overlap in the vertical direction.
  • the first chip in the first wafer corresponds to the second chip in the second wafer, the first chip and the second chip overlap in a vertical direction, and the first chip and the second chip are electrically connected to each other.
  • a second interconnection layer for forming a second chip can be prepared on the second wafer by a subsequent process in the semiconductor process.
  • the second interconnection layer includes a metal circuit layer and an insulating dielectric layer.
  • the metal circuit layer in the second interconnection layer is electrically connected to the second chip.
  • the second interconnection layer may include a rewiring layer for re-layouting the input and output interfaces of the second chip.
  • At least one second bonding pad is formed on the upper surface of the second interconnection layer, and the at least one second bonding pad is formed of metal and can be used to transmit electrical signals of the second chip.
  • the upper surface of the second interconnection layer may also be planarized to form a smooth plane whose flatness and roughness both meet certain threshold requirements.
  • FIG. 17 shows a partial cross-sectional view of the second wafer after this step.
  • the circuit area 221 of the second chip 220 is formed in the second wafer 202
  • the second interconnection layer 250 is formed on the upper surface of the second chip
  • the second interconnection layer 250 includes a metal circuit layer
  • At least one second bonding pad 251 is formed on the surface of the second interconnection layer 250.
  • S350 Turn the first wafer upside down, and bond the first interconnection layer and the second interconnection layer using a wafer-level bonding process, so that the first chip is correspondingly stacked above the second chip and is electrically connected to the second chip.
  • the position of the first interconnection layer is changed to below the first wafer, and the position of at least one first bonding pad in the first interconnection layer is changed to the lower surface of the first interconnection layer.
  • the lower surface of the first interconnection layer and the upper surface of the second interconnection layer are bonded using a wafer-level bonding process.
  • at least one of the first bonding pads in the first interconnection layer and the second interconnection layer At least one of the second bonding pads corresponds to each other, and is bonded to each other to form an electrical connection, thereby forming an electrical connection between the first interconnection layer and the second interconnection layer, thereby forming an electrical connection between the first chip and the second chip. Electrical connection.
  • the upper surface of the first interconnection layer (the lower surface of the first interconnection layer after inversion) and the upper surface of the second interconnection layer are formed to meet certain flatness and roughness.
  • the smooth and flat surface required by the threshold is conducive to wafer-level bonding of the first interconnection layer and the second interconnection layer.
  • a variety of different bonding processes may be used to bond the first interconnection layer and the second interconnection layer.
  • a hybrid bonding process may be used to bond the first interconnection layer and the second interconnection layer.
  • the so-called hybrid bonding refers to the place where electrical connection is required during wafer stack bonding, that is, the connection between at least one first bonding pad and at least one second bonding pad in the implementation of this application is metal bonding Completed, and other places, that is, the insulating dielectric layer other than the bonding pad in the embodiment of the present application, use dielectric bonding to provide mechanical support.
  • the main factor that needs to be considered in the selection of the medium is that it can be compatible with the temperature and surface treatment process during metal bonding. At present, both polymer binders and silicon oxide can be used as hybrid bonding media.
  • the first interconnection layer and the second interconnection layer may be bonded by other wafer-level bonding methods, such as various direct bonding processes, including but not limited to: Anodic Bonding, Surface Activated Bonding (SAB), etc., as well as various indirect bonding processes through the intermediate layer, including but not limited to: Transient Liquid Phase (TLP) ) Bonding, thermal compression bonding (Thermal Compression Bonding), adhesive bonding (Adhesive Bonding) and other methods, which are not specifically limited in the embodiments of the present application.
  • TLP Transient Liquid Phase
  • TLP Transient Compression Bonding
  • Adhesive Bonding adhesive bonding
  • FIG. 18 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this step.
  • the first chip 210 in the first wafer 201 is stacked on the second chip 220 in the second wafer 202 through the first interconnection layer 240 and the second interconnection layer 250, and the first interconnection layer 240 At least one first bonding pad 241 in the second interconnection layer 250 is correspondingly connected to at least one second bonding pad 251 in the second interconnection layer 250.
  • the upper surface of the first wafer is the substrate material.
  • the upper surface of the first wafer can be thinned by mechanical thinning, chemical thinning, chemical polishing, etc., for example, The grinding wheel grinds the upper surface of the first wafer.
  • the embodiments of the present application do not set any limitation on the specific thinning method.
  • the second wafer below it can play a supporting role.
  • the thickness of the thinned first wafer is less than a certain threshold, for example, less than 30 ⁇ m. Preferably, the thickness of the thinned first wafer is less than 10 ⁇ m.
  • the circuit area of the first chip in the thinned first wafer is close to the upper surface of the first chip, but is not exposed to the upper surface, so as to prevent the external environment from affecting the circuit area of the first chip. Thereby affecting the performance of the first chip.
  • the overall thickness of the security chip can be reduced, thereby preventing an attacker from disassembling the security chip, and improving the security performance of the security chip.
  • FIG. 19 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • the circuit area 211 in the first chip 210 is close to the upper surface of the first wafer 201, and the upper surface of the first wafer 201 is a rough flat surface.
  • S370 Prepare a first optically thinner medium layer above the first wafer, and prepare a first optically denser medium layer on the upper surface of the first optically thinner medium layer.
  • This step may be an implementation manner of step S240 in the manufacturing method 20 described above.
  • the first light blocking layer in step S240 may include the first optically thinner medium layer and the first optically denser medium layer in this step.
  • the first light blocking layer in step S240 may also be another film layer or structure for reflecting light signals, which is not limited in the embodiment of the present application.
  • this step there can be the following three implementation manners.
  • S371 Prepare a first optically thinner medium layer on the upper surface of the first wafer, and prepare a first optically denser medium layer on the upper surface of the first optically thinner medium layer.
  • step S360 after the upper surface of the first wafer is thinned by a method such as mechanical thinning or chemical thinning, the upper surface of the first wafer may form a rough surface with a roughness greater than a certain preset threshold.
  • the rough surface can be formed with periodic or randomly distributed spike-like structures or pore-like structures, or any other structure exhibiting high and low undulations.
  • the first optically thinner medium layer with a smaller thickness is directly prepared on the rough surface, so that the upper surface morphology of the first optically thinner medium layer is the same or similar to the morphology of the rough surface, or in other words, the first optically thinner medium is prepared After layering, the upper and lower surfaces of the first optically thin medium layer are both rough surfaces with roughness greater than a preset threshold.
  • the first interface between the first optically thinner medium layer and the first optically denser medium layer also has a roughness greater than a preset threshold.
  • the rough surface can form conditions for total reflection and/or scattering of the incident optical signal, increase the reflection intensity and scattering intensity of the optical signal, greatly reduce the transmission intensity of the optical signal, thereby reducing or even eliminating the entry to the first
  • the optical signal in the chip avoids laser injection attacks.
  • the upper surface of the first optical density medium layer may be planarized to form a relatively smooth plane.
  • preparing a thicker first optical density medium layer can also make the upper surface of the first optical density medium layer present a relatively smooth plane.
  • the above-mentioned methods for preparing the first optically thin dielectric layer and the first optically dense medium include, but are not limited to, chemical vapor deposition (Physical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), and pulsed laser deposition (Pulse Laser Deposition, PLD), atomic layer deposition (Atomic Layer Deposition, ALD), etc., the embodiment of the present application does not specifically limit the specific preparation methods of the first and second optically thin dielectric layers.
  • the upper surface of the first wafer may be further roughened, for example, grinding and/or wetness may be used.
  • Method etching processes the upper surface of the first wafer to enhance the roughness of the upper surface of the first wafer.
  • the upper surface of the thinned first wafer may be coated with an etchant and then heated, where the etchant includes but not limited to: sodium hydroxide NaOH solution, potassium hydroxide KOH solution, tetramethylhydroxide Ammonium TMAH solution, sodium silicate Na 2 SiO 3 solution.
  • the concentration of the corrosive agent is greater than or equal to a preset threshold, for example, 8 wt%.
  • the etchant may be heated to 80 degrees Celsius or more, and etched for 25 minutes or more.
  • FIG. 20 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • a first photophobic medium layer 232 is formed on the rough upper surface of the first wafer 201.
  • the upper and lower surfaces of the first photophobic medium layer 232 are both rough planes.
  • a first optical dense medium layer 231 is also formed above the, and the upper surface of the first optical dense medium layer 231 is a smooth flat surface.
  • S372 Prepare a first optically thinner medium layer on the upper surface of the first wafer, perform roughening treatment on the first optically thinner medium layer, and prepare a first optically denser medium layer on the upper surface of the first optically thinner medium layer.
  • the method for preparing the first photophobic medium layer in this step and the method for roughening the upper surface of the first photophobic medium layer can also refer to the preparation method and the roughening method in step S371, for example, using deposition
  • the method prepares the first light thinning medium layer, and roughening the first light thinning medium layer by sandblasting or hydrofluoric acid wet etching process, so that the upper surface of the first light thinning medium layer forms a rough surface.
  • step S371 The difference between this step and step S371 is that the thickness of the first photophobic medium layer in step S371 is smaller, and its top surface morphology depends on the top surface morphology of the first chip. In this step, the thickness of the first photophobic medium layer The thickness is not required, and the upper surface of the first optically thin medium layer is directly roughened. Step S371 can simplify the overall process flow, but has higher process requirements, while step S373 has lower process requirements.
  • the above step S360 may not be required, and the first light-reducing medium layer is directly prepared on the substrate of the first chip.
  • FIG. 21 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • a first optically thinner dielectric layer 232 is formed on the upper surface of the first wafer 201.
  • the upper and lower surfaces of the first optically thinner dielectric layer 232 are both rough planes, but the shape of the roughened surfaces is inconsistent.
  • a first optically dense medium layer 231 is also formed above an optically thinner medium layer 232, and the upper surface of the first optically denser medium layer 231 is a smooth plane.
  • S373 Prepare a first intermediate layer on the upper surface of the first wafer, perform roughening treatment on the upper surface of the first intermediate layer, prepare a first optical thinning medium layer on the upper surface of the first intermediate layer, and perform the first optical thinning A first optically dense medium layer is prepared on the upper surface of the medium layer.
  • the method for preparing the first intermediate layer in this step and the method for roughening the upper surface of the first intermediate layer can refer to the preparation method and roughening method in step S371.
  • the first intermediate layer is prepared by a deposition method.
  • the middle layer is corroded on the upper surface of the first middle layer by an etching solution and/or grinding, so that the upper surface of the first middle layer forms a rough surface with a roughness greater than a preset threshold.
  • the process of preparing a first optically thinner medium layer on the upper surface of the first intermediate layer, and preparing the first optically denser medium layer on the upper surface of the first optically thinner layer is similar to the process in the above step S371, wherein the first optical The thickness of the thin dielectric layer is small, the upper and lower surfaces thereof are both rough flat surfaces, and the upper surface of the first optical dense medium layer is smooth flat.
  • the first intermediate layer may be a silicon material, including but not limited to polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
  • the relevant features of the first intermediate layer can be referred to the first intermediate layer 233 in the above device embodiment, which will not be repeated here.
  • the above step S360 may not be required, and the first intermediate layer is directly prepared on the substrate of the first chip.
  • FIG. 22 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • a first intermediate layer 233 is formed on the upper surface of the first wafer 201, the upper surface of the first intermediate layer 233 is a rough plane, and the upper surface of the first intermediate layer 233 is formed with a first intermediate layer 233.
  • a light-reduced medium layer 232, the upper and lower surfaces of the first light-reduced medium layer 232 are both rough flat surfaces, and a first light-dense medium layer 231 is further formed on the first light-reduced medium layer 232, and the first light-dense medium layer 231
  • the upper surface is smooth and flat.
  • the material of the first optically dense dielectric layer is silicon (Si), and the material of the first optically dense dielectric layer is silicon dioxide (SiO 2 ); or, in other embodiments,
  • the material of the first optically dense dielectric layer is metal
  • the material of the second optically dense dielectric layer is any one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN)
  • the specific materials of the first optically dense medium layer and the first optically thinner medium layer are not limited.
  • the related features of the first optically thinner medium layer and the first optically denser medium layer can refer to the related descriptions of the first optically thinner medium layer 232 and the first optically denser medium layer 231 in the above device embodiment. I won't repeat them here.
  • the input and output interfaces of the security chip that is, the pads of the security chip, can be prepared to communicate with other electronic components, transmit data signals generated by the security chip, or receive control signals transmitted by other devices. and many more.
  • photolithography and etching processes can be used to form a blind hole between the first optically dense dielectric layer and the metal circuit layer of the first interconnection layer to expose the metal circuit layer in the first interconnection layer.
  • Prepare an insulating dielectric layer on the upper surface of the middle and first optical density dielectric layer and then use photolithography and etching processes to etch away the insulating dielectric layer in the central area of the blind hole to expose the metal circuit layer in the first interconnection layer, and The insulating dielectric layer is still retained on the sidewall of the blind hole.
  • a metal layer is prepared in the blind hole and on the surface of the insulating dielectric layer, and photolithography and etching processes are used again to form a pad on the insulating dielectric layer.
  • the metal structure in the blind hole is connected to the metal circuit layer in the first interconnection layer.
  • the related features of the pad can refer to the related description of the pad 280 in the above device embodiment, which will not be repeated here.
  • the first security chip manufactured is shown in FIGS. 6, 9 and 10, where FIG. 6 corresponds to the step S371 for preparing the first light blocking layer, and FIG. 9 corresponds to the step S371.
  • S372 prepares the first light blocking layer, and FIG. 10 corresponds to the step S373 to prepare the first light blocking layer.
  • the first security chip includes a first chip 210, a second chip 220, a first interconnection layer 240, a second interconnection layer 250, a first optically dense medium layer 231, a first optically thinner medium layer 232, and a bonding pad 280.
  • the first wafer is turned upside down and the first chip is stacked on top of the second chip.
  • the second wafer may be turned upside down to stack the second chip on the first chip.
  • the first optically thinner medium layer and the first optically denser medium layer are prepared on the lower surface of the first chip.
  • the first chip and the second chip are both chips directly formed in the first wafer and the second wafer, and the surface areas of the first chip and the second chip are equal.
  • the first chip and/or the second chip may also be reconstructed and formed in the first wafer and the second wafer.
  • FIG. 23 is a schematic flowchart of another method for manufacturing a security chip.
  • the manufacturing method 30 of the security chip may include the following steps.
  • S312 Prepare and cut out the first chip in the third wafer, manufacture the accommodating structure in the first wafer, and place the first chip in the accommodating structure.
  • This step is another implementation of the above step S210.
  • a semiconductor process is used to prepare a first chip array in the third wafer.
  • Each chip in the first chip array has the same structure.
  • the first chip array is cut to obtain a plurality of separated chips.
  • a chip is a chip in the first chip array.
  • a plurality of accommodating structures are fabricated on the first wafer, and the accommodating structures are grooves or through holes.
  • the first chip is fixed in one accommodating structure of the plurality of accommodating structures.
  • the accommodating structure is a groove
  • the first chip is put into the groove through a pick and place process.
  • the lower surface of the first chip is provided with a first adhesive layer, and the first adhesive layer includes but is not limited to DAF.
  • a plurality of grooves may be prepared on the first wafer through a variety of process methods, including but not limited to: dry etching, laser method , Mechanical method, etc.
  • process methods including but not limited to: dry etching, laser method , Mechanical method, etc.
  • the embodiments of the present application do not specifically limit this.
  • the filling layer is filled in the gap between the first chip and the groove to further fix the first chip.
  • the first chip can be fixed in the through hole through an adhesive layer and/or a filling layer. In this case, the heat dissipation capability of the first chip can be improved.
  • the accommodating structure the first chip and the filling layer
  • S331 Prepare a second chip in the second wafer.
  • S350 Turn the first wafer upside down, and bond the first interconnection layer and the second interconnection layer using a wafer-level bonding process, so that the first chip is correspondingly stacked above the second chip and is electrically connected to the second chip.
  • S370 Prepare a first optically thinner medium layer above the first wafer, and prepare a first optically denser medium layer on the upper surface of the first optically thinner medium layer.
  • the security chip prepared by the manufacturing method of the embodiment of the present application can be seen in FIG. 4.
  • the carrier 260 in FIG. 4 is a partial area of the first wafer after dicing.
  • FIG. 24 is a schematic flowchart of another method for manufacturing a security chip.
  • the manufacturing method 30 of the security chip may include the following steps.
  • S311 Prepare a first chip in the first wafer.
  • S332 Prepare and cut a second chip in the fourth wafer, fabricate a accommodating structure in the second wafer, and place the second chip in the accommodating structure.
  • This step is another implementation of the above step S220.
  • step S312 the implementation process of this step can refer to the process of step S312 above, which will not be repeated here.
  • S350 Turn the first wafer upside down, and bond the first interconnection layer and the second interconnection layer using a wafer-level bonding process, so that the first chip is correspondingly stacked above the second chip and is electrically connected to the second chip.
  • S370 Prepare a first optically thinner medium layer above the first wafer, and prepare a first optically denser medium layer on the upper surface of the first optically thinner medium layer.
  • the security chip prepared by the manufacturing method of the embodiment of the present application can be seen in FIG. 5.
  • the carrier 260 in FIG. 5 is a partial area of the second wafer after dicing.
  • the first light blocking layer is prepared on the first wafer to prevent light signals from entering the first chip.
  • a second light blocking layer can also be prepared under the second wafer to prevent light signals from entering the second chip.
  • FIG. 25 shows a schematic flowchart of another method 40 for manufacturing a security chip.
  • the manufacturing method 40 of the security chip may include the following steps.
  • S410 Prepare a first chip, and the first chip is located in the first wafer.
  • step S210 for the process of this step, reference may be made to related descriptions of step S210, step S311, or step S312 in the foregoing embodiment.
  • FIG. 16 for a partial cross-sectional view of the bonded first wafer and second wafer after this process step.
  • step S220 for the process of this step, reference may be made to related descriptions of step S220, step S331, or step S332 in the foregoing embodiment.
  • S430 Bond the first wafer and the second wafer by using a wafer-level bonding process, so that the first chip and its corresponding second chip are stacked up and down, and are electrically connected to each other.
  • step S230 the process of this step can refer to the related description of step S230, or step S320, step S340, and step S350 in the foregoing embodiment.
  • FIG. 18 for a partial cross-sectional view of the bonded first wafer and second wafer after this process step.
  • the lower surface of the second wafer is the substrate material, and the lower surface of the second wafer can be thinned by methods such as mechanical thinning, chemical thinning, chemical polishing, etc., for example, , A grinding wheel can be used to grind the lower surface of the second wafer.
  • the embodiments of the present application do not set any limitation on the specific thinning method.
  • the thickness of the thinned second wafer is less than a certain threshold, for example, less than 30 ⁇ m. Preferably, the thickness of the thinned second wafer is less than 10 ⁇ m.
  • the circuit area of the second chip in the thinned second wafer is close to the lower surface of the second chip, but is not exposed to the lower surface, so as to prevent the external environment from affecting the circuit area of the second chip. Thereby affecting the performance of the second chip.
  • the overall thickness of the security chip can be further reduced, thereby preventing an attacker from disassembling the security chip and improving the security performance of the security chip.
  • FIG. 26 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • the circuit area 221 in the second wafer 202 is close to the lower surface of the second wafer 202, and the lower surface of the second wafer 202 is a rough flat surface.
  • S450 Prepare a second light blocking layer under the second wafer, where the second light blocking layer is used to totally reflect and/or scatter the second light signal to prevent the second light signal from entering the second chip.
  • the second light blocking layer may include a second optically thinner medium layer and a second optically denser medium layer.
  • the second light blocking layer in this step may also be other film layers or structures for reflecting optical signals, which is not limited in the embodiment of the present application.
  • a second optically thinner medium layer is prepared under the second wafer, and a second optically denser medium layer is prepared on the lower surface of the second optically thinner medium layer.
  • this step there may also be the following three implementation manners.
  • S451 Prepare a second optically thinner medium layer on the lower surface of the second wafer, and prepare a second optically denser medium layer on the lower surface of the second optically thinner medium layer.
  • step S440 after the lower surface of the second wafer is thinned by a method such as mechanical thinning or chemical thinning, the lower surface of the second wafer may form a rough surface with a roughness greater than a certain preset threshold.
  • the rough surface can be formed with periodic or randomly distributed spike-like structures or pore-like structures, or any other structure exhibiting high and low undulations.
  • a second optically thinner medium layer with a smaller thickness is directly prepared below the roughened surface, and upper and lower surfaces of the second optically thinner medium layer are both roughened surfaces with a roughness greater than a preset threshold.
  • the second interface between the second optically thinner medium layer and the second optically denser medium layer also has a roughness greater than a preset threshold.
  • the rough surface can form conditions for total reflection and/or scattering of the incident light signal, increase the reflection intensity and scattering intensity of the light signal, greatly reduce the transmission intensity of the light signal, and thereby reduce or even eliminate the entry to the second The optical signal in the chip avoids laser injection attacks.
  • the upper surface of the second optical density medium layer may be planarized to form a relatively smooth plane.
  • preparing a thicker second optical density medium layer can also make the upper surface of the second optical density medium layer present a relatively smooth plane.
  • the above-mentioned methods for preparing the second optically dense medium layer and the second optically dense medium include, but are not limited to, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition, etc.
  • the embodiments of the present application are specific to a specific second optically dense medium.
  • the preparation method of the layer and the second optically thin medium layer is not specifically limited.
  • the lower surface of the second wafer may be further roughened, for example, grinding and/or wetness may be used.
  • Method etching processes the lower surface of the second wafer to enhance the roughness of the lower surface of the second wafer.
  • FIG. 27 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this step.
  • a second optical thinning medium layer 272 is formed on the rough lower surface of the second wafer 202.
  • the upper and lower surfaces of the second optical thinning medium layer 272 are both rough planes.
  • the second optical thinning medium layer 272 A second optical density medium layer 271 is also formed under the, and the lower surface of the second optical density medium layer 271 is a smooth flat surface.
  • S452 Prepare a second optically thinner medium layer on the lower surface of the second wafer, perform roughening treatment on the second optically thinner medium layer, and prepare a second optically denser medium layer on the lower surface of the second optically thinner medium layer.
  • the method for preparing the second photophobic medium layer in this step and the method for roughening the upper surface of the second photophobic medium layer can also refer to the preparation method and roughening method in step S451, for example, using deposition
  • the method prepares the second optical thinning medium layer, and the second optical thinning medium layer is roughened by sandblasting or hydrofluoric acid wet etching process, so that the upper surface of the second optical thinning medium layer forms a rough surface.
  • step S451 The difference between this step and step S451 is that the thickness of the second photophobic medium layer in step S451 is smaller, and the top surface morphology is attached to the bottom surface morphology of the second chip. In this step, the thickness of the second photophobic medium layer The thickness is not required, and the lower surface of the second optically thin medium layer is directly roughened.
  • the above step S440 may not be required, and the second light thinning medium layer is directly prepared under the substrate of the second chip.
  • FIG. 28 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • a second optically thinner dielectric layer 272 is formed on the lower surface of the second wafer 202.
  • a second optically dense medium layer 271 is also formed above the second optically thinner medium layer 272, and the lower surface of the second optically denser medium layer 271 is a smooth plane.
  • S453 Prepare a second intermediate layer on the lower surface of the second wafer, perform roughening treatment on the lower surface of the second intermediate layer, prepare a second optical thinning medium layer on the lower surface of the second intermediate layer, and perform the second optical thinning A second optically dense medium layer is prepared on the upper surface of the medium layer.
  • the method for preparing the second intermediate layer in this step and the method for roughening the lower surface of the second intermediate layer can refer to the preparation method and roughening method in step S451.
  • the second intermediate layer is prepared by a deposition method.
  • the middle layer is corroded on the upper surface of the second middle layer by using an etching solution and/or grinding, so that the lower surface of the second middle layer forms a rough surface with a roughness greater than a preset threshold.
  • the process of preparing a second optically thinner medium layer on the lower surface of the second intermediate layer, and preparing a second optically denser medium layer on the lower surface of the second optically thinner layer is similar to the process in the above step S451, wherein the second optical The thickness of the sparse dielectric layer is small, the upper and lower surfaces thereof are both rough planes, and the lower surface of the second optically dense dielectric layer is a smooth plane.
  • the second intermediate layer may be a silicon material, including but not limited to polycrystalline silicon, microcrystalline silicon, or amorphous silicon.
  • the relevant features of the second intermediate layer can be referred to the second intermediate layer 273 in the above device embodiment, which will not be repeated here.
  • the above step S440 may not be required, and the second intermediate layer is directly prepared on the lower surface of the substrate of the second chip.
  • FIG. 29 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • a second intermediate layer 273 is formed on the lower surface of the second wafer 202.
  • the lower surface of the second intermediate layer 273 is a rough surface
  • the lower surface of the second intermediate layer 273 is formed with a second A light-reduced medium layer 272.
  • the upper and lower surfaces of the second light-reduced medium layer 272 are both rough planes.
  • a second light-dense medium layer 271 is further formed under the second light-reduced medium layer 272.
  • the second light-dense medium layer 271 The lower surface is smooth and flat.
  • the material of the second optically dense dielectric layer is silicon (Si), and the material of the second optically dense dielectric layer is silicon dioxide (SiO 2 ); or, in other embodiments,
  • the material of the second optically dense dielectric layer is metal, and the material of the second optically dense dielectric layer is any one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN)
  • the specific materials of the second optically dense medium layer and the second optically thinner medium layer are not limited.
  • the related features of the second optically thinner medium layer and the second optically denser medium layer can refer to the related descriptions of the second optically thinner medium layer 272 and the second optically denser medium layer 271 in the above device embodiment. I won't repeat them here.
  • S460 Set a carrier sheet under the second light blocking layer, and use the carrier sheet as a support to perform a thinning process on the upper surface of the first wafer.
  • a carrier sheet may be provided under the second light blocking layer through the adhesive layer, and the carrier sheet may be a material with a certain strength and thickness, which can play a supporting role.
  • the carrier includes, but is not limited to, materials such as silicon, glass, and ceramics.
  • step S360 For the process of performing the thinning process on the upper surface of the first wafer, reference may be made to the related description of step S360.
  • FIG. 30 shows a partial cross-sectional view of the bonded first wafer and the second wafer after this process step.
  • the carrier 290 is adhered under the second light blocking layer through the adhesive layer 291, specifically, adhered to the lower surface of the second optical density medium layer 271.
  • the circuit area 211 in the first wafer 201 is close to the upper surface of the first chip 210, and the upper surface of the first chip 210 is a rough surface.
  • S470 Prepare a first light blocking layer above the first wafer, where the first light blocking layer is used for total reflection/or scattering of the first light signal to prevent the first light signal from entering the first chip.
  • step S370 Any one of steps S371 to S373 can be used to prepare the first light blocking layer.
  • FIG. 31 shows a partial cross-sectional view of the bonded first wafer and second wafer after this process step.
  • the preparation method in step S371 is used to prepare the first light blocking layer thickness.
  • a first light blocking layer 232 is formed on the rough upper surface of the first wafer 201.
  • the upper and lower surfaces are both rough planes, a first optically dense medium layer 231 is formed above the first optically thinner medium layer 232, and the upper surface of the first optically denser medium layer 231 is a smooth and flat surface.
  • S480 Prepare a pad above the first optically dense medium layer, and the pad is electrically connected to the first interconnection layer.
  • step S380 For the process of this step, reference may be made to the related description of step S380.
  • the pads may also be arranged below the second optical density medium layer and soldering The disc is electrically connected to the second interconnection layer.
  • S490 Cutting the stacked first wafer and second wafer to obtain a first security chip, the first security chip including a first chip, a second chip, a first light blocking layer, and a second light blocking layer.
  • the carrier and the adhesive layer in step S460 may be removed, for example, by physical or chemical methods such as grinding and etching.
  • the adhesive layer may be a photosensitive material that is digested with light, and the carrier is a transparent material. After the bonding pad is prepared, the adhesive layer can be illuminated to digest the adhesive layer and remove the carrier under the adhesive layer.
  • the manufactured first security chip is as shown in FIG. 32, and on the basis of FIG. 31, the related structure of the pad 280 is added.
  • the first light blocking layer is prepared on the upper surface of the second wafer after bonding the first wafer and the second wafer.
  • FIG. 33 shows a schematic flowchart of another method 50 for manufacturing a security chip.
  • the manufacturing method 50 of the security chip may include the following steps.
  • S510 Prepare a first chip, which is located in a first wafer including a first light blocking layer.
  • S520 Prepare a second chip, which is located in the second wafer including the second light blocking layer.
  • S530 Use a wafer-level bonding process to bond the first wafer and the second wafer, so that the first chip and its corresponding second chip are stacked up and down, and are electrically connected to each other.
  • S540 Perform a thinning process on the surface of the first wafer and the surface of the second wafer.
  • S550 Prepare a bonding pad, and the bonding pad is electrically connected to the first chip or the second chip.
  • S560 Cutting the stacked first wafer and second wafer to obtain a first security chip, the first security chip including a first chip, a second chip, a first light blocking layer, and a second light blocking layer.
  • the first light blocking layer and the second light blocking layer may also be formed in the first wafer and the second wafer.
  • the first wafer and/or the second wafer may be SOI wafers, in which the buried silicon oxide layer is an optically thin dielectric layer, the bottom silicon layer is an optically dense dielectric layer, and the top silicon layer is used to form the second A circuit structure of a chip and/or a second chip, or a accommodating structure is formed on the top silicon layer to place the first chip and/or the second chip.
  • SOI wafers in which the buried silicon oxide layer is an optically thin dielectric layer, the bottom silicon layer is an optically dense dielectric layer, and the top silicon layer is used to form the second A circuit structure of a chip and/or a second chip, or a accommodating structure is formed on the top silicon layer to place the first chip and/or the second chip.
  • the first light blocking layer and the second light blocking layer are both formed in the wafer.
  • only one light blocking layer may be formed in the first light blocking layer and the second light blocking layer.
  • the other reflective layer is obtained by the method of manufacturing the light blocking layer in the manufacturing methods 20 to 40 described above.
  • the various embodiments of the manufacturing methods 20 to 50 of the security chip listed above can be executed by robots or numerical control processing, and the device software or processes used to execute the manufacturing methods 20 to 50 can be stored in the memory by execution.
  • the computer program code to execute the above-mentioned manufacturing methods 20 to 50 can be executed by robots or numerical control processing, and the device software or processes used to execute the manufacturing methods 20 to 50 can be stored in the memory by execution.
  • the computer program code to execute the above-mentioned manufacturing methods 20 to 50 can be executed by robots or numerical control processing, and the device software or processes used to execute the manufacturing methods 20 to 50 can be stored in the memory by execution.
  • the computer program code to execute the above-mentioned manufacturing methods 20 to 50 can be executed by robots or numerical control processing, and the device software or processes used to execute the manufacturing methods 20 to 50 can be stored in the memory by execution.
  • the application also provides a security chip prepared according to the above preparation method.
  • the present application also provides an electronic device including the security chip 200 described above, or an electronic device including a security chip prepared according to any one of the methods 20 to 50 described above.
  • the size of the sequence number of each process does not mean the order of execution.
  • the execution order of each process should be determined by its function and internal logic, and should not correspond to the embodiments of the present application.
  • the implementation process constitutes any limitation.
  • the units can be implemented by electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the interchangeability of hardware and software.
  • the composition and steps of each example have been described generally in terms of function. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
  • the disclosed system and device may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments of the present application.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application is essentially or the part that contributes to the existing technology, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium. It includes several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disks or optical disks and other media that can store program codes. .

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

一种安全芯片、安全芯片的制造方法和电子设备，能够提高安全芯片的安全等级且降低成本，提高安全芯片的综合性能。该安全芯片包括：第一芯片、第二芯片和第一光阻挡层；第一芯片和第二芯片上下堆叠，且相互电连接；第一光阻挡层靠近于第一芯片中的电路区域，用于将来自外部并朝向第一芯片中的电路区域照射的第一光信号进行全反射和/或散射。在本方案中，通过分别独立制造第一芯片和第二芯片，而不需要将第一芯片与第二芯片集成在同一个芯片中制造，使得第一芯片和第二芯片的制造工艺解耦，降低第一芯片和第二芯片的制造成本。另外，安全芯片中新增光阻挡层对光信号进行全反射和/或散射，在降低制造成本的同时提高芯片的安全性能。

Description

安全芯片、安全芯片的制造方法和电子设备 技术领域
本申请涉及芯片领域，并且更具体地，涉及一种安全芯片、安全芯片的制造方法和电子设备。
背景技术
安全芯片是一个可独立进行密钥生成、加解密的装置，内部拥有独立的逻辑模块和存储模块，可存储密钥和特征数据，为电脑或移动终端提供加密和安全认证服务。用安全芯片进行加密，并存储密钥和加密后的数据，被窃的数据无法解密，从而保护商业隐私和数据安全。
目前，由于一个安全芯片中集成不同功能的模块，安全芯片的制造成本较高，且存在多种手段可以对安全芯片进行攻击，其中，最主要的破解安全芯片的攻击手段之一为激光故障注入。为了获得密钥，攻击者使用红外波段的激光，透过芯片背面照射芯片逻辑模块特定区域。利用激光与硅相互作用生成的光电流，使芯片输出错误结果。最后，攻击者通过采集特定时刻、特定位置发生的具有某种特征的错误，与正确的加密结果进行比较分析，就可以获取密钥，从而破解芯片中存储的加密信息。
因此，如何防止被激光故障注入攻击，提高安全芯片的安全等级且降低安全芯片的成本，提高安全芯片的综合性能，是一项亟待解决的技术问题。
发明内容
本申请实施例提供了一种安全芯片、安全芯片的制造方法和电子设备，能够提高安全芯片的安全等级且降低成本，提高安全芯片的综合性能。
第一方面，提供了一种安全芯片，包括：第一芯片、第二芯片和第一光阻挡层；该第一芯片和该第二芯片上下堆叠，且相互电连接；该第一光阻挡层靠近于该第一芯片中的电路区域，用于将来自外部并朝向该第一芯片中的电路区域照射的第一光信号进行全反射和/或散射。
在本方案中，通过分别独立制造第一芯片和第二芯片，而不需要将第一芯片与第二芯片不同的功能电路集成在同一个芯片中制造，使得第一芯片和第二芯片的制造工艺解耦，降低第一芯片和第二芯片的制造成本，且该第一 芯片和第二芯片堆叠形成安全芯片，从而减小安全芯片的表面面积。另外，安全芯片中新增光阻挡层对光信号进行全反射和/或散射，在降低制造成本的同时，防止激光注入攻击，提高芯片的安全性能，第三，由于光阻挡层靠近于芯片中的电路区域，使得攻击者不容易在不损害电路区域的情况下去除该光阻挡层，从而使得该光阻挡层能够良好阻挡光信号进入芯片的电路区域中。
在一种可能的实施方式中，该第一芯片的厚度小于30μm；和/或，该第二芯片的厚度小于30μm。
采用本申请实施例的方案，通过控制第一芯片和第二芯片的厚度，防止攻击者对安全芯片进行拆解，从而进一步提高安全芯片的安全性能。
在一种可能的实施方式中，该第一芯片的表面面积与该第二芯片的表面面积不相等；该安全芯片还包括：载体，该载体包括容置结构，该容置结构为通孔或者凹槽；该第一芯片和该第二芯片中表面面积较小的芯片设置在该容置结构中，该载体与该第一芯片和该第二芯片中表面面积较大的芯片上下对齐堆叠。
采用本申请实施例的方案，能够实现不同大小的芯片堆叠形成安全芯片，适用于更多的应用场景。此外，在实现堆叠芯片结构的同时，还能够在晶圆上尽可能多的制造小面积的芯片，降低单颗芯片的成本，从而降低整体的制造成本。第三，小面积的芯片不是直接在晶圆上，以晶圆级键合方式与大面积的芯片所在的晶圆进行键合，而是单颗的放入载体的容置结构中，可以在对两个芯片进行堆叠前，对两个芯片进行测试以筛选出性能良好的芯片，去除性能较差的芯片，提高整体安全芯片的良率，进一步降低整体的制造成本。
在一种可能的实施方式中，该安全芯片还包括：第一互联层和第二互联层，该第一互联层和该第二互联层设置在该第一芯片和该第二芯片之间；该第一芯片和该第二芯片通过该第一互联层和该第二互联层实现电连接。
在一种可能的实施方式中，该第一互联层的表面面积和该第二互联层的表面面积相等，该第一芯片与该第二芯片之间通过对该第一互联层和该第二互联层进行晶圆级键合形成电连接。
在一种可能的实施方式中，该第一互联层的下表面形成有至少一个第一键合衬垫，该第二互联层的上表面形成有至少一个第二键合衬垫；该至少一个第一键合衬垫和该至少一个第二键合衬垫一一对应，该至少一个第一键合衬垫中的一个第一键合衬垫键合至其对应的一个第二键合衬垫上形成电连 接。
通过本申请实施例的方案，堆叠后的第一芯片和第二芯片之间的电连接装置，即互联层中的键合衬垫隐藏在安全芯片的内部，从外部无法通过该电连接装置读取到第一芯片和第二芯片中的数据以及芯片的相关信息，从而提高了安全芯片的安全性能以及可靠性。
在一种可能的实施方式中，该第一互联层的表面面积和该第二互联层的表面面积均与该第一芯片和该第二芯片中表面面积较大的芯片的表面面积相等。
在一种可能的实施方式中，该第一光阻挡层包括：第一光疏介质层和第一光密介质层；该第一光密介质层连接于该第一光疏介质层；其中，该第一光密介质层用于接收该第一光信号，并将该第一光信号传输至该第一光密介质层与该第一光疏介质层之间的第一界面；该第一界面为粗糙度大于预设阈值的粗糙面，用于将来自外部并朝向该第一芯片中的电路区域照射的第一光信号进行全反射和/或散射以防止该第一光信号进入该第一芯片中的电路区域。
通过第一光密介质层与第一光疏介质层之间的粗糙第一界面，能够全反射和/或散射从第一光密介质层入射的光线，进而能够降低到达第一芯片的光信号的强度，从而达到抗激光攻击的目的。
在一种可能的实施方式中，该第一界面的粗糙度大于20nm。
在一种可能的实施方式中，该第一界面上形成有尖刺状结构或者孔状结构，该尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
在一种可能的实施方式中，该第一光疏介质层连接于该第一芯片的衬底表面。
在一种可能的实施方式中，，该第一界面的形态与该第一芯片的衬底表面的形态基本一致。
在一种可能的实施方式中，该第一界面的粗糙度大于该第一芯片的衬底表面的粗糙度。
在一种可能的实施方式中，该安全芯片还包括：第一中间层；该第一中间层连接于该第一芯片的衬底表面，该第一光疏介质层连接于该第一中间层，该第一光疏介质层与该第一中间层的连接面的形态与该第一界面的形态基本一致。
在一种可能的实施方式中，该第一光疏介质层和该第一光密介质层位于该第一芯片的衬底中，且该第一光疏介质层接近于该第一芯片中的电路区域。
在一种可能的实施方式中，该第一光密介质层的材料为硅，该第一光疏介质层的材料为二氧化硅；或者，该第一光密介质层的材料为金属，该第一光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
在一种可能的实施方式中，该安全芯片还包括：第二光阻挡层，该第二挡光层靠近于该第二芯片中的电路区域，用于将来自外部并朝向该第二芯片中的电路区域照射的第二光信号进行全反射和/或散射以防止该第二光信号进入该第二芯片中的电路区域。
在一种可能的实施方式中，该第二光阻挡层包括：第二光疏介质层和第二光密介质层；该第二光密介质层连接于该第二光疏介质层；其中，该第二光密介质层用于接收该第二光信号，并将该第二光信号传输至该第二光密介质层与该第二光疏介质层之间的第二界面；该第二界面为粗糙度大于预设阈值的粗糙面，用于将来自外部并朝向该第二芯片中的电路区域照射的该第二光信号进行全反射和/或散射以防止该第二光信号进入该第二芯片中的电路区域。
在一种可能的实施方式中，该第二界面的粗糙度大于20nm。
在一种可能的实施方式中，该第二界面上形成有尖刺状结构或者孔状结构，该尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
在一种可能的实施方式中，该第二光疏介质层连接于该第二芯片的衬底表面。
在一种可能的实施方式中，该第二界面的形态与该第二芯片的衬底表面的形态基本一致。
在一种可能的实施方式中，该第二界面的粗糙度大于该第二芯片的衬底表面的粗糙度。
在一种可能的实施方式中，该安全芯片还包括：第二中间层；该第二中间层连接于该第二芯片的衬底表面，该第二光疏介质层连接于该第二中间层，该第二光疏介质层与该第二中间层的连接面的形态与该第二界面的形态基本一致。
在一种可能的实施方式中，该第二光疏介质层和该第二光密介质层位于该第二芯片的衬底中，且该第二光疏介质层接近于该第二芯片中的电路区域。
在一种可能的实施方式中，该第二光密介质层的材料为硅，该第二光疏介质层的材料为二氧化硅；或者，该第二光密介质层的材料为金属，该第二光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
在一种可能的实施方式中，该安全芯片还包括：焊盘；该焊盘位于该安全芯片的一侧，靠近于该第一芯片，与该第一芯片电连接；或者，该焊盘位于该安全芯片的另一侧，靠近于该第二芯片，与该第二芯片电连接。
在一种可能的实施方式中，该第一芯片和该第二芯片分别为逻辑芯片和存储芯片。
第二方面，提供了一种安全芯片的制造方法，包括：制备第一芯片，该第一芯片位于第一晶圆中；制备第二芯片，该第二芯片位于第二晶圆中；采用晶圆级键合工艺键合该第一晶圆和该第二晶圆，以使得该第一芯片和其对应的该第二芯片上下堆叠，且相互电连接，其中，靠近于该第一芯片中的电路区域设置有第一光阻挡层，该第一光阻挡层用于将来自外部并朝向该第一芯片中的电路区域照射的第一光信号进行全反射和/或散射；对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片，该第一安全芯片包括该第一芯片、该第二芯片以及该第一光阻挡层。
在一种可能的实施方式中，该制备第一芯片，包括：在第三晶圆中制备并分割出该第一芯片；在该第一晶圆中制作容置结构，该容置结构为通孔或者凹槽；将该第一芯片固定放置在该容置结构中。
在一种可能的实施方式中，该制备第一芯片，包括：在该第一晶圆中制备该第一芯片。
在一种可能的实施方式中，该制备第二芯片，包括：在第四晶圆中制备并分割出该第二芯片；在该第二晶圆上制作容置结构，该容置结构为通孔或者凹槽；将该第二芯片固定放置在该容置结构中。
在一种可能的实施方式中，该制备第二芯片，包括：在该第二晶圆中制备该第二芯片。
在一种可能的实施方式中，在采用晶圆级键合工艺键合该第一晶圆和该第二晶圆之前，该制造方法还包括：在该第一芯片的上表面制备第一互联层，该第一互联层与该第一芯片电连接；在该第二芯片的上表面制备第二互联层，该第二互联层与该第二芯片电连接。
在一种可能的实施方式中，该采用晶圆级键合工艺键合该第一晶圆和该 第二晶圆，以使得该第一芯片和其对应的该第二芯片上下堆叠，且相互电连接，包括：上下翻转该第一晶圆或者该第二晶圆；采用晶圆级键合工艺键合该第一互联层和该第二互联层，以使得该第一芯片和其对应的该第二芯片上下堆叠，且相互电连接。
在一种可能的实施方式中，该采用晶圆级键合工艺键合该第一互联层和该第二互联层，包括：采用晶圆级键合工艺键合该第一互联层上表面的至少一个第一键合衬垫与该第二互联层下表面的至少一个第二键合衬垫，以形成该第一互联层和该第二互联层的电连接；其中，该至少一个第一键合衬垫和该至少一个第二键合衬垫一一对应。
在一种可能的实施方式中，该采用晶圆级键合工艺键合该第一晶圆和该第二晶圆之后，该制造方法还包括：在该第一晶圆的衬底表面制备该第一光阻挡层。
在一种可能的实施方式中，该在该第一晶圆的衬底表面制备该第一光阻挡层，包括：在该第一晶圆的衬底表面制备第一光疏介质层；在该第一光疏介质层的表面制备第一光密介质层，该第一光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该在该第一晶圆的衬底表面制备第一光疏介质层，包括：对该第一晶圆的衬底表面进行减薄处理，以使得该第一晶圆的衬底表面为粗糙度大于预设阈值的粗糙面；在该第一晶圆的衬底表面制备该第一光疏介质层，该第一光疏介质层的表面的形态与该第一晶圆的衬底表面形态基本一致。
在一种可能的实施方式中，该在该第一晶圆的衬底表面制备第一光疏介质层，包括：在该第一晶圆的衬底表面制备该第一光疏介质层；对该第一光疏介质层的表面进行粗糙处理，以使得该第一光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该在该第一晶圆的衬底表面制备第一光阻挡层，包括：在该第一晶圆的衬底表面制备第一中间层；对该第一中间层的表面进行粗糙处理，以使得该第一中间层的表面为粗糙度大于预设阈值的粗糙面；在该第一中间层的表面制备第一光疏介质层，该第一光疏介质层的表面的形态与该第一中间层的表面形态基本一致。
在一种可能的实施方式中，在该第一晶圆的上方制备第一光疏介质层之 前，该制造方法还包括：对该第一晶圆的衬底表面进行减薄处理。
在一种可能的实施方式中，该对该第一晶圆的衬底表面进行减薄处理，包括：将该第一晶圆的厚度减薄至30μm或以下。
在一种可能的实施方式中，该第一光疏介质层的表面的粗糙度大于20nm。
在一种可能的实施方式中，该第一光疏介质层的表面形成有尖刺状结构或者孔状结构，该尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
在一种可能的实施方式中，该第一光密介质层的材料为硅，该第一光疏介质层的材料为二氧化硅；或者，该第一光密介质层的材料为金属，该第一光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
在一种可能的实施方式中，该制备第一芯片，包括：在该第一晶圆中制备该第一光阻挡层；在该第一光阻挡层上方制备该第一芯片。
在一种可能的实施方式中，该在该第一晶圆中制备该第一光阻挡层，包括：在该第一晶圆中制备第一光疏介质层；该第一光疏介质层的下方对应形成第一光密介质层；该第一光密介质层与该第一光疏介质层之间的第一界面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该第一光密介质层为硅，该第一光疏介质层为埋层氧化硅BOX。
在一种可能的实施方式中，该采用晶圆级键合工艺键合该第一晶圆和该第二晶圆之后，该制造方法还包括：在该第二晶圆的下方制备第二光阻挡层。
在一种可能的实施方式中，该在该第二晶圆的衬底表面制备第二光阻挡层，包括：在该第二晶圆的衬底表面制备第二光疏介质层，在该第二光疏介质层的表面制备第二光密介质层，该第二光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该在该第二晶圆的衬底表面制备第二光疏介质层，包括：对该第二晶圆的衬底表面进行减薄处理，以使得该第二晶圆的衬底表面为粗糙度大于预设阈值的粗糙面；在该第二晶圆的衬底表面制备该第二光疏介质层，该第二光疏介质层的表面的形态与该第二晶圆的衬底表面形态基本一致。
在一种可能的实施方式中，该在该第二晶圆的下方制备第二光疏介质层，包括：在该第二晶圆的衬底表面制备该第二光疏介质层；对该第二光疏介质 层的表面进行粗糙处理，以使得该第二光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该在该第二晶圆的衬底表面制备第二光阻挡层，包括：在该第二晶圆的衬底表面制备第二中间层；对该第二中间层的表面进行粗糙处理，以使得该第二中间层的表面为粗糙度大于预设阈值的粗糙面；在该第二中间层的表面制备该第二光疏介质层，该第二光疏介质层的表面的形态与该第二中间层的表面形态基本一致。
在一种可能的实施方式中，在制备第二光疏介质层之前，该制造方法还包括：对该第二晶圆的衬底表面进行减薄处理。
在一种可能的实施方式中，该对该第二晶圆的衬底表面进行减薄处理，包括：将该第二晶圆的厚度减薄至30μm或以下。
在一种可能的实施方式中，该第二光疏介质层的表面的粗糙度大于20nm。
在一种可能的实施方式中，该第二光疏介质层的表面形成有尖刺状结构或者孔状结构，该尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
在一种可能的实施方式中，该第二光密介质层的材料为硅，该第二光疏介质层的材料为二氧化硅；或者，该第二光密介质层的材料为金属，该第二光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
在一种可能的实施方式中，该在该第一晶圆的上方制备该第一光阻挡层，包括：在该第二光阻挡层的下方设置载片；以该载片为支撑，在该第一晶圆的上方制备该第一光阻挡层。
在一种可能的实施方式中，该制备第二芯片，包括：在该第二晶圆中制备第二光阻挡层；在该第二光阻挡层上方制备该第二芯片。
在一种可能的实施方式中，该在该第二晶圆中制备第二光阻挡层，包括：在该第二晶圆中制备第二光疏介质层；该第二光疏介质层的下方对应形成第二光密介质层；该第二光密介质层与该第二光疏介质层之间的第二界面为粗糙度大于预设阈值的粗糙面。
在一种可能的实施方式中，该第二光密介质层为硅，该第二光疏介质层为埋层氧化硅BOX。
在一种可能的实施方式中，该制造方法还包括：制造焊盘，该焊盘位于该安全芯片的一侧，靠近于该第一芯片，与该第一芯片电连接；或者，该焊 盘位于该安全芯片的另一侧，靠近于该第二芯片，与该第二芯片电连接。
在一种可能的实施方式中，该第一芯片和该第二芯片分别为逻辑芯片和存储芯片。
第三方面，提供了一种安全芯片，包括按照第二方面以及第二方面中任一种可能的实施方式中所述的制造方法制造的安全芯片。
第四方面，提供了一种电子设备，包括第一方面以及第一方面中任一种可能的实施方式中所述的安全芯片。
附图说明
图1是一种基于片上系统架构的安全芯片的示意性结构图。
图2至图5是根据本申请实施例的几种安全芯片的结构示意图。
图6是根据本申请实施例的一种安全芯片的结构示意图，其中示出了安全芯片第一光阻挡层的一种结构示意图。
图7是根据本申请实施例的一种第一光疏介质层的表面结构立体图。
图8是根据本申请实施例的一种第一光疏介质层的截面图。
图9是根据本申请实施例的另一安全芯片的结构示意图，其中示出了第一光阻挡层的另一结构示意图。
图10是根据本申请实施例的另一安全芯片的结构示意图，其中示出了第一光阻挡层的另一结构示意图。
图11至图13是根据本申请实施例的另几种安全芯片的结构示意图。
图14和图15是根据本申请实施例的两种安全芯片的制造方法的示意性流程框图。
图16至图22示出了根据本申请实施例的几种工艺步骤后的第一晶圆和第二晶圆的局部截面图。
图23至图25是根据本申请实施例的另几种安全芯片的制造方法的示意性流程框图。
图26至图31示出了根据本申请实施例的几种工艺步骤后的第一晶圆和第二晶圆的局部截面图。
图32是根据本申请实施例的另一安全芯片的结构示意图。
图33是根据本申请实施例的另一安全芯片的制造方法的示意性流程框图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
本申请实施例适用于制造各种芯片，尤其是可以执行复杂的加密、解密算法的特殊芯片或安全芯片。例如，所述安全芯片可以是与近距离无线通讯(Near Field Communication，NFC)芯片配合的嵌入式安全芯片(embeddedSecurity Element,eSE)、生物芯片(例如指纹传感器芯片)、设置有电路的芯片(例如处理器)、物联网领域各类芯片等等。例如，所述安全芯片可以包括晶体管、电阻、电容和电感等元件及布线的器件或部件，例如，所述安全芯片可以是承载有集成电路(Integrated Circuit，IC)的微型电子器件或部件。本申请对此不做具体限定。
作为一种常见的应用场景，本申请实施例提供的芯片可以应用在智能手机、平板电脑、可穿戴设备、智能家居、智能车载等移动终端中或者服务器、超算设备、安防设备等其它电子设备中。
需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。应理解，附图示出的本申请实施例中的各种部件的厚度、长宽等尺寸，以及集成装置的整体厚度、长宽等尺寸仅为示例性说明，而不应对本申请构成任何限定。
此外，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
图1示出了一种基于片上系统(System On a Chip，SOC)架构的安全芯片100的示意性结构图。
如图1所示，安全芯片100主要包括逻辑模块110和存储模块120，该逻辑模块110和存储模块120均集成在同一个芯片上，可以实现逻辑模块110和存储模块120之间快速、安全的通信。
可选地，上述逻辑模块110可以为中央处理器(Central Processing Unit，CPU)，或者可以为其他逻辑控制和运算的模块，用于控制安全芯片中各元器件的运行以及对数据的运算和处理，将运算后的数据传输至存储模块120中进行存储。该逻辑模块110包括但不限于是微控制器(Microcontroller Unit， MCU)、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件(Programmable Logic Device，PLD)、分立门或者晶体管逻辑器件、分立硬件组件。本申请实施例对此不做任何限定。
可选地，上述存储模块120可以为动态随机存取存储器(Dynamic Random Access Memory，DRAM)电路。应理解，该存储电路还可以为其它类型的存储电路，例如其它随机存储(Random Access Memory，RAM)器电路、只读存储器电路(Read Only Memory，ROM)电路、闪存(Flash)，本申请实施例对此也不做任何限定。
可选地，除了上述逻辑模块110和存储模块120外，如图1所示，安全芯片100还可以包括数据加密引擎(Data Encryption Engine)模块130，该数据加密引擎模块130基于特定的加解密算法对用户数据进行加密和解密，以保证数据的安全性能。加密后的数据以及密钥可以存储，或者缓存至存储模块120中。具体地，该数据加密引擎可以基于现有技术中任意一种加密算法对用户数据进行加解密，本申请对具体的加解密算法同样不做具体限定。
在一些实施方式中，上述数据加密引擎模块130可以与逻辑模块110集成在一起，换言之，集成加密引擎模块130后的逻辑模块可以用于对数据进行加解密处理。
为了获得密钥，若攻击者采用激光故障注入的方式进行攻击，在一些攻击方式中，攻击者使用红外波段的激光，透过芯片背面照射芯片的逻辑模块特定区域。利用激光与硅相互作用生成的光电流，使芯片输出错误结果。最后，攻击者通过采集特定时刻、特定位置发生的具有某种特征的错误，与正确的加密结果进行比较分析，就可以获取密钥，从而破解安全芯片中存储的加密信息。
目前，为了防止激光故障注入的攻击方式获取到密钥和加密信息，在一些情况下，如图1所示，安全芯片100还包括光敏模块140，用于检测照射到安全芯片中的光信号，当光敏模块140检测到激光照射时，光敏模块140发出指令，发出警报或擦除芯片内存储的信息，例如擦除存储模块120中存储的加密信息等等。可选地，该光敏模块130可以为光敏电阻、光敏二极管、光敏三极管等可以将光信号转换为电信号的元器件，本申请实施例对具体的 光敏模块的类型不做具体限定。
应理解，图1仅示例性的示出了安全芯片中的部分功能模块，安全芯片还可以包括其它功能模块和相应的电路结构，例如，安全芯片100还可以包括接口模块，用于形成安全芯片与外设之间的数据输入输出通道。本申请对安全芯片的具体功能组成不做具体限定。
在图1的安全芯片100中，为了解决激光故障注入这种攻击手段造成的安全问题，安全芯片100中加入了光敏模块130，虽然能够提高安全芯片100整体的安全性能，但是，增加光敏模块会增大了整个安全芯片的面积，也会提高整个安全芯片的制造成本。
此外，在图1中的安全芯片100中，逻辑模块110、存储模块120等模块以SOC等形式集成在一颗芯片上，虽然可以实现快速安全通信，但是，不同模块具有不同的电路以及工艺制成要求，在同一颗芯片上集成不同类型的模块，会造成芯片整体的制造成本更高。
基于此，本申请提出了一种安全芯片，在不使用光敏模块的前提下，仍能提高安全芯片的安全等级，防止被激光故障注入攻击，减小安全芯片的面积，且能够降低安全芯片的制造成本。
图2示出了一种安全芯片200的结构示意图。
如图2所示，该安全芯片200包括：第一芯片210，第二芯片220和第一光阻挡层230；
第一芯片210和第二芯片220上下堆叠，并相互电连接；
第一光阻挡层230靠近于第一芯片210中的电路区域211，用于来自外部并朝向第一芯片210中的电路区域211照射的第一光信号进行全反射和/或散射。
在一些实施例中，第二芯片220堆叠于第一芯片210下方，且第一光阻挡层230设置于第一芯片210中的电路区域211上方。该第一光阻挡层230的面积不小于电路区域211的面积。
具体地，作为示例，如图2所示，第一光阻挡层230可以完全覆盖电路区域211。或者在其它情况下，第一光阻挡层230也可以部分覆盖电路区域211，例如，仅覆盖电路区域211中的局部电路区域，该局部电路区域为第一芯片的核心功能电路区域。
在另一些实施例中，第二芯片220也可以堆叠于第一芯片210上方，且 第一光阻挡层230设置于第一芯片210中的电路区域211下方。该实施方式下的具体方案可以参考本申请实施例以及下文相关描述，此处不再赘述。
在本申请实施例中，第一芯片210和第二芯片220为不同类型的芯片，用于实现不同的功能。
例如，第一芯片210可以为逻辑芯片，该逻辑芯片包括对数字信号进行逻辑运算和操作的逻辑电路，具体可以是可编程逻辑器件或者其它处理器芯片，例如图1中的逻辑模块110和数据加密引擎模块130都可以是逻辑芯片，主要用于实现安全芯片200的控制功能以及数据处理等逻辑运算功能。对应的，第二芯片220可以为存储芯片，例如可以包括图1中的存储模块120，主要用于实现加密数据的存储。当然，在第一芯片210也可以为存储芯片，第二芯片220对应的为逻辑芯片。或者，第一芯片210和第二芯片220均为逻辑芯片，或者均为存储芯片。
应理解，本申请实施例中，第一芯片和第二芯片包括但不限于是逻辑芯片或者存储芯片，其还可以为其他任意类型的芯片，用于执行安全芯片中的特定功能，本申请实施例对第一芯片和第二芯片的具体类型不做限定。
在本申请实施例中，第一芯片210和第二芯片220为两个独立形成的芯片结构，再通过三维(Three Dimensional，3D)封装方式上下堆叠，并进行电连接，形成一个安全芯片。
具体地，第一芯片210和第二芯片220可以分别在两片晶圆(Wafer)上制备形成，例如，逻辑晶圆上仅制备逻辑芯片，存储晶圆上仅制备存储芯片，其中，逻辑晶圆制备逻辑芯片的工艺过程可以基于逻辑芯片的结构进行工艺参数的优化，而存储晶圆制备存储芯片的工艺过程可以基于存储芯片的结构进行工艺参数的优化，从而使得逻辑芯片和存储芯片的工艺过程均达到最优。相比于在同一个晶圆上集成制备逻辑芯片和存储芯片，需要综合考虑逻辑芯片和存储芯片的工艺要求，采用本申请实施例的方式，在提高逻辑芯片和存储芯片各自性能的前提下，还能够降低逻辑芯片和存储芯片的工艺制造成本。
在芯片的制造过程中，在晶圆上通过光刻(Photolithography)、离子注入(Ion implantation)、刻蚀(Etch)、沉积(Deposition)、外延(Epitaxy)等等复杂的半导体工艺形成芯片的电路结构。对于原始的晶圆，我们也可以将其称之为衬底(Substrate)，在制造过程中，通过半导体工艺制备的芯片的 电路区域一般形成于衬底的上部以及衬底上方的外延层。为了便于描述，在下文中，我们将芯片中除电路区域以外的区域称为衬底。
可选地，在本申请实施例中，如图2所示，第一芯片210中的电路区域211位于第一芯片210的下部，衬底212位于第一芯片210的上部，且位于第一芯片210的电路区域211的上方。
在一些实施方式中，该第一光阻挡层230可以形成于第一芯片210的衬底212中，在另一些实施方式中，如图2所示，该第一光阻挡层230也可以形成于第一芯片210的衬底212的上方。
具体地，入射至该第一光阻挡层230的至少部分光信号(例如，第一光信号)能够被该第一光阻挡层230全反射和/或散射，以防止该第一光信号进入至第一芯片210中，特别是防止该第一光信号进入第一芯片210的电路区域211中，从而减少乃至消除进入第一芯片210的电路区域211中的光信号，避免形成对安全芯片的激光注入攻击，提高安全芯片的安全性能。
采用本申请实施例的方案，通过分别独立制造两个芯片，并对两个芯片进行堆叠以形成安全芯片，从而减小安全芯片的面积，也降低了安全芯片的制造成本，另外，安全芯片中新增光阻挡层对光信号进行全反射和/或散射，避免在安全芯片中增加光敏模块检测攻击光信号，在提高安全芯片的安全性能的前提下，进一步减小安全芯片200的面积和制造成本。
可选地，上述第一芯片210和第二芯片220的厚度较小，可以为经过衬底减薄处理后的芯片，能够防止攻击者对安全芯片进行拆解，从而提高安全芯片的安全性能。在一些实施例中，第一芯片210和/或第二芯片220的厚度小于一定的阈值，例如，第一芯片210和/或第二芯片220的厚度小于30μm，优选地，第一芯片和第二芯片的厚度均小于10μm。
图3示出了另一种安全芯片200的结构示意图。
如图3所示，第一芯片210的下表面还设置有第一互联层240，第二芯片220的上表面还设置有第二互联层250。第一芯片210和第二芯片220通过该第一互联层240和第二互联层250实现电连接。
具体地，在芯片的制造过程中，在晶圆上形成芯片中的元器件，例如形成场效应管的过程，我们可以称之为前道(Front End Of Line，FEOL)工艺，在此过程中，芯片中元器件组合形成的区域可以理解为芯片中的电路区域，例如上文中第一芯片210中的电路区域211或者下文中第二芯片220中的电 路区域212。
在此之后，需要进行金属布线将元器件连接形成电路结构，然后对晶圆上形成的多个芯片进行切割和封装，形成独立的多个封装芯片，这一过程我们称之为后道(BackEnd Of Line，BEOL)工艺。
在本申请实施例中，第一芯片210下表面的第一互联层240以及第二芯片220上表面的第二互联层250均可以为后道工艺制备形成的用于连接电路各元器件的金属线路层。该第一互联层240与第一芯片210进行电连接，具体地，与第一芯片210中的电路区域211电连接，且第二互联层250与第二芯片220进行电连接，具体地，与第二芯片220中的电路区域221电连接。
可选地，该第一互联层240和该第二互联层250可以包括再布线层(Re-Distribution Layer，RDL)，用于对第一芯片210和第二芯片220的输入输出(Input Output，IO)接口进行重新布局。
具体地，上述互联层，比如第一互联层240包括至少一层金属线路层以及金属线路层之间的绝缘介质层，该金属线路层的材料包括但不限于下列材料的一种或多种：钛(Ti)、铜(Cu)、铝(Al)、钼(Mo)、镍(Ni)、金(Au)、钯(Pd)，或氮化钛(TiN)，氮化钽(TaN)等等。该绝缘层可以包含但不限于是：氧化硅(SiO 2)，氮化硅(SiN)，氮碳化硅(SiCN)，聚酰亚胺(Polyimide，PI)、聚苯并恶唑(Polybenzoxazole，PBO)以及苯并环丁烯(Benzocyclobutene，BCB)中的一种或多种。类似的，第二互联层250也可以用上述材料制成。
可选地，第一互联层240和第二互联层250的表面面积相等，具体地，此处互联层的表面面积是指上表面面积或者下表面面积，且通常来讲，互联层的上表面面积与下表面面积相等。
在此情况下，在本申请实施例中，可以采用晶圆级键合工艺，以晶圆到晶圆(Wafer to Wafer，W2W)的方式将两层晶圆堆叠至一起时，两层晶圆上多个芯片(Die)一一对应，其中上层晶圆上的第一芯片210和下层晶圆上的第二芯片220对应，将上层晶圆上的第一芯片210和第一互联层240，与下层晶圆上的第二芯片220和第二互联层250堆叠至一起，实现堆叠的安全芯片结构。
可选地，如图3所示，在第一互联层240的下表面形成有至少一个第一键合衬垫241，第二互联层250的上表面形成有至少一个第二键合衬垫251，该至少一个第一键合衬垫241和至少一个第二键合衬垫251同样由金属形成， 可以用于传输电信号，该至少一个第一键合衬垫241和至少一个第二键合衬垫251的材料与上述互联层中的金属线路层的材料相同。
具体地，该至少一个第一键合衬垫241和至少一个第二键合衬垫251一一对应，且至少一个第一键合衬垫241中的每个第一键合衬垫可以通过晶圆级键合工艺键合至其对应的一个第二键合衬垫251上形成电连接，从而形成第一互联层240和第二互联层250之间的电连接，再使得第一芯片210和第二芯片220通过这两个互联层产生电连接。
通过本申请实施例的方案，堆叠后的第一芯片210和第二芯片220之间的电连接装置，即互联层中的键合衬垫隐藏在安全芯片200的内部，从外部无法通过该电连接装置读取到第一芯片210和第二芯片220中的数据以及芯片的相关信息，从而提高了安全芯片200的安全性能以及可靠性。
第一芯片210和第二芯片220堆叠连接后形成的安全芯片200与图1中的安全芯片100相比，具有小尺寸、高可靠性、低功耗等众多优点，能够提高安全芯片的整体性能，使其应用到更多、且具有更高要求的应用场景中。
应理解，第一芯片210和第二芯片220除了可以采用晶圆级键合工艺实现芯片堆叠和电连接外，还可以采用芯片与晶圆堆叠(Chip to Wafer，C2W)的键合工艺，或者芯片与芯片堆叠(Chip to Chip，C2C)键合工艺实现芯片的堆叠和电连接，本申请实施例对芯片的具体堆叠方式和电连接方式不做具体限定。
可选地，安全芯片还包括：焊盘，该焊盘用于与其它电子元器件通信连接，传输安全芯片产生的数据信号，或者接收其它器件传输的控制信号等等。可选地，该焊盘可以位于安全芯片的一侧，靠近于第一芯片，与第一芯片电连接；或者，该焊盘也可以位于安全芯片的另一侧，靠近于第二芯片，与第二芯片电连接。
例如，如图3所示，焊盘280设置在第一光阻挡层230的上方，且与第一互联层240中的金属线路层电连接，以与第一芯片210电连接。
具体地，如图3所示，第一互联层240中的金属线路层与第一光阻挡层230的上表面之间形成盲孔，该盲孔的侧壁以及第一光阻挡层230上方形成有绝缘介质层281，焊盘280形成在该绝缘介质层281上方，通过盲孔中的金属结构连接至第一互联层240中的金属线路层。
除了图3中的实施方式以外，该焊盘280还可以设置在第二芯片220的 下方，与第二互联层250中的金属线路层电连接。
应理解，图3仅举例示出了安全芯片的一个焊盘的结构，该安全芯片还可以包含有多个焊盘，用于传输安全芯片的信号。
在一些实施方式中，例如在上述图2和图3的实施例中，第一芯片210的表面面积与第二芯片220的表面面积相等且上下对齐堆叠。此时，第一芯片210的表面面积、第二芯片220的表面面积、第一互联层240的表面面积以及第二互联层250的表面面积相等，且均上下对齐堆叠。
而在更多的实施方式中，第一芯片210的表面面积也可以与第二芯片220的表面面积不相等。
此处需要说明的是，由于芯片为扁平的片状结构，本申请中的芯片的表面面积为芯片的上表面面积或者为下表面面积，且通常而言，芯片的上表面面积与下表面面积近似相等。当然也可以把芯片安装到PCB板的投影面积视为芯片的表面面积。
若第一芯片210和第二芯片220为不同类型的芯片，两者具有各自的电路结构，因而具有各自的工艺要求，两者的表面面积通常不相等。在此情况下，为了更好的实现两个芯片的堆叠和连接，将第一芯片210和第二芯片220中表面面积较小的一个放置在载体中，该载体的表面面积与另一个表面面积较大的芯片的表面面积相等，且该载体与另一个表面面积较大的芯片上下对齐堆叠。
图4示出了另一种安全芯片200的结构示意图。
如图4所示，第一芯片210的表面面积小于第二芯片220的表面面积。该安全芯片200还包括：载体260，该载体260的表面面积与第二芯片220的表面面积相等。
另外，该载体260中设置有容置结构261，该容置结构261为通孔，第一芯片210设置在该容置结构261中。
可选地，如图4所示，第一芯片210与载体260之间还设置有填充层262以将第一芯片210稳定的固定在容置结构261中。该填充层262包括但不限于是高分子有机材料，例如干膜(Dry Film)材料或者其它流动性较好的高分子材料。在本申请实施例中，该填充层262可以为一种可以光刻的干膜材料，在真空及加热的条件下可以无空洞的填充与第一芯片210与容置结构261之间，且采用可以光刻的材料作为填充层，在对凹槽与第一芯片之间的 空隙进行填充固定的同时，还可以便于工艺加工，节省芯片的制造时间。
可选地，容置结构261除了可以为通孔以外，还可以为凹槽，该凹槽形成于载体260的下表面。可选地，该第一芯片210通过胶层设置在凹槽的底部，以将第一芯片210稳定固定于凹槽中，该胶层包括但不限于晶片粘结膜(Die Attach Film，DAF)。
在本申请实施例中，第一互联层240的表面面积大于第一芯片210的表面面积，且与载体260的表面面积相等。第二互联层250的表面面积与第二芯片220的表面面积相等，因此，第二互联层250的表面面积也与载体260的表面面积相等。
图5示出了另一种安全芯片200的结构示意图。
如图5所示，第二芯片220的表面面积小于第一芯片210的表面面积。第二芯片220设置在载体260中的容置结构261中。
如图5所示，载体260中的容置结构261为凹槽，该凹槽形成在载体260的上表面，第二芯片220通过胶层263和/或填充层262固定在容置结构261中，该胶层263包括但不限于是DAF。此外，与图4类似，在本申请实施例中，容置结构261也可以为通孔。
在本申请实施例中，第二互联层250的表面面积大于第二芯片220的表面面积，且与载体260的表面面积相等。第一互联层240的表面面积与第一芯片210的表面面积相等，因此，第一互联层240的表面面积也与载体260的表面面积相等。
在图4和图5的实施例中，通过将表面面积较小的芯片设置在载体中，实现两个不同大小的芯片之间的堆叠，此外，在第一芯片210和第二芯片220的表面分别形成第一互联层240和第二互联层250，通过第一互联层240和第二互联层250之间的键合，实现第一芯片210和第二芯片220的电连接。采用本申请实施例的方案，能够实现不同大小的芯片堆叠形成安全芯片，适用于更多的应用场景。
在本申请实施例中，通过载体中的容置结构为小面积的芯片提供支撑和稳定，实现将大面积的芯片与小面积的芯片堆叠在一起，从而可以在实现堆叠芯片结构的同时，还能够在晶圆上尽可能多的制造小面积的芯片，降低单颗芯片的成本，从而降低整体的制造成本。此外，小面积的芯片不是直接在晶圆上，以晶圆级键合方式与大面积的芯片所在的晶圆进行键合，而是单颗 的放入载体的容置结构中，可以在对两个芯片进行堆叠前，对两个芯片进行测试以筛选出性能良好的芯片，去除性能较差的芯片，提高整体安全芯片的良率，进一步降低整体的制造成本。可以理解，实施例虽然描述了一大一小两颗芯片的堆叠，但一颗大芯片与更多小芯片的堆叠也是可以的。
在图4和图5的实施例中，载体260包括但不限于是硅、玻璃、陶瓷、等晶圆材料，本申请实施例对具体的载体材料不做具体限定。
应理解，上述图4和图5中，第一芯片210和第二芯片220中一个芯片设置在载体中，另一个芯片直接形成于衬底中，除此之外，该第一芯片210和第二芯片220还可以均设置在载体中，再通过互联层进行堆叠和电连接，该情况下的安全芯片的具体结构可以参见以上相关描述，此处不再赘述。
上文结合图2至图5说明了安全芯片中两个芯片的堆叠结构，下文结合图6至图10说明安全芯片中第一光阻挡层的结构。
图6示出了另一种安全芯片200的结构示意图。
如图6所示，第一光阻挡层230由第一光密介质层231和第一光疏介质层232形成，且第一光疏介质层232连接第一光密介质层231和第一芯片210，或者说第一光疏介质层232介于第一光密介质层231和第一芯片210之间。其中，第一光密介质层231为光接收层，用于接收光信号并将光信号传输至第一光密介质层231与第一光疏介质层232之间的形成的第一界面。
此处需要说明的是，在本申请实施例中，第一光密介质层231为相对于第一光疏介质层232而言的光密介质，换言之，第一光疏介质层232为相对于第一光密介质层231而言的光疏介质，本申请实施例中的光疏介质层和光疏介质层不是绝对概念，而是彼此相互关联的相对概念。在本申请实施例中，第一光密介质层的折射率大于第一光疏介质层232的折射率，但本申请实施例对第一光疏介质层232和第一光密介质层231的折射率的具体取值不做具体限定。
在一种实施方式中，如图6所示，第一光密介质层231和第一光疏介质层232之间的第一界面为粗糙界面，微观上来讲，该粗糙界面由多个不同方向的小平面组成，同一方向的光信号入射到该粗糙界面上时，不同方向的小平面接收的光信号的入射角不同。
针对相对第一光密介质层231的上表面以垂直方向射入的垂直光线，第一光密介质层231和所述第一光疏介质层232的第一界面的粗糙度大于或等 于预设阈值时，能够使得垂直光线到达该第一界面时，增大其入射角，进而使得其入射角大于临界角，以满足发生全反射的条件；通过全反射进入第一光密介质层231的垂直光线，能够有效降低进入所述第一光疏介质层232中的折射光的强度，使得绝大部分光线无法到达安全芯片的第一芯片中，从而达到抗激光攻击的目的。
针对相对第一光密介质层231的下表面以倾斜方向射入的倾斜光线，第一光密介质层231和所述第一光疏介质层232的第一界面的粗糙度大于或等于预设阈值时，能够减小第一光疏介质层232对倾斜光线的受光面积，进而降低了进入第一光疏介质层232中的折射光的光量，从而达到抗激光攻击的目的。此外，与垂直光线在第一光密介质层231中的传播路径相比，倾斜光线在第一光密介质层231中的传播路径较长，进一步增大了倾斜光线到达第一光密介质层231和第一光疏介质层232过程中的损耗，进一步降低了进入第一光疏介质层232中的光线的强度并保障了安全芯片的安全性。
此外，不管第一光密介质层231和第一光疏介质层232的交界面与入射光线垂直还是不垂直，粗糙度大于预设阈值的第一界面，均可以对其进行散射，使得激光无法聚集到特定区域，进一步降低进入第一光疏介质层232中的折射光的强度。
综上所述，通过粗糙的第一光密介质层231和第一光疏介质层232之间的第一界面，能够全反射或散射从第一光密介质层231入射的光线(例如第一光信号)，进而能够降低到达第一芯片，尤其是到达第一芯片中的电路区域的光线强度，从而达到抗激光攻击的目的。
在一些实施方式中，第一界面的粗糙度大于20nm。
作为示例，第一光密介质层231和第一光疏介质层232之间的第一界面可以形成有周期性或者随机分布的尖刺状结构或者孔状结构，或者其他任意呈现高低起伏形态的结构。其中该尖刺状结构有利于增大垂直于第一光密介质层231的入射光线的入射角，进而使其发生全反射，孔状结构有利于对入射光线进行散射。
可选地，图7示出了第一光疏介质层232的一种表面结构图，如图7所示，上述尖刺状结构可以由尺寸不规则的金字塔形凸起或倒金字塔形凹坑形成。图8为该尖刺结构的一种截面示意图，如图8所示，该金字塔形凸起的斜面和芯片所在平面形成有54.7度的夹角。当然，该尖刺状结构也可以由规 则的金字塔形凸起或倒金字塔形凹坑形成，该金字塔形凸起的斜面和芯片所在平面的夹角的角度也可以是其它数值，例如60度，本申请对此不做具体限制。该金字塔形凸起在横剖面上可以为规则或不规则的锯齿结构。
可选地，上述第一光密介质层231的材料为硅(Si)，第一光疏介质层232的材料为二氧化硅(SiO 2)；或者，第一光密介质层231的材料为金属，第二光疏介质层232的材料为氮化硅(SiN)、氧氮化硅(SiON)、碳氮化硅(SiCN)中的任意一种。
在本申请实施例中，通过构造第一光密介质层231和第一光疏介质层232之间的第一界面为粗糙度大于预设阈值的粗糙面，能够使得入射至第一光密介质231中的大部分光信号乃至全部光信号均被反射，进而能够降低或者消除到达第一芯片的光线强度，从而达到抗激光攻击的目的。
另外，通过在第一芯片210上方设置该第一光密介质层231和第一光疏介质层232，不仅能够保证在不占用额外的芯片面积的情况下防止激光攻击，而且工艺流程相对简单，不影响芯片的加工方式，便于量产。
可选地，第一光疏介质层232可以连接于第一芯片210的衬底表面。
例如，在图6所示的安全芯片200中，第一光疏介质层232直接设置在第一芯片210的衬底上表面，其中，第一芯片210的衬底上表面为粗糙度大于预设阈值的粗糙面，该粗糙面的形态与上述第一光密介质层231和第一光疏介质层232之间的第一界面的形态基本一致，其也可以形成有尖刺状结构或者孔状结构。在本申请实施例中，在第一芯片210的衬底上表面生长的第一光疏介质层232的厚度较小，因此，使得该第一光疏介质层231的上表面与第一芯片210的衬底的上表面形态相近，均为粗糙平面。
图9示出了另一种安全芯片200的结构示意图。
如图9所示，在该安全芯片200中，第一光疏介质层232也是直接设置在第一芯片210的衬底上表面，其中，第一芯片210的衬底的上表面与第一光疏介质层232的上表面形态不一致，且第一光疏介质层232的上表面的粗糙度大于第一芯片210的衬底的上表面的粗糙度，即第一光密介质层231和第一光疏介质层232之间的第一界面的粗糙度大于第一芯片210的衬底的上表面的粗糙度。
可选地，第一光疏介质层232也可以通过中间层连接于第一芯片210的衬底表面。
图10示出了另一种安全芯片200的结构示意图。
如图10所示，在该安全芯片200中，第一芯片210的衬底上表面还设置有第一中间层233，第一光疏介质层232设置在第一中间层233的上表面，该第一中间层233的上表面为粗糙面，与图6中的第一光疏介质层的结构近似，在本申请实施例中，第一光疏介质层232的厚度较小，其上表面和下表面的形态基本一致，也可以说，第一光密介质层231和第一光疏介质层232之间的第一界面的形态与第一中间层233的上表面的形态基本一致，均为粗糙平面。
上述第一中间层233的材料包括但不限于是硅材料，例如，可以为多晶硅，微晶硅或者不定型硅等等，该第一中间层233的材料可以与第一芯片210的衬底材料相同或者不相同，该第一中间层233旨在可以形成粗糙表面，以使得其上方第一光疏介质层也形成粗糙界面即可，本申请实施例对第一中间层的材料不做具体限定。
上述图6至图10说明了几种第一光阻挡层230的示意性结构，在上述实施例中，第一光阻挡层230形成在第一芯片210的衬底的上方，该第一光阻挡层230可以在芯片的后道工艺中实现，因而该第一光阻挡层230的制备过程不影响第一芯片210的前道工艺的制造过程，因而不会对第一芯片210的主要制造过程造成影响，使得第一芯片210的设计更为灵活，从而可以让安全芯片200可以应用于更多的场景中。
除此之外，第一光阻挡层230也可以直接形成于第一芯片210的衬底中，即在第一芯片210的前道工艺中进行制备。
具体地，在一些实施方式中，该第一芯片210的衬底为绝缘衬底上的硅(Silicon On Insulator，SOI)结构，该第一芯片210的衬底包括顶部硅层、埋层氧化硅层(Buried Oxide Layer，BOX)以及底部硅层，其中，顶部硅层用于制备形成第一芯片210的电路区域211，该埋层氧化硅层用于制备第一光阻挡层230中的第一光疏介质层232，该底部硅层用于制备第一光密介质层231。在本申请实施例中，第一光阻挡层230的结构与图6中的第一光阻挡层的结构相同，两者之间的差异点主要在于制备工艺的不同。
在上文的实施例中，第一芯片的电路区域附近设置了第一光阻挡层，可以防止第一光信号进入到第一芯片的电路区域中。在此基础上，还可以在第二芯片的电路区域附近设置第二光阻挡层，防止第二光信号进入到第二芯片 的电路区域中。
图11示出了另一种安全芯片200的结构示意图。
如图11所示，该安全芯片200还包括：第二光阻挡层270，该第二挡光层270靠近于第二芯片220中的电路区域221，用于对第二光信号进行全反射和/或散射以防止第二光信号进入第二芯片220中的电路区域221。
可选地，该第二光阻挡层270可以包括第二光疏介质层272和第二光密介质层271。该第二光密介质层271连接于在第二光疏介质层272下，且第二光密介质层271与第二光疏介质层272之间的第二界面为粗糙度大于预设阈值的粗糙面。在一些实施方式中，第二界面的粗糙度大于20nm。
可选地，该第二界面上形成有尖刺状结构或者孔状结构；所述尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
具体地，第二光疏介质层272和第二光密介质层271的结构可以参考上文中第一光疏介质层232和第一光密介质层231的相关描述，此处不再赘述。
与图6至图10中的第一光阻挡层230类似，第二光阻挡层270对称的形成于第二芯片220的下方。
可选地，第二光疏介质层272连接于第二芯片220的衬底表面。
例如，如图11所示，该第二光疏介质层272设置在所述第二芯片220的衬底下表面。其中，第二芯片220的衬底下表面为粗糙度大于预设阈值的粗糙面，该粗糙面的形态与上述第二光密介质层271和第二光疏介质层272之间的第二界面的形态基本一致，其也可以形成有可以形成有尖刺状结构或者孔状结构。在本申请实施例中，第二光疏介质层272厚度较小，其上表面和下表面为形态基本一致的粗糙平面。
又例如，可参考图9中第一光阻挡层230的结构，并如图12所示，第二光疏介质层272也是直接设置在第二芯片220的衬底下表面，其中，第二芯片220的衬底的下表面与第二光疏介质层272的下表面形态不一致，且第二光疏介质层272的上表面的粗糙度大于第二芯片220的衬底的下表面的粗糙度，即第二光密介质层271和第二光疏介质层272之间的第二界面的粗糙度大于第二芯片220的衬底的下表面的粗糙度。
可选地，第二光疏介质层272也可以通过中间层连接于第二芯片220的衬底表面。
例如，可参考图10中的第一光阻挡层230的结构，并如图13所示，第 二芯片220的衬底下表面还设置有第二中间层273，第二光疏介质层272设置在该第二中间层273的下表面，该第二中间层273的下表面为粗糙面，与图11中的第二光疏介质层的结构近似，在本申请实施例中，第二光疏介质层272的厚度较小，其上表面和下表面的形态基本一致，也可以说，第二光密介质层271和第二光疏介质层272之间的第二界面的形态与第二中间层273的下表面的形态基本一致，均为粗糙平面。
与第一中间层类似，上述第二中间层273的材料包括但不限于是硅材料，例如，可以为多晶硅，微晶硅或者不定型硅等等，该第二中间层273的材料可以与第二芯片220的衬底材料相同或者不相同，该第二中间层273旨在可以形成粗糙表面，以使得其下方第二光疏介质层也形成粗糙界面即可，本申请实施例对第二中间层的材料不做具体限定。
可选地，上述第二光密介质层271的材料为硅(Si)，第二光疏介质层272的材料为二氧化硅(SiO 2)；或者，第一光密介质层231的材料为金属，第二光疏介质层232的材料为氮化硅(SiN)、氧氮化硅(SiON)、碳氮化硅(SiCN)中的任意一种。
在图11至图13中，焊盘280设置在第一光阻挡层230的上方，连接至第一互联层240，可选地，在本申请实施例中，焊盘280还可以设置在第二光阻挡层230的下方，例如图11至图13中，第二光密介质层271的下方，连接至第二互联层250。
应理解，在本申请中，光阻挡层(第一光阻挡层和第二光阻挡层)的实现方式中，除了上述采用光密介质层(第一光密介质层和第二光密介质层)和光疏介质层(第一光疏介质层和第二光疏介质层)形成粗糙界面以对光信号进行全反射和/或散射外，还可以采用其它方式形成光反射或者散射条件，例如，该光阻挡层为一种高反射薄膜，其可以为金属材料或者也可以为全电介质材料。本申请实施例对具体的光阻挡层的结构不做具体限定。
还应理解，除了光阻挡层可以实现避免或者减少光信号进入到芯片外，还可以采用光吸收层等其它技术手段，例如，在芯片上方设置光吸收薄膜等等。
通过本申请实施例的方案，对两个芯片均进行激光故障注入的防护，进一步增强了安全芯片的安全性能。
另外，在本申请实施例中，若光阻挡层采用光疏介质层与光密介质层的 结构实现，可以通过在半导体芯片上直接制备两个介质层上制备，不仅能够保证在不占用额外的芯片面积的情况下防止激光攻击，而且工艺流程相对简单，不影响芯片的加工方式，便于量产且制造成本较低。
应理解，本文中，上述图2至图13仅为安全芯片的示例性说明，在另一些实施例中，可以理解为将图2至图13中的安全芯片在空间上进行旋转，或者结构上对称设置等等，都属于本申请的保护范围之内，具体的方案可以参照上文的描述，本文不再赘述。
上文结合图2至图13，详细描述了本申请的安全芯片的装置实施例，下文结合图14至图33，详细描述本申请的安全芯片的制造方法的实施例，应理解，装置实施例与方法实施例相互对应，类似的描述可以参照装置实施例。
图14为一种安全芯片的制造方法的示意性流程框图。
如图14所示，该安全芯片的制造方法20可以包括以下步骤。
S210：制备第一芯片，该第一芯片位于第一晶圆中。
S220：制备第二芯片，该第二芯片位于第二晶圆中。
可选地，该第一晶圆和第二晶圆的材料、结构等物理参数可以相同。第一晶圆上制备的芯片数量和第二晶圆上制备的芯片数量相等。
在本申请实施例中，第一芯片和第二芯片为不同类型等芯片，用于实现不同的功能。
在一些实施方式中，第一芯片和第二芯片分别为逻辑芯片和存储芯片，该第一芯片和第二芯片的相关技术特征可以参见上述装置实施例中第一芯片210和第二芯片220的相关描述，此处不再赘述。
S230：采用晶圆级键合工艺键合第一晶圆和第二晶圆，以使得第一芯片和其对应的第二芯片上下堆叠，且相互电连接。
例如，采用晶圆级键合工艺将第一晶圆堆叠于第二晶圆上方，以使得第一芯片对应堆叠于第二芯片的上方，且与第二芯片电连接。
具体地，第一晶圆和第二晶圆的尺寸相同，第一晶圆和第二晶圆堆叠后，第一晶圆中的每个芯片与第二晶圆中的每个芯片一一对应，对应的两个芯片的中心在垂直方向上重合。
具体地，第一晶圆中的第一芯片与第二晶圆中的第二芯片对应，第一芯片和第二芯片的中心在垂直方向上重合，且第一芯片和第二芯片相互电连接。
S240：在第一晶圆的衬底表面制备第一光阻挡层，该第一光阻挡层用于 对第一光信号进行全反射和/或散射以防止该第一光信号进入第一芯片中的电路区域。
对第一晶圆和第二晶圆进行堆叠之后，若第一晶圆位于第二晶圆上方，则在第一晶圆的上表面制备第一光阻挡层，将从安全芯片上方入射至第一光阻挡层的至少部分光信号(例如第一光信号)进行全反射和/或散射，防止该第一光信号进入至芯片中形成激光故障攻击。在本实施例中，第一晶圆、第二晶圆可以为硅晶圆或者其他半导体材料晶圆。
类似地，对第一晶圆和第二晶圆进行堆叠之后，若第二晶圆位于第二晶圆下方，则在第一晶圆的下表面制备第一光阻挡层，将从安全芯片下方入射至第一光阻挡层的第一光信号进行全反射和/或散射。在一些实施方式中，在第一晶圆的衬底表面制备第一光阻挡层，换句话说，若第一晶圆堆叠于第二晶圆上方，第一晶圆的衬底表面为第一晶圆的上表面，若第一晶圆堆叠于第二晶圆下方，第一晶圆的衬底表面为第一晶圆的下表面。在第一晶圆中，相对于衬底表面，另一面形成有第一芯片的电路结构，该面为键合面。
此处需要说明的是，在制备过程中，可以在第一晶圆的衬底表面整面覆盖制备光阻挡层，其中，该光阻挡层中，对应于第一芯片的局部区域我们称之为第一光阻挡层。
应当理解的是，第一晶圆中除了第一芯片外的其他芯片同样对应设置有与该第一光阻挡层结构相同的光阻挡层。
S250：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片，该第一安全芯片包括第一芯片、第二芯片以及第一光阻挡层。
采用切割工艺，沿切割道对堆叠后的第一晶圆和第二晶圆进行切割，得到多个堆叠式的安全芯片，其中，每个安全芯片的结构相同，每个安全芯片均包括光阻挡层防止激光注入攻击。
本步骤中制造得到的第一安全芯片可以为上述图2的装置实施例中的安全芯片200。
图15为另一种安全芯片的制造方法的示意性流程框图。
如图15所示，该安全芯片的制造方法30可以包括以下步骤。
S311：在第一晶圆中制备第一芯片。
本步骤为上述步骤S210的一种实现方式。
具体地，采用半导体制造工艺，在第一晶圆中制备第一芯片阵列，该第 一芯片阵列中每个芯片的结构相同，本步骤中的第一芯片为该第一芯片阵列中的一个芯片。
具体地，可以通过光刻、离子注入、刻蚀、沉积、外延等半导体工艺在第一晶圆中制备第一芯片阵列中每个芯片的电路结构，例如，制备场效应晶体管等等。
S320：在第一晶圆上方制备第一互联层。
本步骤和下述步骤S340、步骤S350为上述步骤S230中一种实现方式。
可选地，可以采用半导体工艺制程中的后道工艺在第一晶圆上制备形成第一芯片的第一互联层，该第一互联层中包括金属线路层和绝缘介质层，该第一互联层中的金属线路层与第一芯片进行电连接。
可选地，该第一互联层可以包括再布线层，用于对第一芯片的输入输出接口进行重新布局。
可选地，在第一互联层的上表面形成有至少一个第一键合衬垫，该至少一个第一键合衬垫由金属形成，可以用于传输第一芯片的电信号。
在本申请实施例中，该第一互联层可以参考上述装置实施例中第一互联层240的相关描述，此处不再赘述。
进一步地，在制备第一互联层之后，还可以对该第一互联层的上表面进行平坦化处理，以形成平坦度和粗糙度均满足一定阈值要求的光滑平面。例如，对该第一互联层的上表面进行抛光处理，该抛光处理包括但不限于：化学机械抛光(Chemical Mechanical Planarization，CMP)工艺的处理。
图16示出了该步骤之后的部分第一晶圆截面图。如图16所示，第一晶圆201中形成有第一芯片210的电路区域211，第一互联层240形成在第一芯片的上表面，该第一互联层240中包括金属线路层，并且该第一互联层240的表面形成有至少一个第一键合衬垫241。
S331：在第二晶圆中制备第二芯片。
本步骤为上述步骤S220的一种实现方式。
类似地，采用半导体制造工艺，在第二晶圆中制备第二芯片阵列，该第二芯片阵列中每个芯片的结构相同，本步骤中第二芯片为该第二芯片阵列中的一个芯片。
在本申请实施例中，第一晶圆中的每个芯片与第二晶圆中的每个芯片一一对应，对应的两个芯片的表面面积相等，两个芯片在垂直方向上重合。
具体地，第一晶圆中的第一芯片与第二晶圆中的第二芯片对应，第一芯片和第二芯片在垂直方向上重合，且第一芯片和第二芯片相互电连接。
S340：在第二芯片上方制备第二互联层。
与步骤S320类似地，可以采用半导体工艺制程中的后道工艺在第二晶圆上制备形成第二芯片的第二互联层，该第二互联层中包括金属线路层和绝缘介质层，该第二互联层中的金属线路层与第二芯片进行电连接。
可选地，该第二互联层可以包括再布线层，用于对第二芯片的输入输出接口进行重新布局。
可选地，在第二互联层的上表面形成有至少一个第二键合衬垫，该至少一个第二键合衬垫由金属形成，可以用于传输第二芯片的电信号。
在本申请实施例中，该第二互联层可以参考上述装置实施例中第二互联层250的相关描述，此处不再赘述。
进一步地，在制备第二互联层之后，也可以对该第二互联层的上表面进行平坦化处理，以形成平坦度和粗糙度均满足一定阈值要求的光滑平面。
图17示出了该步骤之后的部分第二晶圆截面图。如图17所示，第二晶圆202中形成有第二芯片220的电路区域221，第二互联层250形成在第二芯片的上表面，该第二互联层250中包括金属线路层，并且该第二互联层250的表面形成有至少一个第二键合衬垫251。
S350：上下翻转第一晶圆，采用晶圆级键合工艺键合第一互联层和第二互联层，以使得第一芯片对应堆叠于第二芯片的上方，且与第二芯片电连接。
上下翻转第一晶圆后，第一互联层的位置变换至第一晶圆的下方，且第一互联层中的至少一个第一键合衬垫的位置变换至第一互联层的下表面。
采用晶圆级键合工艺键合第一互联层的下表面和第二互联层的上表面，在键合过程中，第一互联层中的至少一个第一键合衬垫与第二互联层中的至少一个第二键合衬垫一一对应，并且相互键合形成电连接，从而形成第一互联层和第二互联层之间的电连接，进而形成第一芯片和第二芯片之间的电连接。
由于在上述步骤S320和步骤S340中，形成的第一互联层的上表面(翻转后为第一互联层的下表面)和第二互联层的上表面均为平坦度以及粗糙度均满足一定的阈值要求的光滑、平整的平面，有利于进行第一互联层和第二互联层的晶圆级键合。
在本申请实施例中，可以采用多种不同的键合工艺对第一互联层和第二互联层进行键合。例如，可以采用混合键合(Hybrid Bonding)工艺键合第一互联层和第二互联层。所谓混合键合，即在晶圆堆叠键合时，需要电学连接的地方，即本申请实施中至少一个第一键合衬垫和至少一个第二键合衬垫之间的连接采用金属键合完成，而其他地方，即本申请实施例中除键合衬垫以外的绝缘介质层，则采用介质键合提供机械支撑。介质的选择需要考虑的主要因素是能够与金属键合时的温度和表面处理工艺兼容，目前，聚合物粘合剂和氧化硅均可作为混合键合的介质。
可选地，除了采用混合键合方式外，该第一互联层与第二互联层的键合还可以采用其他的晶圆级键合方法，例如各类直接键合工艺，包括但不限于：阳极键合(Anodic Bonding)、表面活化键合(Surface Activated Bonding，SAB)等等，还有各类通过中间层的间接键合工艺，包括但不限于：瞬态液相(Transient Liquid Phase，TLP)键合、热压键合(Thermal Compression Bonding)、粘接键合(Adhesive Bonding)等方法，本申请实施例对此不做具体限定。
图18示出了该步骤之后的键合的第一晶圆和第二晶圆的局部截面图。如图18所示，第一晶圆201中的第一芯片210通过第一互联层240和第二互联层250堆叠于第二晶圆202中的第二芯片220上方，且第一互联层240中的至少一个第一键合衬垫241与第二互联层250中的至少一个第二键合衬垫251对应连接。
S360：对第一晶圆的上表面进行减薄处理。
具体地，经过上下翻转后，第一晶圆的上表面为衬底材料，可以采用机械减薄、化学减薄、化学抛光等方法对第一晶圆的上表面进行减薄，例如，可以采用磨轮对第一晶圆的上表面进行研磨。本申请实施例对具体的减薄方法不做任何限定。在对第一晶圆进行减薄的过程中，其下方的第二晶圆可以起到支撑的作用。
减薄后的第一晶圆的厚度小于一定的阈值，例如，小于30μm，优选地，减薄后的第一晶圆的厚度小于10μm。
可选地，减薄后的第一晶圆中第一芯片的电路区域靠近于第一芯片的上表面，但不暴露于上表面中，以防止外界环境对第一芯片的电路区域造成影响，从而影响第一芯片的性能。
采用本申请实施例的方法，可以减小安全芯片的整体厚度，从而可以防止攻击者对安全芯片的拆解，提高安全芯片的安全性能。
具体地，图19示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图19所示，第一芯片210中的电路区域211接近于第一晶圆201的上表面，第一晶圆201的上表面为粗糙平面。
S370：在第一晶圆的上方制备第一光疏介质层，在第一光疏介质层上表面制备第一光密介质层。
本步骤可以为上述制造方法20中步骤S240的一种实施方式。其中，步骤S240中的第一光阻挡层可以包括本步骤中的第一光疏介质层和第一光密介质层。当然，步骤S240中的第一光阻挡层还可以为其他用于反射光信号的膜层或者结构，本申请实施例对此不做限定。
具体的，在本步骤中，可以有以下三种实施方式。
S371：在第一晶圆的上表面制备第一光疏介质层，在第一光疏介质层上表面制备第一光密介质层。
具体地，在步骤S360中，采用机械减薄或者化学减薄等方法对第一晶圆的上表面进行减薄后，第一晶圆的上表面可以形成粗糙度大于一定预设阈值的粗糙面，该粗糙面可以形成有周期性或者随机分布的尖刺状结构或者孔状结构，或者其他任意呈现高低起伏形态的结构。在该粗糙面上直接制备厚度较小的第一光疏介质层，使得该第一光疏介质层的上表面形态与该粗糙面的形态保持相同或者近似，或者说，制备第一光疏介质层后，第一光疏介质层的上下表面均为粗糙度大于预设阈值的粗糙面。
在该第一光疏介质层的上表面继续制备第一光密介质层，因此，第一光疏介质层和第一光密介质层之间的第一界面同样为粗糙度大于预设阈值的粗糙面，从而可以形成对入射的光信号进行全反射和/或散射的条件，增大光信号的反射强度和散射强度，大大减小光信号的透射强度，从而减小乃至消除进入至第一芯片中的光信号，避免激光注入攻击。
此外，在制备第一光密介质层后，可以对第一光密介质层的上表面进行平坦化处理，形成相对光滑的平面。或者制备厚度较厚的第一光密介质层，也能够使得该第一光密介质层的上表面呈现相对光滑的平面。
上述制备第一光疏介质层和第一光密介质的方法包括但不限于化学气相沉积(Physical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor  Deposition，PVD)、脉冲激光沉积(Pulse Laser Deposition，PLD)、原子层沉积(Atomic Layer Deposition，ALD)等等，本申请实施例对具体的第一光疏介质层和第二光疏介质层的制备方法不做具体限定。
可选地，在本步骤中，在第一晶圆的上表面制备第一光疏介质层之前，还可以进一步对第一晶圆的上表面进行粗糙处理，例如，可以采用研磨和/或湿法腐蚀对第一晶圆的上表面进行处理，以加强第一晶圆的上表面的粗糙程度。
例如，可以在经过减薄后的第一晶圆的上表面涂覆腐蚀剂，然后进行加热，其中，该腐蚀剂包括但不限于：氢氧化钠NaOH溶液、氢氧化钾KOH溶液、四甲基氢氧化铵TMAH溶液、硅酸钠Na 2SiO 3溶液。所述腐蚀剂的浓度大于或等于预设阈值，例如8wt％。具体地，可以将腐蚀剂加热至80摄氏度或以上，并腐蚀25分钟或以上。
具体地，图20示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图20所示，第一晶圆201的粗糙上表面上形成有第一光疏介质层232，该第一光疏介质层232的上下表面均为粗糙平面，该第一光疏介质层232的上方还形成有第一光密介质层231，第一光密介质层231的上表面为光滑平面。
S372：在第一晶圆的上表面制备第一光疏介质层，对第一光疏介质层进行粗糙处理，在第一光疏介质层的上表面制备第一光密介质层。
具体地，本步骤中制备第一光疏介质层的制备方法以及对第一光疏介质层的上表面进行粗糙处理的方法也可以参考步骤S371中的制备方法和粗糙处理方法，例如，采用沉积方法制备第一光疏介质层，且利用喷砂或氢氟酸湿法腐蚀工艺对第一光疏介质层进行粗糙处理，使得第一光疏介质层的上表面形成粗糙面。
本步骤与步骤S371的区别在于，步骤S371中第一光疏介质层的厚度较小，其上表面形态依附于第一芯片的上表面形态，而本步骤中，对第一光疏介质层的厚度无要求，直接对第一光疏介质层的上表面进行粗糙处理。步骤S371能够简化整体的工艺流程，但工艺要求较高，而步骤S373则对工艺要求较低。
另外，若通过本步骤制备形成第一光阻挡层，也可以不需要进行上述步骤S360，直接在第一芯片的衬底上制备第一光疏介质层。
具体地，图21示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图21所示，第一晶圆201的上表面上形成有第一光疏介质层232，该第一光疏介质层232的上下表面均为粗糙平面，但粗糙面的形态不一致，该第一光疏介质层232的上方还形成有第一光密介质层231，第一光密介质层231的上表面为光滑平面。
S373：在第一晶圆的上表面制备第一中间层，对第一中间层的上表面进行粗糙处理，在第一中间层的上表面制备第一光疏介质层，并在第一光疏介质层的上表面制备第一光密介质层。
具体地，本步骤中制备第一中间层的制备方法以及对第一中间层的上表面进行粗糙处理的方法可以参考步骤S371中的制备方法和粗糙处理方法，例如，采用沉积的方法制备第一中间层，并采用腐蚀液和/或研磨的方式对第一中间层的上表面进行腐蚀，使得第一中间层的上表面形成粗糙度大于预设阈值的粗糙平面。
在该第一中间层上表面制备第一光疏介质层，并在第一光疏介质层的上表面制备第一光密介质层的过程与上述步骤S371中的过程近似，其中，第一光疏介质层的厚度较小，其上下表面均为粗糙平面，第一光密介质层的上表面为光滑平面。
在一些实施方式中，第一中间层可以为硅材料，包括但不限于是多晶硅、微晶硅或者不定形硅。
此外，在本申请实施例中，该第一中间层的相关特征可以参见以上装置实施例中的第一中间层233，此处不再赘述。
另外，若通过本步骤制备形成第一光阻挡层，可以不需要进行上述步骤S360，直接在第一芯片的衬底上制备第一中间层。
具体地，图22示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图22所示，第一晶圆201的上表面上形成有第一中间层233，该第一中间层233的上表面为粗糙平面，且该第一中间层233的上表面形成有第一光疏介质层232，该第一光疏介质层232的上下表面均为粗糙平面，该第一光疏介质层232的上方还形成有第一光密介质层231，第一光密介质层231的上表面为光滑平面。
在上述步骤S370中，在一些实施方式中，上述第一光密介质层的材料为硅(Si)，第一光疏介质层的材料为二氧化硅(SiO 2)；或者，在另一些实 施方式中，第一光密介质层的材料为金属，第二光疏介质层的材料为氮化硅(SiN)、氧氮化硅(SiON)、碳氮化硅(SiCN)中的任意一种，本申请实施例对第一光密介质层和第一光疏介质层的具体材料不做限定。
此外，在上述步骤S370中，第一光疏介质层和第一光密介质层的相关特征可以参见以上装置实施例中第一光疏介质层232和第一光密介质层231的相关描述，此处不再赘述。
S380：在第一光密介质层上方制备焊盘，该焊盘与第一互联层进行电连接。
具体地，在本步骤中，可以制备安全芯片的输入输出接口，即安全芯片的焊盘，用于与其它电子元器件通信连接，传输安全芯片产生的数据信号，或者接收其它器件传输的控制信号等等。
具体地，可以采用光刻和刻蚀工艺，在第一光密介质层与第一互联层的金属线路层之间形成盲孔，以露出第一互联层中的金属线路层，在该盲孔中以及第一光密介质层的上表面制备绝缘介质层，然后再次采用光刻和刻蚀工艺刻蚀掉盲孔中心区域的绝缘介质层，以露出第一互联层中的金属线路层，并在盲孔的侧壁上仍然保留绝缘介质层，在盲孔中，以及绝缘介质层的表面制备金属层，并再次采用光刻和刻蚀工艺，在绝缘介质层上方形成焊盘，该焊盘通过盲孔中的金属结构连接至第一互联层中的金属线路层。
应理解，以上描述仅是举例说明制备焊盘的一种方法，还可以采用现有技术中任意一种形成金属焊盘的方法制备本申请实施例中的焊盘。
在本申请实施例中，该焊盘的相关特征可以参见以上装置实施例中焊盘280的相关描述，此处不再赘述。
S390：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片。
采用本申请实施例中的制造方法，制造得到的第一安全芯片如图6、图9和图10所示，其中图6对应于采用步骤S371制备第一光阻挡层，图9对应于采用步骤S372制备第一光阻挡层，图10对应于采用步骤S373制备第一光阻挡层。该第一安全芯片包括第一芯片210、第二芯片220、第一互联层240、第二互联层250、第一光密介质层231、第一光疏介质层232以及焊盘280。
应理解，在上述制造方法中，上下翻转第一晶圆，将第一芯片堆叠于第二芯片的上方，可选地，还可以上下翻转第二晶圆，将第二芯片堆叠于第一 芯片的上方，在第一芯片的下表面制备第一光疏介质层和第一光密介质层，具体的制备方法可以参考以上描述，此处不再赘述。
上述制造方法30中，第一芯片和第二芯片均为直接形成于第一晶圆和第二晶圆中的芯片，第一芯片和第二芯片的表面面积相等。
可选地，在该第一芯片和第二芯片的表面面积不相等的情况下，该第一芯片和/或第二芯片还可以重构形成在第一晶圆和第二晶圆中。
图23为另一种安全芯片的制造方法的示意性流程框图。
如图23所示，该安全芯片的制造方法30可以包括以下步骤。
S312：在第三晶圆中制备并切割出第一芯片，在第一晶圆中制造容置结构，将第一芯片放置于该容置结构中。
本步骤为上述步骤S210的另一种实现方式。
具体地，采用半导体工艺在第三晶圆中制备第一芯片阵列，该第一芯片阵列中每个芯片的结构相同，对第一芯片阵列进行切割得到分离的多个芯片，本步骤中的第一芯片为该第一芯片阵列中的一个芯片。
在第一晶圆上制作多个容置结构，该容置结构为凹槽或通孔。将第一芯片固定在该多个容置结构中的一个容置结构中。
具体地，若容置结构为凹槽，在该第一晶圆上制备多个凹槽后，通过取放(Pick and Place)工艺将第一芯片放入凹槽中。其中，第一芯片的下表面设置有第一胶层，该第一胶层包括但不限于DAF。
可选地，在本申请实施例中，可以通过多种工艺方法在该第一晶圆上制备得到多个凹槽，该工艺方法包括但不限于：干法刻蚀(Dry Etching)、激光法、机械法等等。本申请实施例对此不做具体限定。
进一步地，将第一芯片放置在凹槽后，将填充层填充在第一芯片与凹槽之间的空隙中，以进一步固定该第一芯片。
具体地，若容置结构为通孔，可以通过胶层和/或填充层将该第一芯片固定于通孔中，此时，可以提高第一芯片的散热能力。
可选地，上文中的容置结构、第一芯片以及填充层等相关技术方案可以参见以上装置实施例中容置结构261、第一芯片210以及填充层262的相关描述。
S320：在第一晶圆上方制备第一互联层。
S331：在第二晶圆中制备第二芯片。
S340：在第二芯片上方制备第二互联层。
S350：上下翻转第一晶圆，采用晶圆级键合工艺键合第一互联层和第二互联层，以使得第一芯片对应堆叠于第二芯片的上方，且与第二芯片电连接。
S360：对第一晶圆的上表面进行减薄处理。
S370：在第一晶圆的上方制备第一光疏介质层，在第一光疏介质层上表面制备第一光密介质层。
S380：在第一光密介质层上方制备焊盘，该焊盘与第一互联层进行电连接。
S390：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片。
通过本申请实施例的制造方法制备得到的安全芯片可以参见图4。其中，图4中载体260为切割后的第一晶圆的局部区域。
图24为另一种安全芯片的制造方法的示意性流程框图。
如图24所示，该安全芯片的制造方法30可以包括以下步骤。
S311：在第一晶圆中制备第一芯片。
S320：在第一晶圆上方制备第一互联层。
S332：在第四晶圆中制备并切割出第二芯片，在第二晶圆中制造容置结构，将第二芯片放置于该容置结构中。
本步骤为上述步骤S220的另一种实现方式。
具体地，该步骤的实施过程可以参考以上步骤S312的过程，此处不再赘述。
S340：在第二芯片上方制备第二互联层。
S350：上下翻转第一晶圆，采用晶圆级键合工艺键合第一互联层和第二互联层，以使得第一芯片对应堆叠于第二芯片的上方，且与第二芯片电连接。
S360：对第一晶圆的上表面进行减薄处理。
S370：在第一晶圆的上方制备第一光疏介质层，在第一光疏介质层上表面制备第一光密介质层。
S380：在第一光密介质层上方制备焊盘，该焊盘与第一互联层进行电连接。
S390：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片。
通过本申请实施例的制造方法制备得到的安全芯片可以参见图5。其中，图5中载体260为切割后的第二晶圆的局部区域。
采用上述图23和图24的申请实施例方案，能够实现不同大小的芯片堆叠形成安全芯片，适用于更多的应用场景。且可以在进行堆叠前，对两个晶圆上的芯片进行测试以筛选出性能良好的芯片，去除性能较差的芯片，提高整体安全芯片的良率，低整体的制造成本。
上文的安全芯片的制备方法中，在第一晶圆的上方制备第一光阻挡层以防止光信号进入第一芯片。除此之外，还可以在第二晶圆的下方制备第二光阻挡层以防止光信号进入第二芯片。
图25示出了另一种安全芯片的制造方法40的示意性流程框图。
如图25所示，该安全芯片的制造方法40可以包括以下步骤。
S410：制备第一芯片，该第一芯片位于第一晶圆中。
可选地，本步骤的过程可以参考上述实施例中步骤S210、步骤S311或者步骤S312的相关描述。
该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图可以参见图16。
S420：制备第二芯片，该第二芯片位于第二晶圆中。
可选地，本步骤的过程可以参考上述实施例中步骤S220、步骤S331或者步骤S332的相关描述。
该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图可以参见图17。
S430：采用晶圆级键合工艺键合第一晶圆和第二晶圆，以使得第一芯片和其对应的第二芯片上下堆叠，且相互电连接。
可选地，本步骤的过程可以参考上述实施例中步骤S230，或者步骤S320、步骤S340以及步骤S350的相关描述。
该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图可以参见图18。
S440：以第一晶圆为支撑，对第二晶圆的下表面进行减薄处理。
具体地，在本申请实施例中，对第二晶圆的下表面为衬底材料，可以采用机械减薄、化学减薄、化学抛光等方法对第二晶圆的下表面进行减薄，例如，可以采用磨轮对第二晶圆的下表面进行研磨。本申请实施例对具体的减薄方法不做任何限定。
减薄后的第二晶圆的厚度小于一定的阈值，例如，小于30μm，优选地， 减薄后的第二晶圆的厚度小于10μm。
可选地，减薄后的第二晶圆中第二芯片的电路区域靠近于第二芯片的下表面，但不暴露于下表面中，以防止外界环境对第二芯片的电路区域造成影响，从而影响第二芯片的性能。
采用本申请实施例的方法，可以进一步减小安全芯片的整体厚度，从而可以防止攻击者对安全芯片的拆解，提高安全芯片的安全性能。
具体地，图26示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图26所示，第二晶圆202中的电路区域221接近于第二晶圆202的下表面，第二晶圆202的下表面为粗糙平面。
S450：在第二晶圆的下方制备第二光阻挡层，该第二光阻挡层用于对第二光信号进行全反射和/或散射以防止该第二光信号进入第二芯片。
可选地，与第一光阻挡层类似，作为一种实现方式，第二光阻挡层可以包括第二光疏介质层和第二光密介质层。当然，本步骤中的第二光阻挡层还可以为其他用于反射光信号的膜层或者结构，本申请实施例对此不做限定。
具体地，在第二晶圆的下方制备第二光疏介质层，在第二光疏介质层下表面制备第二光密介质层。
具体的，在本步骤中，也可以有以下三种实施方式。
S451：在第二晶圆的下表面制备第二光疏介质层，在第二光疏介质层下表面制备第二光密介质层。
具体地，在步骤S440中，采用机械减薄或者化学减薄等方法对第二晶圆的下表面进行减薄后，第二晶圆的下表面可以形成粗糙度大于一定预设阈值的粗糙面，该粗糙面可以形成有周期性或者随机分布的尖刺状结构或者孔状结构，或者其他任意呈现高低起伏形态的结构。在该粗糙面下方直接制备厚度较小的第二光疏介质层，该第二光疏介质层的上下表面均为粗糙度大于预设阈值的粗糙面。
在该第二光疏介质层的下表面继续制备第二光密介质层，因此，第二光疏介质层和第二光密介质层之间的第二界面同样为粗糙度大于预设阈值的粗糙面，从而可以形成对入射的光信号进行全反射和/或散射的条件，增大光信号的反射强度和散射强度，大大减小光信号的透射强度，从而减小乃至消除进入至第二芯片中的光信号，避免激光注入攻击。
此外，在制备第二光密介质层后，可以对第二光密介质层的上表面进行 平坦化处理，形成相对光滑的平面。或者制备厚度较厚的第二光密介质层，也能够使得该第二光密介质层的上表面呈现相对光滑的平面。
上述制备第二光疏介质层和第二光密介质的方法包括但不限于化学气相沉积、物理气相沉积、脉冲激光沉积、原子层沉积等等，本申请实施例对具体的第二光密介质层和第二光疏介质层的制备方法不做具体限定。
可选地，在本步骤中，在第二晶圆的下表面制备第二光疏介质层之前，还可以进一步对第二晶圆的下表面进行粗糙处理，例如，可以采用研磨和/或湿法腐蚀对第二晶圆的下表面进行处理，以加强第二晶圆的下表面的粗糙程度。
图27示出了本步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图27所示，第二晶圆202的粗糙下表面上形成有第二光疏介质层272，该第二光疏介质层272的上下表面均为粗糙平面，该第二光疏介质层272的下方还形成有第二光密介质层271，第二光密介质层271的下表面为光滑平面。
S452：在第二晶圆的下表面制备第二光疏介质层，对第二光疏介质层进行粗糙处理，在第二光疏介质层的下表面制备第二光密介质层。
具体地，本步骤中制备第二光疏介质层的制备方法以及对第二光疏介质层的上表面进行粗糙处理的方法也可以参考步骤S451中的制备方法和粗糙处理方法，例如，采用沉积方法制备第二光疏介质层，且利用喷砂或氢氟酸湿法腐蚀工艺对第二光疏介质层进行粗糙处理，使得第二光疏介质层的上表面形成粗糙面。
本步骤与步骤S451的区别在于，步骤S451中第二光疏介质层的厚度较小，其上表面形态依附于第二芯片的下表面形态，而本步骤中，对第二光疏介质层的厚度无要求，直接对第二光疏介质层的下表面进行粗糙处理。
另外，若通过本步骤制备形成第二光阻挡层，也可以不需要进行上述步骤S440，直接在第二芯片的衬底下方制备第二光疏介质层。
具体地，图28示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图28所示，第二晶圆202的下表面上形成有第二光疏介质层272，该第二光疏介质层272的上下表面均为粗糙平面，但粗糙面的形态不一致，该第二光疏介质层272的上方还形成有第二光密介质层271，第二光密介质层271的下表面为光滑平面。
S453：在第二晶圆的下表面制备第二中间层，对第二中间层的下表面进 行粗糙处理，在第二中间层的下表面制备第二光疏介质层，并在第二光疏介质层的上表面制备第二光密介质层。
具体地，本步骤中制备第二中间层的制备方法以及对第二中间层的下表面进行粗糙处理的方法可以参考步骤S451中的制备方法和粗糙处理方法，例如，采用沉积的方法制备第二中间层，并采用腐蚀液和/或研磨的方式对第二中间层的上表面进行腐蚀，使得第二中间层的下表面形成粗糙度大于预设阈值的粗糙平面。
在该第二中间层下表面制备第二光疏介质层，并在第二光疏介质层的下表面制备第二光密介质层的过程与上述步骤S451中的过程近似，其中，第二光疏介质层的厚度较小，其上下表面均为粗糙平面，第二光密介质层的下表面为光滑平面。
在一些实施方式中，第二中间层可以为硅材料，包括但不限于是多晶硅、微晶硅或者不定形硅。
此外，在本申请实施例中，该第二中间层的相关特征可以参见以上装置实施例中的第二中间层273，此处不再赘述。
另外，若通过本步骤制备形成第二光阻挡层，可以不需要进行上述步骤S440，直接在第二芯片的衬底下表面制备第二中间层。
具体地，图29示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图29所示，第二晶圆202的下表面上形成有第二中间层273，该第二中间层273的下表面为粗糙平面，且该第二中间层273的下表面形成有第二光疏介质层272，该第二光疏介质层272的上下表面均为粗糙平面，该第二光疏介质层272的下方还形成有第二光密介质层271，第二光密介质层271的下表面为光滑平面。
在上述步骤S450中，在一些实施方式中，上述第二光密介质层的材料为硅(Si)，第二光疏介质层的材料为二氧化硅(SiO 2)；或者，在另一些实施方式中，第二光密介质层的材料为金属，第二光疏介质层的材料为氮化硅(SiN)、氧氮化硅(SiON)、碳氮化硅(SiCN)中的任意一种，本申请实施例对第二光密介质层和第二光疏介质层的具体材料不做限定。
此外，在上述步骤S450中，第二光疏介质层和第二光密介质层的相关特征可以参见以上装置实施例中第二光疏介质层272和第二光密介质层271的相关描述，此处不再赘述。
S460：在第二光阻挡层下方设置载片，以载片为支撑，对第一晶圆的上表面进行减薄处理。
可选地，可以通过胶层在第二光阻挡层下方设置载片，该载片可以为具有一定强度和厚度的材料，能够起到支撑作用。可选地，该载片包括但不限于为硅、玻璃、陶瓷等材料。
具体地，对第一晶圆的上表面进行减薄处理的过程可以参考步骤S360的相关描述。
图30示出了该工艺步骤后的键合的第一晶圆和第二晶圆的局部截面图。如图30所示，载体290通过胶层291粘接在第二光阻挡层的下方，具体地，粘接在第二光密介质层271的下表面。第一晶圆201中的电路区域211接近于第一芯片210的上表面，第一芯片210的上表面为粗糙平面。
S470：在第一晶圆的上方制备第一光阻挡层，该第一光阻挡层用于对第一光信号进行全反射/或散射以防止该第一光信号进入第一芯片。
具体地，本步骤的过程可以参考步骤S370的相关描述。可以采用步骤S371至步骤S373中任意一种方式制备第一光阻挡层。
图31示出了该工艺步骤后的键合的第一晶圆和第二晶圆的一种局部截面图。如图31所示，采用步骤S371中的制备方式制备第一光阻挡层厚，第一晶圆201的粗糙上表面上形成有第一光疏介质层232，该第一光疏介质层232的上下表面均为粗糙平面，该第一光疏介质层232的上方还形成有第一光密介质层231，第一光密介质层231的上表面为光滑平面。
S480：在第一光密介质层上方制备焊盘，该焊盘与第一互联层进行电连接。
具体地，本步骤的过程可以参考步骤S380的相关描述。
可选地，除了将焊盘设置在第一光密介质层上方，且将焊盘与第一互联层进行电连接外，还可以将焊盘设置在第二光密介质层下方，且将焊盘与第二互联层进行电连接。
S490：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片，该第一安全芯片包括第一芯片、第二芯片、第一光阻挡层和第二光阻挡层。
可选地，在执行本步骤之前，可以去除上述步骤S460中的载体和胶层，例如，通过研磨、腐蚀等物理或者化学方法。在一种实施方式中，该胶层可以为光敏材料，遇光消解，该载体为透明材料，在制备焊盘之后，可以对胶 层进行光照，从而消解胶层并且去除胶层下方的载体。
采用本申请实施例中的制造方法，制造得到的第一安全芯片如图32所示，其在图31的基础上，增加了焊盘280的相关结构。
上文的安全芯片的制备方法中，第一光阻挡层为在对第一晶圆和第二晶圆进行键合之后，在第二晶圆的上表面上制备得到的。
除了该方式外，图33示出了另一种安全芯片的制造方法50的示意性流程框图。
如图33所示，该安全芯片的制造方法50可以包括以下步骤。
S510：制备第一芯片，该第一芯片位于包括第一光阻挡层的第一晶圆中。
S520：制备第二芯片，该第二芯片位于包括第二光阻挡层的第二晶圆中。
S530：采用晶圆级键合工艺键合第一晶圆和第二晶圆，以使得第一芯片和其对应的第二芯片上下堆叠，且相互电连接。
S540：对第一晶圆的表面和第二晶圆的表面进行减薄处理。
S550：制备焊盘，该焊盘与第一芯片或者第二芯片进行电连接。
S560：对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片，该第一安全芯片包括第一芯片、第二芯片、第一光阻挡层和第二光阻挡层。
在本申请实施例中，第一光阻挡层和第二光阻挡层还可以形成于第一晶圆和第二晶圆中。
例如，第一晶圆和/或第二晶圆可以为SOI晶圆，其中的埋层氧化硅层为光疏介质层，其底部硅层为光密介质层，其顶部硅层用于形成第一芯片和/或第二芯片的电路结构，或者在其顶部硅层上形成容置结构以放置第一芯片和/或第二芯片。
该制造方法50中，第一光阻挡层和第二光阻挡层均形成于晶圆中，可选地，第一光阻挡层和第二光阻挡层中也可以仅有一个光阻挡层形成于晶圆中，另一个反射层采用上述制造方法20至40中的光阻挡层的制造方法得到。
还应理解，上述列举的安全芯片的制造方法20至50的各实施例，可以通过机器人或者数控加工方式来执行，用于执行制造方法20至50的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述制造方法20至50。
本申请还提供了一种根据上述制备方法制备的安全芯片。
本申请还提供了一种包括上述安全芯片200的电子设备，或者包括按照 上述方法20至50中任意一种方法制备的安全芯片的电子设备。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围。
还应理解，在本申请的各种实施例中，各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
还应理解，在本申请实施例和所附权利要求书中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请实施例。例如，在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“上述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (66)

  1. 一种安全芯片，其特征在于，包括：第一芯片、第二芯片和第一光阻挡层；
    所述第一芯片和所述第二芯片上下堆叠，且相互电连接；
    所述第一光阻挡层靠近于所述第一芯片中的电路区域，用于将来自外部并朝向所述第一芯片中的电路区域照射的第一光信号进行全反射和/或散射。
  2. 根据权利要求1所述的安全芯片，其特征在于，所述第一芯片的厚度小于30μm；和/或，所述第二芯片的厚度小于30μm。
  3. 根据权利要求1或2所述的安全芯片，其特征在于，所述第一芯片的表面面积与所述第二芯片的表面面积不相等；
    所述安全芯片还包括：载体，所述载体包括容置结构，所述容置结构为通孔或者凹槽；
    所述第一芯片和所述第二芯片中表面面积较小的芯片设置在所述容置结构中，所述载体与所述第一芯片和所述第二芯片中表面面积较大的芯片上下对齐堆叠。
  4. 根据权利要求1至3中任一项所述的安全芯片，其特征在于，所述安全芯片还包括：第一互联层和第二互联层，
    所述第一互联层和所述第二互联层设置在所述第一芯片和所述第二芯片之间；
    所述第一芯片和所述第二芯片通过所述第一互联层和所述第二互联层实现电连接。
  5. 根据权利要求4所述的安全芯片，其特征在于，所述第一互联层的表面面积和所述第二互联层的表面面积相等，所述第一芯片与所述第二芯片之间通过对所述第一互联层和所述第二互联层进行晶圆级键合形成电连接。
  6. 根据权利要求5所述的安全芯片，其特征在于，所述第一互联层的表面形成有至少一个第一键合衬垫，所述第二互联层的表面形成有至少一个第二键合衬垫；
    所述至少一个第一键合衬垫和所述至少一个第二键合衬垫一一对应，所述至少一个第一键合衬垫中的一个第一键合衬垫键合至其对应的一个第二键合衬垫上形成电连接。
  7. 根据权利要求5或6所述的安全芯片，其特征在于，所述第一互联 层的表面面积和所述第二互联层的表面面积均与所述第一芯片和所述第二芯片中表面面积较大的芯片的表面面积相等。
  8. 根据权利要求1至7中任一项所述的安全芯片，其特征在于，所述第一光阻挡层包括：第一光疏介质层和第一光密介质层，所述第一光密介质层连接于所述第一光疏介质层；
    其中，所述第一光密介质层用于接收所述第一光信号，并将所述第一光信号传输至所述第一光密介质层与所述第一光疏介质层之间的第一界面；
    所述第一界面为粗糙度大于预设阈值的粗糙面，用于将来自外部并朝向所述第一芯片中的电路区域照射的所述第一光信号进行全反射和/或散射。
  9. 根据权利要求8所述的安全芯片，其特征在于，所述第一界面的粗糙度大于20nm。
  10. 根据权利要求8或9所述的安全芯片，其特征在于，所述第一界面上形成有尖刺状结构或者孔状结构，所述尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
  11. 根据权利要求8至10中任一项所述的安全芯片，其特征在于，所述第一光疏介质层连接于所述第一芯片的衬底表面。
  12. 根据权利要求11所述的安全芯片，其特征在于，所述第一界面的形态与所述第一芯片的衬底表面的形态基本一致。
  13. 根据权利要求11所述的安全芯片，其特征在于，所述第一界面的粗糙度大于所述第一芯片的衬底表面的粗糙度。
  14. 根据权利要求8至10中任一项所述的安全芯片，其特征在于，所述安全芯片还包括：第一中间层；
    所述第一中间层连接于所述第一芯片的衬底表面，所述第一光疏介质层连接于所述第一中间层，所述第一光疏介质层与所述第一中间层的连接面的形态与所述第一界面的形态基本一致。
  15. 根据权利要求8至10中任一项所述的安全芯片，其特征在于，所述第一光疏介质层和所述第一光密介质层位于所述第一芯片的衬底中，且所述第一光疏介质层接近于所述第一芯片中的电路区域。
  16. 根据权利要求8至15中任一项所述的安全芯片，其特征在于，所述第一光密介质层的材料为硅，所述第一光疏介质层的材料为二氧化硅；或者，
    所述第一光密介质层的材料为金属，所述第一光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
  17. 根据权利要求1至16中任一项所述的安全芯片，其特征在于，所述安全芯片还包括：第二光阻挡层，
    所述第二挡光层靠近于所述第二芯片中的电路区域，用于将来自外部并朝向所述第二芯片中的电路区域照射的第二光信号进行全反射和/或散射。
  18. 根据权利要求17所述的安全芯片，其特征在于，所述第二光阻挡层包括：第二光疏介质层和第二光密介质层，所述第二光密介质层连接于所述第二光疏介质层；
    其中，所述第二光密介质层用于接收所述第二光信号，并将所述第二光信号传输至所述第二光密介质层与所述第二光疏介质层之间的第二界面；
    所述第二界面为粗糙度大于预设阈值的粗糙面，用于将来自外部并朝向所述第二芯片中的电路区域照射的所述第二光信号进行全反射和/或散射。
  19. 根据权利要求18所述的安全芯片，其特征在于，所述第二界面的粗糙度大于20nm。
  20. 根据权利要求18或19所述的安全芯片，其特征在于，所述第二界面上形成有尖刺状结构或者孔状结构，所述尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
  21. 根据权利要求18至20中任一项所述的安全芯片，其特征在于，所述第二光疏介质层连接于所述第二芯片的衬底表面。
  22. 根据权利要求21所述的安全芯片，其特征在于，所述第二界面的形态与所述第二芯片的衬底表面的形态基本一致。
  23. 根据权利要求21所述的安全芯片，其特征在于，所述第二界面的粗糙度大于所述第二芯片的衬底表面的粗糙度。
  24. 根据权利要求18至20中任一项所述的安全芯片，其特征在于，所述安全芯片还包括：第二中间层；
    所述第二中间层连接于所述第二芯片的衬底表面，所述第二光疏介质层连接于所述第二中间层，所述第二光疏介质层与所述第二中间层的连接面的形态与所述第二界面的形态基本一致。
  25. 根据权利要求18至20中任一项所述的安全芯片，其特征在于，所述第二光疏介质层和所述第二光密介质层位于所述第二芯片的衬底中，且所 述第二光疏介质层接近于所述第二芯片中的电路区域。
  26. 根据权利要求18至25中任一项所述的安全芯片，其特征在于，所述第二光密介质层的材料为硅，所述第二光疏介质层的材料为二氧化硅；或者，
    所述第二光密介质层的材料为金属，所述第二光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
  27. 根据权利要求1至26中任一项所述的安全芯片，其特征在于，所述安全芯片还包括：焊盘；
    所述焊盘位于所述安全芯片的一侧，靠近于所述第一芯片，与所述第一芯片电连接；或者，
    所述焊盘位于所述安全芯片的另一侧，靠近于所述第二芯片，与所述第二芯片电连接。
  28. 根据权利要求1至27中任一项所述的安全芯片，其特征在于，所述第一芯片和所述第二芯片分别为逻辑芯片和存储芯片。
  29. 一种安全芯片的制造方法，其特征在于，包括：
    制备第一芯片，所述第一芯片位于第一晶圆中；
    制备第二芯片，所述第二芯片位于第二晶圆中；
    采用晶圆级键合工艺键合所述第一晶圆和所述第二晶圆，以使得所述第一芯片和其对应的所述第二芯片上下堆叠，且相互电连接，其中，靠近于所述第一芯片中的电路区域设置有第一光阻挡层，所述第一光阻挡层用于将来自外部并朝向所述第一芯片中的电路区域照射的第一光信号进行全反射和/或散射；
    对堆叠的第一晶圆和第二晶圆进行切割，得到第一安全芯片，所述第一安全芯片包括所述第一芯片、所述第二芯片以及所述第一光阻挡层。
  30. 根据权利要求29所述的制造方法，其特征在于，所述制备第一芯片，包括：
    在第三晶圆中制备并分割出所述第一芯片；
    在所述第一晶圆中制作容置结构，所述容置结构为通孔或者凹槽；
    将所述第一芯片固定放置在所述容置结构中。
  31. 根据权利要求29所述的制造方法，其特征在于，所述制备第一芯片，包括：在所述第一晶圆中制备所述第一芯片。
  32. 根据权利要求30或31所述的制造方法，其特征在于，所述制备第二芯片，包括：
    在第四晶圆中制备并分割出所述第二芯片；
    在所述第二晶圆上制作容置结构，所述容置结构为通孔或者凹槽；
    将所述第二芯片固定放置在所述容置结构中。
  33. 根据权利要求30或31所述的制造方法，其特征在于，所述制备第二芯片，包括：在所述第二晶圆中制备所述第二芯片。
  34. 根据权利要求29至33中任一项所述的制造方法，其特征在于，在采用晶圆级键合工艺键合所述第一晶圆和所述第二晶圆之前，所述制造方法还包括：
    在所述第一芯片的上表面制备第一互联层，所述第一互联层与所述第一芯片电连接；
    在所述第二芯片的上表面制备第二互联层，所述第二互联层与所述第二芯片电连接。
  35. 根据权利要求34所述的制造方法，其特征在于，所述采用晶圆级键合工艺键合所述第一晶圆和所述第二晶圆，以使得所述第一芯片和其对应的所述第二芯片上下堆叠，且相互电连接，包括：
    上下翻转所述第一晶圆或者所述第二晶圆；
    采用晶圆级键合工艺键合所述第一互联层和所述第二互联层，以使得所述第一芯片和其对应的所述第二芯片上下堆叠，且相互电连接。
  36. 根据权利要求35所述的制造方法，其特征在于，所述采用晶圆级键合工艺键合所述第一互联层和所述第二互联层，包括：
    采用晶圆级键合工艺键合所述第一互联层上表面的至少一个第一键合衬垫与所述第二互联层下表面的至少一个第二键合衬垫，以形成所述第一互联层和所述第二互联层的电连接；
    其中，所述至少一个第一键合衬垫和所述至少一个第二键合衬垫一一对应。
  37. 根据权利要求29至36中任一项所述的制造方法，其特征在于，所述采用晶圆级键合工艺键合所述第一晶圆和所述第二晶圆之后，所述制造方法还包括：
    在所述第一晶圆的衬底表面制备所述第一光阻挡层。
  38. 根据权利要求37所述的制造方法，其特征在于，所述在所述第一晶圆的衬底表面制备所述第一光阻挡层，包括：
    在所述第一晶圆的衬底表面制备第一光疏介质层；
    在所述第一光疏介质层的表面制备第一光密介质层，所述第一光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
  39. 根据权利要求38所述的制造方法，其特征在于，所述在所述第一晶圆的衬底表面制备第一光疏介质层，包括：
    对所述第一晶圆的衬底表面进行减薄处理，以使得所述第一晶圆的衬底表面为粗糙度大于预设阈值的粗糙面；
    在所述第一晶圆的衬底表面制备所述第一光疏介质层，所述第一光疏介质层的表面形态与所述第一晶圆的衬底表面形态基本一致。
  40. 根据权利要求38所述的制造方法，其特征在于，所述在所述第一晶圆的衬底表面制备第一光疏介质层，包括：
    在所述第一晶圆的衬底表面制备所述第一光疏介质层；
    对所述第一光疏介质层的表面进行粗糙处理，以使得所述第一光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
  41. 根据权利要求37所述的制造方法，其特征在于，所述在所述第一晶圆的衬底表面制备所述第一光阻挡层，包括：
    在所述第一晶圆的衬底表面制备第一中间层；
    对所述第一中间层的表面进行粗糙处理，以使得所述第一中间层的表面为粗糙度大于预设阈值的粗糙面；
    在所述第一中间层的表面制备第一光疏介质层，所述第一光疏介质层的表面形态与所述第一中间层的表面形态基本一致。
  42. 根据权利要求40或41所述的制造方法，其特征在于，在制备第一光疏介质层之前，所述制造方法还包括：
    对所述第一晶圆的衬底表面进行减薄处理。
  43. 根据权利要求39或42所述的制造方法，其特征在于，所述对所述第一晶圆的衬底表面进行减薄处理，包括：
    将所述第一晶圆的厚度减薄至30μm或以下。
  44. 根据权利要求38至43中任一项所述的制造方法，其特征在于，所述第一光疏介质层的表面的粗糙度大于20nm。
  45. 根据权利要求38至44中任一项所述的制造方法，其特征在于，所述第一光疏介质层的表面形成有尖刺状结构或者孔状结构，所述尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
  46. 根据权利要求38至45中任一项所述的制造方法，其特征在于，所述第一光密介质层的材料为硅，所述第一光疏介质层的材料为二氧化硅；或者，
    所述第一光密介质层的材料为金属，所述第一光疏介质层的材料为氮化硅、氧氮化硅、碳氮化硅中的任意一种。
  47. 根据权利要求29至36中任一项所述的制造方法，其特征在于，所述制备第一芯片，包括：
    在所述第一晶圆中制备所述第一光阻挡层；
    在所述第一光阻挡层上方制备所述第一芯片。
  48. 根据权利要求47所述的制造方法，其特征在于，所述在所述第一晶圆中制备所述第一光阻挡层，包括：
    在所述第一晶圆中制备第一光疏介质层；
    所述第一光疏介质层的下方对应形成第一光密介质层；
    所述第一光密介质层与所述第一光疏介质层之间的第一界面为粗糙度大于预设阈值的粗糙面。
  49. 根据权利要求48所述的制造方法，其特征在于，所述第一光密介质层为硅，所述第一光疏介质层为埋层氧化硅BOX。
  50. 根据权利要求29至49中任一项所述的制造方法，其特征在于，所述采用晶圆级键合工艺键合所述第一晶圆和所述第二晶圆之后，所述制造方法还包括：
    在所述第二晶圆的衬底表面制备第二光阻挡层。
  51. 根据权利要求50所述的制造方法，其特征在于，所述在所述第二晶圆的衬底表面制备第二光阻挡层，包括：
    在所述第二晶圆的衬底表面制备第二光疏介质层；
    在所述第二光疏介质层的表面制备第二光密介质层，所述第二光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
  52. 根据权利要求51所述的制造方法，其特征在于，所述在所述第二晶圆的衬底表面制备第二光疏介质层，包括：
    对所述第二晶圆的衬底表面进行减薄处理，以使得所述第二晶圆的衬底表面为粗糙度大于预设阈值的粗糙面；
    在所述第二晶圆的衬底表面制备所述第二光疏介质层，所述第二光疏介质层的表面形态与所述第二晶圆的衬底表面形态基本一致。
  53. 根据权利要求51所述的制造方法，其特征在于，所述在所述第二晶圆的衬底表面制备第二光疏介质层，包括：
    在所述第二晶圆的衬底表面制备所述第二光疏介质层；
    对所述第二光疏介质层的表面进行粗糙处理，以使得所述第二光疏介质层的表面为粗糙度大于预设阈值的粗糙面。
  54. 根据权利要求50所述的制造方法，其特征在于，所述在所述第二晶圆的衬底表面制备第二光阻挡层，包括：
    在所述第二晶圆的衬底表面制备第二中间层；
    对所述第二中间层的表面进行粗糙处理，以使得所述第二中间层的表面为粗糙度大于预设阈值的粗糙面；
    在所述第二中间层的表面制备所述第二光疏介质层，所述第二光疏介质层的表面形态与所述第二中间层的表面形态基本一致。
  55. 根据权利要求53或54所述的制造方法，其特征在于，在制备第二光疏介质层之前，所述制造方法还包括：
    对所述第二晶圆的衬底表面进行减薄处理。
  56. 根据权利要求52或55所述的制造方法，其特征在于，所述对所述第二晶圆的衬底表面进行减薄处理，包括：
    将所述第二晶圆的厚度减薄至30μm或以下。
  57. 根据权利要求51至56中任一项所述的制造方法，其特征在于，所述第二光疏介质层的表面的粗糙度大于20nm。
  58. 根据权利要求51至57中任一项所述的制造方法，其特征在于，所述第二光疏介质层的表面形成有尖刺状结构或者孔状结构，所述尖刺状结构由金字塔形凸起或倒金字塔形凹坑形成。
  59. 根据权利要求51至58中任一项所述的制造方法，其特征在于，所述第二光密介质层的材料为硅，所述第二光疏介质层的材料为二氧化硅；或者，
    所述第二光密介质层的材料为金属，所述第二光疏介质层的材料为氮化 硅、氧氮化硅、碳氮化硅中的任意一种。
  60. 根据权利要求29至49中任一项所述的制造方法，其特征在于，所述制备第二芯片，包括：
    在所述第二晶圆中制备第二光阻挡层；
    在所述第二光阻挡层上方制备所述第二芯片。
  61. 根据权利要求60所述的制造方法，其特征在于，所述在所述第二晶圆中制备第二光阻挡层，包括：
    在所述第二晶圆中制备第二光疏介质层；
    所述第二光疏介质层的下方对应形成第二光密介质层；
    所述第二光密介质层与所述第二光疏介质层之间的第二界面为粗糙度大于预设阈值的粗糙面。
  62. 根据权利要求61所述的制造方法，其特征在于，所述第二光密介质层为硅，所述第二光疏介质层为埋层氧化硅BOX。
  63. 根据权利要求29至62中任一项所述的制造方法，其特征在于，所述制造方法还包括：
    制造焊盘，所述焊盘位于所述安全芯片的一侧，靠近于所述第一芯片，与所述第一芯片电连接；或者，
    所述焊盘位于所述安全芯片的另一侧，靠近于所述第二芯片，与所述第二芯片电连接。
  64. 根据权利要求29至63中任一项所述的制造方法，其特征在于，所述第一芯片和所述第二芯片分别为逻辑芯片和存储芯片。
  65. 一种安全芯片，其特征在于，包括：
    按照权利要求29至64中任一项所述的制造方法制造的安全芯片。
  66. 一种电子设备，其特征在于，包括：
    权利要求1至28中任一项所述的安全芯片。
PCT/CN2020/082609 2020-03-31 2020-03-31 安全芯片、安全芯片的制造方法和电子设备 WO2021196039A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/082609 WO2021196039A1 (zh) 2020-03-31 2020-03-31 安全芯片、安全芯片的制造方法和电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/082609 WO2021196039A1 (zh) 2020-03-31 2020-03-31 安全芯片、安全芯片的制造方法和电子设备

Publications (1)

Publication Number Publication Date
WO2021196039A1 true WO2021196039A1 (zh) 2021-10-07

Family

ID=77926885

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/082609 WO2021196039A1 (zh) 2020-03-31 2020-03-31 安全芯片、安全芯片的制造方法和电子设备

Country Status (1)

Country Link
WO (1) WO2021196039A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101027774A (zh) * 2004-07-26 2007-08-29 皇家飞利浦电子股份有限公司 具有光保护层的芯片
CN101617319A (zh) * 2007-02-20 2009-12-30 Nxp股份有限公司 具有背面破坏防护的半导体装置
US20100084758A1 (en) * 2008-10-02 2010-04-08 Samsung Electronics Co.,Ltd. Semiconductor package
CN101803018A (zh) * 2007-09-04 2010-08-11 Nds有限公司 安全芯片
CN102034688A (zh) * 2009-10-05 2011-04-27 意法半导体(胡希)公司 保护集成电路芯片免受激光攻击的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101027774A (zh) * 2004-07-26 2007-08-29 皇家飞利浦电子股份有限公司 具有光保护层的芯片
CN101617319A (zh) * 2007-02-20 2009-12-30 Nxp股份有限公司 具有背面破坏防护的半导体装置
CN101803018A (zh) * 2007-09-04 2010-08-11 Nds有限公司 安全芯片
US20100084758A1 (en) * 2008-10-02 2010-04-08 Samsung Electronics Co.,Ltd. Semiconductor package
CN102034688A (zh) * 2009-10-05 2011-04-27 意法半导体(胡希)公司 保护集成电路芯片免受激光攻击的方法

Similar Documents

Publication Publication Date Title
US11830861B2 (en) Semiconductor package
US11610846B2 (en) Protective elements for bonded structures including an obstructive element
US8802495B2 (en) Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
TW202123412A (zh) 具有矽穿孔之垂直交互連接線連接器
TWI236767B (en) Solid-state image pickup device and its manufacturing method
KR102055840B1 (ko) 이미지 센서 패키지
US20080284037A1 (en) Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US11114383B2 (en) Semiconductor devices having integrated optical components
CN110838499B (zh) 图像传感器及其形成方法
EP1851797A1 (en) Device and method for fabricating double-sided soi wafer scale package with through via connections
TWI778489B (zh) 製作雙側半導體裝置之方法及相關裝置、總成、封裝及系統
KR20150092675A (ko) 반도체 소자의 제조 방법
CN211929489U (zh) 安全芯片和电子设备
WO2021196039A1 (zh) 安全芯片、安全芯片的制造方法和电子设备
WO2017052646A1 (en) Island transfer for optical, piezo and rf applications
US20210043587A1 (en) Security chip, security chip production method and electronic device
CN104409464A (zh) 带应力保护结构的高可靠性影像传感器封装
CN116613080A (zh) 半导体器件及其制作方法
US20210111101A1 (en) Semiconductor Structure Having Through-Substrate Via (TSV) in Porous Semiconductor Region
WO2020191616A1 (zh) 具有随机信号发生器件的集成装置、制备方法及电子设备
WO2024120010A1 (zh) 芯片及其制作方法、多芯片堆叠封装及电子设备
TWI817390B (zh) 具有複合中介結構的光學半導體元件
WO2007123754A1 (en) Integration scheme for semiconductor photodetectors on an integrated circuit chip
TWI817434B (zh) 具有串接導通孔的光學半導體元件
TWI833176B (zh) 具有實現晶粒內連接之積體通孔的光學半導體元件

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20929058

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20929058

Country of ref document: EP

Kind code of ref document: A1