WO2021190263A1 - 像素驱动电路和显示设备 - Google Patents

像素驱动电路和显示设备 Download PDF

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Publication number
WO2021190263A1
WO2021190263A1 PCT/CN2021/078857 CN2021078857W WO2021190263A1 WO 2021190263 A1 WO2021190263 A1 WO 2021190263A1 CN 2021078857 W CN2021078857 W CN 2021078857W WO 2021190263 A1 WO2021190263 A1 WO 2021190263A1
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Prior art keywords
circuit
sub
transistor
control
signal
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PCT/CN2021/078857
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English (en)
French (fr)
Inventor
丛宁
陈小川
玄明花
张粲
杨明
袁丽君
张盎然
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/787,479 priority Critical patent/US11955061B2/en
Publication of WO2021190263A1 publication Critical patent/WO2021190263A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the embodiment of the present disclosure relates to a pixel driving circuit and a display device.
  • Miniature inorganic light-emitting diodes are usually used in display devices because of their advantages of high brightness, long life, small size, etc., and have broad development prospects in the display field.
  • the miniature inorganic light-emitting diodes in such display devices in certain scenarios, for example, when the miniature inorganic light-emitting diodes perform low-gray-scale (ie, low-brightness) display, the total light-emitting time of the light-emitting diodes in one frame is relatively long. Short, and the luminous time is uneven, there will be flicker.
  • At least one embodiment of the present disclosure provides a pixel drive circuit configured to provide a signal to an element to be driven.
  • the pixel drive circuit includes: a current control sub-circuit configured to transmit a current signal; a duration control sub-circuit configured to transmit A time signal; and an output sub-circuit, which are respectively electrically connected to the duration control sub-circuit and the current control sub-circuit.
  • the duration control sub-circuit is further configured to control the turn-on and turn-off of the output sub-circuit according to the time signal
  • the output sub-circuit is configured to control the application of the output sub-circuit according to the current signal when it is turned on.
  • the duration of two adjacent turn-offs of the output sub-circuit is the same, and the duration of two adjacent turn-offs of the output sub-circuit is the same.
  • the duration control sub-circuit includes a comparator configured to compare the time signal with a reference voltage signal to generate a comparison signal, and control the output sub-circuit according to the comparison signal.
  • the comparator includes a non-inverting input terminal, an inverting input terminal, and an output terminal; the non-inverting input terminal is configured to receive one of the time signal and the reference voltage signal, the The inverting input terminal is configured to be the other of the receiving time signal and the reference voltage signal; and the output terminal is connected to the output sub-circuit.
  • the reference voltage signal includes one of a ramp signal, a triangle wave signal, a sawtooth wave signal, a sine wave signal, and a cosine wave signal.
  • the reference voltage signal is a high frequency signal, and the frequency of the reference voltage signal is greater than or equal to 750 Hz and less than or equal to 7500 Hz.
  • the duration control sub-circuit further includes a duration writing sub-circuit and a duration storage capacitor; the duration writing sub-circuit is connected to the non-inverting input terminal or the inverting input terminal of the comparator; The first end of the duration storage capacitor is grounded, and the second end of the duration storage capacitor is connected to the duration writing sub-circuit and connected to the comparator.
  • the current control sub-circuit includes a current writing sub-circuit and a compensation sub-circuit, and the compensation sub-circuit connects the current writing sub-circuit and the output sub-circuit; the current writing sub-circuit The first end of the input sub-circuit is configured to receive the current signal, the second end of the current writing sub-circuit is connected to the compensation sub-circuit, and the first end of the compensation sub-circuit is connected to the current writing A sub-circuit, the second end of the compensation sub-circuit is connected to the output sub-circuit.
  • the compensation sub-circuit includes: a compensation transistor, a current storage capacitor, and a first drive transistor; a first pole of the first drive transistor is connected to the current writing sub-circuit, and the first The second electrode of a driving transistor is connected to the first electrode of the compensation transistor, the gate of the first driving transistor and the second electrode of the compensation transistor are both connected to the current storage capacitor, and the gate of the compensation transistor Connect the data write control signal line.
  • the aspect ratio of the first driving transistor is greater than 3.
  • the current writing sub-circuit includes a current writing transistor.
  • the pixel driving circuit further includes a work control sub-circuit
  • the work control sub-circuit includes a first control transistor; the first pole of the first control transistor is connected to the current control sub-circuit The second pole of the first control transistor is connected to the output sub-circuit; the gate of the first control crystal is connected to a work control signal line, and the work control line is configured to input work control to the first control transistor Signal to control the turn-on and turn-off of the first control transistor; wherein the first control transistor is configured to transmit the current signal to the output sub-circuit when it is turned on.
  • the work control sub-circuit further includes a second control transistor, the first electrode of the second control transistor is connected to the power supply terminal, and the second electrode of the second control transistor is connected to the current Control sub-circuit.
  • the work control sub-circuit further includes a third control transistor, a first pole of the third control transistor is connected to the output sub-circuit, and a second pole of the third control transistor Connect the components to be driven.
  • the output sub-circuit includes an output transistor, a first pole of the output transistor is connected to a second pole of the first control transistor, and a second pole of the output transistor is connected to the third control transistor The first pole.
  • the pixel driving circuit further includes a reset sub-circuit;
  • the reset sub-circuit includes a reset transistor, the gate of the reset transistor is connected to a reset control line, and the first pole of the reset transistor is connected to The reset signal terminal, the second pole of the reset transistor is connected to at least one of the current control sub-circuit, the duration control sub-circuit and the to-be-driven element, and is configured to control the current control sub-circuit, the The duration control sub-circuit and the component to be driven are reset.
  • At least one embodiment of the present disclosure provides a display device that includes an element to be driven and the aforementioned pixel drive circuit, the pixel drive circuit is configured to provide a signal to the element to be driven, and the element to be driven It is a current-driven light-emitting diode.
  • FIG. 1 is a pixel matrix diagram of an embodiment of the disclosure.
  • FIG. 2 is a block diagram of sub-circuits of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 3 is a circuit block diagram of another pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel driving circuit known by the inventor.
  • FIG. 5 is a timing diagram of the pixel driving circuit shown in FIG. 4.
  • FIG. 6 is a schematic diagram of the circuit structure of an embodiment of the present disclosure.
  • FIG. 7A is a waveform diagram of a comparison signal according to an embodiment of the present disclosure.
  • FIG. 7B is another waveform diagram of the comparison signal according to an embodiment of the present disclosure.
  • FIG. 7C is another waveform diagram of the comparison signal according to an embodiment of the present disclosure.
  • Fig. 8 is a timing chart of the pixel driving circuit shown in Fig. 6.
  • FIG. 9 is a schematic diagram of the circuit structure of another embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the circuit structure of another embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the circuit structure of still another embodiment of the present disclosure.
  • FIG. 12 is another timing chart of the pixel driving circuit shown in FIG. 6.
  • FIG. 13 is a specific structure diagram of the circuit structure shown in FIG. 6.
  • Time signal line 11 Time signal Vdata_T Reference signal line 12
  • Reset signal terminal 17 Reset voltage Vint To be driven component 20
  • the output terminal 213 The time length is written into the sub-circuit 220
  • the reference voltage is written into the transistor T9
  • Time length is written into transistor T10 Time length storage capacitor C2 Output sub-circuit 300
  • At least one embodiment of the present disclosure discloses a display device that is applied to electronic devices with display functions such as mobile phones, computers, tablets, e-books, and watches.
  • the display device 2 includes a plurality of pixels 1 arranged in an array.
  • the display device 2 displays an image by driving the light emitting element of each pixel 1 to emit light.
  • the light-emitting element of the display device 2 is used as the element to be driven 20, and the element to be driven 20 is a current-driven light-emitting diode, such as a micro LED or a mini LED or an organic electroluminescent diode OLED.
  • the working time length of the component to be driven 20 referred to below can be understood as the light-emitting time length of the light-emitting diode.
  • the pixel 1 further includes a pixel drive circuit 10 connected to the element to be driven 20.
  • the pixel drive circuit 10 is configured to provide a drive signal to the element to be driven 20 to control the flow through the element to be driven in the process of displaying a frame of image.
  • FIG. 1 only shows a total of nine pixels 1 in three rows and three columns.
  • FIG. 4 shows a schematic circuit diagram of a pixel driving circuit known to the inventor.
  • the pixel driving circuit 10 further includes a connecting transistor T11.
  • the first end of the connecting transistor T11 is connected to the output sub-circuit 300, and the second end of the connecting transistor T11 is connected to the component to be driven 20.
  • the connecting transistor T11 is controlled by a separate operation.
  • the signal EM controls. When the work control signal EM is at a high level, the connecting transistor T11 is turned off; when the work control signal EM is at a low level, the connecting transistor T11 is turned on.
  • Fig. 5 is a timing diagram of Fig. 4. Usually, the time of one frame is divided into multiple periods.
  • Figure 5 shows only three periods, namely Scan1, Scan2, and Scan3.
  • the sub-periods in which the work control signal EM is low are t 1 , t 2 and t 3 , and the lengths of t 1 , t 2 and t 3 are all different.
  • the duration control sub-circuit 200 can only output a constant voltage signal in a period of time, so as to control the output sub-circuit 300 to be turned on or off in the sub-periods t 1 , t 2 and t 3 , thereby determining that the element 20 to be driven is at t 1 , T 2 and t 3 time period of light or no light.
  • n period there is a sub-period in which the work control signal EM is low in that n period, for example: in the first period (Scan1), the work control signal EM is in low level
  • the sub-time period is t1
  • the sub-time period in which the work control signal EM is low in the nth period (Scann) is t n .
  • the pixel driving circuit 10 can only control the element 20 to be driven to emit light or not to emit light during the sub-time periods t 1 , t 2 , t 3 to t n , so as to determine the amount of light emitted by the element 20 to be driven during the entire frame time.
  • the total duration determines the brightness of the component 20 to be driven in this frame.
  • flickering may occur under visual observation.
  • any one frame to be the driving element 20 needs to be a low intensity, because the light emitting diode length shorter total time of light emission within the time of one frame, for example: to be driven 20 t 1 and t n sub-only member Lights up during the time period, and goes out during the time period from t 2 to t n-1 . The same is true for the next frame. If the cycle is repeated, then the light-emitting time is unevenly distributed, and the time between two adjacent light-ups is too long and uneven , It is prone to flicker visible to the naked eye.
  • At least one embodiment of the present disclosure provides a pixel drive circuit configured to provide a signal to an element to be driven, wherein the pixel drive circuit includes: a current control sub-circuit configured to transmit a current signal; a duration control sub-circuit configured to Is a transmission time signal; an output sub-circuit is electrically connected to the duration control sub-circuit and the current control sub-circuit; wherein the duration control sub-circuit is also configured to control the output sub-circuit according to the time signal
  • the output sub-circuit is configured to control the current of the drive element according to the current signal when it is turned on; the duration of two adjacent conduction of the output sub-circuit is the same, and the phase The duration of the two cutoffs is the same.
  • the pixel driving circuit 10 includes a current control sub-circuit 100, a duration control sub-circuit 200 and an output sub-circuit 300.
  • the current control sub-circuit 100 is configured to transmit a current signal Vdata_I.
  • the duration control sub-circuit 200 is configured to transmit the time signal Vdata_T.
  • the output sub-circuit 300 is electrically connected to the duration control sub-circuit 200 and the current control sub-circuit 100, respectively.
  • the duration control sub-circuit 200 is further configured to control the on and off of the output sub-circuit 300 according to the time signal Vdata_T.
  • the output sub-circuit 300 is configured to control the current flowing through the element 20 to be driven according to the current signal Vdata_I when it is turned on.
  • the duration of two adjacent turns on of the output sub-circuit 300 is the same, and the duration of two adjacent turns off is the same.
  • the duration control sub-circuit 200 can directly control the on and off of the output sub-circuit 300 according to the time signal Vdata_T. In this case, there is no need to use the work control signal to control the overall light-emitting time of the element 20 to be driven.
  • the duration of two adjacent turn-offs of the output sub-circuit 300 is the same, and the duration of two adjacent turn-offs is the same. In other words, the brightness of the component 20 to be driven in any frame is converted into the length of time the component to be driven 20 needs to light up in this frame, and the time length is evenly distributed to the entire frame.
  • the number of times of the output sub-circuit 300 being turned on should be greater than or equal to 10 times within one frame.
  • the number of conduction times in one frame may be 12 times, 14 times, 15 times, 18 times, 20 times, and so on.
  • the display is only performed during any period of time among t1, t2...tn, that is, guide The number of passes is only once, so flickering will also occur.
  • a large number of experiments have shown that, within one frame, when the number of times the output sub-circuit 300 is turned on is greater than or equal to 10 times, the visible flicker can be reduced or avoided.
  • the duration control sub-circuit 200 includes a comparator 210, and the comparator 210 includes a non-inverting input terminal 211, an inverting input terminal 212 and an output terminal 213.
  • the non-inverting input terminal 211 and the inverting input terminal 212 are respectively configured to receive the time signal Vdata_T and the reference voltage signal Vramp_T, and the output terminal 213 is connected to the output sub-circuit 300.
  • the comparator 210 is configured to compare the time signal Vdata_T and the reference voltage signal Vramp_T, and output a comparison signal through the output terminal 213.
  • the comparator 210 is also configured to control the on and off of the output sub-circuit 300 according to the comparison signal.
  • FIG. 13 shows the circuit structure shown in FIG. 6 in more detail, in which the connection relationship and internal structure of the comparator 210 are shown.
  • the non-inverting input terminal 211 is connected to the duration signal line 11 and configured to receive the time signal Vdata_T; the inverting input terminal 212 is connected to the reference signal line 12 and configured to receive the reference voltage signal Vramp_T.
  • the comparison signal output by the comparator 210 when the time signal Vdata_T is greater than the reference voltage signal Vramp_T, the comparison signal output by the comparator 210 is low level, that is, the output terminal 213 transmits a low level comparison signal to the output sub-circuit 300, and outputs The sub-circuit 300 is turned on; when the carrier time signal Vdata_T is less than the reference voltage signal Vramp_T, the comparison signal output by the comparator 210 is at a high level, that is, the output terminal 213 transmits a high-level comparison signal to the output sub-circuit 300, and the output sub-circuit The circuit 300 is turned off.
  • the non-inverting input terminal 211 may be connected to the reference signal line 12 and configured to receive the reference voltage signal Vramp_T; the inverting input terminal 212 is connected to the duration signal line 11 and configured to receive the time signal Vdata_T. Then, when the time signal Vdata_T is greater than the reference voltage signal Vramp_T, the comparison signal output by the comparator 210 is at a high level; when the time signal Vdata_T is less than the reference voltage signal Vramp_T, the comparison signal output by the comparator 210 is at a low level. flat.
  • the comparison signal is a periodic square wave signal. Only when the comparison signal is a periodic square wave signal, can it be ensured that the duration of the two adjacent turn-offs of the output sub-circuit 300 is the same, and the duration of the two adjacent turn-offs is the same, so as to ensure that the component 20 to be driven is at one time. Within the frame time, the duration of two adjacent light-emittings is the same, and the duration of two adjacent non-light-emittings is also the same. In the case of reducing or avoiding the light emission of the component 20 to be driven, the flicker that is visible to the naked eye occurs within one frame.
  • the comparison signal is a periodic square wave signal
  • only one data write is required for a row of pixels 1 within a frame of time to realize the intermittent light emission and light emission of the element 20 to be driven. Does not emit light.
  • the duty ratio of the periodic square wave signal By adjusting the duty ratio of the periodic square wave signal, the light-emitting time of the element 20 to be driven in one frame can be adjusted, that is, the display brightness of the element 20 to be driven in one frame can be adjusted. It can be seen that by reducing the number of data writing, the time for writing data in one frame can be reduced, and the time left for the element 20 to be driven to emit light will also increase.
  • the resolution of the display device increases, the number of pixels 1 increases, and the number of corresponding rows also increases. In one frame, each row of pixels 1 only needs to write data once, and each pixel 1 still has enough time for show. Therefore, the display device according to the embodiment of the present disclosure can perform high-resolution display.
  • the time signal Vdata_T obtained by the comparator 210 is a fixed voltage value within one frame, and the reference voltage signal Vramp_T is a ramp signal.
  • the comparison signal output by the comparator 210 is a periodic square wave signal.
  • comparison signals with different duty cycles ie, periodic square wave signals
  • FIG. 7A-7C comparison signals with different duty cycles
  • the comparison signal is similar to that shown in FIG. The brightness is greater.
  • the comparison signal is similar to that shown in FIG. 7B. In one frame of time, the total time period during which the device to be driven 20 emits light is shorter, and the brightness of the device to be driven 20 is smaller.
  • the reference voltage signal Vramp_T may also be a triangle wave signal, a sawtooth wave signal, a sine wave signal, or a cosine wave signal, etc.
  • a plurality of pixels 1 in the display device 2 are arranged in an array.
  • the frequency of the reference voltage signal Vramp_T is relatively low.
  • data writing is generally performed on the pixels 1 of all rows. After that, the reference voltage signal Vramp_T is written. Since it takes a certain amount of time to write data to the pixel 1 in each row, the display of the pixel 1 in the previous row will be delayed.
  • the display device 2 has n rows of pixels 1, then after the first row of pixels 1 is written with data and registered, it needs to wait until the nth row of pixels 1 are written with data before writing the reference voltage signal Vramp_T, and then compare the registered time signal Vdata_T with the reference voltage signal Vramp_T, and finally determine the light-emitting condition of each pixel 1. This also wastes display time and is not conducive to high-resolution display.
  • the reference voltage signal Vramp_T is a high-frequency signal.
  • the reference voltage signal Vramp_T is a high-frequency ramp signal.
  • the frequency of the reference voltage signal Vramp_T is greater than or equal to 750 Hz, and is less than or equal to 7500 Hz. In the above setting, the frequency of the reference voltage signal Vramp_T is limited to keep it high frequency change. In an embodiment of the present disclosure, the frequency of the reference voltage signal Vramp_T is 800HZ.
  • the frequency of the reference voltage signal Vramp_T may also be 900HZ, 1000HZ, 1500HZ, 2000HZ, 3000HZ, 4000HZ, 4500HZ, 5000HZ, 6000HZ, 7000HZ, and any frequency greater than or equal to 750HZ, and less than or equal to any other frequency in the range of 7500HZ.
  • the duty ratio of the comparison signal ie, the periodic square wave signal obtained by comparing the reference voltage signal Vramp_T with the time signal Vdata_T by the comparator 210 is relatively stable.
  • the duration of light emission of the element 20 to be driven does not change due to the time when the reference voltage signal Vramp_T is input, so as to ensure that the brightness of the element 20 to be driven is the same as the preset brightness.
  • the display device when the display device is displaying, after each row of pixels is written and registered, the registered time signal Vdata_T can be directly compared with the reference voltage signal Vramp_T, which can directly emit light without waiting for the final The pixels of a row emit light after data is written.
  • the lag display can be avoided or improved, which is beneficial to realize the high-resolution display of the display device.
  • the duration control sub-circuit 200 further includes a duration writing sub-circuit 220 and a duration storage capacitor C2, and the first end of the duration writing sub-circuit 220 is connected to the duration signal Line 11, the second terminal is connected to the non-inverting input terminal 211 of the comparator 210, the first terminal of the duration storage capacitor C2 is connected to the second terminal of the duration writing sub-circuit 220 and the non-inverting input terminal 211 of the comparator 210, and the duration storage capacitor C2 The second terminal is grounded.
  • the duration writing sub-circuit 220 may also be connected to the inverting input terminal 212 of the comparator 210.
  • the first end of the duration storage capacitor C2 is connected to the duration writing sub-circuit 220. And the inverting input terminal 212 of the comparator 210, and the second terminal of the duration storage capacitor C2 is grounded.
  • the time storage capacitor C2 is used to register the time signal Vdata_T, so that the non-inverting input terminal 211 of the comparator 210 can obtain the time signal Vdata_T with a stable voltage within one frame.
  • the duration writing sub-circuit 220 includes a duration writing transistor T10.
  • the first pole of the duration write transistor T10 is connected to the duration signal line 11, the second pole is connected to the non-inverting input terminal 211 of the comparator 210, and the gate is connected to the data write control signal line 13.
  • the data write control signal line 13 inputs a data write control signal Gate to the gate.
  • the duration write transistor T10 is turned on, and the time signal Vdata_T is stored in the duration storage capacitor C2 connected to the non-inverting input terminal 211 after the duration write transistor T10.
  • the duration write transistor T10 is turned off.
  • the duration control sub-circuit 200 further includes a reference voltage writing transistor T9, and the reference signal line 12 is connected to the comparator 210 through the reference voltage writing transistor T9.
  • the first pole of the reference voltage writing transistor T9 is connected to the reference signal line 12
  • the second pole of the reference voltage writing transistor T9 is connected to the inverting input terminal 212 of the comparator 210
  • the gate of the reference voltage writing transistor T9 is connected to work
  • the control signal line 15 and the operation control signal line 15 write the operation control signal EM to the reference voltage writing transistor T9.
  • the reference voltage writing transistor T9 When the work control signal EM is at a low level, the reference voltage writing transistor T9 is turned on, and the reference voltage signal Vramp_T is input to the inverting input terminal 212 of the comparator 210. When the operation control signal EM is at a high level, the reference voltage writing transistor T9 is turned off.
  • the current control sub-circuit 100 includes a current writing sub-circuit 110 and a compensation sub-circuit 120.
  • the current writing sub-circuit 110 includes a current writing transistor T2.
  • the compensation sub-circuit 120 includes a compensation transistor T3, a current storage capacitor C1 and a first driving transistor T4.
  • the compensation sub-circuit 120 connects the current writing sub-circuit 110 and the output sub-circuit 300.
  • the first electrode of the first driving transistor T4 is connected to the current writing sub-circuit 110
  • the second electrode of the first driving transistor T4 is connected to the first electrode of the compensating transistor T3, and the gate of the first driving transistor T4 is connected to the compensating transistor T3.
  • the second pole is connected to the current storage capacitor C1 and connected to the power supply terminal VDD1 via the current storage capacitor C1.
  • the gate of the compensation transistor T3 is connected to the data writing control signal line 13.
  • the first pole of the current writing transistor T2 is connected to the current signal line 14
  • the second pole of the current writing transistor T2 is connected to the first pole of the first driving transistor T4 in the compensation sub-circuit 120, and the gate of the current writing transistor T2 is connected Data is written into the control signal line 13.
  • the current writing transistor T2, the duration writing transistor T10 and the compensation transistor T3 are all controlled by the data writing control signal line 13 to be turned on and off.
  • the data writing control signal Gate output by the data writing control signal line 13 is at a low level, the current writing transistor T2, the duration writing transistor T10, and the compensation transistor T3 are turned on.
  • the data writing control signal Gate output by the data writing control signal line 13 is at a high level, the current writing transistor T2, the duration writing transistor T10, and the compensation transistor T3 are turned off.
  • the current writing transistor T2 When the current writing transistor T2 is turned on, the current signal Vdata_I is written into the first pole of the first driving transistor T4 through the current writing transistor T2.
  • the first driving transistor T4 when its gate potential is lower than the first electrode potential, the first driving transistor T4 is turned on, and the current signal Vdata_I passes through the first driving transistor T4 and the compensation transistor T3 to the current storage capacitor C1 is charged, so as to realize the storage of the current signal Vdata_I by the current storage capacitor C1.
  • the voltage on the first electrode of the first driving transistor T4 remains Vdata_I, and the voltage on the gate of the first driving transistor T4 increases.
  • the first driving transistor T4T4 When the voltage on the gate of the first driving transistor T4 is Vdata+Vth, the first driving transistor T4T4 is turned off, where Vdata represents the voltage of the current signal Vdata_I, and Vth represents the threshold voltage of the first driving transistor T4.
  • the compensation sub-circuit 120 is not only used to store the current signal Vdata_I input by the current writing sub-circuit 110, but also used to store the threshold voltage Vth of the first driving transistor T4.
  • the current storage capacitor C1 is connected to the gate of the first driving transistor T4, and the compensation transistor T3 is connected to the second electrode of the first driving transistor T4.
  • the current storage capacitor C1 stores the threshold voltage Vth of the first driving transistor T4 and the current signal Vdata_I.
  • the threshold voltage Vth signal stored by the current storage capacitor C1 can compensate the first driving transistor T4, so that the current output by the first driving transistor T4 is only related to the current signal Vdata_I, and is not driven by the first drive.
  • Transistor T4 affects, thereby improving the accuracy of the output drive current.
  • the pixel driving circuit 10 also includes a power supply terminal VDD1.
  • the current control sub-circuit 100 When the current control sub-circuit 100 is turned on, that is, the current control sub-circuit 100 is connected to the power supply terminal VDD1, and the data writing control signal Gate is at a low level, the compensation transistor T3, the current writing transistor T2, and the first driver The transistor T4 is turned on.
  • the operating current generated by the first driving transistor T4 applied to the component to be driven 20 is:
  • ⁇ is the electron mobility
  • C ox is the gate oxide capacitance
  • VGS is the voltage of the gate relative to the source
  • the operating current generated by the first driving transistor T4 applied to the component 20 to be driven can directly determine the luminous intensity of the component 20 to be driven.
  • the formula shows that the size of the operating current of the first drive transistor threshold voltage Vth of T4 is irrelevant, but related to the characteristics ( ⁇ , C ox and VGS) and a first current signal Vdata_I driving transistor T4.
  • Vth of T4 is irrelevant, but related to the characteristics ( ⁇ , C ox and VGS) and a first current signal Vdata_I driving transistor T4.
  • the characteristics of the components 20 to be driven such as micro LEDs and mini LEDs, their luminous efficiency, brightness of emitted light, and color coordinates will vary with the current density at low current densities. Change, which in turn leads to display quality problems.
  • the first driving transistor T4 Since a current with a large current density can drive the component 20 to be driven to emit stable light, in order to ensure luminous efficiency, it may be considered to use a current with a large current density to drive the component 20 to be driven to emit light to display an image.
  • the current generated by the first driving transistor T4 must enable the component 20 to be driven to work in a high current density region, so as to avoid problems such as the main peak drifting with the current density and poor brightness uniformity at low current density. It is known through experiments that when the aspect ratio of the first driving transistor T4 is greater than 3, the uniformity of the brightness displayed by the element to be driven 20 is better. In an embodiment of the present disclosure, the aspect ratio of the first driving transistor T4 is 4. Of course, in some embodiments of the present disclosure, the aspect ratio of the first driving transistor T4 can also be any value greater than 3. , Such as 5, 6, 7, 8, 9.1 and so on.
  • the pixel driving circuit 10 further includes a work control sub-circuit 400, and the work control sub-circuit 400 includes a first control transistor T6 and a second control transistor T5. And the third control transistor T8.
  • the gates of the first control transistor T6, the second control transistor T5, and the third control transistor T8 are all connected to the work control signal line 15, and the work control signal line 15 is configured to connect to the first control transistor T6, the second control transistor T5, and the The three control transistors T8 transmit the work control signal EM to control the on and off of the first control transistor T6, the second control transistor T5, and the third control transistor T8.
  • the first pole of the first control transistor T6 is connected to the current control sub-circuit 100; the second pole of the first control transistor T6 is connected to the output sub-circuit 300.
  • the first control transistor T6 is configured to transmit the current signal Vdata_I to the output sub-circuit 300 when it is turned on.
  • the first pole of the second control transistor T5 is connected to the power supply terminal VDD1, and the second pole of the second control transistor T5 is connected to the current writing transistor T2 in the current writing sub-circuit 110.
  • the work control signal EM is at a low level
  • the second control transistor T5 is turned on, and the power supply terminal VDD1 is connected to the second pole of the current writing transistor T2.
  • a voltage can be provided to the current control sub-circuit 100.
  • the first pole of the third control transistor T8 is connected to the output sub-circuit 300, and the second pole of the third control transistor T8 is connected to the component 20 to be driven.
  • the third control transistor T8 is turned on, and the third control transistor T8 is configured to supply power to the original 20 to be driven, which can also be understood as transmitting the current signal Vdata_I and the time signal Vdata_T to the drive to be driven Element 20. That is, determine the current and light-emitting duration of the element 20 to be driven within a frame time, thereby determining the light-emitting intensity and light-emitting time of the element 20 to be driven, that is, determine the display brightness of the element 20 to be driven within the frame time.
  • the output sub-circuit 300 includes an output transistor T7, the first pole of the output transistor T7 is connected to the current control sub-circuit 100 through the first control transistor T6, and the second pole of the first control transistor T6 passes through the third
  • the control transistor T8 is connected to the component 20 to be driven.
  • the gate of the output transistor T7 is connected to the output terminal 213 of the comparator 210 in the duration control sub-circuit 200.
  • the pixel driving circuit 10 further includes a reset sub-circuit 500.
  • the reset sub-circuit 500 is connected to the current control sub-circuit 100 and is configured to reset the current control sub-circuit 100.
  • the reset sub-circuit 500 may also be connected to the duration control sub-circuit 200 and/or the component to be driven 20.
  • the reset sub-circuit 500 is configured to control the duration control sub-circuit 200 and /Or the brightness displayed by the component 20 to be driven is reset.
  • the reset sub-circuit 500 includes a reset transistor T1.
  • the gate of the reset transistor T1 is connected to the reset control line 16; the first pole of the reset transistor T1 is connected to the reset signal terminal 17, and the reset voltage Vint is input through the reset signal terminal 17.
  • the second pole of the reset transistor T1 is connected to the current storage capacitor C1 and the second pole of the compensation transistor T3.
  • the current storage capacitor C1 and the gate of the first driving transistor T4 can be reset, that is, the current control sub-circuit 100 can be reset, so as to eliminate the residual current data signal Vdata_I in the previous frame from the current frame. Influence.
  • the reset sub-circuit 500 is also connected to the duration control sub-circuit 200 and/or the component to be driven 20.
  • the second pole of the reset transistor T1 is connected to the duration storage capacitor C2 and/or the component to be driven 20.
  • other reset transistors can also be added.
  • FIG. 8 is a timing diagram of the pixel driving circuit 10 shown in FIG. 6, which is a signal timing diagram of the pixel driving circuit 10 of a row of pixels in one frame period. According to FIG. 8, the pixel driving circuit 10 needs to go through a reset phase, a data writing phase S2 and a light-emitting phase S3 in one frame period.
  • the reset stage S1 In the reset stage S1, only the reset control signal Rst output by the reset control line 16 is low, the reset transistor T1 is turned on, and all other transistors are turned off.
  • the pixel driving circuit 10 initializes the current storage capacitor C1, so that the potentials at both ends of the current storage capacitor C1 are the power supply terminal VDD1 and the reset voltage Vint, respectively.
  • the reset voltage Vint is applied to the gate of the first driving transistor T4 and the second pole of the compensation transistor T3 to clear the residual current signal Vdata_I of the previous frame, thereby improving the display accuracy of the current frame period.
  • the reset voltage Vint can be a low potential voltage, such as grounding.
  • a transistor marked with a double oblique dashed line in FIG. 8 indicates that the transistor is in an off state, and a transistor not marked with a double oblique dashed line indicates that the transistor is in an on state.
  • the time signal Vdata_T is written through the time-length writing transistor T10, and the time signal Vdata_T is written into the time-length storage capacitor C2 for storage and retention, and is input to the non-inverting input terminal 211 of the comparator 210 at the same time.
  • a transistor marked with a double oblique dashed line in FIG. 10 indicates that the transistor is in an off state
  • a transistor not marked with a double oblique dashed line indicates that the transistor is in an on state.
  • the current control sub-circuit 100 generates a working current of the element 20 to be driven, that is, a working current that is independent of the threshold voltage Vth of the first driving transistor T4.
  • the inverting input terminal 212 of the comparator 210 inputs a high-frequency ramp reference voltage signal Vramp_T, and the non-inverting input terminal 211 of the comparator 210 inputs the time signal Vdata_T stored in the time storage capacitor C2.
  • the output terminal 213 of the comparator 210 outputs a high level VDD2.
  • the output transistor T7 is turned off, and the driving element 20 does not emit light.
  • the output terminal 213 of the comparator 210 outputs a low level VSS2. At this time, the output transistor T7 is turned on, and the driving element 20 emits light.
  • a transistor marked with a double oblique dashed line in FIG. 11 indicates that the transistor is in an off state
  • a transistor not marked with a double oblique dashed line indicates that the transistor is in an on state.
  • the state of the output transistor T7 in FIG. 11 is controlled by the output signal of the output terminal 213 of the comparator 210, and it is not indicated as an off state.
  • FIG. 12 shows the timing diagram of FIG. 6, which is a signal timing diagram of the pixel driving circuit 10 of multiple rows of pixels in one frame period.
  • the display device 1 of this embodiment includes n rows of pixels 1, the subscripts of the signals indicated by Roman letters should be understood as the corresponding number of rows.
  • the reset control signal Rst1, the write control signal Gate1, and the work control signal EMEM1 all represent the signals input to the pixels 1 of the first row, that is, the signals input to the pixel driving circuit 10 of the pixels 1 of the first row.
  • the reset control signal Rstn, the write control signal Gaten, and the operation control signal EMn all represent signals input to the pixels 1 of the nth row, that is, signals input to the pixel driving circuit 10 of the pixels 1 of the nth row. And so on.
  • the work control signal EM before inputting a signal to the next row of pixels 1, it is necessary to input the work control signal EM to the row of pixels 1, so that the corresponding time signal Vdata_T and the reference voltage signal Vramp_T can be compared to determine the frame
  • the brightness of the component 20 to be driven within the time and the lighting of the pixels 1 in this row are controlled to avoid delayed display.
  • the relevant part can refer to the part of the description of the device embodiment.
  • the method embodiment and the device embodiment are complementary to each other.

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Abstract

一种像素驱动电路（10），用于向待驱动元件（20）提供信号，包括：电流控制子电路（100），配置为传输电流信号（Vdata_I）；时长控制子电路（200），配置为传输时间信号（Vdata_T）；以及输出子电路（300），分别电连接于时长控制子电路（200）和电流控制子电路（100）；其中，时长控制子电路（200）还配置为根据时间信号（Vdata_T），控制输出子电路（300）的导通与截止；输出子电路（300）配置为在导通时，根据电流信号（Vdata_I）控制施加给待驱动元件（20）的电流，其中，输出子电路（300）的相邻的两次导通的持续时间相同，并且，相邻的两次截止的持续时间相同。

Description

像素驱动电路和显示设备 技术领域
本公开的实施例涉及一种像素驱动电路和显示设备。
背景技术
微型无机发光二极管因为其高亮度、寿命长、体积小等优点，通常被应用于显示设备，在显示领域具有广阔的发展前景。但是，这样的显示设备中的微型无机发光二极管在某些场景下，例如：微型无机发光二极管在进行低灰阶(即低亮度)显示时，由于发光二极管在一帧的时间内发光总时长较短，且发光时间不均，会出现闪烁的现象。
发明内容
本公开的至少一个实施例提供了一种像素驱动电路，配置为向待驱动元件提供信号，所述像素驱动电路包括：电流控制子电路，配置为传输电流信号；时长控制子电路，配置为传输时间信号；以及输出子电路，分别与所述时长控制子电路和所述电流控制子电路电连接。其中，所述时长控制子电路还配置为根据所述时间信号，控制所述输出子电路的导通与截止，所述输出子电路配置为在导通时，根据所述电流信号控制施加给所述驱动元件的电流，其中，所述输出子电路的相邻的两次导通的持续时间相同，并且，所述输出子电路的相邻的两次截止的持续时间相同。
在本公开的一些实施例中，时长控制子电路包括比较器，所述比较器配置为对所述时间信号和基准电压信号进行比较以产生比较信号，并根据所述比较信号控制所述输出子电路的导通和截止，其中，所述比较信号为周期方波信号。
在本公开的一些实施例中，所述比较器包括同相输入端、反相输入端和输出端；所述同相输入端配置为接收所述时间信号和所述基准电压信号中的一个，所述反相输入端配置为所述接收时间信号和所述基准电压信号中的另一个；以及所述输出端连接所述输出子电路。
在本公开的一些实施例中，所述基准电压信号包括斜坡信号、三角波信号、锯齿波信号、正弦波信号以及余弦波信号中的一个。
在本公开的一些实施例中，所述基准电压信号为高频信号，所述基准电压信号 的频率大于等于750HZ，并且，小于等于7500HZ。
在本公开的一些实施例中，所述时长控制子电路还包括时长写入子电路和时长存储电容；所述时长写入子电路连接所述比较器的同相输入端或反相输入端；所述时长存储电容的第一端接地，所述时长存储电容的第二端连接至所述时长写入子电路并连接至所述比较器。
在本公开的一些实施例中，所述电流控制子电路包括电流写入子电路和补偿子电路，所述补偿子电路连接所述电流写入子电路和所述输出子电路；所述电流写入子电路的第一端配置为接收所述电流信号，所述电流写入子电路的第二端连接至所述补偿子电路，所述补偿子电路的第一端连接至所述电流写入子电路，所述补偿子电路的第二端连接至所述输出子电路。
在本公开的一些实施例中，所述补偿子电路包括：补偿晶体管、电流存储电容和第一驱动晶体管；所述第一驱动晶体管的第一极连接所述电流写入子电路，所述第一驱动晶体管的第二极连接所述补偿晶体管的第一极，所述第一驱动晶体管的栅极和所述补偿晶体管的第二极均连接所述电流存储电容，所述补偿晶体管的栅极连接数据写入控制信号线。
在本公开的一些实施例中，所述第一驱动晶体管的宽长比大于3。
在本公开的一些实施例中，所述电流写入子电路包括电流写入晶体管。
在本公开的一些实施例中，所述像素驱动电路还包括工作控制子电路，所述工作控制子电路包括第一控制晶体管；所述第一控制晶体管的第一极连接所述电流控制子电路；所述第一控制晶体管的第二极连接所述输出子电路；所述第一控制晶体的栅极连接工作控制信号线，所述工作控制线配置为向所述第一控制晶体管输入工作控制信号，以控制所述第一控制晶体管的导通和截止；其中，所述第一控制晶体管配置为在导通时，向所述输出子电路传输所述电流信号。
在本公开的一些实施例中，所述工作控制子电路还包括第二控制晶体管，所述第二控制晶体管的第一极连接电源端，所述第二控制晶体管的第二极连接所述电流控制子电路。
在本公开的一些实施例中，所述工作控制子电路还包括第三控制晶体管，所述第三控制晶体管的第一极连接所述输出子电路，以及所述第三控制晶体管的第二极连接所述待驱动元件。
在本公开的一些实施例中，所述输出子电路包括输出晶体管，所述输出晶体管的第一极连接第一控制晶体管第二极，所述输出晶体管的第二极连接所述第三控制晶体管的第一极。
在本公开的一些实施例中，所述像素驱动电路还包括复位子电路；所述复位子电路包括复位晶体管，所述复位晶体管的栅极连接复位控制线，所述复位晶体管的第一极连接复位信号端，所述复位晶体管的第二极连接所述电流控制子电路、所述时长控制子电路和所述待驱动元件中的至少一个，其配置为对所述电流控制子电路、所述时长控制子电路和所述待驱动元件进行复位。
本公开的至少一个实施例提供了一种显示设备，所述显示设备包括待驱动元件和上述的像素驱动电路，所述像素驱动电路配置为向所述待驱动元件提供信号，所述待驱动元件为电流驱动型发光二极管。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
图1为本公开一实施例的像素矩阵图。
图2为本公开一实施例的像素驱动电路的子电路框图。
图3为本公开一实施例的另一像素驱动电路的电路框图。
图4为发明人已知的一种像素驱动电路的结构示意图。
图5为图4所示的像素驱动电路的时序图。
图6是本公开一实施例的电路结构示意图。
图7A是本公开一实施例的比较信号的波形图。
图7B是本公开一实施例的比较信号的另一波形图。
图7C是本公开一实施例的比较信号的又一波形图。
图8是图6所示的像素驱动电路的时序图。
图9是本公开另一实施例的电路结构示意图。
图10是本公开又一实施例的电路结构示意图。
图11是本公开再一实施例的电路结构示意图。
图12是图6所示的像素驱动电路的另一时序图。
图13是图6所示的电路结构的具体结构图。
附图标记说明
像素1                显示设备2              像素驱动电路10
时长信号线11         时间信号Vdata_T        基准信号线12
基准电压信号Vramp_T  数据写入控制信号线13   数据写入控制信号Gate
电流信号线14         电流信号Vdata_I        工作控制信号线15
工作控制信号EM       复位控制线16           复位控制信号RST
复位信号端17         复位电压Vint           待驱动元件20
复位阶段S1           数据写入阶段S2         发光阶段S3
电流控制子电路100    电流写入子电路110      补偿子电路120
电流写入晶体管T2     补偿晶体管T3           第一驱动晶体管T4
电流存储电容C1       阈值电压Vth            时长控制子电路200
比较器210            同相输入端211          反相输入端212
输出端213            时长写入子电路220      基准电压写入晶体管T9
时长写入晶体管T10    时长存储电容C2         输出子电路300
输出晶体管T7         工作控制子电路400      第一控制晶体管T6
第二控制晶体管T5     第三控制晶体管T8       复位子电路500
复位晶体管T1         电源端VDD1
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”表示至少两个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本公开的至少一个实施例公开了一种显示设备，该显示设备应用于手机、电脑、平板、电子书、手表等具有显示功能的电子装置。
如图1所示，显示设备2包括多个呈阵列排布的像素1。显示设备2通过驱动每个像素1的发光元件发光以显示图像。将显示设备2的发光元件作为待驱动元件20，待驱动元件20为电流驱动型发光二极管，例如：微型发光二极管(micro LED)或者迷你发光二极管(mini LED)或者有机电致发光二极管OLED。在此情况下，下文所指的待驱动元件20的工作时长可以被理解为发光二极管的发光时长。像素1还包括像素驱动电路10，像素驱动电路10与待驱动元件20连接，像素驱动电路10配置为向待驱动元件20提供驱动信号，以在显示一帧图像的过程中控制流经待驱动元件20的电流和在一帧的时间内向待驱动元件20供电的总时长，从而在控制其发光强度和发光持续时间。
需要说明的是，由于显示设备2中的像素1的数量十分庞大，图1中仅示意了三行三列一共九个像素1。
图4示出了发明人已知的一种像素驱动电路的示意电路图。如图4所示，像素驱动电路10还包括连通晶体管T11，连通晶体管T11的第一端连接输出子电路300，连通晶体管T11的第二端连接待驱动元件20，连通晶体管T11由单独的工作控制信号EM进行控制。在工作控制信号EM为高电平的情况下，连通晶体管T11截止；在工作控制信号EM为低电平的情况下，连通晶体管T11导通。图5为图4的时序图。通常将以一帧的时间分为多个时段，图5中仅显示了三个时段，分别为Scan1、Scan2和Scan3。在图示的三个时段中，工作控制信号EM为低电平的子时段分别为t 1、t 2和t 3，其中，t 1、 t 2和t 3的长度均不相同。时长控制子电路200在一个时段中仅能输出一个恒定电压信号，从而控制输出子电路300在t 1、t 2和t 3子时段内的导通或者截止，进而决定待驱动元件20在t 1、t 2和t 3时间段内的发光或者不发光。假设一帧分为n个时段，那个n个时段内均有一段工作控制信号EM为低电平的子时间段，举例说明：第一个时段(Scan1)内工作控制信号EM为低电平的子时间段为t1，第n个时段(Scann)内工作控制信号EM为低电平的子时间段为t n。每一个时间段内的工作控制信号EM为低电平的子时段均不同，即，t 1≠t 2……≠t n。在上述设计中，像素驱动电路10仅能控制待驱动元件20在t 1、t 2、t 3至t n子时间段内发光或者不发光，从而决定待驱动元件20在整帧时间中发光的总时长，进而决定了待驱动元件20在这一帧中的亮度。但是，由于在一帧的时间内，待驱动元件20的相邻子时段内的发光时间不相同，或者一次点亮的时间过短，肉眼观察会出现闪烁的情况。举例说明，若在任意一帧中，待驱动元件20需要进行低亮度显示时，由于发光二极管在一帧的时间内发光总时长较短，例如：待驱动元件20仅在t 1和t n子时间段内点亮，在t 2至t n-1时间段内熄灭，下一帧亦是如此，如此循环，那么发光时间分布不均，相邻两次点亮间隔的时间过长且不均等，便容易出现肉眼可见的闪烁现象。
同时，每一个时段都需要对像素驱动电路10写入一次数据。那么，在一帧的时间内需向像素驱动电路10多次写入数据，写入数据占用了大量的时间。假设一帧包含n个时段，那么，在一帧的时间内，需要向像素驱动电路10写入数据n次。图5仅显示出三个时段，那么便对应写入数据三次，然而，通常一帧包括远不止三个时段。显示设备由多行像素1组成，数据写入的顺序为逐行写入。那么，若显示设备为高分辨率显示设备，那么，显示设备中像素1的个数也会增多，对应的行数也会对应增多，数据写入的时间便会增长。由此可知，在一帧的时间中，数据写入的时间占比过大，留给像素1中的发光元件发光的时间便会缩短。因此，上述设计无法应用于高分辨率显示。
本公开的至少一个实施例提供了一种像素驱动电路，配置为向待驱动元件提供信号，其中，所述像素驱动电路包括：电流控制子电路，配置为传输电流信号；时长控制子电路，配置为传输时间信号；输出子电路，分别电连接于所述时长控制子电路和所述电流控制子电路；其中，所述时长控制子电路还配置为根据所述时间信号，控制所述输出子电路的导通与截止；所述输出子电路配置为在导通时，根据所述电流信号控制驱动元件的电流；所述输出子电路的相邻的两次导通的持续时间相同，并且，相邻的两次截止的持续时间相同。
如图2和图3所示，根据本公开的一个实施例的像素驱动电路10包括电流控制子电路100、时长控制子电路200和输出子电路300。电流控制子电路100配置为传输电流信号Vdata_I。时长控制子电路200配置为传输时间信号Vdata_T。输出子电路300分别电连接于时长控制子电路200和电流控制子电路100。
时长控制子电路200还配置为根据时间信号Vdata_T，控制输出子电路300的导通与截止。输出子电路300配置为在导通时，根据电流信号Vdata_I控制流经待驱动元件20的电流。输出子电路300的相邻的两次导通的持续时间相同，并且，相邻的两次截止的持续时间相同。
如图2所示，在本公开的一个实施例中，时长控制子电路200可以根据时间信号Vdata_T，直接控制输出子电路300的导通与截止。在这种情况下，不需要利用工作控制信号来控制待驱动元件20的整体发光时间。并且，输出子电路300的相邻的两次导通的持续时间相同，相邻的两次截止的持续时间相同。换言之，将待驱动元件20在任意一帧中所需呈现的亮度转化为对应的该待驱动元件20在这一帧中所需点亮的时间长度，并将该时间长度均匀分配至整帧的时间长度中，避免其中一部分相邻的两次不发光的时间过短，另外一部分相邻的两次不发光的时间过长，从而减弱或者避免待驱动元件20在显示时候出现肉眼可见的闪烁现象，提升用户的体验感。
进一步的，在待驱动元件20需要被驱动发光的情况下，在一帧的时间内，输出子电路300的导通的次数应该大于等于10次。一帧内的导通次数可以为12次、14次、15次、18次、20次等。如图4和图5所示，如果在待驱动元件20在一帧的时间中发光总时长非常短的情况下，仅在t1、t2……tn之中的任意一段时间内进行显示，即导通的次数仅为1次，那么也会出现闪烁的现象。通过大量实验表明，在一帧的时间内，当输出子电路300的导通的次数大于等于10次时，便可减弱或者避免肉眼可见的闪烁。
如图6所示，时长控制子电路200包括比较器210，比较器210包括同相输入端211、反相输入端212和输出端213。同相输入端211和反相输入端212分别配置为接收时间信号Vdata_T和基准电压信号Vramp_T，输出端213连接输出子电路300。比较器210配置为比较时间信号Vdata_T和基准电压信号Vramp_T，并通过输出端213输出比较信号。比较器210还配置为根据比较信号以控制输出子电路300的导通与截止。图13更详细地示出了图6所示的电路结构，其中示出了比较器210的连接关系以及内部结构。
在本实施例中，同相输入端211连接时长信号线11，并配置为接收时间信号Vdata_T；反相输入端212连接基准信号线12，并配置为接收基准电压信号Vramp_T。 在这种电路结构中，在时间信号Vdata_T大于基准电压信号Vramp_T的情况下，比较器210输出的比较信号为低电平，即输出端213向输出子电路300传输低电平的比较信号，输出子电路300导通；载时间信号Vdata_T小于基准电压信号Vramp_T的情况下，比较器210输出的比较信号为高电平，即输出端213向输出子电路300传输高电平的比较信号，输出子电路300截止。当然，在本公开的一些实施例中，同相输入端211可以连接基准信号线12，并配置为接收基准电压信号Vramp_T；反相输入端212连接时长信号线11，并配置为接收时间信号Vdata_T。那么，在时间信号Vdata_T大于基准电压信号Vramp_T的情况下，比较器210输出的比较信号为高电平；在时间信号Vdata_T小于基准电压信号Vramp_T的情况下，比较器210输出的比较信号为低电平。
需要说明的是，比较信号为周期方波信号。仅在比较信号为周期方波信号的情况下，才能够保证输出子电路300的相邻的两次导通的时长相同，相邻的两次截止的时长相同，从而保证待驱动元件20在一帧的时间内，相邻的两次发光的时长相同，相邻的两次不发光的时长也相同。减弱或者避免待驱动元件20发光的情况下，在一帧的时间内出现肉眼可见的闪烁现象。
必要时结合图1所示，由于比较信号为周期方波信号，从而使得在一帧的时间内，针对一行像素1仅需要进行一次数据写入，便可实现待驱动元件20间隔性的发光和不发光。通过调节周期方波信号的占空比，便可调整待驱动元件20的在一帧中的发光时间，也就是说，即可调整待驱动元件20的在一帧中的显示亮度。由此可知，通过减少数据写入的次数，便可减小一帧的时间中用于写入数据的时间，那么，留给待驱动元件20发光的时间也会增大。当显示设备的分辨率提升时，像素1增多，对应的行数也增多，在一帧的时间中，每一行像素1只需要进行一次数据写入，每一个像素1仍具有足够的时间用于显示。因此，根据本公开实施例的显示设备可进行高分辨率显示。
在本公开的一个实施例中，比较器210得到的时间信号Vdata_T在一帧的时间内为一固定的电压值，基准电压信号Vramp_T为斜坡信号。通过上述设置，可保证比较器210输出的比较信号为周期方波信号。在实际使用过程中，可通过调节时间信号Vdata_T的大小，得到不同占空比的比较信号(即，周期方波信号)(参考图7A-图7C所示)。举例说明，若时间信号Vdata_T的电压值较大，那么，比较信号类似于如图7A所示，在一帧的时间中，待驱动元件20发光的总时长较长，此时，待驱动元件20的亮度较大。若时间信号Vdata_T的电压值较小，那么，比较信号类似于如图7B所示，在一帧的时间中，待驱动元件20发光的总时长较短，待驱动元件20的亮度较小。
当然，在本公开的一些实施例中，基准电压信号Vramp_T还可以为三角波信号、锯齿波信号、正弦波信号或者余弦波信号等等。
结合图1所示，显示设备2中的多个像素1呈阵列排布。在本公开的一个实施例中，基准电压信号Vramp_T的频率较低，为了保证每一行像素1接收到的基准电压信号Vramp_T对应的电压值相同，一般会在对所有行的像素1进行数据写入后，再写入基准电压信号Vramp_T。由于对每一行的像素1写入数据占用了一定的时间，位于前行的像素1显示会被滞后。举例说明，假设显示设备2具有n行像素1，那么，第一行像素1在被写入数据并寄存后，需要等待直至第n行像素1被写入数据后，才可以写入基准电压信号Vramp_T，之后再将寄存的时间信号Vdata_T与基准电压信号Vramp_T进行比较，最终决定每一像素1的发光情况。这样同样浪费了显示时间，不利于高分辨率显示。
进一步的，基准电压信号Vramp_T为高频信号。在本公开的一个实施例中，基准电压信号Vramp_T为高频斜坡信号。基准电压信号Vramp_T的频率大于等于750HZ，并且，小于等于7500HZ。在上述设置中，通过限制基准电压信号Vramp_T的频率，使其保持高频变化。在本公开的一个实施例中，基准电压信号Vramp_T的频率为800HZ，当然，在本公开的一些实施例中，基准电压信号Vramp_T的频率还可以为900HZ、1000HZ、1500HZ、2000HZ、3000HZ、4000HZ、4500HZ、5000HZ、6000HZ、7000HZ，以及大于等于750HZ，并且，小于等于7500HZ这个范围内的其他任意一个频率。那么，无论何时输入基准电压信号Vramp_T，通过比较器210对基准电压信号Vramp_T与时间信号Vdata_T进行比较得到的比较信号(即，周期方波信号)的占空比相对稳定。换言之，在一帧的时间中，待驱动元件20发光的时长不会因为输入基准电压信号Vramp_T的时间不同而发生变化，从而保证待驱动元件20的亮度与预设的亮度相同。在此情况下，当显示设备进行显示时，每一行像素在被写入数据并寄存后，便可直接将寄存的时间信号Vdata_T与基准电压信号Vramp_T进行比较，可以直接进行发光，无需等到对最后一行的像素被写入数据之后再发光。通过上述设置，可避免或者改善滞后显示，有利于实现显示设备的高分辨率显示。
在本公开的一个实施例中，如图3和图6所示，时长控制子电路200还包括时长写入子电路220和时长存储电容C2，时长写入子电路220的第一端连接时长信号线11，第二端连接比较器210的同相输入端211，时长存储电容C2的第一端连接至时长写入子电路220的第二端以及比较器210的同相输入端211，时长存储电容C2的第二 端接地。当然，在本公开的一些实施例中，时长写入子电路220还可连接于比较器210的反相输入端212，此时，时长存储电容C2的第一端连接至时长写入子电路220的第二端以及比较器210的反相输入端212，时长存储电容C2的第二端接地。在上述设置中，利用时长存储电容C2对时间信号Vdata_T进行寄存，使得在一帧的时间内，比较器210的同相输入端211能够得到电压稳定的时间信号Vdata_T。在本公开的一个实施例中，时长写入子电路220包括时长写入晶体管T10。时长写入晶体管T10的第一极连接时长信号线11，第二极连接比较器210的同相输入端211，栅极连接数据写入控制信号线13。数据写入控制信号线13向栅极输入数据写入控制信号Gate。在数据写入控制信号Gate为低电平的情况下，时长写入晶体管T10导通，时间信号Vdata_T经过时长写入晶体管T10存储到与同相输入端211连接的时长存储电容C2。在数据写入控制信号Gate为高电平的情况下，时长写入晶体管T10截止。
在本公开的一个实施例中，时长控制子电路200还包括基准电压写入晶体管T9，基准信号线12通过基准电压写入晶体管T9连接比较器210。其中，基准电压写入晶体管T9的第一极连接基准信号线12，基准电压写入晶体管T9的第二极连接比较器210的反相输入端212，基准电压写入晶体管T9的栅极连接工作控制信号线15，工作控制信号线15向基准电压写入晶体管T9写入工作控制信号EM。在工作控制信号EM为低电平的情况下，基准电压写入晶体管T9导通，并将基准电压信号Vramp_T输入至比较器210的反相输入端212。在工作控制信号EM为高电平的情况下，基准电压写入晶体管T9截止。
继续参考图3和图6，在本公开的一个实施例中，电流控制子电路100包括电流写入子电路110和补偿子电路120。电流写入子电路110包括电流写入晶体管T2。补偿子电路120包括补偿晶体管T3、电流存储电容C1和第一驱动晶体管T4。补偿子电路120连接电流写入子电路110和输出子电路300。其中，第一驱动晶体管T4的第一极连接电流写入子电路110，第一驱动晶体管T4的第二极连接补偿晶体管T3的第一极，第一驱动晶体管T4的栅极和补偿晶体管T3的第二极均连接电流存储电容C1并经由电流存储电容C1连接至电源端VDD1，补偿晶体管T3的栅极连接数据写入控制信号线13。电流写入晶体管T2的第一极连接电流信号线14，电流写入晶体管T2的第二极连接补偿子电路120中的第一驱动晶体管T4的第一极，电流写入晶体管T2的栅极连接数据写入控制信号线13。
电流写入晶体管T2、时长写入晶体管T10和补偿晶体管T3均由数据写入控制 信号线13控制其导通和截止。在数据写入控制信号线13输出的数据写入控制信号Gate为低电平的情况下，电流写入晶体管T2、时长写入晶体管T10和补偿晶体管T3导通。在数据写入控制信号线13输出的数据写入控制信号Gate为高电平的情况下，电流写入晶体管T2、时长写入晶体管T10和补偿晶体管T3截止。
在电流写入晶体管T2导通的情况下，电流信号Vdata_I通过电流写入晶体管T2写入第一驱动晶体管T4的第一极。鉴于第一驱动晶体管T4的自身特性，在其栅极电位低于第一极电位的情况下，第一驱动晶体管T4导通，电流信号Vdata_I经过第一驱动晶体管T4和补偿晶体管T3对电流存储电容C1进行充电，从而实现电流存储电容C1对电流信号Vdata_I的存储。第一驱动晶体管T4的第一极上的电压保持为Vdata_I，第一驱动晶体管T4栅极上的电压增大，当第一驱动晶体管T4栅极上的电压为Vdata+Vth时，第一驱动晶体管T4T4截止，其中，Vdata表示电流信号Vdata_I的电压，Vth表示第一驱动晶体管T4的阈值电压。
如图6所示，补偿子电路120不仅用于存储电流写入子电路110输入的电流信号Vdata_I，还用于存储第一驱动晶体管T4的阈值电压Vth。
继续参考图6所示，电流存储电容C1连接第一驱动晶体管T4的栅极，补偿晶体管T3连接第一驱动晶体管T4的第二极。在数据写入控制信号Gate的控制下，电流存储电容C1存储第一驱动晶体管T4的阈值电压Vth和电流信号Vdata_I。在一帧周期的发光时段中，电流存储电容C1存储的阈值电压Vth信号可对第一驱动晶体管T4进行补偿，使得第一驱动晶体管T4输出的电流只与电流信号Vdata_I相关，不受第一驱动晶体管T4影响，从而提高了输出的驱动电流的准确性。像素驱动电路10还包括电源端VDD1。在电流控制子电路100导通，即电流控制子电路100与电源端VDD1连通，并且，数据写入控制信号Gate为低电平的情况下，补偿晶体管T3、电流写入晶体管T2和第一驱动晶体管T4导通。第一驱动晶体管T4产生施加于待驱动元件20上工作电流为：
Figure PCTCN2021078857-appb-000001
需要说明的是，μ为电子迁移率、C ox为栅氧化层电容、VGS为栅极相对于源极 的电压、
Figure PCTCN2021078857-appb-000002
为第一驱动晶体管T4的宽长比。
第一驱动晶体管T4产生施加于待驱动元件20上工作电流可直接决定待驱动元件20的发光强度。根据公式可知，工作电流的大小与第一驱动晶体管T4的阈值电压Vth无关，反而与电流信号Vdata_I以及第一驱动晶体管T4的特性(μ、C ox和VGS)有关。同时，由于待驱动元件20的特性，如微型发光二极管(micro LED)和迷你发光二极管(mini LED)，其发光效率、发射光线的亮度以及色坐标在低电流密度下会随着电流密度变化而变化，进而导致显示品质问题。由于大电流密度的电流能驱动待驱动元件20发出稳定的光线，为了保证发光效率，可以考虑使用大电流密度的电流驱动待驱动元件20发光来显示图像。第一驱动晶体管T4产生的电流须使待驱动元件20工作在高电流密度区域，避免主波峰随着电流密度的变化而漂移，以及低电流密度下亮度均一性较差等问题。通过实验得知，在第一驱动晶体管T4的宽长比大于3的情况下，待驱动元件20显示的亮度的均一性较好。在本公开的一个实施例中，第一驱动晶体管T4的宽长比为4，当然，在本公开的一些实施例中，第一驱动晶体管T4的宽长比还可以为任意的大于3的数值，例如5、6、7、8、9.1等等。
进一步的，如图3和图6所示，在本公开的一个实施例中，像素驱动电路10还包括工作控制子电路400，工作控制子电路400包括第一控制晶体管T6、第二控制晶体管T5和第三控制晶体管T8。第一控制晶体管T6、第二控制晶体管T5和第三控制晶体管T8的栅极均连接工作控制信号线15，工作控制信号线15配置为分别向第一控制晶体管T6、第二控制晶体管T5和第三控制晶体管T8传输工作控制信号EM，以控制第一控制晶体管T6、第二控制晶体管T5和第三控制晶体管T8的导通和截止。
第一控制晶体管T6的第一极连接电流控制子电路100；第一控制晶体管T6的第二极连接输出子电路300。第一控制晶体管T6配置为在导通时，向输出子电路300传输电流信号Vdata_I。通过设置第一控制晶体管T6，可保证电流控制子电路100和时长控制子电路200的相对独立，避免两者的相互影响。
第二控制晶体管T5的第一极连接电源端VDD1，第二控制晶体管T5的第二极连接电流写入子电路110中的电流写入晶体管T2。在工作控制信号EM为低电平的情况下，第二控制晶体管T5导通，电源端VDD1与电流写入晶体管T2的第二极连通。通过设置第二控制晶体管T5，可对电流控制子电路100提供电压。
第三控制晶体管T8的第一极连接输出子电路300，第三控制晶体管T8的第二 连接待驱动元件20。在工作控制信号EM为低电平的情况下，第三控制晶体管T8导通，第三控制晶体管T8配置为待驱动原件20供电，也可以理解为将电流信号Vdata_I和时间信号Vdata_T传输至待驱动元件20。即决定待驱动元件20的在一帧的时间内的电流和发光时长，从而决定待驱动元件20的发光强度和发光时间，即，决定待驱动元件20在该帧时间内的显示亮度。
在本公开的一个实施例中，输出子电路300包括输出晶体管T7，输出晶体管T7的第一极通过第一控制晶体管T6连接电流控制子电路100，第一控制晶体管T6的第二极通过第三控制晶体管T8连接待驱动元件20。输出晶体管T7的栅极连接时长控制子电路200中的比较器210的输出端213。
进一步的，继续参考图3和图6所示，在本公开的一个实施例中，像素驱动电路10还包括复位子电路500。复位子电路500连接电流控制子电路100，其配置为对电流控制子电路100进行复位。在本公开的其他实施例中，复位子电路500还可以连接时长控制子电路200和/或待驱动元件20，在这种情况下，所述复位子电路500配置为对时长控制子电路200和/或待驱动元件20显示的亮度进行复位。在本公开的一个实施例中，复位子电路500包括复位晶体管T1。复位晶体管T1的栅极连接复位控制线16；复位晶体管T1的第一极连接复位信号端17，通过复位信号端17输入复位电压Vint。复位晶体管T1的第二极连接电流存储电容C1和补偿晶体管T3的第二极。在复位控制线16输出的复位控制信号Rst为高电平的情况下，复位晶体管T1截止。在复位控制线16输出的复位控制信号Rst为低电平的情况下，复位晶体管T1导通，复位电压Vint由电流存储电容C1进行存储。通过上述方式，可实现对电流存储电容C1、第一驱动晶体管T4的栅极的复位，即实现对电流控制子电路100的复位，以消除上一帧中残留的电流数据信号Vdata_I对当前帧的影响。在本公开的一些实施例中，复位子电路500还连接时长控制子电路200和/或待驱动元件20，此时，复位晶体管T1的第二极连接时长存储电容C2和/或待驱动元件20。当然，也可以增设其他的复位晶体管。
图8为图6所示的像素驱动电路10的时序图，其为一行像素的像素驱动电路10在一个帧周期内的信号时序图。根据图8可知，像素驱动电路10在一个帧周期内，需要经历复位阶段、数据写入阶段S2和发光阶段S3。
如图8和图9所示，在复位阶段S1中，仅有复位控制线16输出的复位控制信号Rst为低电平，复位晶体管T1导通，其余所有晶体管截止。此时，像素驱动电路10对电流存储电容C1进行初始化，从而使得电流存储电容C1两端的电位分别为电源端 VDD1和复位电压Vint。同时，复位电压Vint施加到第一驱动晶体管T4的栅极以及补偿晶体管T3的第二极，清除上一帧残留的电流信号Vdata_I，进而提高了当前帧周期的显示准确度。
需要说明的是，复位电压Vint是可以为低电位的电压，例如接地。图8中被划上双斜虚线的晶体管表示该晶体管处于截止状态，未被划上双斜虚线的晶体管表示该晶体管处于导通状态。
如图8和图10所示，在数据写入阶段S2中，仅有数据写入控制信号Gate为低电平。电流写入晶体管T2、时长写入晶体管T10和补偿晶体管T3导通，同时，由于第一驱动晶体管T4的栅极的电压小于第一极的电压与阈值电压Vth的总和，第一驱动晶体管T4也处于导通状态。其余所有晶体管截止。此时，电流信号Vdata_I通过电流写入晶体管T2写入，第一驱动晶体管T4处于饱和导通状态，其栅极的电压变为Vdata+Vth。该电压由电流存储电容C1进行存储和保持。时间信号Vdata_T通过时长写入晶体管T10写入，时间信号Vdata_T写入时长存储电容C2进行存储和保持，并同时输入比较器210的同相输入端211。
需要说明的是，图10中被划上双斜虚线的晶体管表示该晶体管处于截止状态，未被划上双斜虚线的晶体管表示该晶体管处于导通状态。
如图8和图11所示，必要时参考图6所示，在发光阶段S3中，仅有工作控制信号EM为低电平。第一驱动晶体管T4、基准电压写入晶体管T9、第一控制晶体管T6、第二控制晶体管T5和第三控制晶体管T8均导通。电流控制子电路100产生待驱动元件20的工作电流，即产生与第一驱动晶体管T4的阈值电压Vth无关的工作电流。在时长控制子电路200中，比较器210的反相输入端212输入高频斜坡的基准电压信号Vramp_T，比较器210的同相输入端211输入存储于时间存储电容C2中的时间信号Vdata_T。在基准电压信号Vramp_T＞时间信号Vdata_T的情况下，比较器210的输出端213输出高电平VDD2，此时，输出晶体管T7截止，待驱动元件20不发光。在基准电压信号Vramp_T＜时间信号Vdata_T的情况下，比较器210的输出端213输出低电平VSS2，此时，输出晶体管T7导通，待驱动元件20发光。
需要说明的是，图11中被划上双斜虚线的晶体管表示该晶体管处于截止状态，未被划上双斜虚线的晶体管表示该晶体管处于导通状态。图11中的输出晶体管T7的状态受比较器210的输出端213的输出信号的控制，并未将为表示为截止状态。
图12示出了图6的时序图，其为多行像素的像素驱动电路10在一个帧周期内的信号时序图。结合图1所示，假设本实施例的显示设备1包括n行像素1，信号的用罗马字母示意的下角标应该被理解为对应的行数。举例说明：复位控制信号Rst1、写入控制信号Gate1和工作控制信号EMEM1均表示对第一行像素1输入的信号，即向第一行像素1的像素驱动电路10输入的信号。复位控制信号Rstn、写入控制信号Gaten和工作控制信号EMn均表示对第n行像素1输入的信号，即向第n行像素1的像素驱动电路10输入的信号。以此类推。同时，如图可知，在对下一行像素1输入信号之前，均需要对该行像素1先输入工作控制信号EM，使得对应的时间信号Vdata_T和基准电压信号Vramp_T可进行比较，以决定该帧的时间内待驱动元件20的亮度，并控制这一行像素1的点亮，避免延时显示。
对于方法实施例而言，由于其基本对应于装置实施例，所以相关之处参见装置实施例的部分说明即可。方法实施例和装置实施例互为补充。
以上所述仅为本公开的实施例而已，并不用以限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开保护的范围之内。

Claims (16)

  1. 一种像素驱动电路，配置为向待驱动元件提供信号，包括：
    电流控制子电路，配置为传输电流信号；
    时长控制子电路，配置为传输时间信号；以及
    输出子电路，分别电连接于所述时长控制子电路和所述电流控制子电路；
    其中，所述时长控制子电路还配置为根据所述时间信号，控制所述输出子电路的导通与截止；
    所述输出子电路配置为在导通时，根据所述电流信号控制施加给所述待驱动元件的电流，其中，所述输出子电路的相邻的两次导通的持续时间相同，并且，相邻的两次截止的持续时间相同。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述时长控制子电路包括比较器，
    所述比较器配置为对所述时间信号和基准电压信号进行比较以产生比较信号，并根据所述比较信号控制所述输出子电路的导通和截止，其中，所述比较信号为周期方波信号。
  3. 根据权利要求2所述的像素驱动电路，其中，
    所述比较器包括同相输入端、反相输入端和输出端；
    所述同相输入端配置为接收所述时间信号和所述基准电压信号中的一个，
    所述反相输入端配置为接收时间信号和基准电压信号中的另一个；
    所述输出端连接所述输出子电路。
  4. 根据权利要求3所述的像素驱动电路，其中，所述基准电压信号包括斜坡信号、三角波信号、锯齿波信号、正弦波信号以及余弦波信号中的一个。
  5. 根据权利要求4所述的像素驱动电路，其中，所述基准电压信号为高频信号，所述基准电压信号的频率大于等于750HZ，并且，小于等于7500HZ。
  6. 根据权利要求3至5中任何一项所述的像素驱动电路，其中，
    所述时长控制子电路还包括时长写入子电路和时长存储电容；
    所述时长写入子电路连接所述比较器的所述同相输入端或者所述反相输入端；
    所述时长存储电容的第一端接地，所述时长存储电容的第二端连接至所述时长写入子电路并连接至所述比较器。
  7. 根据权利要求1至6中任何一项所述的像素驱动电路，其中，
    所述电流控制子电路包括电流写入子电路和补偿子电路，
    所述电流写入子电路的第一端配置为接收所述电流信号，所述电流写入子电路的第二端连接至所述补偿子电路，
    所述补偿子电路的第一端连接至所述电流写入子电路，所述补偿子电路的第二端连接至所述输出子电路。
  8. 根据权利要求7所述的像素驱动电路，其中，
    所述补偿子电路包括：补偿晶体管、电流存储电容和第一驱动晶体管；
    所述第一驱动晶体管的第一极连接所述电流写入子电路，
    所述第一驱动晶体管的第二极连接所述补偿晶体管的第一极，
    所述第一驱动晶体管的栅极和所述补偿晶体管的第二极均连接所述电流存储电容，
    所述补偿晶体管的栅极连接数据写入控制信号线。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一驱动晶体管的宽长比大于3。
  10. 根据权利要求7至9中任何一项所述的像素驱动电路，其中，所述电流写入子电路包括电流写入晶体管。
  11. 根据权利要求1至10中任何一项所述的像素驱动电路，其中，所述像素驱动电路还包括工作控制子电路，
    所述工作控制子电路包括第一控制晶体管；
    所述第一控制晶体管的第一极连接所述电流控制子电路；
    所述第一控制晶体管的第二极连接所述输出子电路；
    所述第一控制晶体的栅极连接工作控制信号线，所述工作控制线配置为向所述第一控制晶体管输入工作控制信号，以控制所述第一控制晶体管的导通和截止；
    其中，所述第一控制晶体管配置为在导通时，向所述输出子电路传输所述电流信号。
  12. 根据权利要求11所述的像素驱动电路，其中，
    所述工作控制子电路还包括第二控制晶体管，
    所述第二控制晶体管的第一极连接电源端，
    所述第二控制晶体管的第二极连接所述电流控制子电路。
  13. 根据权利要求11或12所述的像素驱动电路，其中，
    所述工作控制子电路还包括第三控制晶体管，
    所述第三控制晶体管的第一极连接所述输出子电路，以及
    所述第三控制晶体管的第二极连接所述待驱动元件。
  14. 根据权利要求13中所述的像素驱动电路，其中，
    所述输出子电路包括输出晶体管，
    所述输出晶体管的第一极连接第一控制晶体管第二极，
    所述输出晶体管的第二极连接所述第三控制晶体管的第一极。
  15. 根据权利要求1至14中任何一项所述的像素驱动电路，其中，所述像素驱动电路还包括复位子电路；
    所述复位子电路包括复位晶体管，
    所述复位晶体管的栅极连接复位控制线，
    所述复位晶体管的第一极连接复位信号端，
    所述复位晶体管的第二极连接所述电流控制子电路、所述时长控制子电路和所述待驱动元件中的至少一个，其配置为对所述电流控制子电路、所述时长控制子电路和所述待驱动元件进行复位。
  16. 一种显示设备，包括待驱动元件和根据权利要求1-15中任意一项所述的像素驱动电路，所述像素驱动电路配置为向所述待驱动元件提供信号，所述待驱动元件为电流驱动型发光二极管。
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