WO2021185040A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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WO2021185040A1
WO2021185040A1 PCT/CN2021/077837 CN2021077837W WO2021185040A1 WO 2021185040 A1 WO2021185040 A1 WO 2021185040A1 CN 2021077837 W CN2021077837 W CN 2021077837W WO 2021185040 A1 WO2021185040 A1 WO 2021185040A1
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layer
forming
etching
semiconductor structure
electrode layer
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French (fr)
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陆勇
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/043—Manufacture or treatment of capacitors having no potential barriers using patterning processes to form electrode extensions, e.g. etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • each memory cell usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the opening and closing of the transistor, so that the storage can be read through the bit line Data information in the capacitor, or write data information into the capacitor.
  • a method that can be adopted is to increase the height of the bottom electrode or reduce the thickness of the bottom electrode.
  • increasing the height of the bottom electrode or reducing the thickness of the bottom electrode will result in a relatively high length and a thinner thickness of the bottom electrode, which will affect the performance reliability of the capacitor array area. For example, it may cause the lower electrode to collapse or overturn, causing the adjacent lower electrode to short-circuit.
  • a lateral continuous support layer of the electrode can be added to increase the stability of the lower electrode.
  • the single-layer lateral support layer has its height limit, so that the capacitance value of the capacitor is limited by the electrode height, and the risk of electrode overturning and collapse of the sheet still exists.
  • the present application provides a method for forming a semiconductor structure and a semiconductor structure, which are used to solve the problem of poor lateral stability of the capacitor array region in the semiconductor structure, so as to reduce the risk of collapse or overturning of the lower electrode and improve the performance stability of the semiconductor device.
  • the present application provides a method for forming a semiconductor structure, which includes the following steps:
  • the substrate has a capacitive contact
  • the laminated structure includes a supporting layer and a sacrificial layer alternately stacked in a direction perpendicular to the substrate;
  • a dielectric layer covering the surface of the first electrode layer and the remaining laminated structure and a second electrode layer covering the surface of the dielectric layer are formed to form a capacitor.
  • the specific steps of forming a laminated structure on the surface of a substrate include:
  • a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer are sequentially deposited along a direction perpendicular to the substrate.
  • the first electrode layer covers the inner wall of the capacitor hole and the surface of the buffer layer; the specific steps of forming an etching window penetrating the buffer layer and exposing the laminated structure include:
  • the first electrode layer and the buffer layer are sequentially etched along the etching pattern to form an etching window exposing the third support layer.
  • the specific steps of removing part of the supporting layer and all of the sacrificial layer in the laminated structure along the etching window include:
  • the first sacrificial layer is removed along the second opening.
  • one etching window overlaps three or more capacitor holes.
  • the specific steps of forming the first opening exposing the second sacrificial layer include:
  • a portion of the third support layer is removed along the etching pattern to form a first opening exposing the second sacrificial layer.
  • the specific step of removing part of the supporting layer and all of the sacrificial layer in the laminated structure along the etching window further includes:
  • the first electrode layer covering the surface of the buffer layer is removed to expose the buffer layer.
  • the specific steps of forming a dielectric layer covering the surface of the first electrode layer and the remaining laminated structure, and a second electrode layer covering the surface of the dielectric layer include:
  • a conductive layer covering the surface of the second electrode layer is formed.
  • the thickness of the third supporting layer is greater than the thickness of the second supporting layer.
  • the present application also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure as described in any one of the above.
  • a buffer layer is formed on the surface of the laminated structure, so that the supporting layer on the top can be protected during the etching process, so that all supporting layers in the initially formed laminated structure At least part of the sidewalls of the first electrode layer can be retained, so that the finally formed capacitor has a sufficient height, avoiding the limitation of the capacitor height by the single-layer lateral support layer in the prior art, and improving the lateral stability of the capacitor array area. Performance, thereby improving the electrical performance of the semiconductor structure. Moreover, by providing multiple lateral support layers, it helps to further reduce the thickness of the first electrode layer, thereby effectively increasing the capacitance value of the capacitor.
  • Fig. 1 is a flowchart of a method for forming a semiconductor structure in a specific embodiment of the present application
  • Figures 2A-2P are schematic cross-sectional views of main processes in the process of forming a semiconductor structure in specific embodiments of the present application.
  • FIG. 1 is a flowchart of a method for forming a semiconductor structure in a specific embodiment of this application. Schematic diagram of the main process section. As shown in FIGS. 1 and 2A-2P, the method for forming a semiconductor structure provided in this embodiment includes the following steps:
  • Step S11 forming a laminated structure on the surface of a substrate, the substrate has capacitive contacts, and the laminated structure includes alternately stacking support layers and sacrificial layers in a direction perpendicular to the substrate, as shown in FIG. 2A Shown.
  • the specific number of layers of the supporting layer and the sacrificial layer stacked in the laminated structure can be set by those skilled in the art according to actual needs.
  • the number of layers of the support layer in the laminated structure is at least three, and correspondingly, the layer of the sacrificial layer The number is at least two floors.
  • the specific steps of forming a laminated structure on the surface of a substrate include:
  • a first supporting layer 20, a first sacrificial layer 21, a second supporting layer 22, a second sacrificial layer 23, and a third supporting layer 24 are sequentially deposited on the surface of the substrate in a direction perpendicular to the substrate, as shown in FIG. 2A Shown.
  • the substrate has a plurality of active regions arranged in an array, and the capacitive contacts are electrically connected to the active regions.
  • the first supporting layer 20, the first sacrificial layer 21, the second supporting layer 22, the second sacrificial layer 23, the The third supporting layer 24 is stacked one after another.
  • the materials of the first support layer 20, the second support layer 22, and the third support layer 24 may be the same, for example, all are nitride materials (such as silicon nitride).
  • the materials of the first sacrificial layer 21 and the second sacrificial layer 23 may also be the same, for example, both are oxide materials (such as silicon oxide).
  • Step S12 forming a buffer layer 25 on the surface of the laminated structure away from the substrate, as shown in FIG. 2A.
  • the material of the buffer layer 25 may be an organic material, such as carbon.
  • Step S13 forming a capacitor hole 26 penetrating the laminated structure and the buffer layer 25 and exposing the capacitor contact, as shown in FIG. 2B and FIG. 2C, and FIG. 2B is a schematic cross-sectional view of FIG. 2C along the dashed line.
  • a dry etching process or a wet etching process may be used to form the buffer layer 25 and penetrating through the buffer layer 25 in a direction perpendicular to the substrate.
  • the capacitor hole 26 of the laminated structure exposes the capacitor contact in the substrate through the capacitor hole.
  • Step S14 forming a first electrode layer 27 covering the inner wall of the capacitor hole 26 and contacting the capacitor contact, as shown in FIG. 2D and FIG. 2E.
  • FIG. 2D is a schematic cross-sectional view of FIG. 2E along the dashed line.
  • Step S15 forming an etching window penetrating the buffer layer 25 and exposing the laminated structure.
  • first electrode layer 27 may be, but is not limited to, titanium nitride, and the thickness of the first electrode layer 27 can be set by those skilled in the art according to actual needs.
  • the first electrode layer 27 covers the inner wall of the capacitor hole 26 and the surface of the buffer layer 25, as shown in FIG. 2D and FIG. 2E;
  • the specific steps of etching the window include:
  • the first electrode layer 27 and the buffer layer 25 are sequentially etched along the etching pattern to form an etching window exposing the third support layer 24.
  • the third support layer 24 is etched.
  • the mask layer may be a hard mask layer, and the mask layer may be a single-layer mask layer or a stack of multiple mask layers.
  • the mask layer includes the first sub-mask layer 28 and the second sub-mask layer 29 as an example for description.
  • the material of the first sub-mask layer 28 may be a nitride material, such as silicon nitride; the material of the second sub-mask layer 29 may be an oxide or an oxynitride material.
  • a photoresist layer 30 is formed on the surface of the second sub-mask layer 29 away from the first sub-mask layer 28
  • the photoresist layer 30 has an etching opening 301 exposing the second sub-mask layer 29, as shown in FIG. 2G and FIG. 2H.
  • FIG. 2G is a schematic cross-sectional view of FIG. 2H along the dashed line.
  • the second sub-mask layer 29 and the first sub-mask layer 28 are etched along the etching opening 301 to form the second sub-mask layer 29 and the first sub-mask layer.
  • Step S16 removing part of the supporting layer and all of the sacrificial layer in the laminated structure along the etching window, as shown in FIG. 2L.
  • the specific steps of removing part of the supporting layer and all of the sacrificial layer in the laminated structure along the etching window include:
  • a portion of the third support layer 24 etched along the etching window forms a first opening 31 exposing the second sacrificial layer 23, and the remaining third support layer 24 and the first electrode layer 27 ⁇ sidewall connection, as shown in Figure 2I;
  • a portion of the second support layer 22 is etched along the first opening 31 to form a second opening exposing the first sacrificial layer 21, as shown in FIG. 2K;
  • the first sacrificial layer 21 is removed along the second opening, as shown in FIG. 2L.
  • the specific steps of forming the first opening 31 exposing the second sacrificial layer 23 include:
  • a portion of the third support layer 24 is removed along the etching pattern to form a first opening 31 exposing the second sacrificial layer 23.
  • the first electrode layer 27 is selectively etched along the etching window, so that the top surface of the first electrode layer 27 in the area overlapping the etching pattern and the third support The bottom surface of the layer 24 is flush to facilitate subsequent etching of the buffer layer 25 and the third support layer 24.
  • the buffer layer 25 and the third support layer 24 are selectively etched along the etching pattern to form a first opening 31 exposing the second sacrificial layer 23.
  • the third support layer 24 (the third support layer 24 shown in the dashed frame in FIG. 2I) is vertically connected to the sidewall of the first electrode layer 27 to support the first electrode layer.
  • the second sub-mask layer 29 may be removed first. Then, a wet etching process is used to remove all the second sacrificial layer 23 from the first opening 31 to obtain a structure as shown in FIG. 2J. After that, a portion of the second supporting layer 22 is etched along the first opening 31 to form the second opening exposing the first sacrificial layer 21, as shown in FIG. 2K. The remaining second support layer 22 is vertically connected to the sidewall of the first electrode layer 27 to support the first electrode layer 27. Next, a wet etching process is used to remove all of the first sacrificial layer 21 from the second opening to obtain a structure as shown in FIG. 2L.
  • the specific step of removing part of the supporting layer and all of the sacrificial layer in the laminated structure along the etching window further includes:
  • the first electrode layer 27 covering the surface of the buffer layer 25 is removed, and the buffer layer 25 is exposed.
  • the first supporting layer 20, the second supporting layer 22, the third supporting layer 24 and the first sub-mask layer 28 in the laminated structure are all made of the same nitride Made of material (such as silicon nitride).
  • part of the first sub-mask layer 28 is also etched away, and is covered by the buffer layer 25 and is not in contact with each other.
  • the third supporting layer 24 in the overlapped area of the etching window is not etched.
  • the remaining first sub-mask layer 28 is also etched away, thereby exposing the top of the buffer layer 25
  • the first electrode layer 27 on the surface uses the buffer layer 25 as an etching stop layer, and the first electrode layer 27 covering the surface of the buffer layer 25 is etched away to expose the buffer layer 25.
  • the material of the first sub-mask layer 28 can also set the material of the first sub-mask layer 28 to be different from the material of the third support layer 24 and the second support layer 22 in the laminated structure according to actual needs. Therefore, the removal process of the first sub-mask layer 28 is performed separately from the etching process of the third support layer 24 and the second support layer 22.
  • the sequence of removing the first sub-mask layer 28, the third support layer 24, the second support layer 22, the second sacrificial layer 23, and the first sacrificial layer 21 It is not limited, and those skilled in the art can make selections according to actual needs.
  • step S17 the buffer layer 25 is removed, and the first electrode layer 27 protrudes above the remaining laminated structure, as shown in FIG. 2M.
  • the buffer layer 25 is etched away by using the third support layer 24 as an etch stop layer, so that a portion of the first electrode layer 27 protrudes above the remaining third support layer 24 , Thereby increasing the height of the first electrode layer 27.
  • the first electrode layer with a higher height can be 27 for stable support, thereby enhancing the lateral stability of the capacitor array area.
  • the thickness of the first electrode layer 27 can be correspondingly reduced, thereby increasing the capacitance value of the capacitor.
  • Step S18 forming a dielectric layer 32 covering the surface of the first electrode layer 27 and the remaining laminated structure, and a second electrode layer 33 covering the surface of the dielectric layer 32 to form a capacitor, as shown in FIG. 2N, As shown in Figure 2O.
  • the specific steps of forming the dielectric layer 32 covering the surface of the first electrode layer 27 and the remaining laminated structure and the second electrode layer 33 covering the surface of the dielectric layer 32 include:
  • a conductive layer 34 covering the surface of the second electrode layer 33 is formed, as shown in FIG. 2P.
  • the material of the dielectric layer 32 is preferably a material with a relatively high dielectric constant.
  • the material of the second electrode layer 33 may be the same as the material of the first electrode layer 27, for example, both are titanium nitride.
  • the material of the conductive layer 34 may be, but is not limited to, polysilicon material.
  • the thickness of the third supporting layer 24 is greater than the thickness of the second supporting layer 22.
  • the thickness of the third support layer 24 helps to support the top of the first electrode layer 27 and improves the first electrode layer 27. Stability at the top.
  • Those skilled in the art can also set the thickness of the first sacrificial layer 21 to be greater than the thickness of the second sacrificial layer 23 as needed, which also helps to support the top of the first electrode layer 27.
  • this embodiment also provides a semiconductor structure, which is formed by the method for forming a semiconductor structure as described in any one of the above.
  • a semiconductor structure which is formed by the method for forming a semiconductor structure as described in any one of the above.
  • FIG. 2P For a schematic diagram of the semiconductor structure provided in this specific embodiment, refer to FIG. 2P.
  • the method for forming a semiconductor structure and the semiconductor structure provided in this embodiment mode form a buffer layer on the surface of the stacked structure, so that the supporting layer on the top can be protected during the etching process, so that all of the initially formed stacked structure
  • the supporting layer can retain at least part of the sidewall of the first electrode layer, so that the finally formed capacitor has a sufficient height, avoiding the limitation of the capacitor height by the single-layer lateral supporting layer in the prior art, and increasing the lateral direction of the capacitor array area.
  • the stability of the semiconductor structure improves the electrical performance of the semiconductor structure.
  • by providing multiple lateral support layers it is helpful to further reduce the thickness of the first electrode layer, thereby effectively increasing the capacitance value of the capacitor.

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Abstract

一种半导体结构的形成方法及半导体结构。所述半导体结构的形成方法包括如下步骤：形成叠层结构于一衬底表面，所述叠层结构包括交替叠置的支撑层和牺牲层；形成缓冲层（25）于所述叠层结构背离所述衬底的表面；形成贯穿所述叠层结构和所述缓冲层（25）并暴露电容触点的电容孔（26）；形成覆盖所述电容孔（26）内壁的第一电极层（27）；形成贯穿所述缓冲层（25）的刻蚀窗口；沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层；去除所述缓冲层（25），所述第一电极层（27）凸出于残留的所述叠层结构之上；形成电介质层（32）、以及第二电极层（33），形成电容器。所述半导体结构提高了电容阵列区域横向的稳定性，并能有效提高电容器的电容值。

Description

半导体结构的形成方法及半导体结构
相关申请引用说明
本申请要求于2020年3月16日递交的中国专利申请号202010181067.5、申请名为“半导体结构的形成方法及半导体结构”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的形成方法及半导体结构。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体结构，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启与关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
随着半导体器件尺寸的微缩，其在衬底上的横向面积减小。为了提高或者维持电容器具有足够高的电容值，可以采用的做法是增加下电极(bottom electrode)的高度或者是减小下电极的厚度。但是，增加下电极的高度或者是减小下电极的厚度会导致下电极的长径比较高，厚度较薄，从而对电容阵列区域的性能可靠性造成影响。比如，会引起下电极的坍塌或者倾覆，导致相邻的下电极短路。为了解决这一问题，可以通过添加电极的横向连续支撑层，以增加下电极的稳定性。但是，单层横向支撑层有其高度极限，从而使得电容器的电容值受到电极高度的限制，电极倾覆和成片坍塌的风险依然存在。
因此，如何解决电容阵列区域横向不稳定的问题，减小下电极坍塌或者倾覆的风险，提高半导体器件的性能稳定性，是目前亟待解决的技术问题。
发明内容
本申请提供一种半导体结构的形成方法及半导体结构，用于解决半导体结构中电容阵列区域横向稳定性较差的问题，以减小下电极坍塌或者倾覆的风险，提高半导体器件的性能稳定性。
为了解决上述问题，本申请提供了一种半导体结构的形成方法，包括如下步骤：
形成叠层结构于一衬底表面，所述衬底内具有电容触点，所述叠层结构包括沿垂直于所述衬底的方向交替叠置的支撑层和牺牲层；
形成缓冲层于所述叠层结构背离所述衬底的表面；
形成贯穿所述叠层结构和所述缓冲层并暴露所述电容触点的电容孔；
形成覆盖所述电容孔内壁并与所述电容触点接触的第一电极层；
形成贯穿所述缓冲层并暴露所述叠层结构的刻蚀窗口；
沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层，至少残留三层所述支撑层与所述第一电极层的侧壁连接；
去除所述缓冲层，所述第一电极层凸出于残留的所述叠层结构之上；
形成覆盖于所述第一电极层和残留的所述叠层结构表面的电介质层、以及覆盖于所述电介质层表面的第二电极层，形成电容器。
可选的，形成叠层结构于一衬底表面的具体步骤包括：
提供一衬底，所述衬底内部具有电容触点；
沿垂直于所述衬底的方向依次沉积第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层。
可选的，所述第一电极层覆盖所述电容孔内壁和所述缓冲层表面；形成贯穿所述缓冲层并暴露所述叠层结构的刻蚀窗口的具体步骤包括：
形成覆盖所述第一电极层表面的掩膜层，所述掩膜层中具有暴露所述第一电极层的刻蚀图案；
沿所述刻蚀图案依次刻蚀所述第一电极层和所述缓冲层，形成暴露所述第三支撑层的刻蚀窗口。
可选的，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤包括：
沿所述刻蚀窗口刻蚀部分的所述第三支撑层，形成暴露所述第二牺牲层的第一开口，残留的所述第三支撑层与所述第一电极层的侧壁连接；
沿所述第一开口去除所述第二牺牲层，暴露所述第二支撑层；
沿所述第一开口刻蚀部分的所述第二支撑层，形成暴露所述第一牺牲层的 第二开口；
沿所述第二开口去除所述第一牺牲层。
可选的，一个所述刻蚀窗口与三个及以上的所述电容孔交叠。
可选的，形成暴露所述第二牺牲层的第一开口的具体步骤包括：
去除与所述刻蚀图案交叠区域的部分所述第一电极层；
沿所述刻蚀图案去除部分的所述缓冲层；
沿所述刻蚀图案去除部分的所述第三支撑层，形成暴露所述第二牺牲层的第一开口。
可选的，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤还包括：
沿所述刻蚀窗口刻蚀部分所述第三支撑层的同时、刻蚀部分所述掩膜层；
沿所述第一开口刻蚀部分的所述第二支撑层的同时、刻蚀掉残留的所述掩膜层，暴露所述第一电极层；
去除覆盖于所述缓冲层表面的所述第一电极层，暴露所述缓冲层。
可选的，形成覆盖于所述第一电极层和残留的所述叠层结构表面的电介质层、以及覆盖于所述电介质层表面的第二电极层的具体步骤包括：
形成覆盖所述第一电极层、残留的所述第三支撑层、残留的所述第二支撑层、以及所述第一支撑层表面的电介质层；
形成覆盖所述电介质层表面的第二电极层；
形成覆盖所述第二电极层表面的导电层。
可选的，所述第三支撑层的厚度大于所述第二支撑层的厚度。
为了解决上述问题，本申请还提供了一种半导体结构，采用如上述任一项所述的半导体结构的形成方法形成。
本申请提供的半导体结构的形成方法及半导体结构，通过叠层结构的表面形成缓冲层，从而在刻蚀过程中能够对顶部的支撑层进行保护，使得初始形成的叠层结构中的所有支撑层都能至少保留部分于第一电极层的侧壁，使得最终形成的电容器具有足够的高度，避免了现有技术中的单层横向支撑层对电容器高度的限制，提高了电容阵列区域横向的稳定性，从而改善了半导体结构的电学性能。而且，通过设置多层横向支撑层，有助于进一步减小第一电极层的厚 度，从而有效提高电容器的电容值。
附图说明
附图1是本申请具体实施方式中半导体结构的形成方法流程图；
附图2A-2P是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本申请提供的半导体结构的形成方法及半导体结构的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的形成方法，附图1是本申请具体实施方式中半导体结构的形成方法流程图，附图2A-2P是本申请具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。如图1、图2A-图2P所示，本具体实施方式提供的半导体结构的形成方法，包括如下步骤：
步骤S11，形成叠层结构于一衬底表面，所述衬底内具有电容触点，所述叠层结构包括沿垂直于所述衬底的方向交替叠置支撑层和牺牲层，如图2A所示。
所述叠层结构中叠置的所述支撑层和所述牺牲层的具体层数，本领域技术人员可以根据实际需要进行设置。在本具体实施方式中，为了后续能够形成多层支撑层以支撑电容器中的电极结构，所述叠层结构中所述支撑层的层数至少为三层，相应的，所述牺牲层的层数至少为两层。为了进一步简化半导体结构的制造工序，可选的，形成叠层结构于一衬底表面的具体步骤包括：
提供一衬底，所述衬底内部具有电容触点(图中未示出)；
沿垂直于所述衬底的方向依次沉积第一支撑层20、第一牺牲层21、第二支撑层22、第二牺牲层23和第三支撑层24于所述衬底表面，如图2A所示。
具体来说，所述衬底内部具有呈阵列排布的多个有源区，所述电容触点电连接所述有源区。在沿所述衬底指向所述叠层结构的方向上，所述第一支撑层20、所述第一牺牲层21、所述第二支撑层22、所述第二牺牲层23、所述第三支撑层24依次叠置。所述第一支撑层20、所述第二支撑层22和所述第三支撑层24的材料可以相同，例如均为氮化物材料(例如氮化硅)。所述第一牺牲层21与所述第二牺牲层23的材料也可以相同，例如均为氧化物材料(例如氧化 硅)。
步骤S12，形成缓冲层25于所述叠层结构背离所述衬底的表面，如图2A所示。
具体来说，所述缓冲层25的材料可以为有机材料，例如碳。
步骤S13，形成贯穿所述叠层结构和所述缓冲层25并暴露所述电容触点的电容孔26，如图2B、图2C所示，图2B是图2C沿虚线方向的截面示意图。
具体来说，在形成覆盖所述叠层结构的所述缓冲层25之后，可以采用干法刻蚀工艺或者湿法刻蚀工艺沿垂直于所述衬底的方向形成贯穿所述缓冲层25和所述叠层结构的所述电容孔26，通过所述电容孔暴露所述衬底内的所述电容触点。
步骤S14，形成覆盖所述电容孔26内壁并与所述电容触点接触的第一电极层27，如图2D、图2E所示，图2D是图2E沿虚线方向的截面示意图。
步骤S15，形成贯穿所述缓冲层25并暴露所述叠层结构的刻蚀窗口。
具体来说，可以采用化学气相沉积工艺或者物理气相沉积工艺沉积所述第一电极层27于所述电容孔26的侧壁、底壁以及所述缓冲层25背离所述第三支撑层24的表面。所述第一电极层27的材料可以是但不限于氮化钛，所述第一电极层27的厚度本领域技术人员可以根据实际需要进行设置。
可选的，所述第一电极层27覆盖所述电容孔26内壁和所述缓冲层25表面，如图2D、图2E所示；形成贯穿所述缓冲层25并暴露所述叠层结构的刻蚀窗口的具体步骤包括：
形成覆盖所述第一电极层27表面的掩膜层，所述掩膜层中具有暴露所述第一电极层27的刻蚀图案；
沿所述刻蚀图案依次刻蚀所述第一电极层27和所述缓冲层25，形成暴露所述第三支撑层24的刻蚀窗口。
具体来说，在形成所述第一电极层27之后，形成掩膜层于位于所述缓冲层25顶面的所述第一电极层27之上，并封闭所述电容孔26，以便于后续对所述第三支撑层24进行刻蚀。所述掩膜层可以为硬掩膜层，且所述掩膜层可以为单层掩膜层，也可以为多层掩膜层构成的叠层。在本具体实施方式中以所述掩膜层包括第一子掩膜层28和第二子掩膜层29为例进行说明。所述第一子掩 膜层28的材料可以为氮化物材料，例如氮化硅；所述第二子掩膜层29的材料可以为氧化物或者氮氧化物材料。
在形成所述第一子掩膜层28和所述第二子掩膜层29之后，形成光阻层30于所述第二子掩膜层29背离所述第一子掩膜层28的表面，所述光阻层30中具有暴露所述第二子掩膜层29的刻蚀开口301，如图2G、图2H所示，图2G是图2H沿虚线方向的截面示意图。接着，沿所述刻蚀开口301刻蚀所述第二子掩膜层29和所述第一子掩膜层28，形成贯穿所述第二子掩膜层29和所述第一子掩膜层28的刻蚀图案，所述刻蚀图案暴露所述第一电极层27。然后，继续沿所述刻蚀图案刻蚀所述第一电极层27和所述缓冲层25，形成暴露所述第三支撑层24的刻蚀窗口。
在本具体实施方式中，以一个所述刻蚀开口301与三个所述电容孔26交叠为例进行说明，如图2G、图2H所示。在其他具体实施方式中，本领域技术人员也可以根据实际需要设置一个所述刻蚀开口301与一个、两个或者三个以上的所述电容孔交叠。
步骤S16，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层，如图2L所示。
可选的，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤包括：
沿所述刻蚀窗口刻蚀部分的所述第三支撑层24，形成暴露所述第二牺牲层23的第一开口31，残留的所述第三支撑层24与所述第一电极层27的侧壁连接，如图2I所示；
沿所述第一开口31去除所述第二牺牲层23，暴露所述第二支撑层22，如图2J所示；
沿所述第一开口31刻蚀部分的所述第二支撑层22，形成暴露所述第一牺牲层21的第二开口，如图2K所示；
沿所述第二开口去除所述第一牺牲层21，如图2L所示。
可选的，形成暴露所述第二牺牲层23的第一开口31的具体步骤包括：
去除与所述刻蚀图案交叠区域的部分所述第一电极层27；
沿所述刻蚀图案去除部分的所述缓冲层25；
沿所述刻蚀图案去除部分的所述第三支撑层24，形成暴露所述第二牺牲层23的第一开口31。
具体来说，沿所述刻蚀窗口选择性的刻蚀所述第一电极层27，使得与所述刻蚀图案交叠区域的所述第一电极层27的顶面与所述第三支撑层24的底面平齐，以便于后续对所述缓冲层25和所述第三支撑层24进行刻蚀。之后，继续沿所述刻蚀图案选择性的刻蚀所述缓冲层25和所述第三支撑层24，形成暴露所述第二牺牲层23的第一开口31。
在沿所述刻蚀图案去除部分的所述缓冲层25、部分的所述第三支撑层24和部分的所述第一电极层27的过程中，与所述刻蚀图案交叠区域的所述第一电极层27的高度降低，低于未与所述刻蚀图案交叠区域的所述第一电极层27的高度。未与所述刻蚀图案交叠区域的部分，由于所述第一电极层27以及所述缓冲层25的覆盖，所述第三支撑层24得以保留，从而使得在刻蚀结束之后，残留的所述第三支撑层24(如图2I中虚线框中所示的第三支撑层24)与所述第一电极层27的侧壁垂直连接，以支撑所述第一电极层。
在形成所述第一开口31之后，可以先去除所述第二子掩膜层29。然后，采用湿法刻蚀工艺自所述第一开口31去除所有的所述第二牺牲层23，得到如图2J所示的结构。之后，继续沿所述第一开口31刻蚀部分的所述第二支撑层22，形成暴露所述第一牺牲层21的所述第二开口，如图2K所示。残留的所述第二支撑层22与所述第一电极层27的侧壁垂直连接，以支撑所述第一电极层27。接着，采用湿法刻蚀工艺自所述第二开口去除所有的所述第一牺牲层21，得到如图2L所示的结构。
可选的，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤还包括：
沿所述刻蚀窗口刻蚀部分所述第三支撑层24的同时、刻蚀部分所述掩膜层；
沿所述第一开口31刻蚀部分的所述第二支撑层22的同时、刻蚀掉残留的所述掩膜层28，暴露所述第一电极层27；
去除覆盖于所述缓冲层25表面的所述第一电极层27，暴露所述缓冲层25。
举例来说，所述叠层结构中的所述第一支撑层20、所述第二支撑层22、 所述第三支撑层24和所述第一子掩膜层28均采用相同的氮化物材料(例如氮化硅)制成。在沿所述刻蚀窗口刻蚀所述第三支撑层24的过程中，部分的所述第一子掩膜层28也被刻蚀掉，而被所述缓冲层25覆盖、且未与所述刻蚀窗口交叠区域的所述第三支撑层24不被刻蚀。在沿所述第一开口31刻蚀部分的所述第二支撑层22的过程中，剩余的所述第一子掩膜层28也被刻蚀掉，从而暴露出位于所述缓冲层25顶面的所述第一电极层27，以所述缓冲层25为刻蚀截止层，刻蚀掉覆盖于所述缓冲层25表面的所述第一电极层27，暴露所述缓冲层25。
本领域技术人员也可以根据实际需要，将所述第一子掩膜层28的材料设置为与所述叠层结构中所述第三支撑层24和所述第二支撑层22的材料不同，从而将所述第一子掩膜层28的去除过程与所述第三支撑层24、所述第二支撑层22的刻蚀过程分开进行。本具体实施方式对所述第一子掩膜层28与所述第三支撑层24、所述第二支撑层22、所述第二牺牲层23、所述第一牺牲层21去除的先后顺序不作限定，本领域技术人员可以根据实际需要进行选择。
步骤S17，去除所述缓冲层25，所述第一电极层27凸出于残留的所述叠层结构之上，如图2M所示。
具体来说，以所述第三支撑层24作为刻蚀截止层刻蚀掉所述缓冲层25，使得所述第一电极层27的部分凸出于残留的所述第三支撑层24之上，从而增加了所述第一电极层27的高度。另外，由于所述第一电极层27的侧壁仍然存在残留的所述第三支撑层24和残留的所述第二支撑层22，因此，能够对具有较高高度的所述第一电极层27进行稳定的支撑，从而增强了电容阵列区域的横向稳定性。同时，由于残留的所述第三支撑层24和残留的所述第二支撑层22的存在，还可以相应减小所述第一电极层27的厚度，从而增加电容器的电容值。
步骤S18，形成覆盖于所述第一电极层27和残留的所述叠层结构表面的电介质层32、以及覆盖于所述电介质层32表面的第二电极层33，形成电容器，如图2N、图2O所示。
可选的，形成覆盖于所述第一电极层27和残留的所述叠层结构表面的电介质层32、以及覆盖于所述电介质层32表面的第二电极层33的具体步骤包括：
形成覆盖所述第一电极层27、残留的所述第三支撑层24、残留的所述第二支撑层22、以及所述第一支撑层20表面的电介质层32，如图2N所示；
形成覆盖所述电介质层32表面的第二电极层33，如图2O所示；
形成覆盖所述第二电极层33表面的导电层34，如图2P所示。
具体来说，所述电介质层32的材料优选为具有较高介电常数的材料。所述第二电极层33的材料可以与所述第一电极层27的材料相同，例如均为氮化钛。所述导电层34的材料可以为但不限于多晶硅材料。
可选的，所述第三支撑层24的厚度大于所述第二支撑层22的厚度。
具体来说，将所述第三支撑层24的厚度设置为大于所述第二支撑层22的厚度，有助于对所述第一电极层27顶部的支撑，提高所述第一电极层27顶部的稳定性。本领域技术人员还可以根据需要将所述第一牺牲层21的厚度设置为大于所述第二牺牲层23的厚度，也有助于对所述第一电极层27顶部的支撑。
不仅如此，本具体实施方式还提供了一种半导体结构，采用如上述任一项所述的半导体结构的形成方法形成。本具体实施方式提供的半导体结构的示意图可参见图2P。
本具体实施方式提供的半导体结构的形成方法及半导体结构，通过叠层结构的表面形成缓冲层，从而在刻蚀过程中能够对顶部的支撑层进行保护，使得初始形成的叠层结构中的所有支撑层都能至少保留部分于第一电极层的侧壁，使得最终形成的电容器具有足够的高度，避免了现有技术中的单层横向支撑层对电容器高度的限制，提高了电容阵列区域横向的稳定性，从而改善了半导体结构的电学性能。而且，通过设置多层横向支撑层，有助于进一步减小第一电极层的厚度，从而有效提高电容器的电容值。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种半导体结构的形成方法，包括如下步骤：
    形成叠层结构于一衬底表面，所述衬底内具有电容触点，所述叠层结构包括沿垂直于所述衬底的方向交替叠置的支撑层和牺牲层；
    形成缓冲层于所述叠层结构背离所述衬底的表面；
    形成贯穿所述叠层结构和所述缓冲层并暴露所述电容触点的电容孔；
    形成覆盖所述电容孔内壁并与所述电容触点接触的第一电极层；
    形成贯穿所述缓冲层并暴露所述叠层结构的刻蚀窗口；
    沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层；
    去除所述缓冲层，所述第一电极层凸出于残留的所述叠层结构之上；
    形成覆盖于所述第一电极层和残留的所述叠层结构表面的电介质层、以及覆盖于所述电介质层表面的第二电极层，形成电容器。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成叠层结构于一衬底表面的具体步骤包括：
    提供一衬底，所述衬底内部具有电容触点；
    沿垂直于所述衬底的方向依次沉积第一支撑层、第一牺牲层、第二支撑层、第二牺牲层和第三支撑层。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，所述第一电极层覆盖所述电容孔内壁和所述缓冲层表面；形成贯穿所述缓冲层并暴露所述叠层结构的刻蚀窗口的具体步骤包括：
    形成覆盖所述第一电极层表面的掩膜层，所述掩膜层中具有暴露所述第一电极层的刻蚀图案；
    沿所述刻蚀图案依次刻蚀所述第一电极层和所述缓冲层，形成暴露所述第三支撑层的刻蚀窗口。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤包括：
    沿所述刻蚀窗口刻蚀部分的所述第三支撑层，形成暴露所述第二牺牲层的第一开口，残留的所述第三支撑层与所述第一电极层的侧壁连接；
    沿所述第一开口去除所述第二牺牲层，暴露所述第二支撑层；
    沿所述第一开口刻蚀部分的所述第二支撑层，形成暴露所述第一牺牲层的第二开口；
    沿所述第二开口去除所述第一牺牲层。
  5. 根据权利要求4所述的半导体结构的形成方法，其中，一个所述刻蚀窗口与三个及以上的所述电容孔交叠。
  6. 根据权利要求4所述的半导体结构的形成方法，其中，形成暴露所述第二牺牲层的第一开口的具体步骤包括：
    去除与所述刻蚀图案交叠区域的部分所述第一电极层；
    沿所述刻蚀图案去除部分的所述缓冲层；
    沿所述刻蚀图案去除部分的所述第三支撑层，形成暴露所述第二牺牲层的第一开口。
  7. 根据权利要求4所述的半导体结构的形成方法，其中，沿所述刻蚀窗口除去所述叠层结构中部分的所述支撑层和全部的所述牺牲层的具体步骤还包括：
    沿所述刻蚀窗口刻蚀部分所述第三支撑层的同时、刻蚀部分所述掩膜层；
    沿所述第一开口刻蚀部分的所述第二支撑层的同时、刻蚀掉残留的所述掩膜层，暴露所述第一电极层；
    去除覆盖于所述缓冲层表面的所述第一电极层，暴露所述缓冲层。
  8. 根据权利要求4所述的半导体结构的形成方法，其中，形成覆盖于所述第一电极层和残留的所述叠层结构表面的电介质层、以及覆盖于所述电介质层表面的第二电极层的具体步骤包括：
    形成覆盖所述第一电极层、残留的所述第三支撑层、残留的所述第二支撑层、以及所述第一支撑层表面的电介质层；
    形成覆盖所述电介质层表面的第二电极层；
    形成覆盖所述第二电极层表面的导电层。
  9. 根据权利要求2所述的半导体结构的形成方法，其中，所述第三支撑层的厚度大于所述第二支撑层的厚度。
  10. 一种半导体结构，其中，所述半导体结构采用如权利要求1-9中任一项所述的半导体结构的形成方法形成。
PCT/CN2021/077837 2020-03-16 2021-02-25 半导体结构的形成方法及半导体结构 Ceased WO2021185040A1 (zh)

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