WO2021184441A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2021184441A1
WO2021184441A1 PCT/CN2020/083366 CN2020083366W WO2021184441A1 WO 2021184441 A1 WO2021184441 A1 WO 2021184441A1 CN 2020083366 W CN2020083366 W CN 2020083366W WO 2021184441 A1 WO2021184441 A1 WO 2021184441A1
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WO
WIPO (PCT)
Prior art keywords
layer
display panel
hole
cathode
anode
Prior art date
Application number
PCT/CN2020/083366
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English (en)
French (fr)
Inventor
曾维静
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/757,419 priority Critical patent/US20220310967A1/en
Publication of WO2021184441A1 publication Critical patent/WO2021184441A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • This application relates to the field of display technology, in particular to a display panel and a preparation method thereof.
  • OLED Organic Light-Emitting Diode
  • the packaging of OLED display panels usually adopts the surface packaging method, but after the thin film transistor substrate completes the film formation of the electroluminescent layer, a depression will be formed in the pixel opening area. Display effect and packaging effect.
  • the present application provides a display panel and a manufacturing method thereof, so that the display panel does not generate air bubbles during packaging or subsequent manufacturing processes, thereby not affecting the display effect and packaging effect of the display panel.
  • the present application provides a display panel, which includes:
  • An anode layer, the anode layer is disposed on the array substrate;
  • a pixel definition layer covering the array substrate and the anode layer, the pixel definition layer includes a first through hole, the first through hole penetrates the pixel definition layer to expose the anode Floor;
  • a light-emitting layer, the light-emitting layer is disposed in the first through hole to be electrically connected to the anode layer;
  • a cathode layer covers the pixel definition layer and the light-emitting layer, the cathode layer includes a groove, and the groove is located on the first through hole;
  • the filling layer is arranged in the groove and on the cathode layer.
  • the total thickness of the anode layer, the light-emitting layer, the cathode layer, and the filling layer is greater than the thickness of the pixel definition layer.
  • the material of the filling layer includes one or a combination of polyimide, polyethylene, polyethylene naphthalate, and hexamethyl simethicone.
  • the surface of the filling layer is higher than the surface of the cathode layer or flush with the surface of the cathode layer.
  • the display panel further includes a barrier layer, and the barrier layer covers the cathode layer and the filling layer.
  • the display panel further includes a flat layer disposed on the array substrate, the flat layer includes a second through hole, and the second through hole penetrates the The planarization layer exposes the array substrate, and the anode layer is disposed in the second through hole and is electrically connected to the array substrate on the planarization layer.
  • the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on the barrier layer.
  • the display panel further includes a cover layer, and the cover layer is disposed on the encapsulation layer.
  • This application also provides a display panel, including:
  • An anode layer, the anode layer is disposed on the array substrate;
  • a pixel definition layer covering the array substrate and the anode layer, the pixel definition layer includes a first through hole, the first through hole penetrates the pixel definition layer to expose the anode Floor;
  • a light-emitting layer, the light-emitting layer is disposed in the first through hole to be electrically connected to the anode layer;
  • a cathode layer covers the pixel definition layer and the light-emitting layer, the cathode layer includes a groove, and the groove is located on the first through hole;
  • a filling layer, the filling layer is arranged in the groove.
  • the total thickness of the anode layer, the light-emitting layer, the cathode layer, and the filling layer is greater than the thickness of the pixel definition layer.
  • the material of the filling layer includes one or a combination of polyimide, polyethylene, polyethylene naphthalate, and hexamethyl simethicone.
  • the surface of the filling layer is higher than the surface of the cathode layer or flush with the surface of the cathode layer.
  • the display panel further includes a barrier layer, and the barrier layer covers the cathode layer and the filling layer.
  • the display panel further includes a flat layer disposed on the array substrate, the flat layer includes a second through hole, and the second through hole penetrates the The planarization layer exposes the array substrate, and the anode layer is disposed in the second through hole and is electrically connected to the array substrate on the planarization layer.
  • the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on the barrier layer.
  • the display panel further includes a cover layer, and the cover layer is disposed on the encapsulation layer.
  • the present application also provides a method for manufacturing a display panel, including:
  • a cathode layer is covered on the pixel definition layer and the light-emitting layer, the cathode layer includes a groove, and the groove is located on the first through hole;
  • An inkjet printing method is used to print the filling layer material in the groove to form the filling layer.
  • the method further includes the step of forming the filling layer on the cathode layer and the filling layer. A barrier layer is formed on it.
  • the method further includes:
  • An encapsulation layer is formed on the barrier layer.
  • the surface of the filling layer is higher than the surface of the cathode layer or flush with the surface of the cathode layer.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes an array substrate, an anode layer, a pixel definition layer, a light-emitting layer, a cathode layer, and a filling layer.
  • the anode layer is disposed on the array substrate.
  • a pixel definition layer covers the array substrate and the anode layer, the definition layer includes a first through hole, the first through hole penetrates the pixel definition layer to expose the anode layer, and the light emitting layer is disposed
  • the anode layer is electrically connected in the first through hole
  • the cathode layer covers the pixel defining layer and the light emitting layer
  • the cathode layer includes a groove, and the groove is located on the first through hole
  • the filling layer is arranged in the groove.
  • the filling layer is arranged in the groove of the cathode layer to prevent the display panel from generating bubbles in the subsequent packaging process, and improve the packaging effect and display effect of the display panel.
  • FIG. 1 is a schematic diagram of the first structure of the display panel provided by this application.
  • FIG. 2 is a schematic diagram of the structure of the array substrate provided by this application.
  • FIG. 3 is a schematic diagram of the second structure of the display panel provided by this application.
  • FIG. 4 is a flow chart of the manufacturing method of the display panel provided by this application.
  • FIG. 1 is a schematic diagram of the first structure of the display panel provided by this application.
  • the application provides a display panel 10.
  • the display panel 10 includes an array substrate 100, an anode layer 300, a pixel definition layer 400, a light emitting layer 500, a cathode layer 600, and a filling layer 700.
  • FIG. 2 is a schematic diagram of the structure of the array substrate provided by this application.
  • the array substrate 100 includes a substrate 110 and a thin film transistor 120.
  • the thin film transistor 120 is disposed on the substrate 110.
  • the thin film transistor 120 includes a buffer layer 121, an active layer 122, a gate insulating layer 123, a gate layer 124, an interlayer dielectric layer 125, a source electrode 126 and a drain electrode 127.
  • the buffer layer 121 is disposed on the substrate 110.
  • the material of the buffer layer 121 includes SiOx and SiNx.
  • the active layer 122 is disposed on the buffer layer 121.
  • the material of the active layer 122 includes indium gallium zinc oxide, indium zinc tin oxide, gallium zinc oxide, zinc oxynitride, and indium gallium zinc titanium oxide.
  • the gate insulating layer 123 is disposed on the active layer 122.
  • the material of the gate insulating layer 123 includes SiOx and SiNx.
  • the gate layer 124 is disposed on the gate insulating layer 123.
  • the material of the gate layer 124 includes one or a combination of Mo, Al, Cu, and Ti.
  • the interlayer dielectric layer 125 covers the buffer layer 121, the active layer 122, the gate insulating layer 123 and the gate layer 124.
  • the interlayer dielectric layer 125 has a third through hole 1251 and a fourth through hole 1252.
  • the third through hole 1251 penetrates the interlayer dielectric layer 125 to expose one side of the active layer 122.
  • the fourth through hole 1252 penetrates the interlayer dielectric layer 125 to expose the other side of the active layer 122.
  • the material of the interlayer dielectric layer 125 includes SiOx and SiNx.
  • the source electrode 126 is filled in the third through hole 1251 and on the interlayer dielectric layer 125 to electrically connect the active layer 122.
  • the drain 127 is filled in the fourth through hole 1252 and on the interlayer dielectric layer 125 to be electrically connected to the active layer 122.
  • the material of the source electrode 126 and the drain electrode 127 includes one or a combination of Mo, Al, Cu, and Ti.
  • the display panel 10 further includes a flat layer 200.
  • the flat layer 200 is disposed on the substrate 110 and the thin film transistor 120.
  • the flat layer 200 includes a second through hole 210.
  • the second through hole 210 penetrates the planarization layer 200 to expose the thin film transistor 120.
  • the material of the flat layer 200 includes SiOx and SiNx.
  • the anode layer 300 is disposed in the second through hole 210 and on the flat layer 200 to be electrically connected to the thin film transistor 120.
  • the anode layer 200 has a first filling groove 310.
  • the pixel definition layer 400 covers the flat layer 200 and the anode layer 300.
  • the definition layer 400 includes a first through hole 410.
  • the first through hole 410 penetrates the pixel definition layer 400 to expose the anode layer 300.
  • the light-emitting layer 500 is disposed in the first through hole 410 to be electrically connected to the anode layer 300.
  • the light-emitting layer 500 has a second filling groove 510.
  • the first through hole 410 is further provided with an electron transport layer and a hole transport layer.
  • the cathode layer 600 covers the pixel defining layer 400 and the light emitting layer 500.
  • the cathode layer 600 includes a groove 610.
  • the groove 610 is located on the first through hole 410.
  • the filling layer 700 is disposed in the groove 610.
  • the surface of the filling layer 700 is flush with the surface of the cathode layer 600.
  • the material of the filling layer 700 includes one or a combination of polyimide, polyethylene, polyethylene naphthalate, and hexamethyl simethicone.
  • the total thickness H of the anode layer 300, the light-emitting layer 500, the cathode layer 600, and the filling layer 700 located on the first through hole 410 is greater than the thickness D of the pixel definition layer 400.
  • FIG. 3 is a schematic diagram of the second structure of the display panel provided by this application.
  • the filling layer 700 is disposed in the groove 610 and on the cathode layer 600.
  • the surface of the filling layer 700 is higher than the surface of the cathode layer 600.
  • the display panel 10 further includes a barrier layer 800.
  • the barrier layer 800 covers the cathode layer 600 and the filling layer 700.
  • the display panel 10 further includes an encapsulation layer 900.
  • the encapsulation layer 900 covers the barrier layer 800.
  • the display panel 10 further includes a cover layer 1000.
  • the cover layer 1000 is disposed on the encapsulation layer 900.
  • the filling layer 700 is disposed in the groove 610 of the cathode layer 600 to prevent the display panel 10 from generating bubbles in the subsequent packaging process, and improve the packaging effect and display effect of the display panel.
  • FIG. 4 is a flow chart of the manufacturing method of the display panel provided by this application.
  • the application also provides a method for manufacturing the display panel.
  • the preparation method includes:
  • the array substrate 100 includes a substrate 110 and a thin film transistor 120.
  • the thin film transistor 120 is disposed on the substrate 110.
  • a chemical vapor deposition process or a physical vapor deposition process is used to deposit a buffer layer material on the substrate 110 to form the buffer layer 121.
  • the material of the buffer layer 121 includes SiOx and SiNx.
  • a chemical vapor deposition process is used to deposit the material of the active layer 122 on the buffer layer 121, and the material of the active layer 122 is etched to form the buffer layer 121.
  • the material of the active layer 122 includes indium gallium zinc oxide, indium zinc tin oxide, gallium zinc oxide, zinc oxynitride, and indium gallium zinc titanium oxide.
  • a chemical vapor deposition process or a physical vapor deposition process is used to deposit a gate insulating layer material on the active layer 122, and the gate insulating layer material is etched to form a gate insulating layer 123.
  • the material of the gate insulating layer 123 includes SiOx and SiNx.
  • a physical vapor deposition process is used to deposit a gate layer material on the gate insulating layer 123, and the gate layer material is etched to form a gate layer 124.
  • the material of the gate layer 124 includes one or a combination of Mo, Al, Cu, and Ti.
  • the active layer 122 is partially conductive, so that it contains conductive characteristics and semiconducting characteristics.
  • An interlayer dielectric layer 125 is covered on the buffer layer 121, the active layer 122, the gate insulating layer 123 and the gate layer 124.
  • the interlayer dielectric layer 125 is etched to form a third through hole 1251 and a fourth through hole 1252.
  • the third through hole 1251 penetrates the interlayer dielectric layer 125 to expose one side of the active layer 122.
  • the fourth through hole 1252 penetrates the interlayer dielectric layer 125 to expose the other side of the active layer 122.
  • a source electrode material is deposited on the interlayer dielectric layer 125 and in the third through hole 1251, and the source electrode 126 is formed by etching.
  • the material of the source electrode 126 includes one or a combination of Mo, Al, Cu, and Ti.
  • a drain material is deposited on the interlayer dielectric layer 125 and in the fourth through hole 1252, and the drain 126 is formed by etching.
  • the material of the drain 127 includes one or a combination of Mo, Al, Cu,
  • the manufacturing process of the array substrate 100 is completed, which further includes depositing the material of the flat layer 200 on the array substrate 100 to form the flat layer 200.
  • the flat layer 200 is etched to form a second through hole 210.
  • the second through hole 210 penetrates the planarization layer 200 to expose the thin film transistor 120.
  • the material of the flat layer 200 includes SiOx and SiNx.
  • An anode layer 300 is formed on the array substrate 100.
  • a chemical vapor deposition process is used to form an anode layer 300 on the flat layer 200 and the second through hole 210.
  • the anode layer 300 is etched to form a first filling groove 210.
  • the anode layer material includes indium tin oxide.
  • a pixel defining layer 400 is formed on the anode layer 300.
  • a pixel definition layer 400 is formed on the flat layer 200 and the anode layer 300.
  • the pixel defining layer 400 is etched to form a first through hole 410, and the first through hole 410 penetrates the pixel defining layer 400 to expose the anode layer 300.
  • the light-emitting layer 500 is formed in the first through hole 410 and on the pixel defining layer 400 by evaporation or inkjet printing.
  • the light-emitting layer has a second filling groove 510.
  • the second filling groove 510 is located above the first through hole 410.
  • an electron transport layer and a hole transport layer are further formed on the pixel definition layer 400 in the first through hole 410.
  • a cathode layer 600 is covered on the pixel defining layer 400 and the light-emitting layer 500, the cathode layer 600 includes a groove 610, and the groove 610 is located on the first through hole 410.
  • a cathode layer 600 is formed on the pixel defining layer 400 and the light emitting layer 500 by evaporation or inkjet printing.
  • a groove 610 is formed on the cathode layer 600.
  • the surface of the filling layer 700 is flush with or higher than the surface of the cathode layer 600.
  • the material of the filling layer 700 includes one or a combination of polyimide, polyethylene, polyethylene naphthalate, and hexamethyl simethicone.
  • the total thickness H of the anode layer 300, the light-emitting layer 500, the cathode layer 600, and the filling layer 700 located on the first through hole 410 is greater than the thickness D of the pixel definition layer 400.
  • the method further includes forming a barrier layer 800 covering the cathode layer 600 and the filling layer 700.
  • the method further includes forming an encapsulation layer 900 on the barrier layer 800.
  • the method further includes forming a cover layer 1000 on the encapsulation layer 900.
  • the present application provides a display panel and a manufacturing method thereof.
  • the display panel includes an array substrate, an anode layer, a pixel definition layer, a light-emitting layer, a cathode layer, and a filling layer.
  • the anode layer is disposed on the array substrate.
  • a pixel definition layer covers the array substrate and the anode layer, the definition layer includes a first through hole, the first through hole penetrates the pixel definition layer to expose the anode layer, and the light emitting layer is disposed
  • the anode layer is electrically connected in the first through hole
  • the cathode layer covers the pixel defining layer and the light emitting layer
  • the cathode layer includes a groove, and the groove is located on the first through hole
  • the filling layer is arranged in the groove.
  • the filling layer is arranged in the groove of the cathode layer to prevent the display panel from generating bubbles in the subsequent packaging process, and improve the packaging effect and display effect of the display panel.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（10）及其制备方法，显示面板（10）包括阵列基板（100）、阳极层（300）、像素定义层（400）、发光层（500）、阴极层（600）和填充层（700），阳极层（300）设置于阵列基板（100）上，像素定义层（400）覆盖阵列基板（100）及阳极层（600）上，像素定义层（400）包括第一通孔（410），发光层（500）设置于第一通孔（410）中，阴极层（600）覆盖像素定义层（400）和发光层（500），阴极层（600）包括凹槽（610），填充层（700）设置于凹槽（610）中。

Description

显示面板及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制备方法。
 背景技术
OLED 即有机发光二极管(Organic Light-Emitting Diode)，因具有自发光、高亮度、宽视角、高对比度、可挠曲和低能耗等特点，被广泛应用在手机屏幕、电脑显示器和全彩电视中。OLED显示面板的封装通常采用面封装方法，但因薄膜晶体管基板完成电致发光层成膜后，在像素开口区会形成凹陷，该区域采用面封装方法封装后易形气泡，进而影响显示面板的显示效果及封装效果。
 技术问题
本申请提供一种显示面板及其制备方法，使得显示面板在封装或后续的制程中不产生气泡，进而不影响显示面板的显示效果和封装效果。
 技术解决方案
本申请提供一种显示面板，其包括：
一阵列基板；
阳极层，所述阳极层设置于所述阵列基板上；
像素定义层，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述像素定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层；
发光层，所述发光层设置于所述第一通孔中以电连接所述阳极层；
阴极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
填充层，所述填充层设置于所述凹槽中及所述阴极层上。
在本申请所提供的显示面板中，所述阳极层、所述发光层、所述阴极层及所述填充层的厚度之和大于所述像素定义层的厚度。
在本申请所提供的显示面板中，所述填充层的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。
在本申请所提供的显示面板中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
在本申请所提供的显示面板中，所述显示面板还包括阻挡层，所述阻挡层覆盖所述阴极层及所述填充层。
在本申请所提供的显示面板中，所述显示面板还包括平坦层，所述平坦层设置于所述阵列基板上，所述平坦层包括第二通孔，所述第二通孔贯穿所述平坦层以暴露所述阵列基板，所述阳极层设置于所述第二通孔中及所述平坦层上与所述阵列基板电连接。
在本申请所提供的显示面板中，所述显示面板还包括封装层，所述封装层设置于所述阻挡层上。
在本申请所提供的显示面板中，所述显示面板还包括覆盖层，所述覆盖层设置于所述封装层上。
本申请还提供一种显示面板，包括：
一阵列基板；
阳极层，所述阳极层设置于所述阵列基板上；
像素定义层，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述像素定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层；
发光层，所述发光层设置于所述第一通孔中以电连接所述阳极层；
阴极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
填充层，所述填充层设置于所述凹槽中。
在本申请所提供的显示面板中，所述阳极层、所述发光层、所述阴极层及所述填充层的厚度之和大于所述像素定义层的厚度。
在本申请所提供的显示面板中，所述填充层的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。
在本申请所提供的显示面板中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
在本申请所提供的显示面板中，所述显示面板还包括阻挡层，所述阻挡层覆盖所述阴极层及所述填充层。
在本申请所提供的显示面板中，所述显示面板还包括平坦层，所述平坦层设置于所述阵列基板上，所述平坦层包括第二通孔，所述第二通孔贯穿所述平坦层以暴露所述阵列基板，所述阳极层设置于所述第二通孔中及所述平坦层上与所述阵列基板电连接。
在本申请所提供的显示面板中，所述显示面板还包括封装层，所述封装层设置于所述阻挡层上。
在本申请所提供的显示面板中，所述显示面板还包括覆盖层，所述覆盖层设置于所述封装层上。
本申请还提供一种显示面板的制备方法，包括：
提供一阵列基板；
在所述阵列基板上形成阳极层；
在所述阳极层上形成像素定义层；
对所述像素定义层进行蚀刻，形成第一通孔，所述第一通孔贯通所述像素定义层以暴露所述阳极层；
在所述第一通孔中形成发光层；
在所述像素定义层上和所述发光层上覆盖有阴极层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
在所述凹槽中采用喷墨打印方法打印填充层材料，形成填充层。
在本申请所提供的显示面板的制备方法中，所述在所述凹槽中采用喷墨打印方法打印填充层材料，形成填充层的步骤之后，还包括在所述阴极层及所述填充层上形成阻挡层。
在本申请所提供的显示面板的制备方法中，所述在所述阴极层及所述填充层上形成阻挡层的步骤之后还包括：
在所述阻挡层上形成封装层。
在本申请所提供的显示面板的制备方法中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
 有益效果
本申请提供一种显示面板及其制备方法，所述显示面板包括阵列基板、阳极层、像素定义层、发光层、阴极层和填充层，所述阳极层设置于所述阵列基板上，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层，所述发光层设置于所述第一通孔中以电连接所述阳极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上，所述填充层设置于所述凹槽中。在本申请中，将填充层设置于阴极层的凹槽中，避免了显示面板在后续封装制程中产生气泡，提高显示面板的封装效果和显示效果。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请所提供的显示面板的第一种结构示意图。
图2为本申请所提供的阵列基板的结构示意图。
图3为本申请所提供的显示面板的第二种结构示意图。
图4为本申请所提供的显示面板的制备方法流程图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1为本申请所提供的显示面板的第一种结构示意图。本申请提供一种显示面板10。所述种显示面板10包括阵列基板100、阳极层300、像素定义层400、发光层500、阴极层600和填充层700。
请参阅图2，图2为本申请所提供的阵列基板的结构示意图。所述阵列基板100包括基板110和薄膜晶体管120。所述薄膜晶体管120设置于所述基板110上。所述薄膜晶体管120包括缓冲层121、有源层122、栅极绝缘层123、栅极层124、层间介质层125、源极126和漏极127。所述缓冲层121设置于所述基板110上。所述缓冲层121的材料包括SiOx和SiNx。所述有源层122设置于所述缓冲层121上。所述有源层122的材料包括铟镓锌氧化物、铟锌锡氧化物、镓锌氧化物、氮氧化锌和铟镓锌钛氧化物。所述栅极绝缘层123设置于所述有源层122上。所述栅极绝缘层123的材料包括SiOx和SiNx。所述栅极层124设置于所述栅极绝缘层123上。所述栅极层124的材料包括Mo、Al、Cu和Ti中的一种或几种组合。所述层间介质层125覆盖所述缓冲层121、所述有源层122、所述栅极绝缘层123和所述栅极层124。所述层间介质层125具有第三通孔1251和第四通孔1252。所述第三通孔1251贯穿所述层间介质层125，以暴露所述有源层122的一侧。所述第四通孔1252贯穿所述层间介质层125以暴露所述有源层122的另一侧。所述层间介质层125的材料包括SiOx和SiNx。所述源极126填充于所述第三通孔1251中及所述层间介质层125上，以电连接所述有源层122。所述漏极127填充于所述第四通孔1252中及所述层间介质层125上，以电连接所述有源层122。所述源极126和所述漏极127的材料包括Mo、Al、Cu和Ti中的一种或几种组合。
所述显示面板10还包括平坦层200。所述平坦层200设置于所述基板110和所述薄膜晶体管120上。所述平坦层200包括第二通孔210。所述第二通孔210贯穿所述平坦层200以暴露所述薄膜晶体管120。所述平坦层200的材料包括SiOx和SiNx。
所述阳极层300设置于所述第二通孔210中及所述平坦层200上与所述薄膜晶体管120电连接。所述阳极层200具有第一填充槽310。
所述像素定义层400覆盖所述平坦层200及所述阳极层300上。所述定义层400包括第一通孔410。所述第一通孔410贯穿所述像素定义层400，以暴露所述阳极层300。
所述发光层500设置于所述第一通孔410中以电连接所述阳极层300。所述发光层500具有第二填充槽510。
在另一实施例中，所述第一通孔410中还设置有电子传输层和空穴传输层。
所述阴极层600覆盖所述像素定义层400和所述发光层500。所述阴极层600包括凹槽610。所述凹槽610位于所述第一通孔410上。
所述填充层700设置于所述凹槽610中。所述填充层700的表面与所述阴极层600的表面平齐。所述填充层700的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。位于所述第一通孔410上的所述阳极层300、所述发光层500、所述阴极层600及所述填充层700的厚度之和H大于所述像素定义层400的厚度D。
请参阅图3，图3为本申请所提供的显示面板的第二种结构示意图。所述填充层700设置于所述凹槽610中及所述阴极层600上。所述填充层700的表面高于所述阴极层600的表面。
在另一实施例中，所述显示面板10还包括阻挡层800。所述阻挡层800覆盖所述阴极层600及所述填充层700。
在另一实施例中，所述显示面板10还包括封装层900。所述封装层900覆盖所述阻挡层800。
在另一实施例中，所述显示面板10还包括覆盖层1000。所述覆盖层1000设置于所述封装层900上。
在本申请中，将填充层700设置于阴极层600的凹槽610中，避免了显示面板10在后续封装制程中产生气泡，提高显示面板的封装效果和显示效果。
请参阅图4，图4为本申请所提供的显示面板的制备方法流程图。本申请还提供一种显示面板的制备方法。所述制备方法包括：
21、提供一阵列基板100。
所述阵列基板100包括基板110和薄膜晶体管120。在所述薄膜晶体管120设置于所述基板110上。采用化学气相沉积工艺或物理气相沉积工艺在所述基板110上沉积缓冲层材料，形成缓冲层121。所述缓冲层121的材料包括SiOx和SiNx。采用化学气相沉积工艺在所述缓冲层121上沉积有源层122材料，对有源层122材料进行蚀刻形成缓冲层121。所述有源层122的材料包括铟镓锌氧化物、铟锌锡氧化物、镓锌氧化物、氮氧化锌和铟镓锌钛氧化物。采用化学气相沉积工艺或物理气相沉积工艺在所述有源层122上沉积栅极绝缘层材料，对所述栅极绝缘层材料进行蚀刻形成栅极绝缘层123。所述栅极绝缘层123的材料包括SiOx和SiNx。采用物理气相沉积工艺在所述栅极绝缘层123上沉积栅极层材料，对所述栅极层材料进行蚀刻形成栅极层124。所述栅极层124的材料包括Mo、Al、Cu和Ti中的一种或几种组合。对所述有源层122进行部分导体化，使其含有导体化的特性和半导体化的特性。在所述缓冲层121、所述有源层122、所述栅极绝缘层123和所述栅极层124上覆盖层间介质层125。对所述层间介质层125进行蚀刻，形成第三通孔1251和第四通孔1252。所述第三通孔1251贯穿所述层间介质层125，以暴露所述有源层122的一侧。所述第四通孔1252贯穿所述层间介质层125以暴露所述有源层122的另一侧。在所述层间介质层125上及所述第三通孔1251中沉积源极材料，蚀刻形成源极126。所述源极126的材料包括Mo、Al、Cu和Ti中的一种或几种组合。在所述层间介质层125上及所述第四通孔1252中沉积漏极材料，蚀刻形成漏极126。所述漏极127的材料包括Mo、Al、Cu和Ti中的一种或几种组合。
在另一实施例中，所述阵列基板100的制程完成，还包括在所述阵列基板100上沉积平坦层200的材料，形成平坦层200。对所述平坦层200进行蚀刻形成第二通孔210。所述第二通孔210贯穿所述平坦层200以暴露所述薄膜晶体管120。所述平坦层200的材料包括SiOx和SiNx。
22、在所述阵列基板100上形成阳极层300。
在所述平坦层200上及所述第二通孔210采用化学气相沉积工艺形成阳极层300。对所述阳极层300进行蚀刻，形成第一填充槽210。所述阳极层材料包括氧化铟锡。
23、在所述阳极层300上形成像素定义层400。
在所述平坦层200及所述阳极层300上形成像素定义层400。
24、对所述像素定义层400进行蚀刻，形成第一通孔410，所述第一通孔410贯通所述像素定义层400以暴露所述阳极层300。
25、在所述第一通孔410中形成发光层500。
在所述第一通孔410中及所述像素定义层400上采用蒸镀或喷墨打印的方法形成发光层500。所述发光层具有第二填充槽510。所述第二填充槽510位于所述第一通孔410之上。
在另一实施例中，在所述第一通孔410中所述像素定义层400上还形成电子传输层和空穴传输层。
26、在所述像素定义层400上和所述发光层500上覆盖有阴极层600，所述阴极层600包括凹槽610，所述凹槽610位于所述第一通孔410上。
在所述像素定义层400上及所述发光层500上采用蒸镀或喷墨打印的方法形成阴极层600。对所述阴极层600形成凹槽610。
27、在所述凹槽610中采用喷墨打印方法打印填充层材料，形成填充层700。
所述填充层700的表面与所述阴极层600的表面平齐或高于所述阴极层600的表面。所述填充层700的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。位于所述第一通孔410上的所述阳极层300、所述发光层500、所述阴极层600及所述填充层700的厚度之和H大于所述像素定义层400的厚度D。
在另一实施例中，在所述填充层700设置于所述凹槽610的步骤之后，还包括在形成覆盖所述阴极层600及所述填充层700的阻挡层800。
在另一实施例中，在所述阴极层600及所述填充层700上形成所述阻挡层800的步骤之后，还包括在所述阻挡层800上形成封装层900。
在另一实施例中，在所述阻挡层800上形成封装层900的步骤之后，还包括在所述封装层900上形成覆盖层1000。
本申请提供一种显示面板及其制备方法，所述显示面板包括阵列基板、阳极层、像素定义层、发光层、阴极层和填充层，所述阳极层设置于所述阵列基板上，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层，所述发光层设置于所述第一通孔中以电连接所述阳极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上，所述填充层设置于所述凹槽中。在本申请中，将填充层设置于阴极层的凹槽中，避免了显示面板在后续封装制程中产生气泡，提高显示面板的封装效果和显示效果。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，其包括：
    一阵列基板；
    阳极层，所述阳极层设置于所述阵列基板上；
    像素定义层，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述像素定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层；
    发光层，所述发光层设置于所述第一通孔中以电连接所述阳极层；
    阴极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
    填充层，所述填充层设置于所述凹槽中及所述阴极层上。
  2. 如权利要1所述的显示面板，其中，所述阳极层、所述发光层、所述阴极层及所述填充层的厚度之和大于所述像素定义层的厚度。
  3. 如权利要1所述的显示面板，其中，所述填充层的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。
  4. 如权利要求1所述的显示面板，其中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
  5. 如权利要求1所述的显示面板，其中，所述显示面板还包括阻挡层，所述阻挡层覆盖所述阴极层及所述填充层。
  6. 如权利要求1所述的显示面板，其中，所述显示面板还包括平坦层，所述平坦层设置于所述阵列基板上，所述平坦层包括第二通孔，所述第二通孔贯穿所述平坦层以暴露所述阵列基板，所述阳极层设置于所述第二通孔中及所述平坦层上与所述阵列基板电连接。
  7. 如权利要求5所述的显示面板，其中，所述显示面板还包括封装层，所述封装层设置于所述阻挡层上。
  8. 如权利要求7所述的显示面板，其中，所述显示面板还包括覆盖层，所述覆盖层设置于所述封装层上。
  9. 一种显示面板，其包括：
    一阵列基板；
    阳极层，所述阳极层设置于所述阵列基板上；
    像素定义层，所述像素定义层覆盖所述阵列基板及所述阳极层上，所述像素定义层包括第一通孔，所述第一通孔贯穿所述像素定义层，以暴露所述阳极层；
    发光层，所述发光层设置于所述第一通孔中以电连接所述阳极层；
    阴极层，所述阴极层覆盖所述像素定义层和发光层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
    填充层，所述填充层设置于所述凹槽中。
  10. 如权利要9所述的显示面板，其中，所述阳极层、所述发光层、所述阴极层及所述填充层的厚度之和大于所述像素定义层的厚度。
  11. 如权利要9所述的显示面板，其中，所述填充层的材料包括聚酰亚胺、聚乙烯、聚萘二甲酸乙二醇酯和六甲基二甲硅醚中的一种或几种组合。
  12. 如权利要求9所述的显示面板，其中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
  13. 如权利要求9所述的显示面板，其中，所述显示面板还包括阻挡层，所述阻挡层覆盖所述阴极层及所述填充层。
  14. 如权利要求9所述的显示面板，其中，所述显示面板还包括平坦层，所述平坦层设置于所述阵列基板上，所述平坦层包括第二通孔，所述第二通孔贯穿所述平坦层以暴露所述阵列基板，所述阳极层设置于所述第二通孔中及所述平坦层上与所述阵列基板电连接。
  15. 如权利要求13所述的显示面板，其中，所述显示面板还包括封装层，所述封装层设置于所述阻挡层上。
  16. 如权利要求15所述的显示面板，其中，所述显示面板还包括覆盖层，所述覆盖层设置于所述封装层上。
  17. 一种显示面板的制备方法，其包括：
    提供一阵列基板；
    在所述阵列基板上形成阳极层；
    在所述阳极层上形成像素定义层；
    对所述像素定义层进行蚀刻，形成第一通孔，所述第一通孔贯通所述像素定义层以暴露所述阳极层；
    在所述第一通孔中形成发光层；
    在所述像素定义层上和所述发光层上覆盖有阴极层，所述阴极层包括凹槽，所述凹槽位于所述第一通孔上；
    在所述凹槽中采用喷墨打印方法打印填充层材料，形成填充层。
  18. 如权利要求17所述的显示面板的制备方法，其中，所述在所述凹槽中采用喷墨打印方法打印填充层材料，形成填充层的步骤之后，还包括在所述阴极层及所述填充层上形成阻挡层。
  19. 如权利要求17所述的显示面板的制备方法，其中，所述在所述阴极层及所述填充层上形成阻挡层的步骤之后还包括：
    在所述阻挡层上形成封装层。
  20. 如权利要求17所述的显示面板的制备方法，其中，所述填充层的表面高于所述阴极层的表面或者与所述阴极层的表面平齐。
PCT/CN2020/083366 2020-03-18 2020-04-03 显示面板及其制备方法 WO2021184441A1 (zh)

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