WO2021179279A1 - 一种半导体发光元件及其制作方法 - Google Patents

一种半导体发光元件及其制作方法 Download PDF

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Publication number
WO2021179279A1
WO2021179279A1 PCT/CN2020/079155 CN2020079155W WO2021179279A1 WO 2021179279 A1 WO2021179279 A1 WO 2021179279A1 CN 2020079155 W CN2020079155 W CN 2020079155W WO 2021179279 A1 WO2021179279 A1 WO 2021179279A1
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Prior art keywords
light
area
semiconductor light
emitting element
protrusions
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PCT/CN2020/079155
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English (en)
French (fr)
Inventor
陈功
许圣贤
林素慧
彭康伟
洪灵愿
何敏游
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厦门三安光电有限公司
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Priority to CN202080003013.8A priority Critical patent/CN112236873B/zh
Priority to PCT/CN2020/079155 priority patent/WO2021179279A1/zh
Publication of WO2021179279A1 publication Critical patent/WO2021179279A1/zh
Priority to US17/930,109 priority patent/US20230006096A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the invention relates to a semiconductor light-emitting element with improved light extraction efficiency and a manufacturing method thereof.
  • LED Semiconductor light-emitting element
  • Semiconductor light-emitting elements include front-mounted, flip-chip and vertical chips according to different shapes and electrode positions.
  • the existing blue light-emitting semiconductor light-emitting elements are horizontally wired, and are mainly used in fields such as lighting, white light, and display.
  • the form-mounted semiconductor light-emitting element includes a sapphire light-transmitting substrate 100 and a semiconductor light-emitting sequence stacked on the sapphire light-transmitting substrate in sequence.
  • the semiconductor light-emitting sequence includes a first conductive semiconductor layer 101, a light emitting layer 102, and a The second conductivity type semiconductor layer 103, wherein the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are respectively provided with electrodes of different polarities.
  • the semiconductor light-emitting sequence is also covered with an insulating layer, and the refractive index of the transparent substrate and the insulating layer are generally lower than the refractive index of the semiconductor light-emitting sequence.
  • part of the light in the A direction generated by the light-emitting layer will be directed to the second conductivity type semiconductor layer 103
  • part of the light in the B direction will be directed to the sidewall of the semiconductor light emitting sequence
  • part of the light in the C direction will be directed to the light-transmitting substrate.
  • Due to the difference in refractive index between the semiconductor light-emitting sequence and the insulating layer and the light-transmitting substrate the light in the A, B, and C directions is easily confined to the inside of the semiconductor light-emitting element and reflected back and forth, resulting in low light-emitting efficiency of the semiconductor light-emitting element.
  • the prior art discloses that by roughening or patterning the light-emitting surface to change the critical angle, the light in the A direction can be refracted on the light-emitting surface to directly emit the semiconductor light-emitting element. , Improve the efficiency of the front light.
  • changing the sidewalls of the semiconductor light-emitting sequence to be inclined relative to the horizontal direction can also improve the front light emission efficiency.
  • the sapphire substrate is covered with protrusions, which have relatively inclined sidewalls to facilitate more reflection and diffraction of light when the light in the C direction hits the surface of the pattern, and also improve the light extraction efficiency.
  • the convex portion is a heterogeneous convex portion 110, which has a lower refractive index than a light-transmitting substrate, such as silicon oxide, to increase the refractive index difference between the semiconductor light-emitting sequence and the convex portion, and can further improve the light.
  • the reflectivity that reaches the surface of the graphic improves the efficiency of light emission in the forward direction.
  • the prior art discloses that on the back side of the sapphire transparent substrate 100 A reflective layer 106 is provided on the side, and the back side of the sapphire light-transmitting substrate is reflected by the reflective layer, and light can be emitted from the sidewall of the sapphire light-transmitting substrate or the sidewall of the semiconductor light-emitting sequence or the front surface of the semiconductor light-emitting sequence.
  • the present invention aims to further improve the light extraction efficiency of the light emitting element.
  • a semiconductor light emitting element which includes: a light-transmitting substrate composed of a first material, the light-transmitting substrate having a first surface, and the first surface includes a first region and a second region;
  • the semiconductor light-emitting sequence is stacked on the first area of the first surface of the light-transmitting substrate, and includes a first conductive semiconductor layer, a light-emitting layer, and a second conductive semiconductor layer in sequence from the first surface; the first of the light-transmitting substrate
  • the first area of the surface has a first surface area and a first projected area.
  • the second area of the first surface of the light-transmitting substrate has a second surface area and a second projected area.
  • the ratio of the second surface area to the second projected area is greater than the first surface area. The ratio to the first projected area.
  • a second aspect of the present invention provides the following method for manufacturing a semiconductor light-emitting element, which includes the following steps:
  • a semiconductor light emitting sequence is formed on the first surface of the light-transmitting substrate
  • the semiconductor light-emitting sequence is etched from the side of the semiconductor light-emitting sequence away from the light-transmitting substrate to form a groove exposing the light-transmitting substrate.
  • the first surface of the substrate covered by the semiconductor light-emitting sequence is defined as the first region.
  • the first surface of the light-transmitting substrate around the light emitting sequence is defined as a second area, the first area has a first surface area and a first projected area, and the second area has a second surface area and a second projected area;
  • 1 to 2 are schematic diagrams of the structure of the semiconductor light-emitting element mentioned in the background art.
  • FIG. 3 is a schematic diagram of the structure of the semiconductor light-emitting element mentioned in the first embodiment.
  • 4 to 9 are schematic diagrams of the intermediate structures of each step of the specific manufacturing method of the semiconductor light-emitting device structure of the first embodiment.
  • FIG. 10 is a schematic diagram of the structure of the semiconductor light-emitting element mentioned in the second embodiment.
  • 11 to 12 are schematic diagrams of the structure of the semiconductor light-emitting element mentioned in the third embodiment.
  • FIG. 13 is a schematic diagram of the structure of the semiconductor light-emitting element mentioned in the fourth embodiment.
  • FIG. 14 is a schematic diagram of the structure of the semiconductor light-emitting element mentioned in the fifth embodiment.
  • 100 light-transmitting substrate; 101: first conductivity type semiconductor layer; 102: light-emitting layer; 103: second conductivity type semiconductor layer; 104: first electrode; 105: second electrode; 106: reflective layer; 110: different Qualitative protrusion; 100A: first area; 100B: second area; 111: first protrusion; 112: second protrusion; 113: groove.
  • the present invention provides a semiconductor light-emitting element including: a light-transmitting substrate 100, the light-transmitting substrate 100 has a first surface, and the first surface includes a first region 100A and a second region 100B.
  • the semiconductor light emitting sequence stacked on the first area 100A of the first surface of the light-transmitting substrate 100, includes a first conductivity type semiconductor layer 101, a light emitting layer 102, and a second conductivity type semiconductor layer 103;
  • the first area 100A is flat or non-planar, the first area 100A of the first surface of the light-transmitting substrate 100 has a first surface area and a first projected area, and the second area 100B of the first surface of the light-transmitting substrate 100 has a second The ratio of the surface area to the second projected area, and the ratio of the second surface area to the second projected area is greater than the ratio of the first surface area to the first projected area.
  • the first electrode 104 and the second electrode 105 are respectively arranged on the semiconductor light emitting sequence.
  • the second area 100B It has a larger relative surface area and higher surface unevenness, that is, a relatively larger proportion of non-horizontal or inclined surfaces, which is conducive to the refraction of part of the light in the D direction from the surface of the first surface and the second area 100B of the substrate ,
  • the light is emitted directly, the propagation distance of the light in the D direction in the substrate is shortened, the loss caused by light absorption is reduced, and the light extraction efficiency is improved.
  • the light from the part B direction is emitted from the sidewall of the semiconductor light-emitting sequence and reaches the surface of the second region 100B to be reflected, which can also increase the forward light emission and improve the light emission efficiency.
  • the specific manufacturing method of the semiconductor light-emitting element structure of the present invention includes the following steps:
  • a light-transmitting substrate 100 is selected.
  • the light-transmitting substrate 100 is composed of a first material and has a first surface and a second surface opposite to each other.
  • the first surface of 100 forms a semiconductor light emitting sequence.
  • the light-transmitting substrate 100 may be a sapphire light-transmitting substrate, and the refractive index of the sapphire (about 1.7) is lower than the refractive index of the semiconductor light-emitting sequence (the refractive index of the nitride semiconductor light-emitting sequence is about 2.5-3.0).
  • the transmittance of the substrate is determined by the transmittance of the material of the substrate to the light-emitting layer. In the present invention, the transmittance of the transparent substrate is at least 60%.
  • the first surface of the transparent substrate 100 is a flat surface.
  • the first surface of the light-transmitting substrate 100 may be covered with a plurality of heterogeneous protrusions 110.
  • the heterogeneous protrusion 110 is composed of a second material, which is different from the first material.
  • the refractive index of the second material is lower than the refractive index of the semiconductor light-emitting sequence and lower than the refractive index of the first material.
  • the light radiated by the light-emitting layer 102 can reach the heterogeneous protrusion 110
  • the reflectivity of the surface is higher than the reflectivity of the surface reaching the transparent substrate, which improves the light extraction efficiency of the light from the light-emitting layer 102 in a direction away from the substrate.
  • the heterogeneous protrusion 110 may be one or more of silicon oxide, silicon nitride, or metal oxide.
  • the heterogeneous protrusion 110 is a cone-shaped figure, and the side of the cone-shaped figure has a fixed or non-fixed inclination angle. Specifically, there is a distance between two adjacent cones, wherein each cone includes a top, a bottom, and an inclined side wall between the top and the bottom, and the inclined side wall surrounds the top and the bottom, and The top and bottom top views can be circular.
  • Each cone is periodically arranged on the light-transmitting substrate 100, and the periodicity can be a fixed period, a variable period or a quasi-period, which means that the distance between the two heterogeneous protrusions 110 can be For regular or irregular.
  • the width of the top of each cone is smaller than the width of the bottom, or the width of the top may be zero.
  • a plurality of heterogeneous protrusions 110 may be formed on the first surface of the sapphire transparent substrate 100 through a thin film deposition process combined with a photomask process and an etching process.
  • the light-transmitting substrate 100 is sapphire
  • the heterogeneous protrusions 110 are silicon oxide.
  • a silicon oxide film is first deposited on the sapphire light-transmitting substrate 100, and then a photomask process and a dry or wet etching process are combined to form the oxide. Silicon heterogeneous bumps 110.
  • the dry etching may be inductively coupled plasma etching (ICP etching), and the etching gas for ICP etching may be BCl 3 , HBr, SF 6 , CF4, C4F 8 , CHF 3 , Ar or O 2 .
  • the wet etching process uses HF or BOE solution.
  • a photomask pattern of a specific size and shape can be formed on the surface of the silicon oxide film before etching, and then the silicon oxide film can be etched using the photomask pattern as a mask to obtain the target heterogeneous protrusion 110 size And shape.
  • the heterogeneous protrusion 110 has an arc protruding from the inclined side, the arc has an inclined surface with an unfixed inclination angle, and the width of the top is zero.
  • the arc has an inclined surface with an unfixed inclination angle, which can make the light emitted by the light-emitting layer 102 reach the arc-shaped cone surface to produce more diffuse reflection, thereby improving light extraction.
  • a dry etching process may be used to form the heterogeneous convex portion 110 with an arc-shaped inclined side.
  • the size of the heterogeneous convex portion 110 is a width dimension between 0.1-10 micrometers, a height between 0.1-3 micrometers, and an interval of 0.01-0.9 micrometers.
  • the semiconductor light-emitting sequence is formed on the first surface of the substrate by an epitaxial process, and the semiconductor light-emitting sequence simultaneously covers the heterogeneous protrusion 110, wherein the epitaxial process may include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or hydrogenation Vapour phase epitaxy (HVPE) and other similar epitaxial processes.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • HVPE hydrogenation Vapour phase epitaxy
  • the semiconductor light emitting sequence includes a first conductivity type semiconductor layer 101, a second conductivity type semiconductor layer 103 and a light emitting layer 102, wherein the light emitting layer 102 is located between the first conductivity type semiconductor layer 101 and the second conductivity type semiconductor layer 103.
  • the semiconductor light-emitting sequence stack layer is an AlN buffer layer, an N-type layer (first conductive semiconductor layer), a light-emitting layer, and a P-type layer (the first conductive semiconductor layer) which are sequentially stacked on the light-transmitting substrate 100 Two-conductivity semiconductor layer).
  • the AlN buffer layer can effectively alleviate the lattice mismatch between sapphire and GaN.
  • the thickness of the AlN buffer layer may be 0.5 nm to 5 ⁇ m.
  • the thickness of the AlN buffer layer is less than 0.5 nm, it cannot play the role of mitigating the lattice mismatch; when the thickness of the AlN buffer layer is greater than 5 ⁇ m, material waste is caused and the implementation cost is increased.
  • the light-emitting layer 102 can provide luminescent radiation between 420 and 550 nm, such as blue light and green light.
  • the N-type layer can be an AlxIn1-xGaN layer (0 ⁇ x ⁇ 1), and the light-emitting layer 102 can be alternately stacked.
  • the well layer is an InGaN layer and an epitaxial GaN layer (or AlGaN layer), and the P-type layer is an AlyIn1-yGaN layer (0 ⁇ y ⁇ 1) layer.
  • part of the second conductivity type semiconductor layer 103 and the light emitting layer 102 are etched to expose part of the first conductivity type semiconductor layer 101.
  • a light-emitting platform area for setting the second electrode 105 (for example, P electrode) type electrode on the surface of the second conductivity type semiconductor layer 103 is defined a light-emitting platform area for setting the second electrode 105 (for example, P electrode) type electrode, and on the top surface of the first conductivity type semiconductor layer 101 is defined A region of the first electrode 104 (for example, an N-type electrode) is provided.
  • An etching process may be used, such as a dry etching process to etch part of the P-type layer and the light-emitting layer 102 to expose the N-type layer, preferably an inductively coupled plasma reactive ion etching process.
  • the N-type layer is exposed to form an area where the N-type electrode is installed.
  • a cutting process or an ICP etching process is performed to remove the semiconductor light-emitting sequence from the side of the semiconductor light-emitting sequence away from the transparent substrate 100 to form a groove surrounding the semiconductor light-emitting sequence.
  • the groove may be U-shaped, the groove surrounds the semiconductor light emitting sequence on the first surface of the light-transmitting substrate 100, and the bottom of the groove makes a partial area of the first surface of the light-transmitting substrate 100 and The plurality of heterogeneous protrusions 110 are exposed.
  • the area covered by the semiconductor light emitting sequence on the first surface of the transparent substrate 100 is defined as the first area 100A, and the area not covered by the semiconductor light emitting sequence is the second area 100B.
  • the surfaces of the first region 100A and the second region 110B are both covered with heterogeneous protrusions 110.
  • the first area 100A of the first surface of the substrate has a first surface area and a first projected area.
  • the projected area is a projected area of the first surface relative to a horizontal plane, and the horizontal plane is perpendicular to the stacking direction of the conductor light emitting sequence.
  • the first surface area and the first projected area are only the area of the first area 100A and the second area 100B of the first surface of the substrate body, excluding the area of the surface of the heterogeneous protrusion.
  • the ratio of the first surface area to the first projected area is 1, and the ratio of the second surface area to the second projected area is 1.
  • the second area 100B of the first surface of the substrate has a second surface area and a second projected area.
  • the first surface area and the first projected area are only the area of the first area 100A and the second area 100B of the first surface of the substrate body, excluding the area of the heterogeneous protrusion.
  • an etching process is performed to etch the second area 100B of the first surface of the light-transmitting substrate 100, so that the second area 100B of the first surface of the light-transmitting substrate 100 has a second surface area and a second surface area. Projected area, and the ratio of the second surface area to the second projected area is higher than the ratio of the first surface area to the second projected area of the first region 100A.
  • the surface topography of the second area can be improved to obtain a plurality of convexities and concavities.
  • the uneven structure makes the surface of the second area uneven, and has a more inclined surface relative to the plane, so that when light reaches its surface from the second surface side of the substrate, more proportions can occur The refraction is more conducive for the light to reach the surface of the second area and emit light directly.
  • the second area 100B of the first surface of the substrate with multiple uneven structures has a larger unit surface area than the first area 100A, that is, the second area 100B has a ratio of the second surface area to the second projected area. It is higher than the ratio of the first surface area to the second projected area of the first region 100A.
  • the projected area is the projected area of the first surface of the light-transmitting substrate 100 along a horizontal plane.
  • the plurality of uneven structures includes a plurality of first protrusions 111 and recesses between the first protrusions 111, the first protrusions 111 may have a top and side walls, and the top may be dotted or flat. .
  • the plurality of uneven structures may have at least one inclined surface with a fixed inclination rate with respect to the horizontal plane.
  • the heterogeneous protrusions are stacked on the surface of the second area of the transparent substrate, in order to form an uneven structure in the second area 100B of the first surface of the transparent substrate 100, the heterogeneous protrusions can be used as a mask. , Using a wet etching process to etch the second area of the first surface of the substrate. Taking a sapphire single crystal substrate as an example, due to wet etching, the second area of the first surface of the sapphire substrate can be etched simultaneously in both the horizontal and vertical directions, thereby forming a plurality of protrusions with inclined sidewalls As well as the recesses between the multiple protrusions, it is beneficial to increase the surface area.
  • the ratio of the height of the first protrusion to the width of the bottom is at least 1:1, and at most 1:3.
  • the greater the ratio of the height of the first protrusion to the width of the bottom the greater the surface area of the side wall, which is more conducive to the extraction of light in the D direction from the substrate. If the ratio of the height to the width of the bottom is low, the inclination angle of the side wall is insufficient. Then, the proportion of the light in the D direction that is refracted from the surface of the second region of the substrate is relatively low, and a too high ratio of the height to the bottom width will cause the light to be confined between the plurality of first protrusions, causing light loss.
  • the height of the first protrusion is 0.1 micrometer or more and 2 micrometer or less.
  • the light-transmitting substrate is a sapphire single crystal substrate
  • the wet etching solution may be a mixture of sulfuric acid and phosphoric acid, the volume ratio of phosphoric acid to sulfuric acid is 1: (1.5-5), and the etching temperature It is 240 ⁇ 280°C.
  • the volume ratio of phosphoric acid and sulfuric acid is 1:(2.5-4),
  • the etching temperature is 240 to 280°C.
  • the second area 100B of the first surface of the substrate has the following wet etching process.
  • the heterogeneous protrusion 110 covers the surface of the second area 100B, the direction indicated by the arrow is different
  • the quality protrusion 110 is a mask.
  • the etching solution longitudinally etches the surface of the substrate surrounding the heterogeneous protrusion 110.
  • multiple recesses are gradually formed on the surface of the substrate around the heterogeneous protrusions 110, and the surface of the substrate below the heterogeneous protrusions 110 will have inclined sidewalls due to the isotropic wet etching. Therefore, when the inclined sidewalls are formed, the solution will simultaneously etch laterally along the sidewalls and longitudinally etch along the recesses until the target depth and width of the first protrusion 110 are obtained.
  • the first protrusion 111 is formed on the surface of the substrate below the heterogeneous protrusion 110.
  • the first protrusion 111 has a top, and the top may be a dot or a platform, and the side wall of the first protrusion 111 has an inclined surface. Since wet etching has different etching rates for different crystal planes of the crystal (for example, the R-plane, C-plane, and A-plane of the sapphire substrate), the sidewall of the first protrusion 111 may include at least one crystal plane exposed to form a slope
  • the inclined surface has at least one fixed slope. Opposing recesses are formed between the first protrusions 111.
  • the heterogeneous protrusion 110 may also be partially etched, and the final surface of the first protrusion 111 may have patterns or heterogeneous protrusions remaining on the surface.
  • the qualitative protrusions 110 are completely removed, exposing all the surfaces of the first protrusions 110.
  • a transparent conductive film (not shown in the figure) is formed on the P-type layer, a second electrode 105 (P electrode) is formed on the transparent conductive film, a first electrode 104 (N electrode) is formed on the N-type layer, and
  • the insulating layer covers the surface of the semiconductor light-emitting sequence and the first surface second region 100B of the transparent substrate 100. As shown in Figure 9.
  • the transparent conductive film can be indium tin oxide (ITO), aluminum-doped zinc oxide transparent conductive glass (AZO), gallium-doped zinc oxide transparent conductive glass (GZO), indium gallium zinc oxide (IGZO), NiAu, A kind of graphene.
  • ITO indium tin oxide
  • AZO aluminum-doped zinc oxide transparent conductive glass
  • GZO gallium-doped zinc oxide transparent conductive glass
  • IGZO indium gallium zinc oxide
  • NiAu NiAu
  • the first electrode 104 and the second electrode 105 are partially arranged on the side of the semiconductor light-emitting sequence away from the substrate, and the side of the semiconductor light-emitting sequence away from the substrate is the light-emitting surface.
  • the second electrode 105 may be formed by stacking one or more of Cr, Pt, Au, Ti, Ni, Al, Mo, and Pd
  • the first electrode 104 may be One or more metals of Cr, Pt, Au, Ti, Ni, Al, Mo, and Pd are stacked.
  • a single semiconducting light-emitting element is obtained by cutting and separating the substrate from the position of the second region on the first surface of the light-transmitting substrate. As shown in Figure 3.
  • the second surface of the transparent substrate 100 can be provided with a distributed Bragg reflector DBR or a metal reflective layer such as Ag or Al to improve light efficiency.
  • FIG. 2 is a semiconductor light emitting element structure in the prior art.
  • the first surface of the transparent substrate 100 around the first conductive semiconductor layer 100 is exposed.
  • Part of the first surface of the substrate 100 is reflected, and the other part of the light passes through the transparent substrate 100 and reaches the second surface of the transparent substrate 100.
  • the refractive index of the transparent substrate 100 is higher than that of air or the transparent substrate.
  • the second surface of the bottom has a reflective layer, so the light reaching the second surface of the light-transmitting substrate will be further reflected, and the reflected light beam will come from the sidewall of the epitaxial layer or the second area 100B of the first surface of the light-transmitting substrate 100 Or the sidewall of the light-transmitting substrate 100 escapes. If the second area of the first surface of the light-transmitting substrate 100 is flat, the light will be easily reflected when it reaches the second area 100B of the first surface, causing the light to continue to propagate in the substrate, and it is easy to be absorbed. Loss affects the light extraction efficiency.
  • the present invention changes the topography of the second area 100B of the first surface of the light-transmitting substrate 100 to have the first convex portion 111 and the concave portion between the first convex portion, so that the first surface Compared with the first area 100A, the second area 100B has a larger surface area to projected area ratio.
  • a larger specific surface area means greater unevenness, and a relatively inclined surface with a larger proportion is more conducive to D
  • the light in the direction of the second region 100B of the first surface of the light-transmitting substrate 100 directly overflows and is directed to the air, thereby improving the light escape efficiency of this part.
  • the light from the part B direction is emitted from the sidewall of the semiconductor light-emitting sequence and reaches the surface of the second region 100B to be reflected, which can also increase the forward light emission and improve the light emission efficiency.
  • the wet etching step of step 4) in the first embodiment can also simultaneously etch the sidewalls of the semiconductor light emitting sequence, including at least the sidewalls of the first conductivity type semiconductor layer 101 to form inclined sidewalls.
  • the sidewalls of the first conductive semiconductor layer 101 and the aluminum nitride layer have at least one inclined surface, and have at least one inclined angle relative to the stacking direction of the semiconductor light emitting sequence.
  • the angle ranges are all less than 90°, and there may be multiple inclined surfaces, and the multiple inclined surfaces may not be parallel.
  • the inclined side wall can be used as a total reflection surface, so that light is reflected to other inclined side walls in the upper part to emit light, or reflected to the top surface of the semiconductor light emitting sequence to emit light, Can increase the efficiency of the light source.
  • the wet etching solution may be a mixed solution of sulfuric acid and phosphoric acid, the volume ratio of phosphoric acid to sulfuric acid is 1: (1.5-5), and the etching temperature is 240-280°C.
  • the etching temperature is 240-280°C.
  • the first surface of the light-transmitting substrate 100 is not necessarily flat.
  • a plurality of heterogeneous protrusions 110 are formed on the first surface of the sapphire transparent substrate 100 by a thin film deposition process combined with an etching process, and the heterogeneous protrusions 110 are dispersed on the transparent substrate 100 at a certain distance. on the surface.
  • the silicon oxide film is etched by dry etching to form a plurality of separated heterogeneous protrusions 110, so that the first surface of the transparent substrate 100 is exposed.
  • the dry etching gas may also cause the sapphire substrate
  • the first surface of the bottom is etched to form a plurality of protrusions.
  • the convex portion is defined as the second convex portion 112, and the second convex portion 112 is covered by the heterogeneous convex portion 110.
  • the ratio of the depth of the heterogeneous protrusions 110 to the depth of the second protrusions 112 is at least 9:1.
  • the second region is etched by the etching process in step 4) of the first embodiment to form the first protrusion 111.
  • the heterogeneous protrusions 110 are used as a mask, and the etching solution etches the second region of the light-transmitting substrate 100 around the heterogeneous protrusions.
  • the heterogeneous protrusions 110 cover the second protrusions 112, and the second protrusions
  • the portion 112 already has sidewalls relative to the surrounding recesses, so the etching process will be carried out in the horizontal and longitudinal directions at the same time, and finally a second convexity relative to the first area is formed between the heterogeneous convex portions 112 on the second area.
  • the semiconductor light-emitting sequence covers the first area 100A of the first surface of the light-transmitting substrate 100, the second protrusion 112 and the second protrusion of the first area 100
  • the recesses between the portions 112 make the ratio of the first surface area to the first projected area greater than one.
  • the first raised portion 111 of the second area 100B has a deeper thickness than the second raised portion 112 of the first area 100A.
  • the first raised portion 111 has an inclined surface with a larger area ratio.
  • the second area 100B has a larger ratio of the second surface area to the second projected area, which is more conducive to light refracting from the second area and directly emitting light.
  • the heterogeneous protrusions covered on the second area 100B of the first surface of the light-transmitting substrate 100 can be removed, exposing the second area 100B of the first surface of the light-transmitting substrate 100 A raised portion 111.
  • the heterogeneous protrusions 111 may be removed in the process of step 4) of the first embodiment or after the step, the heterogeneous protrusions 111 may be removed by an additional etching step (for example, a BOE etching solution).
  • a plurality of partial grooves 113 extending to a certain depth inside the first conductivity type semiconductor layer can be formed on the sidewall of the first conductivity type semiconductor layer.
  • the surfaces of the first protrusions 111 and the recesses between the first protrusions 111 are continuously insulated Layer coverage.
  • the first surface of the light-transmitting substrate 100 is not necessarily covered with heterogeneous protrusions 110.
  • the etching process requires additional production of mask patterns, such as photoresist patterns, arranged in the second area 100B of the first surface of the substrate, and the photoresist patterns are used as a mask.
  • the pattern is wet-etched on the first surface of the substrate to form a plurality of recesses and first protrusions 111 around the recesses.
  • the sidewalls of the first protrusions 111 have at least one slope with a fixed slope to make the final light transmittance.
  • the second area 100B on the first surface of the substrate 100 has a larger ratio of the first surface area to the first projected area than the first area 100A, which is more conducive to light refracting from the second area and directly emitting light.

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Abstract

一种半导体发光元件，其包括：透光衬底，由第一材料组成，透光衬底具有第一表面，第一表面包括第一区域和第二区域；半导体发光序列，堆叠在透光衬底的第一表面的第一区域，自第一表面开始依次包括第一导电型半导体层、发光层和第二导电型半导体层；透光衬底的第一表面的第一区域具有第一表面积与第一投影面积，透光衬底的第一表面第二区域具有第二表面积与第二投影面积，第二表面积与第二投影面积的比值大于第一表面积与第一投影面积的比值。

Description

一种半导体发光元件及其制作方法 技术领域
涉及一种提高出光效率的半导体发光元件及其制作方法。
背景技术
半导体发光元件(LED)是一种能发光的半导体电子元件，具有体积小、亮度高、能耗小的特点，被广泛地应用于显示屏、背光源和照明领域。
半导体发光元件包括根据不同形状和电极位置主要包括正装、倒装和垂直芯片。
而现有的蓝光正装半导体发光元件是水平打线方式，主要用于照明、白光、显示等领域。如图1所示，正装半导体发光元件包括蓝宝石透光衬底100、以及依次层叠在蓝宝石透光衬底上的半导体发光序列，半导体发光序列包括第一导电型半导体层101、发光层102、第二导电型半导体层103，其中第一导电型半导体层和第二导电型半导体层上分别设置有不同极性的电极。半导体发光序列的周围还会包覆有一层绝缘层，该透光衬底和绝缘层的折射率通常都低于半导体发光序列的折射率。
图1所示，发光层产生的一部分A方向的光会射向第二导电型半导体层103，一部分B方向的光射向半导体发光序列的侧壁，一部分的C方向的光射向透光衬底。易受制于半导体发光序列与绝缘层、透光衬底之间的折射率差异，A、B、C方向的光容易局限在半导体发光元件内部来回反射，造成半导体发光元件的出光效率较低。
为了提高出光效率，如图2所示，已有现有技术揭露，通过出光面的粗化或图形化处理以改变临界角，能够促进A方向的光在出光面上发生折射直接射出半导体发光元件，提升正面出光效率。
此外，改变半导体发光序列的侧壁相对水平方向为倾斜，也可提升正面出光效率。
另外，在蓝宝石衬底上覆盖有凸起部，凸起部具有相对倾斜的侧壁，以利于C 方向的光射向图形表面时产生更多的光的反射和衍射，也可提高出光效率。进一步的，凸起部为异质凸起部110，具有相对于透光衬底更低折射率，例如氧化硅，以增加半导体发光序列与凸起部之间的折射率差异，能进一步提升光到达图形表面的反射率，提升正向出光效率。
此外，还有一部分的D方向的光穿过透光衬底到达透光衬底的背面侧，为改善这部分光的出光效率，已有现有技术揭露，在蓝宝石透光衬底100的背面侧设置反射层106，在蓝宝石的透光衬底的背面侧再经过反射层的反射，可从蓝宝石透光衬底的侧壁或者半导体发光序列的侧壁或者半导体发光序列的正面出光。
发明概述
技术问题
问题的解决方案
技术解决方案
本发明旨在进一步改善发光元件的出光效率。
本发明的第一方面，提供如下一种半导体发光元件，其包括：透光衬底，由第一材料组成，透光衬底具有第一表面，第一表面包括第一区域和第二区域；
半导体发光序列，堆叠在透光衬底的第一表面的第一区域，自第一表面开始依次包括第一导电型半导体层、发光层和第二导电型半导体层；透光衬底的第一表面的第一区域具有第一表面积与第一投影面积，透光衬底的第一表面第二区域具有第二表面积与第二投影面积，第二表面积与第二投影面积的比值大于第一表面积与第一投影面积的比值。
本发明的第二方面，提供如下一种半导体发光元件的制作方法，其包括如下步骤：
1)在透光衬底的第一表面上形成半导体发光序列；
2)从半导体发光序列的远离透光衬底的一侧开始蚀刻半导体发光序列，以形成露出透光衬底的凹槽，半导体发光序列覆盖的衬底的第一表面定义为第一区域，半导体发光序列周围的透光衬底的第一表面定义为第二区域，第一区域具有第一表面积与第一投影面积，第二区域具有第二表面积与第二投影面积；
3)蚀刻透光衬底的第一表面的第二区域，使第二表面积与第二投影面积的比 值大于第一表面积与第一投影面积的比值。
发明的有益效果
有益效果
在具体实施方式中会对本发明的第一方面和第二方面方案的有益效果进行详细说明。
对附图的简要说明
附图说明
图1～2是背景技术中提到的半导体发光元件的结构示意图。
图3是实施例一提到的半导体发光元件的结构示意图。
图4～9是实施例一的半导体发光元件结构的具体制作方法的每一步骤的中间结构示意图。
图10是实施例二提到的半导体发光元件的结构示意图。
图11～12是实施例三提到的半导体发光元件的结构示意图。
图13是实施例四提到的半导体发光元件的结构示意图。
图14是实施例五提到的半导体发光元件的结构示意图。
附图标记：
100：透光衬底；101：第一导电型半导体层；102：发光层；103：第二导电型半导体层；104：第一电极；105：第二电极；106：反射层；110：异质凸起部；100A：第一区域；100B：第二区域；111：第一凸起部；112：第二凸起部；113：凹槽。
发明实施例
本发明的实施方式
实施例一
如图3所示，本发明提供如下一种半导体发光元件，其包括：透光衬底100，透光衬底100具有第一表面，第一表面包括第一区域100A和第二区域100B。
半导体发光序列，堆叠在透光衬底100的第一表面的第一区域100A，依次包括第一导电型半导体层101、发光层102和第二导电型半导体层103；衬底的第一表 面的第一区域100A为平面或者非平面，透光衬底100的第一表面的第一区域100A具有第一表面积与第一投影面积，透光衬底100的第一表面第二区域100B具有第二表面积与第二投影面积，第二表面积与第二投影面积的比值大于第一表面积与第一投影面积的比值，在半导体发光序列上分别设置第一电极104和第二电极105。
通过半导体发光序列周围的第二区域100B的第二表面积与第二投影面积的比值大于半导体发光序列下方的第一区域100A的第一表面积与第一投影面积的比值的设计，使第二区域100B具有更大的相对表面积，具有更高表面不平整度，即相对更大占比的非水平面或倾斜面，有利于D方向的部分光从衬底的第一表面第二区域100B的表面发生折射，直接出光，缩短D方向的光在衬底内的传播距离以及减少光吸收导致的损失，提高出光效率。同时从部分B方向的光从半导体发光序列的侧壁射出，到达第二区域100B的表面发生反射，也可以提升正向的出光，提高出光效率。
在下文中，会描述本发明的半导体发光元件结构的具体制作方法和本发明的半导体发光元件的结构，使得本技术领域中的一般技术人员可以实施本发明。这些具体实施方法可以参考相对应的附图，使得所述附图构成实施方法的一部分。虽然本发明的优选实施例揭露如下，但不是用来限定本发明，任何本领域的技术人员，在不违背本发明的精神和范畴内，可以作些许的更动和修改。
本发明半导体发光元件结构的具体制作方法包括以下步骤：
1)如图4所示，选择一透光衬底100，所述的透光衬底100由第一材料组成，且具有相对的第一表面和第二表面，利用外延工艺在透光衬底100的第一表面形成半导体发光序列。
其中透光衬底100，可以是蓝宝石透光衬底，其蓝宝石的折射率(1.7左右)低于半导体发光序列的折射率(氮化物半导体发光序列的折射率为2.5～3.0左右)。衬底的透光性决定于衬底的材料本身对发光层的透射率，本发明中，所述的透光衬底的透光率至少为60％以上。
本实施例中透光衬底100为的第一表面为平面。
透光衬底100的第一表面上可覆盖有多个异质凸起部110。其中异质凸起部110 由第二材料组成，第二材料不同于第一材料。优选地，第二材料的折射率低于半导体发光序列的折射率并且低于第一材料的折射率，相较于透光衬底，可使发光层102辐射的光到达异质凸起部110表面的反射率高于到达透明衬底的表面的反射率，提升发光层102的光从远离衬底的方向的出光效率。具体的，异质凸起部110可以是氧化硅或氮化硅或金属氧化物中的一种或多种。
优选地，异质凸起部110为锥型图形，锥形图形的侧边具有固定或者不具有固定的倾斜角度。具体的，两个相邻的锥形之间具有一间距，其中，每一个锥形包含一顶部、一底部以及位于顶部与底部之间的一倾斜侧壁，倾斜侧壁环绕顶部及底部，且顶部及底部的上视图可为圆形。每一个锥形是以周期方式设置于透光衬底100上，且此周期方式可为固定周期、可变周期或准周期，意即，位于两个异质凸起部110之间的间距可为规则或不规则。每一个锥形图形的顶部的宽度小于底部的宽度，或者顶部的宽度可以是0。
可通过薄膜沉积工艺结合光罩工艺以及蚀刻工艺在蓝宝石透光衬底100的第一表面上形成多个异质凸起部110。例如透光衬底100为蓝宝石，异质凸起部110为氧化硅，在蓝宝石透光衬底100上先沉积一层氧化硅薄膜，然后结合光罩工艺以及干法或湿法蚀刻工艺形成氧化硅的异质凸起部110。所述的干法蚀刻可以是感应耦合等离子体刻蚀(ICP刻蚀)，ICP刻蚀的刻蚀气体可以是BCl 3、HBr、SF 6、CF4、C4F 8、CHF 3、Ar或O 2。所述的湿法蚀刻工艺采用HF或者BOE溶液。进一步的，可在蚀刻前先形成特定尺寸和形状的光罩图形在氧化硅薄膜表面，然后以光罩图形为掩膜对氧化硅薄膜进行蚀刻，以获得目标的异质凸起部110的尺寸和形状。
优选地，异质凸起部110具有从倾斜侧边突起的一弧部，该弧部具有不固定倾斜角度的倾斜面，顶部的宽度是0。相对于固定的倾斜角度的倾斜面，弧部具有不固定倾斜角度的倾斜面，可使得发光层102发出的光到达弧形的锥形体表面产生更多的漫反射现象，进而提高光取出。可采用干法蚀刻工艺形成倾斜侧边为弧形的异质凸起部110。
优选地，异质凸起部110的尺寸为0.1～10微米之间的宽度尺寸，高度为0.1到3微米之间，间隔为0.01-0.9微米。
通过外延工艺形成半导体发光序列在衬底的第一表面上，半导体发光序列同时覆盖异质凸起部110，其中外延工艺可以包含有机金属化学气相沉积(MOCVD)、分子束外延(MBE)或氢化物气相外延(HVPE)等类似的外延工艺。
半导体发光序列包括第一导电型半导体层101、第二导电型半导体层103以及发光层102，其中发光层102位于第一导电型半导体层101与第二导电型半导体层103之间。以蓝宝石透光衬底100为例，半导体发光序列堆叠层为依次层叠在透光衬底100上的AlN缓冲层、N型层(第一导电型半导体层)、发光层、P型层(第二导电型半导体层)。
AlN缓冲层可以有效减缓蓝宝石与GaN之间的晶格失配。
可选地，AlN缓冲层的厚度可以为0.5nm～5μm。当AlN缓冲层的厚度小于0.5nm时，无法起到晶格失配的减缓作用；当AlN缓冲层的厚度大于5μm时，造成材料浪费，提高实现成本。
所述的发光层102可以提供420～550nm之间的发光辐射，例如蓝光、绿光，具体地，N型层可以为AlxIn1-xGaN层(0≤x≤1)，发光层102可以为交替层叠的阱层InGaN层和磊层GaN层(或者AlGaN层)，P型层为AlyIn1-yGaN层(0≤y≤1)层。
2)如图5所示，蚀刻部分第二导电型半导体层103、发光层102，以暴露部分第一导电型半导体层101。
具体的，在第二导电型半导体层103的表面定义出一用来设置第二电极105(例如P电极)型电极的发光平台区，和在第一导电型半导体层101的顶面定义出可以设置一第一电极104(例如N型电极)的区域。可采用一蚀刻工艺，例如干蚀刻工艺蚀刻部分P型层和发光层102以暴露N型层，较佳为一感应耦合等离子体反应性离子蚀刻工艺。暴露N型层以形成安装N型电极的区域。
3)接着，进行一切割工艺或者ICP蚀刻工艺，从半导体发光序列的远离透光衬底100的一侧开始去除半导体发光序列，以形成一包围半导体发光序列四周的凹槽。
上述的切割工艺包含二氧化碳激光、钇铝石榴石激光(YAG激光器)、准分子激光(excimer激光器)或脉冲激光(pulsed激光器)等激光切割工艺，但不限于 此。如图6所示，凹槽可以是U型，凹槽包围透光衬底100的第一表面上的半导体发光序列，并且凹槽的底部使透光衬底100的第一表面的部分区域以及多个异质凸起部110暴露。定义透光衬底100的第一表面半导体发光序列覆盖的区域为第一区域100A，未被半导体发光序列覆盖的区域为第二区域100B。第一区域100A和第二区域110B的表面均覆盖有异质凸起部110。
衬底的第一表面第一区域100A具有第一表面积与第一投影面积，所述的投影面积为第一表面相对于水平面的投影面积，所述的水平面垂直于导体发光序列堆叠方向。第一表面积与第一投影面积仅为衬底本体第一表面的第一区域100A和第二区域100B的面积，不包括异质凸起部表面的面积。
在衬底本体的第一表面为平面的情况下，所述的第一表面积和第一投影面积的比例为1，第二表面积与第二投影面积比为1。
衬底的第一表面第二区域100B具有第二表面积与第二投影面积。
第一表面积与第一投影面积仅为衬底本体第一表面的第一区域100A和第二区域100B的面积，不包括异质凸起部的面积。
4)接着，进行一蚀刻工艺，对透光衬底100的第一表面的第二区域100B进行蚀刻处理，以使透光衬底100第一表面的第二区域100B具有第二表面积和第二投影面积，并且第二表面积和第二投影面积的比值高于第一区域100A的第一表面积与第二投影面积的比值。
由于该透明衬底100的第一表面为平面，当衬底的第一表面的第二区域从半导体发光序列周围被暴露，可通过对第二区域的表面形貌进行改进，以获得多个凸凹不平的结构，凸凹不平的结构使第二区域的表面表面不平整，相对于平面具有更多占比的倾斜面，使光线从衬底的第二表面侧到达其表面时，能够发生更多比例的折射，更有利于光到达在第二区域的表面直接出光。
具体的，多个凸凹不平的结构在衬底的第一表面的第二区域100B相对于第一区域100A具有更大的单位表面积，即第二区域100B具有第二表面积和第二投影面积的比值高于第一区域100A的第一表面积与第二投影面积的比值。其中投影面积为透光衬底100的第一表面沿着水平面投影的面积。
具体的，多个凸凹不平的结构包括多个第一凸起部111和第一凸起部111之间的 凹部，第一凸起部111可具有顶部和侧壁，顶部可以使点状或者平台。
多个凸凹不平的结构可具有至少一个相对于水平面为固定倾斜率的倾斜面。
由于异质凸起部堆叠在透明衬底的第二区域的表面上，为了在透光衬底100的第一表面的第二区域100B形成凸凹不平的结构，可以异质凸起部为掩膜，采用湿法刻蚀工艺对衬底的第一表面的第二区域进行蚀刻。以蓝宝石单晶衬底为例，由于湿法蚀刻，可在水平方向和纵向两个方向同时对蓝宝石衬底第一表面的第二区域进行蚀刻，从而形成具有倾斜侧壁的多个凸起部以及多个凸起部之间的凹部，利于增加表面积。
较佳的，第一凸起部的高度与底部宽度之比至少为1∶1，至多为1∶3。第一凸起部的高度与底部宽度比例越大，则侧壁的表面积越大，越有利于D方向的光从衬底取出，若高度与底部宽度之比较低，则侧壁倾斜角不够，则D方向的光从衬底的第二区域表面发生折射出光的比例较低，过高的高度与底部宽度之比会导致光局限在多个第一凸起部之间，引起光损失。优选的，其中所述的第一凸起部的高度为0.1微米以上，2微米以下。
作为一个实施例，透光衬底为蓝宝石单晶衬底，所述的湿法蚀刻的溶液可以是硫酸和磷酸的混合液，磷酸与硫酸的体积比为1∶(1.5～5)，蚀刻温度为240～280℃。
较佳的，为了形成该第一凸起部的高度与底部宽度之比为至少1∶1，至多为1∶3的范围的比例，磷酸与硫酸的体积比为1∶(2.5～4)，蚀刻温度为240～280℃。
衬底的第一表面的第二区域100B具有如下湿法蚀刻过程，如图6所示，由于异质凸起部110覆盖在第二区域100B表面，因此，如箭头所指示的方向，以异质凸起部110为掩膜，首先，蚀刻溶液对异质凸起部110周围衬底的表面进行纵向蚀刻。如图7所示，异质凸起部110周围衬底的表面逐渐形成的多个凹部，并且异质凸起部110下方衬底的表面会有倾斜的侧壁，由于湿法蚀刻的等向性，当倾斜的侧壁形成后，溶液会同时沿着侧壁发生横向蚀刻以及沿着凹部进行纵向蚀刻，直到获得第一凸起部110的目标深度和宽度。
如图8所示，最终在异质凸起部110的下方，衬底的表面形成第一凸起部111。第一凸起部111具有顶部，顶部可以为点状或者平台，第一凸起部111的侧壁具 有倾斜面。由于湿法蚀刻对晶体的不同晶面具有不同的蚀刻速率(例如蓝宝石衬底的R面，C面以及A面)，第一凸起部111的侧壁可以包括至少一个晶面被暴露形成倾斜面，并且倾斜面具有至少一个固定斜率。第一凸起部111之间形成相对的凹部。
在形成第一凸起部111的蚀刻过程中，所述的异质凸起部110也可以被部分蚀刻，最终的第一凸起部111的表面可残留有异质凸起部的图形或者异质凸起部110被全部去除，露出全部第一凸起部110的表面。
5)接着，在P型层上形成透明导电薄膜(图中未示意)，透明导电薄膜上形成第二电极105(P电极)，N型层上形成第一电极104(N电极)，并且形成绝缘层包覆半导体发光序列的表面以及透光衬底100的第一表面第二区域100B。如图9所示。
其中透明导电薄膜可以为氧化铟锡(ITO)、铝掺杂的氧化锌透明导电玻璃(AZO)、镓掺杂的氧化锌透明导电玻璃(GZO)、铟镓锌氧化物(IGZO)、NiAu、石墨烯中的一种。
第一电极104和第二电极105局部的设置在半导体发光序列远离衬底的一面侧，使半导体发光序列远离衬底的一面侧为出光面。
可选地，第二电极105(P电极)可以为Cr、Pt、Au、Ti、Ni、Al、Mo、Pd中的一种或多种金属堆叠形成，第一电极104(N电极)可以为Cr、Pt、Au、Ti、Ni、Al、Mo、Pd的一种或多种金属堆叠形成。
从透光衬底的第一表面的第二区域的位置切割分离衬底的获得单一的半导提发光元件。如图3所示。
可选的，最终半导体发光元件上，透光衬底100的第二表面可以设置分布式布拉格反射镜DBR或者金属反射层如Ag或者Al，以提升出光效率。
如图2所示的是现有技术中的一种半导体发光元件结构，其第一导电型半导体层100周围透光衬底100的第一表面被暴露，当发光层102的光束射向透光衬底100的第一表面，一部分发生反射，另一部分光穿过透光衬底100，到达透光衬底100的第二表面，由于透光衬底100的折射率高于空气或者透光衬底的第二表面有反射层，因此到达透光衬底的第二表面的光将进一步发生反射，反射回来的光 束从外延层侧壁或者透光衬底100的第一表面的第二区域100B或者透光衬底100的侧壁逃逸出。如果透光衬底100的第一表面的第二区域为平面，则光到达第一表面的第二区域100B时会容易发生反射，导致光继续在衬底内进行传播，且容易被吸收导致光损失，影响出光效率。
如图3所示，本发明通过改变透光衬底100的第一表面的第二区域100B的形貌，具有第一凸起部111和第一凸起部之间的凹部，使第一表面的第二区域100B相对于第一区域100A具有更大的表面积与投影面积比，更大的比表面积意味着具有更大的凸凹不平整度，更大占比的相对倾斜表面，更有利于D方向的光射向透光衬底100的第一表面的第二区域100B的部分直接溢出，射向空气，从而提升该部分的光的逸出效率。同时从部分B方向的光从半导体发光序列的侧壁射出，到达第二区域100B的表面发生反射，也可以提升正向的出光，提高出光效率。
实施例二
实施例一中步骤4)的湿法蚀刻步骤也可同时对半导体发光序列的侧壁，至少包括第一导电型半导体层101的侧壁进行蚀刻形成倾斜的侧壁。如图10所示，经过所述湿蚀刻工艺后，第一导电型半导体层101和氮化铝层的侧壁具有至少一个倾斜面，相对于半导体发光序列的堆叠方向具有至少一倾斜角，倾斜角的范围都小于90°，倾斜面也可以为多个，多个倾斜面之间可以不平行。由于第一导电型半导体层101具有至少一倾斜侧壁，倾斜侧壁可以作为一全反射面，使得光线反射到更上部的其它的倾斜侧壁出光，或者反射到半导体发光序列的顶面出光，可以增加光源出光的效率。
较佳的，所述的湿法蚀刻溶液可以是硫酸和磷酸的混合液，磷酸与硫酸的体积比为1∶(1.5～5)，蚀刻温度为240～280℃。其中磷酸溶液比例越大，对第一导电类型半导体层的蚀刻速率越快，硫酸比例越大，对蓝宝石的蚀刻速率越快，因此为了获得该第一凸起部的高度与底部宽度之比至少为1∶1，至多为1∶3，磷酸与硫酸的体积比为1∶(1.5～5)，蚀刻温度为240～280℃。
实施例三
如图11所示，透光衬底100的第一表面并不一定是平面。
在实施例一步骤1)中，通过薄膜沉积工艺结合蚀刻工艺在蓝宝石透光衬底100 的第一表面上形成多个异质凸起部110，且间隔一定距离的分散在透光衬底100的表面上。以蓝宝石衬底为例，通过干法蚀刻将氧化硅薄膜蚀刻形成多个分离的异质凸起部110，使透明衬底100的第一表面露出，干法蚀刻的气体也可能会引起蓝宝石衬底的第一表面被蚀刻，形成多个凸起部。凸起部定义为第二凸起部112，并且第二凸起部112被异质凸起部110覆盖。较佳的，为了保证异质凸起部的光反射效果，异质凸起部110的深度与第二凸起部112的深度的比例至少为9∶1。
通过实施例一的步骤4)的蚀刻工艺对第二区域进行蚀刻形成第一凸起部111。蚀刻过程中，以异质凸起部110作为掩膜，蚀刻溶液对异质凸起部周围的透光衬底100第二区域进行蚀刻。由于，蚀刻之前第二区域的表面具有多个第二凸起部112和第二凸起部112之间的凹部，异质凸起部110覆盖在第二凸起部112上，第二凸起部112相对于周围的凹部已经有侧壁，因此蚀刻过程会在横向和纵向的方向上同时进行，最终在第二区域上的异质凸起部112之间形成相对第一区域的第二凸起部112更深的第一凸起部111。
如图12所示的半导体发光元件，最终的发光元件上，半导体发光序列覆盖透光衬底100的第一表面的第一区域100A，第一区域的第二凸起部112和第二凸起部112之间的凹部使第一表面积与第一投影面积的比例大于1。
衬底的第一表面上第二区域100B的第一凸起部111相对于第一区域100A第二凸起部112更深的厚度，第一凸起部111具有更大面积占比的倾斜面使第二区域100B具有更大的第二表面积与第二投影面积比，更有利于光线从第二区域发生折射，直接出光。
实施例四
如图13所示，所述透光衬底100的第一表面的第二区域100B上覆盖的异质凸起部可以被去除，露出透光衬底100第一表面的第二区域100B的第一凸起部111。可以在实施例一的步骤4)过程中去除异质凸起部111或者在步骤之后再经过额外的蚀刻步骤(例如BOE蚀刻溶液)去除异质凸起部111。去除异质凸起部111后，可在第一导电型半导体层的侧壁上形成多个延伸至第一导电型半导体层内部一定深度的局部凹槽113。且最终的半导体发光元件上，在透光衬底100的第 一表面第二区域，所述多个第一凸起部111和多个第一凸起部111之间的凹部表面被连续的绝缘层覆盖。
实施例五
如图14所示，不同于实施例一的步骤1)所选择的透光衬底100，透光衬底100的第一表面并不必须的覆盖有异质凸起部110。且不同于实施例一步骤4)的是，蚀刻工艺需要额外制作掩膜图形，例如光刻胶图形，排列在衬底的第一表面的第二区域100B，并以光刻胶图形作为掩膜图形对衬底的第一表面进行湿法蚀刻形成具有多个凹部以及凹部周围的第一凸起部111，第一凸起部111侧壁具有至少一个固定倾斜率的斜面，使最终的透光衬底100的第一表面上第二区域100B具有相对于第一区域100A更大的第一表面积与第一投影面积比，更有利于光线从第二区域发生折射，直接出光。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (26)

  1. 一种半导体发光元件，其包括：透光衬底，由第一材料组成，透光衬底具有第一表面，第一表面包括第一区域和第二区域；
    半导体发光序列，堆叠在透光衬底的第一表面的第一区域，自第一表面开始依次包括第一导电型半导体层、发光层和第二导电型半导体层；透光衬底的第一表面的第一区域具有第一表面积与第一投影面积，透光衬底的第一表面第二区域具有第二表面积与第二投影面积，第二表面积与第二投影面积的比值大于第一表面积与第一投影面积的比值。
  2. 根据权利要求1所述的一种半导体发光元件，其特征在于：还包括多个异质凸起部，覆盖在所述的透光衬底的第一表面的第一区域上，异质凸起部由第二材料组成，第二材料不同于第一材料。
  3. 根据权利要求2所述的一种半导体发光元件，其特征在于：所述第二材料的折射率低于所述第一材料的折射率。
  4. 根据权利要求1或2所述的一种半导体发光元件，其特征在于：所述的透光衬底的第一表面的第二区域具有多个第一凸起部和多个第一凸起部之间的凹部。
  5. 根据权利要求4所述的一种半导体发光元件，其特征在于：所述的第一凸起部具有至少一个固定斜率的倾斜面。
  6. 根据权利要求4所述的一种半导体发光元件，其特征在于：所述的第一凸起部的顶部为点状或平台。
  7. 根据权利要求1或2所述的一种半导体发光元件，其特征在于：所述的透光衬底的第一表面的第一区域为平面。
  8. 根据权利要求1或2所述的一种半导体发光元件，其特征在于：所述的透光衬底的第一表面的第一区域为非平面，第一区域具有多个第二凸起部和多个第二凸起部之间的凹部。
  9. 根据权利要求8所述的一种半导体发光元件，其特征在于：所述的第二区域具有的多个第一凸起部相对于其周围的凹部的深度大于 所述第一区域的多个第二凸起部相对于其周围的凹部的深度。
  10. 根据权利要求8所述的一种半导体发光元件，其特征在于：所述的异质凸起部与第一凸起部的深度比至少为9∶1。
  11. 根据权利要求4所述的一种半导体发光元件，其特征在于：所述异质凸起部覆盖在所述第一凸起部表面。
  12. 根据权利要求4所述的一种半导体发光元件，其特征在于：所述多个第一凸起部和多个第一凸起部之间的凹部表面被连续的绝缘层覆盖。
  13. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述第一导电型半导体层侧壁具有至少一个相对半导体发光序列的堆叠方向倾斜的倾斜面。
  14. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的半导体发光序列具有第一导电型半导体层，第一导电型半导体层的侧壁上具有深入其内部一定深度的凹槽。
  15. 根据权利要求2所述的一种半导体发光元件，其特征在于：所述的异质凸起部的侧壁为非固定倾斜角度的弧形。
  16. 根据权利要求2所述的一种半导体发光元件，其特征在于：所述的异质凸起部为氧化硅或氮化硅或金属氧化物中的一种或多种。
  17. 根据权利要求1所述的一种半导体发光元件，其特征在于：所述的透明衬底为蓝宝石。
  18. 根据权利要求1所述的一种半导体发光元件，其特征在于：半导体发光序列远离衬底的一面侧为出光面。
  19. 根据权利要求4所述的一种半导体发光元件，其特征在于：第一凸起部的高度与底部宽度之比至少为1∶1，至多为1∶3。
  20. 一种半导体发光元件的制作方法，其包括如下步骤：
    1)在透光衬底的第一表面上形成半导体发光序列；
    2)从半导体发光序列的远离透光衬底的一侧开始蚀刻半导体发光序列，以形成露出透光衬底的凹槽，半导体发光序列覆盖的衬底 的第一表面定义为第一区域，半导体发光序列周围的透光衬底的第一表面定义为第二区域，第一区域具有第一表面积与第一投影面积，第二区域具有第二表面积与第二投影面积；
    3)蚀刻透光衬底的第一表面的第二区域，使第二表面积与第二投影面积的比值大于第一表面积与第一投影面积的比值。
  21. 根据权利要求20所述的的制作方法，其特征在于：步骤1)的透明衬底的第一表面上覆盖有异质凸起部。
  22. 根据权利要求21的所述的制作方法，其特征在于：所述的多个异质凸起部在步骤3)作为掩膜，蚀刻透光衬底的第一表面的第二区域。
  23. 根据权利要求20或22的所述的制作方法，其特征在于：所述的步骤3)的蚀刻为湿法蚀刻。
  24. 根据权利要求20的所述的制作方法，其特征在于：所述的步骤3)的蚀刻使衬底的第一表面的第二区域上形成多个第一凸起部以及多个第一凸起部之间的凹部，所述的第一凸起部的侧壁具有至少一个固定斜率的倾斜面。
  25. 根据权利要求24的所述的制作方法，其特征在于：步骤1)中透光衬底的第一表面为平面或者非平面。
  26. 根据权利要求25的所述的制作方法，其特征在于：最终的半导体发光元件上所述的凸起部的顶部残留有异质凸起部或者异质凸起部被去除。
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