WO2021179128A1 - 电压攻击检测电路和芯片 - Google Patents

电压攻击检测电路和芯片 Download PDF

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Publication number
WO2021179128A1
WO2021179128A1 PCT/CN2020/078445 CN2020078445W WO2021179128A1 WO 2021179128 A1 WO2021179128 A1 WO 2021179128A1 CN 2020078445 W CN2020078445 W CN 2020078445W WO 2021179128 A1 WO2021179128 A1 WO 2021179128A1
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WIPO (PCT)
Prior art keywords
voltage
signal
detection circuit
reference voltage
attack detection
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PCT/CN2020/078445
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English (en)
French (fr)
Inventor
杨江
薛建锋
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深圳市汇顶科技股份有限公司
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Priority to CN202080001165.4A priority Critical patent/CN111670366B/zh
Priority to EP20923693.4A priority patent/EP3926349B1/en
Priority to PCT/CN2020/078445 priority patent/WO2021179128A1/zh
Publication of WO2021179128A1 publication Critical patent/WO2021179128A1/zh
Priority to US17/483,040 priority patent/US11934566B2/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G01R19/16552—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies in I.C. power supplies

Definitions

  • the embodiments of the present application relate to the field of electronics, and more specifically, to voltage attack detection circuits and chips.
  • a security chip can be used to realize functions such as user identification and key data storage, and it is widely used in the financial field.
  • security chips play a vital role in information security.
  • more and more chip-level attack methods and examples have been disclosed, and accordingly, higher and higher requirements are put forward for chip-level security.
  • error injection attack There are many ways to attack the chip level, of which error injection attacks are the most effective.
  • the purpose of the error injection attack is to force the chip to perform an abnormal operation, thereby exposing the security information in the chip. At this point, the attacker can easily obtain the confidential data in the security chip by using fault analysis technology.
  • error injection attack such as voltage attack, temperature attack, laser attack, electromagnetic attack, etc.
  • a voltage attack detection circuit and chip are provided, which can detect whether the chip is attacked by voltage.
  • a voltage attack detection circuit including:
  • the first terminal of the first programmable resistor is connected to the power supply voltage, the second terminal of the first programmable resistor is connected to the ground voltage through the second programmable resistor, and the first terminal is used to output a first Voltage, the second terminal is used to output a second voltage;
  • the voltage detection circuit is configured to receive the first voltage and the first reference voltage and output a first signal, and the first signal is used to indicate whether the first voltage is greater than or equal to the first reference voltage;
  • the voltage detection circuit is also used to receive the second voltage and the second reference voltage and output a second signal, the second signal is used to indicate whether the second voltage is less than or equal to the second reference voltage, so The first reference voltage is greater than the second reference voltage.
  • the power supply voltage is divided by the first programmable resistor and the second programmable resistor to form the first voltage and the second voltage, and the first voltage and the second voltage are divided
  • the voltage is compared with the first reference voltage and the second reference voltage respectively to generate the first signal and the second signal; correspondingly, the first signal may be used to indicate the Whether the first voltage has a high voltage abnormality, the second signal can be used to indicate whether the second voltage has a low voltage abnormality, which is equivalent to that the first signal and the second signal can respectively indicate Whether the power supply voltage is abnormally high or low, that is, the first signal and the second signal can be used to indicate whether the power supply voltage is attacked, so as to remind the user to pay attention to safety when the power supply voltage is attacked Protect or take safety measures.
  • the first voltage and/or the second voltage can be configured, so that the voltage detection threshold deviation caused by the process can be compensated to improve Yield.
  • the first reference voltage is less than or equal to the voltage value of the first voltage when the power supply voltage is the maximum operating voltage of the bandgap reference
  • the second reference voltage is greater than Or equal to the voltage value of the second voltage when the power supply voltage is the minimum operating voltage of the bandgap reference.
  • the first reference voltage is less than or equal to the first voltage divided by the first programmable resistor and the second programmable resistor when the power supply voltage is the maximum operating voltage of the bandgap reference.
  • the voltage value of a voltage, the second reference voltage is greater than or equal to the voltage divided by the first programmable resistance and the second programmable resistance when the power supply voltage is the minimum operating voltage of the bandgap reference. The voltage value of the second voltage after pressing.
  • the first reference voltage is configured to be less than or equal to the voltage value of the first voltage when the power supply voltage is the maximum operating voltage of the bandgap reference
  • the second reference voltage is configured to be greater than or equal to The voltage value of the second voltage under the condition that the power supply voltage is the minimum operating voltage of the bandgap reference can reduce the probability of false warning as much as possible when the circuit is working normally, so as to improve user experience.
  • the voltage detection circuit includes:
  • the first hysteresis comparator and the second hysteresis comparator are identical to each other.
  • the positive input terminal of the first hysteresis comparator is connected to the first terminal to receive the first voltage
  • the negative input terminal of the first hysteresis comparator is connected to the first reference voltage
  • the The output terminal of the first hysteresis comparator is used to output the first signal
  • the positive input terminal of the second hysteresis comparator is connected to the second terminal to receive the second voltage
  • the negative input terminal of is connected to the second reference voltage
  • the output terminal of the second hysteresis comparator is used to output the second signal.
  • the anti-interference ability of the voltage detection circuit can be effectively increased, and accordingly, the reliability of the voltage attack detection circuit is improved.
  • the sensitivity of the voltage attack detection circuit can be improved.
  • the first signal is used to indicate whether the first voltage in the rising phase is greater than or equal to the first reference voltage, and the first signal is also used to indicate that the first voltage is in the falling phase. Whether the first voltage is less than or equal to a first threshold, and the difference between the first reference voltage and the first threshold is the hysteresis of the first hysteresis comparator.
  • the second signal is used to indicate whether the second voltage in the falling phase is less than or equal to the second reference voltage, and the second voltage is also used to indicate whether the second voltage is in the rising phase. Whether the second voltage is greater than or equal to a second threshold, and the difference between the second threshold and the second reference voltage is the hysteresis of the second hysteresis comparator.
  • the voltage attack detection circuit further includes:
  • the first AND gate and the second AND gate are The first AND gate and the second AND gate
  • the first AND gate is used to receive the first signal and the first indicator signal and output a third signal
  • the second AND gate is used to receive the second signal and the second indicator signal and output the fourth signal.
  • the first indication signal is used to indicate whether the first reference voltage is abnormal
  • the second indication signal is used to indicate whether the second reference voltage is abnormal.
  • the voltage attack detection circuit further includes:
  • the reference voltage generation circuit is used to generate the first reference voltage and the second reference voltage
  • the reference voltage detection circuit is connected to the reference voltage generation circuit
  • the reference voltage detection circuit is used to receive the The first reference voltage and the output of the first indication signal
  • the reference voltage detection circuit is further configured to receive the second reference voltage and output the second indication signal.
  • the voltage attack detection circuit further includes:
  • the reference voltage generating circuit is respectively connected to the first AND gate and the second AND gate through the glitch elimination circuit, and the glitch elimination circuit is used to indicate that the duration is less than or equal to a preset threshold
  • the indication signal that the reference signal is abnormal is reset to the indication signal that indicates that the reference signal is not abnormal.
  • the glitch elimination circuit can ensure the accuracy of the first indicator signal and the second indicator signal, and accordingly, can ensure that the third signal and the first indicator signal are accurate.
  • the accuracy of the four signals In other words, the glitch elimination circuit can correctly indicate whether the power supply voltage is attacked when the reference voltage has glitches, so as to remind the user to pay attention to safety protection or take safety measures when the power supply voltage is attacked.
  • the voltage attack detection circuit further includes:
  • the first OR gate and the second OR gate are The first OR gate and the second OR gate
  • the first OR gate is used to receive the first signal and the first test signal and output a fifth signal
  • the second OR gate is used to receive the second signal and the second test signal and output A sixth signal
  • the first test signal is used to indicate that the first voltage is greater than or equal to the first reference voltage
  • the second test signal is used to indicate that the second voltage is less than or equal to the second reference voltage Voltage.
  • the fifth signal can be forced to indicate that the first voltage is greater than or equal to the reference voltage
  • the sixth signal can be forced to indicate the second voltage It is less than or equal to the reference voltage, so that the designer can detect the voltage attack detection circuit.
  • the fifth signal and the sixth signal can be forced to enter the alarm state respectively.
  • the voltage attack detection circuit further includes:
  • the first programmable circuit is connected to the power supply voltage through the first resistor.
  • a chip including:
  • the power management unit is connected to the voltage attack detection circuit, and the voltage attack detection circuit is used to detect whether the power supply voltage of the power management unit is under voltage attack.
  • Fig. 1 is a schematic structural diagram of a voltage attack detection circuit according to an embodiment of the present application.
  • Fig. 2 is a working sequence diagram of the voltage attack detection circuit shown in Fig. 1.
  • FIG. 1 is a schematic structural diagram of a voltage attack detection circuit 100 according to an embodiment of the present application.
  • Fig. 2 is a working sequence diagram of the voltage attack detection circuit shown in Fig. 1.
  • the voltage attack detection circuit 100 may include a first programmable resistor 112, a second programmable resistor 113 and a voltage detection circuit 120.
  • the first terminal of the first programmable resistor 112 is connected to the supply voltage (VDD)
  • the second terminal of the first programmable resistor 112 is connected to the ground voltage through the second programmable resistor 113, so The first terminal is used to output a first voltage
  • the second terminal is used to output a second voltage.
  • the voltage detection circuit 120 is configured to receive the first voltage and a first reference voltage (Voltage Reference, VREF) and output a first signal, and the first signal is used to indicate whether the first voltage is greater than or equal to The first reference voltage; the voltage detection circuit 120 is also used to receive the second voltage and the second reference voltage and output a second signal, the second signal is used to indicate whether the second voltage is less than or equal to For the second reference voltage, the first reference voltage is greater than the second reference voltage.
  • a first reference voltage Voltage Reference, VREF
  • the first programmable resistor 112 and the second programmable resistor 113 can be used to form a detection threshold value generating circuit 110, and the detection threshold value generating circuit 110 is used to generate the first voltage and the second voltage.
  • the first voltage may also be referred to as a high voltage detection threshold (Voltage high threshold detection, VHD), and the second voltage may also be referred to as a low voltage detection threshold (Voltage low threshold detection, VLD).
  • VH high voltage
  • VLD low voltage detection threshold
  • the first signal may also be referred to as a high voltage (VH) alarm signal
  • the second signal may also be referred to as a low voltage (VH) alarm signal.
  • the power supply voltage is divided by the first programmable resistor 112 and the second programmable resistor 113 to form the first voltage and the second voltage, and the first voltage and the second voltage are divided
  • the second voltage is respectively compared with the first reference voltage and the second reference voltage to generate the first signal and the second signal; correspondingly, the first signal may be used to indicate the Whether the first voltage has a high voltage abnormality, the second signal may be used to indicate whether the second voltage has a low voltage abnormality. Equivalently, the first signal and the second signal can respectively indicate whether the power supply voltage has a high voltage abnormality and a low voltage abnormality.
  • the first voltage when the first voltage is greater than or equal to the first reference voltage, it means that the power supply voltage is abnormally high, and when the second voltage is less than the second reference voltage, it means that the power supply voltage is low. abnormal.
  • the abnormal high voltage or abnormal low voltage of the power supply voltage indicates that the power supply voltage has been attacked.
  • the first signal and the second signal can remind the user to pay attention to safety protection or take safety measures.
  • the first voltage and/or the second voltage can be dynamically configured, so as to compensate for the voltage detection threshold caused by the process ( That is, the deviation between the first reference voltage and the second reference voltage, so as to improve the yield.
  • the first reference voltage is less than or equal to the voltage value of the first voltage when the power supply voltage is the maximum operating voltage of the bandgap reference, and the first signal uses It indicates that the first voltage has a high voltage abnormality.
  • the second reference voltage is greater than or equal to the voltage value of the second voltage when the power supply voltage is the minimum operating voltage of the bandgap reference, and the second signal is used to indicate the second voltage A low voltage abnormality has occurred.
  • the first reference voltage is less than or equal to the first voltage, and the first signal is used to indicate that the power supply voltage is abnormally high.
  • the second reference voltage is greater than or equal to the second voltage, and the second signal is used to indicate that the power supply voltage has a low voltage abnormality .
  • the band gap reference may also be referred to as a band gap reference circuit, and the band gap reference may be used to convert the power supply voltage into the operating voltage of some or all of the devices in the voltage attack detection circuit 100.
  • the power supply voltage can be used as the operating voltage of the band gap reference, so that the band gap reference can output the operating voltage for some or all of the devices in the voltage attack detection circuit 100 based on the power supply voltage.
  • the operating voltage of the band gap reference may be a range value.
  • the operating voltage of the band gap reference may also be a preset value.
  • the size of the operating voltage of the band gap reference depends on the size of the power supply voltage. For example, the power supply voltage can be directly used as the operating voltage of the bandgap reference.
  • the first voltage can reach the maximum value, which is formed by comparing the maximum value of the first voltage with the first reference voltage
  • the first signal indicates whether the power supply voltage is in a high-voltage abnormal state, which can increase the accuracy of the first signal.
  • the first programmable After the resistor 112 and the second programmable resistor 113 divide the power supply voltage, the second voltage can reach the minimum value, which is formed by comparing the minimum value of the second voltage with the second reference voltage.
  • the second signal is used to indicate whether the power supply voltage is in a low voltage abnormal state, which can increase the accuracy of the second signal.
  • the power supply voltage is the maximum operating voltage of the bandgap reference
  • the first reference voltage is less than or equal to 113 minutes through the first programmable resistor 112 and the second programmable resistor 113
  • the voltage value of the first voltage after being compressed, and the first signal is used to indicate that the power supply voltage has a high voltage abnormality.
  • the second reference voltage is greater than or equal to the voltage divided by the first programmable resistor 112 and the second programmable resistor 113
  • the voltage value of the second voltage the second signal is used to indicate that the power supply voltage has a low voltage abnormality.
  • the first signal may be used to indicate whether the first voltage is greater than or equal to the maximum value of a preset voltage range
  • the second signal may be used to indicate whether the second voltage is less than or equal to the preset voltage range.
  • the minimum value of the voltage range is the preset voltage range.
  • the preset voltage range is the operating voltage range of the bandgap reference.
  • the preset voltage range may include multiple voltage values
  • the first signal is used to indicate whether the first voltage is greater than or equal to the maximum value of the multiple voltage values
  • the second signal is used to indicate Whether the second voltage is less than or equal to the minimum value of the plurality of voltage values.
  • the first reference voltage is configured to be less than or equal to the voltage value of the first voltage when the power supply voltage is the maximum operating voltage of the bandgap reference
  • the second reference The voltage is configured to be greater than or equal to the voltage value of the second voltage when the power supply voltage is the minimum operating voltage of the bandgap reference, and the first signal and the second voltage can be boosted when the circuit is operating normally.
  • the accuracy of the second signal is to reduce the probability of false warning as much as possible, so as to improve the user experience.
  • the voltage detection circuit includes a first hysteresis comparator 121 and a second hysteresis comparator 122.
  • the positive input terminal of the first hysteresis comparator 121 is connected to the first terminal to receive the first voltage, and the negative input terminal of the first hysteresis comparator 121 is connected to the first reference voltage,
  • the output terminal of the first hysteresis comparator 121 is used to output the first signal
  • the positive input terminal of the second hysteresis comparator 122 is connected to the second terminal to receive the second voltage
  • the first The negative input terminal of the two hysteresis comparator 122 is connected to the second reference voltage
  • the output terminal of the second hysteresis comparator 122 is used to output the second signal.
  • the first hysteresis comparator 121 when the reference voltage is normal, when the power supply voltage VDD rises such that the first voltage is greater than or equal to the first reference voltage (that is, exceeds the detection threshold of the first hysteresis comparator 121), the first hysteresis comparator 121 A hysteresis comparator 121 will output a high voltage alarm signal with a level of 1 to indicate that the power supply voltage VDD has a high voltage abnormality. If the power supply voltage VDD drops so that the first voltage drops below the difference between the first reference voltage and the hysteresis ⁇ VHD of the first hysteresis comparator, the high-voltage alarm signal can be cancelled.
  • the second hysteresis comparator 122 When the power supply voltage VDD drops so that the second voltage is less than or equal to the second reference voltage (that is, exceeds the detection threshold of the second hysteresis comparator 122), the second hysteresis comparator 122 will output a voltage. A low voltage alarm signal with a level of 1 indicates that the power supply voltage VDD has a low voltage abnormality. If the power supply voltage VDD rises so that the second voltage rises higher than the second reference voltage and the hysteresis of the second hysteresis comparator 122 is the sum of ⁇ VLD, the low voltage alarm signal can be cancelled.
  • the setting of ⁇ VHD is to prevent the fluctuation of the first voltage from causing the circuit to frequently send out and cancel the alarm signal, and to enhance the reliability and anti-interference ability of the circuit; at the same time, after a high voltage alarm occurs again, the first voltage is reduced to When the voltage value of ⁇ VHD is lower than the set first reference voltage, the high voltage alarm is released, which can improve the safety of the chip.
  • the setting of ⁇ VLD is to prevent the fluctuation of the second voltage from causing the circuit to frequently send out and cancel the alarm signal, and enhance the reliability and anti-interference ability of the circuit; at the same time, let the second voltage rise to a higher value than the set value. When the predetermined second reference voltage is still higher by ⁇ VLD, the low-voltage alarm is released, which can improve the safety of the chip.
  • the anti-interference ability of the voltage detection circuit can be effectively increased, and accordingly, the reliability of the voltage attack detection circuit 120 is improved.
  • the sensitivity of the voltage attack detection circuit 120 can be improved.
  • a single-limit comparator may also be used to replace the first hysteresis comparator 121 or the second hysteresis comparator 122.
  • the hysteresis comparator is equivalent to introducing a positive feedback circuit in the circuit, which can prevent the output voltage (that is, the first signal or the second signal) from jittering.
  • the hysteresis comparator has two threshold voltages, and the difference between the two threshold voltages can be the hysteresis of the hysteresis comparator.
  • the first signal is used to indicate whether the first voltage in the rising phase is greater than or equal to the first reference voltage, and the first signal is also used to indicate the falling phase Whether the first voltage in is less than or equal to a first threshold, the difference between the first reference voltage and the first threshold is the hysteresis amount ⁇ VHD of the first hysteresis comparator 121.
  • the threshold voltage that is, the maximum value of the reference voltage VREF1
  • the small threshold voltage that is, the The difference between the maximum value VREF1 of the reference voltage and the hysteresis ⁇ VHD, that is, the first threshold
  • the second signal is used to indicate whether the second voltage in the falling phase is less than or equal to the reference voltage, and the second voltage is also used to indicate whether the second voltage is in the rising phase. Whether the second voltage is greater than or equal to a second threshold, the difference between the second threshold and the reference voltage is the hysteresis of the second hysteresis comparator 122.
  • the second voltage when the second voltage becomes smaller and larger, the corresponding threshold voltage (that is, the second threshold value, that is, the minimum value VREF2 of the reference voltage, and the hysteresis amount ⁇ VLD, that is, the first Two thresholds), the second voltage changes from large to small corresponding to a small threshold voltage (that is, the minimum value VREF2 of the reference voltage).
  • the supply voltage VDD starts to rise from 0.
  • the low voltage alarm signal ie, the second signal
  • the low voltage alarm signal VL changes from 0 to 1 to indicate that the power supply voltage VDD has a low voltage abnormality.
  • the power supply voltage VDD continues to rise, and when the second voltage exceeds VREF2+ ⁇ VLD at time t2, the low voltage alarm signal VL changes from 1 to 0 to indicate that the power supply voltage VDD does not have a low voltage abnormality.
  • the high-voltage alarm signal VH changes from 0 to 1 to indicate that the supply voltage VDD has a high voltage abnormality.
  • the power supply voltage VDD starts to drop, and when the first voltage is lower than VREF1- ⁇ VHD at time t4, the high voltage alarm signal (that is, the first signal) VH changes from 1 to 0 to indicate that the power supply voltage VDD does not have a high voltage abnormality .
  • the supply voltage VDD continues to decrease, and when the second voltage is lower than VREF2 at time t5, the low-voltage alarm signal VL changes from 0 to 1 to indicate that the supply voltage VDD has a low voltage abnormality.
  • the second voltage does not fall below VMIN, it starts to rise, that is, the supply voltage VDD continues to rise, and when the second voltage exceeds VREF2+ ⁇ VLD at time t6, the low-voltage alarm signal VL changes from 1 to 0 to indicate The power supply voltage VDD does not have a low voltage abnormality.
  • the supply voltage VDD continues to rise, and when the first voltage exceeds VREF1 at time t7, the high-voltage alarm signal VH changes from 0 to 1 to indicate that the supply voltage VDD has a high voltage abnormality.
  • the voltage attack detection circuit further includes a first AND gate 140 and a second AND gate 150.
  • the first AND gate 140 is used to receive the first signal and the first indication signal and output a third signal
  • the second AND gate 150 is used to receive the second signal and the second indication signal and output A fourth signal
  • the first indication signal is used to indicate whether the first reference voltage is abnormal
  • the second indication signal is used to indicate whether the second reference voltage is abnormal.
  • AND gate is also called “and circuit”, logical “product”, and logical “and” circuit. It is the basic logic gate circuit that performs the "and” operation.
  • the AND gate may have multiple input terminals and one output terminal. When the signals received by all the input terminals are high level (logic “1"), the output signal is high level (logic “1"), otherwise the output signal is low level (logic “0”). In other words, when the first signal and the first indication signal are both at a high level (logic "1"), the third signal is at a high level (logic "1"). Similarly, the first signal is at a high level (logic "1"). When both the second signal and the second indication signal are at a high level (logic "1”), the fourth signal is only at a high level (logic "1").
  • first AND gate 140 and the second AND gate 150 it is possible to prevent the indication of the first signal and the second signal from being incorrect due to the abnormality of the first reference voltage or the second reference voltage.
  • the exact situation In other words, through the first AND gate 140 and the second AND gate 150, false warnings caused by the abnormality of the reference voltage can be avoided, so as to improve the accuracy of the voltage attack warning.
  • the voltage attack detection circuit further includes a reference voltage generation circuit 160 and a reference voltage detection circuit 170.
  • the reference voltage generation circuit 160 is used to generate the first reference voltage and the second reference voltage
  • the reference voltage detection circuit 170 is connected to the reference voltage generation circuit 160
  • the reference voltage detection circuit 170 uses Receiving the first reference voltage and outputting the first indication signal.
  • the reference voltage detection circuit 170 is further configured to receive the second reference voltage and output the second indication signal.
  • the first signal is used to indicate that the first voltage is greater than or equal to the first reference voltage
  • the first signal is at a high level (logic "1")
  • the first indication signal is It is used to indicate that the first reference voltage is abnormal
  • the first indication signal is low level (logic "0").
  • the second signal is used to indicate that the second voltage is less than or equal to the second reference voltage
  • the second signal is at a high level (logic "1")
  • the second indication signal is used to indicate that the second reference voltage is abnormal
  • the second indication signal is at a low level (logic "0").
  • the first indication signal when used to indicate that the first reference voltage is abnormal, even if the first voltage is greater than or equal to the first reference voltage, it is reset to indicate the first voltage It is less than the first reference voltage.
  • the first indication information may also be referred to as a reset signal (RST).
  • RST reset signal
  • the reference voltage detection circuit 170 is not used to output RST when the first reference voltage is not abnormal, and is used to output RST when the first reference voltage is abnormal. Similar to the first indication information, the reference voltage detection circuit 170 is not used to output RST when the second reference voltage is not abnormal, and is used to output RST when the second reference voltage is abnormal.
  • the reference voltage generating circuit 160 may be a bandgap reference (Bandgap voltage reference, Bandgap) generating circuit, that is, the first reference voltage and the second reference voltage may be a bandgap reference.
  • the bandgap reference can be the sum of a voltage proportional to temperature and a voltage inversely proportional to temperature, and the temperature coefficients of the two cancel each other to realize a voltage reference independent of temperature.
  • the bandgap reference may be a DC voltage that is independent of power supply and process and has certain temperature characteristics.
  • the band gap reference may be approximately 1.25V.
  • the reference voltage of the band gap reference may be similar to the band gap voltage of silicon.
  • the reference voltage generating circuit 160 is connected to an external power supply (VDD), and when the reference voltage generating circuit 160 is able to provide accurate information to the at least one voltage sensor based on the external power supply (VDD) When the first reference voltage and the second reference voltage are set, the first indication signal and the second indication information are both high level (logic "1").
  • the reference voltage generating circuit 160 works abnormally, that is, when the external power supply VDD is too high or too low, the first reference voltage or the second reference voltage provided by the reference voltage generating circuit 160 is no longer accurate.
  • the first indication signal or the second indication information is low level (logic "0"), that is, the first signal or the second signal is output as low level (logic "0"). ”), that is, no alarm signal will be issued. It is equivalent to invalidate the alarm signal output by the hysteresis comparator to avoid false alarms.
  • the first indicator signal is used to indicate that the first reference voltage is abnormal, the first indicator signal is at a high level (logic "1").
  • the second indicator signal is used to indicate that the second reference voltage is abnormal, the second indicator signal is at a high level (logic "1").
  • the first indication signal may be used to warn whether the power domain where the first reference voltage is located is subject to high voltage attacks, and the second indication signal may be used to notify the power source where the second reference voltage is located. Early warning of whether the domain is attacked by voltage.
  • the reference voltage detection circuit 170 can not only indicate whether the at least one internal power source is under attack, but also whether the power domain where the first reference voltage or the second reference voltage is located is under attack, so that the at least one internal power source is under attack. Reminding the user to pay attention to safety protection or take safety measures when under attack or when the other power domain is under attack.
  • the voltage attack detection circuit further includes a glitch elimination circuit 180.
  • the reference voltage generating circuit 160 is respectively connected to the first AND gate 140 and the second AND gate 150 through the burr elimination circuit 180, and the burr elimination circuit 180 is used for reducing the duration of time less than or equal to a preset value.
  • the indication signal for indicating the abnormality of the reference signal of the threshold value is reset to the indicating signal for indicating that the reference signal is not abnormal.
  • the glitch elimination circuit 180 may be used to reset the first indicator signal used to indicate that the first reference signal is abnormal and whose duration is less than or equal to a preset threshold value to be used to indicate that the first reference signal does not exist.
  • the first indicator of abnormality may be used to reset the second indicator signal that is less than or equal to a preset threshold and is used to indicate that the second reference signal is abnormal, to be used to indicate that the second reference signal is not abnormal. There is an abnormal second indication signal.
  • the glitch may be a regular or irregular pulse signal or spike signal in the input waveform of the circuit.
  • the voltage value when a glitch in a positive direction appears on the reference voltage is equal to the voltage value when there is no glitch on the reference voltage plus the voltage value of the glitch.
  • the voltage value when a negative and positive burr appears on the reference voltage is equal to the voltage value when there is no burr on the reference voltage minus the voltage value of the burr.
  • an unstable reference voltage it can also be considered as a voltage after a glitch is superimposed on the stable reference voltage.
  • the glitch elimination circuit 180 in the case of a glitch in the reference voltage, the accuracy of the first indicator signal and the second indicator signal can be guaranteed, and accordingly, the accuracy of the third signal and the second indicator signal can be guaranteed.
  • the accuracy of the fourth signal is described.
  • the glitch elimination circuit 180 can correctly indicate whether the power supply voltage is attacked when the reference voltage has a glitch, so as to remind the user to pay attention to safety protection or take safety measures when the power supply voltage is attacked.
  • the voltage attack detection circuit further includes a first OR gate 131 and a second OR gate 132.
  • the first OR gate 131 is used to receive the first signal and the first test signal and output a fifth signal
  • the second OR gate 132 is used to receive the second signal and the second test signal And output a sixth signal.
  • the first test signal is used to indicate that the first voltage is greater than or equal to the first reference voltage
  • the second test signal is used to indicate that the second voltage is less than or equal to the first reference voltage. 2.
  • Reference voltage As shown in FIG. 1, the first test signal may also be referred to as a high voltage detection signal (TEST_HL), and the second test signal may also be referred to as a low voltage detection signal (TEST low voltage, TEST_VL).
  • TEST_HL high voltage detection signal
  • TEST low voltage, TEST_VL low voltage detection signal
  • the first OR gate 131 and the second OR gate 132 can be used to form a set self-detection circuit 130 for testing the first signal and the second signal output by the voltage detection circuit 120.
  • TEST_VH is set to 1
  • TEST_VL is set to 1
  • the sixth signal is also forcibly set to 1, in order to facilitate the system's functionality and integrity debugging .
  • OR gate is also called OR circuit, logical OR circuit. Specifically, if one of several conditions is met, an event will occur. This relationship is called an "or” logical relationship, and correspondingly, a circuit with an "or” logical relationship is called an OR gate.
  • the OR gate can have multiple input terminals and one output terminal. As long as one of the input terminals receives a high level signal (logic "1"), the output signal at the output terminal is high level (logic "1"). “1"); Only when the signals received by all the input terminals are low level (logic "0"), the output signal at the output terminal is low level (logic "0").
  • the fifth signal is at a high level (logic "1")
  • the sixth signal is at a high level (logic "1").
  • the fifth signal can be forced to indicate that the first voltage is greater than or equal to the reference voltage, or the sixth signal can be forced to indicate the second voltage It is less than or equal to the reference voltage, so that the designer can detect the voltage attack detection circuit.
  • the fifth signal and the sixth signal can be forced to enter the alarm state respectively.
  • the voltage attack detection circuit further includes a first resistor 111.
  • the first programmable circuit 112 is connected to the power supply voltage through the first resistor 111.
  • the detection threshold value generating circuit 110 may include the first resistor 111.
  • the present application also provides a chip that includes a power management unit and the voltage attack detection circuit described above; wherein, the power management unit is connected to the voltage attack detection circuit, and the voltage attack detection circuit is used for It is detected whether the power supply voltage of the power management unit is attacked by voltage.
  • the voltage attack detection circuit can be applied to any chip with a power management unit.
  • a security chip for example, the security chip may be a fingerprint sensor chip or a processor chip or the like.
  • the security chip is suitable for any kind of electronic equipment.
  • portable or mobile computing devices such as smartphones, notebook computers, tablet computers, and gaming devices, as well as other electronic devices such as electronic databases, automobiles, and bank automated teller machines (ATM).
  • ATM bank automated teller machines
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

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Abstract

一种电压攻击检测电路和芯片，电压攻击检测电路（100）包括：第一可编程电阻（112）和第二可编程电阻（113）；第一可编程电阻（112）的第一端连接至电源电压，第一可编程电阻（112）的第二端通过第二可编程电阻（113）连接至地电压，第一端用于输出第一电压，第二端用于输出第二电压；电压检测电路（120）；用于接收第一电压和第一参考电压并输出第一信号，第一信号用于指示第一电压是否大于或等于第一参考电压；还用于接收第二电压和第二参考电压并输出第二信号，第二信号用于指示第二电压是否小于或等于第二参考电压。电压攻击检测电路（100）不仅可以实现电压攻击的预警，还可以弥补由工艺造成的电压检测阈值偏差，以提升良率。

Description

电压攻击检测电路和芯片 技术领域
本申请实施例涉及电子领域，并且更具体地，涉及电压攻击检测电路和芯片。
背景技术
随着移动支付与交易得到广泛的普及，电子设备被越来越多的用于存储、处理、传输包含关键信息的数据。例如，安全芯片可以用于实现用户身份识别与关键数据存储等功能，其被广泛应用于金融领域。安全芯片作为安全硬件的基础，对信息安全起着至关重要的作用。近年来，越来越多的芯片级攻击方法与实例被公开，相应的，对芯片级的安全提出来越来越高的要求。
针对芯片级的攻击方式有多种，其中错误注入攻击最为有效。错误注入攻击的目的是迫使芯片执行一个非正常的操作，从而使得芯片中的安全信息暴露出来。此时，攻击者可以利用故障分析技术轻易获取安全芯片中的机密数据。错误注入攻击的方式有很多种，例如电压攻击、温度攻击、激光攻击、电磁攻击等。
针对电压攻击，通过改变芯片电源域的供电电压，使得芯片内部的电路工作发生异常，从而引起触发器进入错误状态，致使处理器跳过或执行错误的操作，以便芯片内的安全信息暴露出来。
因此，针对电压攻击，提供一套完整且可靠的防护方案十分迫切。
发明内容
提供一种电压攻击检测电路和芯片，能够检测到芯片是否受到电压攻击。
第一方面，提供了一种电压攻击检测电路，包括：
第一可编程电阻和第二可编程电阻；
所述第一可编程电阻的第一端连接至电源电压，所述第一可编程电阻的第二端通过所述第二可编程电阻连接至地电压，所述第一端用于输出第一电压，所述第二端用于输出第二电压；
电压检测电路；
其中，所述电压检测电路用于接收所述第一电压和第一参考电压并输出第一信号，所述第一信号用于指示所述第一电压是否大于或等于所述第一参考电压；所述电压检测电路还用于接收所述第二电压和第二参考电压并输出第二信号，所述第二信号用于指示所述第二电压是否小于或等于所述第二参考电压，所述第一参考电压大于所述第二参考电压。
通过所述第一可编程电阻和所述第二可编程电阻对所述电源电压进行分压，以形成所述第一电压和所述第二电压，将所述第一电压和所述第二电压分别与所述第一参考电压和所述第二参考电压进行比较，以生成所述第一信号和所述第二信号；相应的，所述第一信号可以用于指示出所述所述第一电压是否出现高电压异常，所述第二信号可以用于指示出所述第二电压是否出现低电压异常，相当于，通过所述第一信号和所述第二信号可以分别指示出所述电源电压是否出现高电压异常和低电压异常，即所述第一信号和所述第二信号可以用于指示所述电源电压是否受到攻击，以便在所述电源电压受到攻击时提醒用户注意安全防护或采取安全措施。
此外，通过所述第一可编程电阻和所述第二可编程电阻，可以实现配置所述第一电压和/或所述第二电压，从而可以弥补由工艺造成的电压检测阈值偏差，以提升良率。
在一些可能的实现方式中，所述第一参考电压小于或等于在所述电源电压为带隙基准的最大工作电压的情况下的所述第一电压的电压值，所述第二参考电压大于或等于在所述电源电压为所述带隙基准的最小工作电压的情况下的所述第二电压的电压值。
换言之，所述第一参考电压小于或等于在所述电源电压为带隙基准的最大工作电压的情况下经由所述第一可编程电阻和所述第二可编程电阻分压后的所述第一电压的电压值，所述第二参考电压大于或等于在所述电源电压为所述带隙基准的最小工作电压的情况下经由所述第一可编程电阻和所述第二可编程电阻分压后的所述第二电压的电压值。
将所述第一参考电压构造为小于或等于在所述电源电压为带隙基准的最大工作电压的情况下所述第一电压的电压值，并将所述第二参考电压构造为大于或等于所述在所述电源电压为所述带隙基准的最小工作电压的情况下的所述第二电压的电压值，在电路正常工作的情况下，能够尽可能的降低错误预警的概率，以提高用户体验。
在一些可能的实现方式中，所述电压检测电路包括：
第一迟滞比较器和第二迟滞比较器；
其中，所述第一迟滞比较器的正输入端连接至所述第一端以接收所述第一电压，所述第一迟滞比较器的负输入端连接至所述第一参考电压，所述第一迟滞比较器的输出端用于输出所述第一信号，所述第二迟滞比较器的正输入端连接至所述第二端以接收所述第二电压，所述第二迟滞比较器的负输入端连接至所述第二参考电压，所述第二迟滞比较器的输出端用于输出所述第二信号。
通过所述第一迟滞比较器和所述第二迟滞比较器，能够有效增加所述电压检测电路的抗干扰能力，相应的，提高了所述电压攻击检测电路的可靠性。
此外，在高速运行所述第一迟滞比较器和所述第二迟滞比较器时，可以提升所述电压攻击检测电路的灵敏度。
在一些可能的实现方式中，所述第一信号用于指示处于上升阶段中的所述第一电压是否大于或等于所述第一参考电压，所述第一信号还用于指示处于下降阶段中的所述第一电压是否小于或等于第一阈值，所述第一参考电压与所述第一阈值的差值为所述第一迟滞比较器的迟滞量。
在一些可能的实现方式中，所述第二信号用于指示处于下降阶段中的所述第二电压是否小于或等于所述第二参考电压，所述第二电压还用于指示处于上升阶段中的所述第二电压是否大于或等于第二阈值，所述第二阈值与所述第二参考电压的差值为所述第二迟滞比较器的迟滞量。
在一些可能的实现方式中，所述电压攻击检测电路还包括：
第一与门和第二与门；
其中，所述第一与门用于接收所述第一信号和第一指示信号并输出第三信号，所述第二与门用于接收所述第二信号和第二指示信号并输出第四信号，所述第一指示信号用于指示所述第一参考电压是否存在异常，所述第二指示信号用于指示所述第二参考电压是否存在异常。
通过所述第一与门和所述第二与门，可以避免由于所述第一参考电压或第二参考电压存在异常，导致的所述第一信号和所述第二信号的指示不准确的情况。换言之，通过所述第一与门和所述第二与门，可以避免由于所述参考电压存在异常导致的错误预警，以提升电压攻击预警的准确率。
在一些可能的实现方式中，所述电压攻击检测电路还包括：
参考电压生成电路和参考电压检测电路；
其中，所述参考电压生成电路用于生成所述第一参考电压和所述第二参考电压，所述参考电压检测电路连接至所参考电压生成电路，所述参考电压检测电路用于接收所述第一参考电压并输出所述第一指示信号，所述参考电压检测电路还用于接收所述第二参考电压并输出所述第二指示信号。
在一些可能的实现方式中，所述电压攻击检测电路还包括：
毛刺消除电路；
其中，所述参考电压生成电路通过所述毛刺消除电路分别连接至所述第一与门和所述第二与门，所述毛刺消除电路用于将时长小于或等于预设阈值的用于指示参考信号存在异常的指示信号重置为用于指示参考信号不存在异常的指示信号。
在所述参考电压出现毛刺的情况下，通过所述毛刺消除电路能够保证所述第一指示信号和所述第二指示信号的准确率，相应的，能够保证所述第三信号和所述第四信号的准确率。换言之，通过所述毛刺消除电路，能够在所述参考电压出现毛刺的情况下正确指示所述电源电压是否受到攻击，以便在所述电源电压受到攻击时提醒用户注意安全防护或采取安全措施。
所述电压攻击检测电路还包括：
第一或门和第二或门；
其中，所述第一或门用于接收所述第一信号和第一测试信号并输出第五信号，所述第二或门用于接收所述第二信号和所述第二测试信号并输出第六信号，所述第一测试信号用于指示所述第一电压大于或等于所述第一参考电压，所述第二测试信号用于指示所述第二电压小于或等于所述第二参考电压。
通过所述第一测试信号和所述第二测试信号，可以强制让第五信号指示所述第一电压大于或等于所述参考电压，或可以强制让所述第六信号指示所述第二电压小于或等于所述参考电压，以便于设计人员对所述电压攻击检测电路进行检测。换言之，通过所述第一或门和所述第二或门，可以分别强制让所述第五信号和所述第六信号进入报警状态。
在一些可能的实现方式中，所述电压攻击检测电路还包括：
第一电阻；
其中，所述第一可编程电路通过所述第一电阻连接至所述电源电压。
第二方面，提供了一种芯片，包括：
电源管理单元；以及
第一方面或第一方面任一可能实现的方式中所述的电压攻击检测电路；
其中，所述电源管理单元连接至所述电压攻击检测电路，所述电压攻击检测电路用于检测所述电源管理单元的电源电压是否受到电压攻击。
附图说明
图1是本申请实施例的电压攻击检测电路的示意性结构图。
图2是图1所示的电压攻击检测电路的工作时序图。
具体实施方式
图1是本申请实施例的电压攻击检测电路100的示意性结构图。图2是图1所示的电压攻击检测电路的工作时序图。下面将结合附图，对本申请实施例中的技术方案进行描述。
如图1所示，所述电压攻击检测电路100可以包括第一可编程电阻112、第二可编程电阻113以及电压检测电路120。所述第一可编程电阻112的第一端连接至电源电压(Supply Voltage，VDD)，所述第一可编程电阻112的第二端通过所述第二可编程电阻113连接至地电压，所述第一端用于输出第一电压，所述第二端用于输出第二电压。
其中，所述电压检测电路120用于接收所述第一电压和第一参考电压(Voltage Reference，VREF)并输出第一信号，所述第一信号用于指示所述第一电压是否大于或等于所述第一参考电压；所述电压检测电路120还用于接收所述第二电压和第二参考电压并输出第二信号，所述第二信号用于指示所述第二电压是否小于或等于所述第二参考电压，所述第一参考电压大于所述第二参考电压。
换言之，所述第一可编程电阻112和所述第二可编程电阻113可用于形成检测阈值产生电路110，所述检测阈值产生电路110用于生成所述第一电压和所述第二电压。
如图1所示，所述第一电压也可称为高电压检测阈值(Voltage high threshold detection，VHD)，所述第二电压也可称为低电压检测阈值(Voltage low threshold detection，VLD)。类似地，所述第一信号也可以称为高电压 (Voltage high，VH)报警信号，所述第二信号也可称为低电压(Voltage low，VL)报警信号。
通过所述第一可编程电阻112和所述第二可编程电阻113对所述电源电压进行分压，以形成所述第一电压和所述第二电压，将所述第一电压和所述第二电压分别与所述第一参考电压和所述第二参考电压进行比较，以生成所述第一信号和所述第二信号；相应的，所述第一信号可以用于指示出所述第一电压是否出现高电压异常，所述第二信号可以用于指示出所述第二电压是否出现低电压异常。相当于，通过所述第一信号和所述第二信号可以分别指示出所述电源电压是否出现高电压异常和低电压异常。
例如，所述第一电压大于或等于所述第一参考电压时，说明所述电源电压出现高电压异常，所述第二电压小于所述第二参考电压时，说明所述电源电压出现低电压异常。相应的，所述电源电压出现高电压异常或低电压异常说明所述电源电压已经受到攻击。在所述电源电压受到攻击时通过所述第一信号和所述第二信号可以提醒用户注意安全防护或采取安全措施。
此外，通过所述第一可编程电阻112和所述第二可编程电阻113，可以实现动态配置所述第一电压和/或所述第二电压，从而可以弥补由工艺造成的电压检测阈值(即所述第一参考电压和所述第二参考电压)偏差，以提升良率。
在本申请的一些实施例中，所述第一参考电压小于或等于在所述电源电压为带隙基准的最大工作电压的情况下的所述第一电压的电压值，所述第一信号用于指示所述第一电压出现高电压异常。所述第二参考电压大于或等于在所述电源电压为所述带隙基准的最小工作电压的情况下的所述第二电压的电压值，所述第二信号用于指示所述第二电压出现低电压异常。
换言之，在所述电源电压等于带隙基准的最大工作电压的情况下，所述第一参考电压小于或等于所述第一电压，所述第一信号用于指示所述电源电压出现高电压异常。在所述电源电压等于所述带隙基准的最小工作电压的情况下，所述第二参考电压大于或等于所述第二电压，所述第二信号用于指示所述电源电压出现低电压异常。
其中，所述带隙基准也可以称为带隙基准电路，所述带隙基准可以用于将所述电源电压转换成所述电压攻击检测电路100中的部分或全部器件的工作电压。换言之，所述电源电压可以作为所述带隙基准的工作电压，以便所 述带隙基准可以基于所述电源电压输出用于所述电压攻击检测电路100中的部分或全部器件的工作电压。所述带隙基准的工作电压可以是一个范围值。所述带隙基准的工作电压也可以是预设值。所述带隙基准的工作电压的大小取决于所述电源电压的大小。例如，所述电源电压可以直接作为所述带隙基准的工作电压。
当判断所述电源电压是否出现高电压异常时，如果所述带隙基准的工作电压处于最大工作电压，由于所述带隙基准的工作电压由所述电源电压提供，通过所述第一可编程电阻112和所述第二可编程电阻113对所述电源电压进行分压后，所述第一电压能够达到最大值，通过比较所述第一电压的最大值与所述第一参考电压形成的所述第一信号，以指示所述电源电压是否处于高电压异常状态，能够增加所述第一信号的准确率。
类似的，当判断所述电源电压是否出现低电压异常时，如果所述带隙基准处于最小工作电压，由于所述带隙基准的工作电压由所述电源电压提供，通过所述第一可编程电阻112和所述第二可编程电阻113对所述电源电压进行分压后，所述第二电压能够达到最小值，通过比较所述第二电压的最小值与所述第二参考电压形成的所述第二信号，以指示所述电源电压是否处于低电压异常状态，能够增加所述第二信号的准确率。
具体而言，在所述电源电压为带隙基准的最大工作电压的情况下，若所述第一参考电压小于或等于经由所述第一可编程电阻112和所述第二可编程电阻113分压后的所述第一电压的电压值，所述第一信号用于指示所述电源电压出现高电压异常。在所述电源电压为所述带隙基准的最小工作电压的情况下，若所述第二参考电压大于或等于经由所述第一可编程电阻112和所述第二可编程电阻113分压后的所述第二电压的电压值，所述第二信号用于指示所述电源电压出现低电压异常。
换言之，所述第一信号可以用于指示所述第一电压是否大于或等于预设电压范围的最大值，所述第二信号可以用于指示所述第二电压是否小于或等于所述预设电压范围的最小值。例如，所述预设电压范围为带隙基准的工作电压范围。例如，所述预设电压范围可以包括多个电压值，所述第一信号用于指示所述第一电压是否大于或等于所述多个电压值的最大值，所述第二信号用于指示所述第二电压是否小于或等于所述所述多个电压值的最小值。
综上所述，将所述第一参考电压构造为小于或等于在所述电源电压为带 隙基准的最大工作电压的情况下的所述第一电压的电压值，并将所述第二参考电压构造为大于或等于在所述电源电压为所述带隙基准的最小工作电压的情况下的所述第二电压的电压值，在电路正常工作的情况下，能够提升所述第一信号和所述第二信号的准确率，并尽可能的降低错误预警的概率，以提高用户体验。
如图1所示，在本申请的一些实施例中，所述电压检测电路包括第一迟滞比较器121和第二迟滞比较器122。
其中，所述第一迟滞比较器121的正输入端连接至所述第一端以接收所述第一电压，所述第一迟滞比较器121的负输入端连接至所述第一参考电压，所述第一迟滞比较器121的输出端用于输出所述第一信号，所述第二迟滞比较器122的正输入端连接至所述第二端以接收所述第二电压，所述第二迟滞比较器122的负输入端连接至所述第二参考电压，所述第二迟滞比较器122的输出端用于输出所述第二信号。
换言之，在参考电压正常的情况下，当电源电压VDD上升使得所述第一电压大于或等于所述第一参考电压(即超过所述第一迟滞比较器121的检测阈值)时，所述第一迟滞比较器121将会输出电平为1的高压报警信号，以指示电源电压VDD出现高电压异常。若电源电压VDD下降使得所述第一电压下降至低于所述第一参考电压与所述第一迟滞比较器的迟滞量ΔVHD的差值，则可以解除高压报警信号。当电源电压VDD下降使得所述第二电压小于或等于所述第二参考电压时(即超过所述第二迟滞比较器122的检测阈值)时，所述第二迟滞比较器122将会输出电平为1的低压报警信号，以指示电源电压VDD出现低电压异常。若电源电压VDD上升使得所述第二电压上升至高于所述第二参考电压与所述第二迟滞比较器122的迟滞量为ΔVLD的和，则可以解除低压报警信号。
ΔVHD的设置是为了防止所述第一电压的波动导致电路频繁发出与解除报警信号，增强电路的可靠性与抗干扰能力；与此同时，再发生高压报警后，让所述第一电压降低到比设定的所述第一参考电压还要低一个ΔVHD的电压值时再解除高压报警，可以提升芯片的安全性。与ΔVHD类似，ΔVLD的设置是为了防止所述第二电压的波动导致电路频繁发出与解除报警信号，增强电路的可靠性与抗干扰能力；与此同时，让所述第二电压上升到比设定的所述第二参考电压还要高一个ΔVLD时再解除低压报警，可以提升芯片的 安全性。
换言之，通过所述第一迟滞比较器121和所述第二迟滞比较器122，能够有效增加所述电压检测电路的抗干扰能力，相应的，提高了所述电压攻击检测电路120的可靠性。
此外，在高速运行所述第一迟滞比较器121和所述第二迟滞比较器122时，可以提升所述电压攻击检测电路120的灵敏度。
当然，在其他可替代实施例中，也可以采用单限比较器替代所述第一迟滞比较器121或所述第二迟滞比较器122。
需要说明的是，迟滞比较器相当于在电路中引入正反馈电路，可以避免输出电压(即所述第一信号或所述第二信号)发生抖动的情况。其中，迟滞比较器有两个门限电压，这两个门限电压之间的差值可以为迟滞比较器的迟滞量。
在本申请的一些实施例中，所述第一信号用于指示处于上升阶段中的所述第一电压是否大于或等于所述第一参考电压，所述第一信号还用于指示处于下降阶段中的所述第一电压是否小于或等于第一阈值，所述第一参考电压与所述第一阈值的差值为所述第一迟滞比较器121的迟滞量△VHD。
换言之，如图2所示，所述第一电压小变大时对应大门限电压(即所述参考电压的最大值VREF1)，所述第一电压由大变小时对应小门限电压(即所述参考电压的最大值VREF1与所述迟滞量△VHD的差值，即所述第一阈值)。
在本申请的一些实施例中，所述第二信号用于指示处于下降阶段中的所述第二电压是否小于或等于所述参考电压，所述第二电压还用于指示处于上升阶段中的所述第二电压是否大于或等于第二阈值，所述第二阈值与所述参考电压的差值为所述第二迟滞比较器122的迟滞量。
换言之，如图2所示，所述第二电压小变大时对应大门限电压(即所述第二阈值，即所述参考电压的最小值VREF2与所述迟滞量△VLD，即所述第二阈值)，所述第二电压由大变小时对应小门限电压(即所述参考电压的最小值VREF2)。
下面结合图2对图1所示的电压攻击检测电路的工作原理进行说明。
如图2所示，t1时刻之前，供电电压VDD由0开始上升，当供电电压VDD上升，且在t1时刻超过电路最低工作电压VMIN时，电路开始正常工 作。但是，由于此时的第二电压仍然低于第二参考电压VREF2，低压报警信号(即第二信号)VL由0变为1，以指示供电电压VDD出现低电压异常。供电电压VDD继续上升，且在t2时刻所述第二电压超过VREF2+ΔVLD时，低压报警信号VL由1变为0，以指示供电电压VDD未出现低电压异常。供电电压VDD继续上升且在t3时刻所述第一电压超过所述VREF1时，高压报警信号VH由0变为1，以指示供电电压VDD出现高电压异常。供电电压VDD开始下降，且在t4时刻所述第一电压低于VREF1-ΔVHD时，高压报警信号(即所述第一信号)VH由1变为0，以指示供电电压VDD未出现高电压异常。供电电压VDD继续下降，且在t5时刻所述第二电压低于VREF2时，低压报警信号VL由0变为1，以指示供电电压VDD出现低电压异常。若所述第二电压并未低于VMIN后就开始上升，即供电电压VDD继续上，且在t6时刻所述第二电压超过VREF2+ΔVLD时，低压报警信号VL由1变为0，以指示供电电压VDD未出现低电压异常。供电电压VDD继续上升，且在t7时刻所述第一电压超过VREF1时，高压报警信号VH由0变为1，以指示供电电压VDD出现高电压异常。
如图1所示，在本申请的一些实施例中，所述电压攻击检测电路还包括第一与门140和第二与门150。
其中，所述第一与门140用于接收所述第一信号和第一指示信号并输出第三信号，所述第二与门150用于接收所述第二信号和第二指示信号并输出第四信号，所述第一指示信号用于指示所述第一参考电压是否存在异常，所述第二指示信号用于指示所述第二参考电压是否存在异常。
需要说明的是，与门(AND gate)又称“与电路”、逻辑“积”、逻辑“与”电路。是执行“与”运算的基本逻辑门电路。所述与门可以有多个输入端，一个输出端。当所有的输入端接收的信号均为高电平(逻辑“1”)时，输出信号才为高电平(逻辑“1”)，否则输出信号为低电平(逻辑“0”)。换言之，所述第一信号和所述第一指示信号均为高电平(逻辑“1”)时，所述第三信号才为高电平(逻辑“1”)，类似地，所述第二信号和所述第二指示信号均为高电平(逻辑“1”)时，所述第四信号才为高电平(逻辑“1”)。
通过所述第一与门140和所述第二与门150，可以避免由于所述第一参考电压或第二参考电压存在异常，导致的所述第一信号和所述第二信号的指示不准确的情况。换言之，通过所述第一与门140和所述第二与门150，可 以避免由于所述参考电压存在异常导致的错误预警，以提升电压攻击预警的准确率。
如图1所示，在本申请的一些实施例中，所述电压攻击检测电路还包括参考电压生成电路160和参考电压检测电路170。
其中，所述参考电压生成电路160用于生成所述第一参考电压和所述第二参考电压，所述参考电压检测电路170连接至所参考电压生成电路160，所述参考电压检测电路170用于接收所述第一参考电压并输出所述第一指示信号。所述参考电压检测电路170还用于接收所述第二参考电压并输出所述第二指示信号。
例如，若所述第一信号用于指示所述第一电压大于或等于所述第一参考电压时，所述第一信号为高电平(逻辑“1”)，若所述第一指示信号用于指示所述第一参考电压存在异常，所述第一指示信号为低电平(逻辑“0”)。与所述第一指示信号类似，若所述第二信号用于指示所述第二电压小于或等于所述第二参考电压时，所述第二信号为高电平(逻辑“1”)，若所述第二指示信号用于指示所述第二参考电压存在异常，所述第二指示信号为低电平(逻辑“0”)。
换言之，在所述第一指示信号用于指示所述第一参考电压异常时，即使所述第一电压大于或等于所述第一参考电压，也将其复位为用于指示所述第一电压小于所述第一参考电压，此时，所述第一指示信息也可以称为复位信号(reset signal，RST)。换言之，所述参考电压检测电路170在所述第一参考电压不存在异常时不用于输出RST，在所述第一参考电压存在异常时用于输出RST。与所述第一指示信息类似，所述参考电压检测电路170在所述第二参考电压不存在异常时不用于输出RST，在所述第二参考电压存在异常时用于输出RST。
其中，所述参考电压生成电路160可以是带隙基准(Bandgap voltage reference，Bandgap)生成电路，即所述第一参考电压和所述第二参考电压可以是带隙基准。例如，带隙基准可以是一个与温度成正比的电压与一个与温度成反比的电压之和，二者温度系数相互抵消，实现与温度无关的电压基准。例如，所述带隙基准可以是一个与电源和工艺无关，具有确定温度特性的直流电压。例如，所述带隙基准可以约为1.25V。又例如，所述带隙基准的基准电压可以近似于硅的带隙电压。
在本申请的一些实施例中，所述参考电压生成电路160连接至外部电源(VDD)，当所述参考电压生成电路160基于所述外部电源(VDD)能够向所述至少一个电压传感器提供准确的第一参考电压和第二参考电压时，所述第一指示信号和所述第二指示信息均为高电平(逻辑“1”)。
当所述参考电压生成电路160工作异常时，即外部电源VDD已经过高或过低时，导致所述参考电压生成电路160提供的所述第一参考电压或所述第二参考电压不再准确，此时，所述第一指示信号或所述第二指示信息为低电平(逻辑“0”)，即让所述第一信号或所述第二信号输出为低电平(逻辑“0”)，即均不发出报警信号。相当于，使得迟滞比较器输出的报警信号被失效，以避免产生错误报警。
通过所述参考电压检测电路170，可以避免由于所述参考电压存在异常导致的错误预警，以提升电压攻击预警的准确率。
当然，若所述第一指示信号用于指示所述第一参考电压存在异常，所述第一指示信号为高电平(逻辑“1”)。或者，若所述第二指示信号用于指示所述第二参考电压存在异常，所述第二指示信号为高电平(逻辑“1”)。相当于，所述第一指示信号可以用于对所述第一参考电压所在的电源域是否受到高电压攻击进行预警，所述第二指示信号可以用于对所述第二参考电压所在的电源域是否受到电压攻击进行预警。换言之，通过所述参考电压检测电路170，不仅能够指示至少一个内部电源是否受到攻击，而且能够指示第一参考电压或第二参考电压所在的电源域是否受到攻击，以便在所述至少一个内部电源受到攻击或所述其他电源域受到攻击时提醒用户注意安全防护或采取安全措施。
如图1所示，在本申请的一些实施例中，所述电压攻击检测电路还包括毛刺消除电路180。
其中，所述参考电压生成电路160通过所述毛刺消除电路180分别连接至所述第一与门140和所述第二与门150，所述毛刺消除电路180用于将时长小于或等于预设阈值的用于指示参考信号存在异常的指示信号重置为用于指示参考信号不存在异常的指示信号。
例如，所述毛刺消除电路180可以用于将时长小于或等于预设阈值的用于指示所述第一参考信号存在异常的第一指示信号重置为用于指示所述第一参考信号不存在异常的第一指示信号。又例如，所述毛刺消除电路180可 以用于将时长小于或等于预设阈值的用于指示所述第二参考信号存在异常的第二指示信号重置为用于指示所述第二参考信号不存在异常的第二指示信号。
需要说明的是，毛刺可以是电路的输入波形中包括有规律或没有规律的脉冲信号或尖峰信号。例如，所述参考电压上出现正方向的毛刺时的电压值等于所述参考电压上未出现毛刺时的电压值加所述毛刺的电压值。又例如，参考电压上出现负正方向的毛刺时的电压值等于所述参考电压上未出现毛刺时的电压值减去所述毛刺的电压值。
换言之，针对不稳定的参考电压，其也可以认为是稳定的参考电压上叠加有一个毛刺后的电压。
通过所述毛刺消除电路180，在所述参考电压出现毛刺的情况下，能够保证所述第一指示信号和所述第二指示信号的准确率，相应的，能够保证所述第三信号和所述第四信号的准确率。换言之，通过所述毛刺消除电路180，能够在所述参考电压出现毛刺的情况下正确指示所述电源电压是否受到攻击，以便在所述电源电压受到攻击时提醒用户注意安全防护或采取安全措施。
如图1所示，在本申请的一些实施例中，所述电压攻击检测电路还包括第一或门131和第二或门132。
其中，所述第一或门131用于接收所述第一信号和第一测试信号并输出第五信号，所述第二或门132用于接收所述第二信号和所述第二测试信号并输出第六信号，所述第一测试信号用于指示所述第一电压大于或等于所述第一参考电压，所述第二测试信号用于指示所述第二电压小于或等于所述第二参考电压。如图1所示，所述第一测试信号也可称为高电压检测信号(TEST high voltage，TEST_HL)，所述第二测试信号也可称为低电压检测信号(TEST low voltage，TEST_VL)。所述第一或门131和所述第二或门132可以用于形成置位自检测电路130，用于对所述电压检测电路120输出的第一信号和所述第二信号进行测试。
换言之，若将TEST_VH置1，则所述第五信号也被强制置为1；若将TEST_VL置1，则所述第六信号也被强制置为1，以便于系统的功能性以及完整性调试。
需要说明的是，或门(OR gate)又称或电路、逻辑或电路。具体地， 如果几个条件中，只要有一个条件得到满足，某事件就会发生，这种关系叫做“或”逻辑关系，相应的，具有“或”逻辑关系的电路叫做或门。例如，或门可以有多个输入端，一个输出端，只要输入端中有一个输入端接收的信号为高电平(逻辑“1”)时，输出端输出的信号就为高电平(逻辑“1”)；只有当所有的输入端接收的信号均为低电平(逻辑“0”)时，输出端输出的信号才为低电平(逻辑“0”)。本申请实施例中，所述第一信号和所述第一测试信号中有一个信号为高电平(逻辑“1”)时，所述第五信号为高电平(逻辑“1”)，类似地，所述第二信号和所述第二测试信号中有一个信号为高电平(逻辑“1”)时，所述第六信号为高电平(逻辑“1”)。
通过所述第一测试信号和所述第二测试信号，可以强制让第五信号指示所述第一电压大于或等于所述参考电压，或可以强制让所述第六信号指示所述第二电压小于或等于所述参考电压，以便于设计人员对所述电压攻击检测电路进行检测。
换言之，通过所述第一或门131和所述第二或门132，可以分别强制让所述第五信号和所述第六信号进入报警状态。
如图1所示，在本申请的一些实施例中，所述电压攻击检测电路还包括第一电阻111。其中，所述第一可编程电路112通过所述第一电阻111连接至所述电源电压。
换言之，所述检测阈值产生电路110可以包括所述第一电阻111。
本申请还提供了一种芯片，所述包括电源管理单元以及上文所述的电压攻击检测电路；其中，所述电源管理单元连接至所述电压攻击检测电路，所述电压攻击检测电路用于检测所述电源管理单元的电源电压是否受到电压攻击。
换言之，所述电压攻击检测电路可以适用于任意一种具有电源管理单元的芯片。例如安全芯片。例如，所述安全芯片可以是指纹传感器芯片或者处理器芯片等等。所述安全芯片适用于任意一种电子设备。例如，智能手机、笔记本电脑、平板电脑、游戏设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机(Automated Teller Machine，ATM)等其他电子设备。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结 合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (11)

  1. 一种电压攻击检测电路，其特征在于，包括：
    第一可编程电阻和第二可编程电阻；
    所述第一可编程电阻的第一端连接至电源电压，所述第一可编程电阻的第二端通过所述第二可编程电阻连接至地电压，所述第一端用于输出第一电压，所述第二端用于输出第二电压；
    电压检测电路；
    其中，所述电压检测电路用于接收所述第一电压和第一参考电压并输出第一信号，所述第一信号用于指示所述第一电压是否大于或等于所述第一参考电压；所述电压检测电路还用于接收所述第二电压和第二参考电压并输出第二信号，所述第二信号用于指示所述第二电压是否小于或等于所述第二参考电压，所述第一参考电压大于所述第二参考电压。
  2. 根据权利要求1所述的电压攻击检测电路，其特征在于，所述第一参考电压小于或等于在所述电源电压为带隙基准的最大工作电压的情况下的所述第一电压的电压值，所述第二参考电压大于或等于在所述电源电压为所述带隙基准的最小工作电压的情况下的所述第二电压的电压值。
  3. 根据权利要求1或2所述的电压攻击检测电路，其特征在于，所述电压检测电路包括：
    第一迟滞比较器和第二迟滞比较器；
    其中，所述第一迟滞比较器的正输入端连接至所述第一端以接收所述第一电压，所述第一迟滞比较器的负输入端连接至所述第一参考电压，所述第一迟滞比较器的输出端用于输出所述第一信号，所述第二迟滞比较器的正输入端连接至所述第二端以接收所述第二电压，所述第二迟滞比较器的负输入端连接至所述第二参考电压，所述第二迟滞比较器的输出端用于输出所述第二信号。
  4. 根据权利要求3所述的电压攻击检测电路，其特征在于，所述第一信号用于指示处于上升阶段中的所述第一电压是否大于或等于所述第一参考电压，所述第一信号还用于指示处于下降阶段中的所述第一电压是否小于或等于第一阈值，所述第一参考电压与所述第一阈值的差值为所述第一迟滞比较器的迟滞量。
  5. 根据权利要求3所述的电压攻击检测电路，其特征在于，所述第二信号用于指示处于下降阶段中的所述第二电压是否小于或等于所述第二参考电压，所述第二电压还用于指示处于上升阶段中的所述第二电压是否大于或等于第二阈值，所述第二阈值与所述第二参考电压的差值为所述第二迟滞比较器的迟滞量。
  6. 根据权利要求1至5中任一项所述的电压攻击检测电路，其特征在于，所述电压攻击检测电路还包括：
    第一与门和第二与门；
    其中，所述第一与门用于接收所述第一信号和第一指示信号并输出第三信号，所述第二与门用于接收所述第二信号和第二指示信号并输出第四信号，所述第一指示信号用于指示所述第一参考电压是否存在异常，所述第二指示信号用于指示所述第二参考电压是否存在异常。
  7. 根据权利要求6所述的电压攻击检测电路，其特征在于，所述电压攻击检测电路还包括：
    参考电压生成电路和参考电压检测电路；
    其中，所述参考电压生成电路用于生成所述第一参考电压和所述第二参考电压，所述参考电压检测电路连接至所参考电压生成电路，所述参考电压检测电路用于接收所述第一参考电压并输出所述第一指示信号，所述参考电压检测电路还用于接收所述第二参考电压并输出所述第二指示信号。
  8. 根据权利要求7所述的电压攻击检测电路，其特征在于，所述电压攻击检测电路还包括：
    毛刺消除电路；
    其中，所述参考电压生成电路通过所述毛刺消除电路分别连接至所述第一与门和所述第二与门，所述毛刺消除电路用于将时长小于或等于预设阈值的用于指示参考信号存在异常的指示信号重置为用于指示参考信号不存在异常的指示信号。
  9. 根据权利要求1至8中任一项所述的电压攻击检测电路，其特征在于，所述电压攻击检测电路还包括：
    第一或门和第二或门；
    其中，所述第一或门用于接收所述第一信号和第一测试信号并输出第五信号，所述第二或门用于接收所述第二信号和所述第二测试信号并输出第六 信号，所述第一测试信号用于指示所述第一电压大于或等于所述第一参考电压，所述第二测试信号用于指示所述第二电压小于或等于所述第二参考电压。
  10. 根据权利要求1至9中任一项所述的电压攻击检测电路，其特征在于，所述电压攻击检测电路还包括：
    第一电阻；
    其中，所述第一可编程电路通过所述第一电阻连接至所述电源电压。
  11. 一种芯片，其特征在于，包括：
    电源管理单元；以及
    根据权利要求1至10中任一项所述的电压攻击检测电路；
    其中，所述电源管理单元连接至所述电压攻击检测电路，所述电压攻击检测电路用于检测所述电源管理单元的电源电压是否受到电压攻击。
PCT/CN2020/078445 2020-03-09 2020-03-09 电压攻击检测电路和芯片 WO2021179128A1 (zh)

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