Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level
  • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/20—Design optimisation, verification or simulation
  • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N20/00—Machine learning
  • G06N20/20—Ensemble learning
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/04—Ageing analysis or optimisation against ageing
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/22—Yield analysis or yield optimisation

Definitions

• This application relates to semiconductor manufacturing processes, and more particularly, to systems and methods for predicting die that are susceptible to early lifetime failure.
• FIG. 1 is a flow chart illustrating a process for modeling die-level yield to predict early lifetime failure.
• FIG. 2 is a graph of parametric yield prediction versus parametric prediction yield.
• FIG. 3 is a graph of percentage die lost versus percentage of early lifetime failures.
• FIG. 4 is a flow chart illustrating additional detail of the process of FIG. 1.
• FIG. 5 is a table illustrating how to identify parameter groups.
• This disclosure is directed to a method and systems for modeling yield at the die level to predict die that are susceptible to early lifetime failure (ELF) based primarily on parametric data obtained from the wafer test and sort step in a semiconductor manufacturing process.
• ELF early lifetime failure
• the modeled yield method described herein has been shown to provide significantly improved predictive capability on a large data set with a limited number of known field returns.
• Modern machine learning technologies can be used to configure algorithmic-based software models that learn the complex non-linear relationships, initially from training sets of data, and updated from newly acquired data, to better understand the relationships among the input parameters.
• a neural network is an example of an implementation of a machine learning model
• XGBoost is another machine learning model based on extremely complex tree models.
• the processor-based models could be desktop-based, i.e., standalone or part of a networked system, and should preferably be implemented with current state-of-the-art hardware and processor capabilities (CPU, RAM, OS, etc.).
• a Python object-oriented programming language can be used for coding machine language models, and program instruction sets can be stored on computer-readable media.
• Fabrication is the major step in a typical semiconductor manufacturing process, wherein a large number of integrated circuits are formed on a single slice or wafer of semiconductor substrate, such as silicon, through multiple steps and different processing techniques over a period of time (e.g., months).
• the wafers are tested and sorted. Initially, a small set of structures formed in the scribe lines of the wafer may be tested, for example, to make sure that V t or other voltage or current levels are within range across the wafer, or that contact resistance or other electrical properties are within specifications.
• the scribe line structure tests must typically meet customer criteria for the wafers.
• each integrated circuit formed on a die is subject to a variety of further tests.
• Functional testing typically involves applying test patterns to individual circuits using a circuit probe, and if the expected digital output is detected, the circuit passes; if not, the circuit fails.
• Other tests are parametric in nature, obtaining numerical values as responses for parametric tests of, e.g., ring oscillator frequencies, current/voltage values for a particular size transistor, etc. Generally, if the numerical parametric value is greater than or less than a threshold or limit, then even if the chip functions, it is viewed as non-viable and fails because of the parametric value.
• Circuits that fail the testing procedure may be discarded (or marked for destruction once the wafer is diced), and the status of the circuits can be marked or otherwise identified, for example, stored in a file that represents a wafer map.
• the present modeling methods can utilize the wafer sort testing data for all die, pass or fail, in forming more effective predictions. After wafer testing and sort, the wafer is diced up into its individual circuits or dies, and each die that passes wafer test/sort is packaged.
• a simplified process 100 for modeling yield to predict die susceptible to early lifetime failure is illustrated.
• a first machine learning model is configured to predict yield for each die, i.e., determine the likelihood that a particular die is good, based (at least initially) on all the data from all the die in a grouping of parameters that appear together with the particular die in testing that has passed all the die in the group.
• Inputs to the first model are the location of the die, the wafer sort parametric values, and any other available data (e.g., from fabrication or packaging steps).
• the first model analyzes the input data and decides which inputs are more important in predicting yield, then finalizes the model for parametric yield prediction (PY) for each die based only on the more important input data, and stores the resultant prediction PY in step 103.
• PY parametric yield prediction
• a second machine learning model is configured to predict yield for each die based only on the location of the die. This result is the reference yield (RY) prediction for each die. In general, locations closer to the edge are more likely to result in failing die while locations closer to the center more typically result in passing die.
• the reference yield prediction RY is subtracted from the parametric yield prediction PY and the result is a parametric yield delta (DRU).
• FIG. 2 is a graphical plot 200 of the parametric yield prediction PY on the x-axis and the parametric yield delta DRU on the y-axis for an actual sampling of wafer sort and test parametric data for more than 12,000 die indicated by symbols 201. Die that have been identified as field returns are indicated by symbols 209.
• the graphical plot 300 of FIG. 3 illustrates the comparison between a conventional method for identifying outliers to predict yield, indicated by line 310, and the modeled yield method for predicting early lifetime failures, indicated by line 320.
• the x-axis indicates the percentage of good die sacrificed to reduce field returns and the y-axis indicates the percentage of early lifetime failures known from the prediction method.
• the graph 300 shows an improvement of 10% or more in the ability to identify early lifetime failures with the modeled yield approach for this data set, a significant and valuable improvement.
• a customer can make choices about how much risk of die failure is acceptable. For example, a customer with a high-reliability application (such as avionics) would have a very low tolerance for field failures, while a more cost-conscious customer may have a higher tolerance for failures.
• a high-reliability application such as avionics
• a maximum limit is estimated for each die relevant parameter. Although there may be thousands of such parameters for each unique die design, each parameter has a value at which the die will always fail, and those limits are considered first. Typically, a customer will provide data for its list of parameters and a threshold value or customer limit for each parameter. However, for the purposes of modeling, it may be more effective if the limit or threshold for each parameter is determined independently from the customer data. For example, in one embodiment, the maximum limit is taken from a review of the customer data as the largest value of any die that yields, while all larger values consistently result in failing the die.
• the parameters for each die are compared to thresholds based on the estimated limits, and if any die exceeds the threshold for any parameter in step 406, it is removed or marked for removal in step 408 to avoid further processing.
• a parameter group is one in which a group of passing die all have testing values for the same parameters as a result of a wafer sort and testing procedure.
• the parameter groups can be non-exclusive.
• table 500 provides an example to illustrate identifying parameter groups.
• the first column 501 lists the bin into which die have been classified according the results from wafer test/sort.
• the second column 502 lists the specific parametric test performed, including tests A1 - A4 and B1 - B3.
• Columns 503 - 506 indicate whether a parameter data value has been returned for the respective test in that row. It can be seen that the parameters of tests A1 are present in Die2, Die3 and Die4, thus forming a first parameter group 511. It can be further seen that the parameters of tests A2 - A4 are present in Diel and Die2 thus forming a second parameter group 512. Finally, the parameters of tests B1 - B3 are present in Die2 and Die3 thus forming a third parameter group 513.
• a first machine learning model is built in step 412 as a cross-validated model for determining a yield prediction for each identified parameter group.
• the first model is run for each parameter group using data from all die that show values for all parameters in that parameter group.
• the yield prediction from the first model is stored and saved for each die in the parameter group.
• step 416 the yield predictions across all parameter groups to which the particular die belongs are combined, for example, as a statistical function.
• the average is taken across all yield predictions for the die and stored and saved as the parametric yield prediction PY in step 418.
• a second machine learning model is built in step 420 for reference yield prediction.
• the result is determined by computing the yield prediction for each individual die based solely on the location of the die on the wafer.
• polar coordinates are used to provide a smoother modeling result.
• a parametric yield prediction delta DRU is calculated in step 422 by subtracting the reference yield prediction RY (step 420) from the parametric yield prediction PY (step 418).
• a negative delta is undesirable because it means that the reference yield prediction is higher than the parametric yield prediction.
• step 424 after all predictions have been determined, any die that failed wafer sort testing are discarded thereby limiting the remaining die to be analyzed.
• the die that fail wafer sort testing cannot be early lifetime failures since they would never be shipped or even packaged.
• the parametric yield predictions PY are sorted from lowest to highest in step 426, and the applicable predicted yield PY percentile of each die is calculated in step 428.
• the parametric yield prediction deltas DRU are sorted from lowest to highest in step 430, and the applicable percentile DRU of each die is calculated in step 432.
• a target for acceptable loss can be established in step 436, and die in the target region(s) predicted for early lifetime failure removed from further processing in step 438.
• the minimum of the PY percentile and the DRU percentile is the primary indicator of the likelihood for the die to be an early lifetime failure.
• a customer can establish its tolerance for some level of loss and establish a policy to remove selected die that have a likelihood of early lifetime failure meeting a PY percentile criteria and/or a DRU percentile criteria.

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• 2021
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