WO2021174977A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021174977A1
WO2021174977A1 PCT/CN2020/140796 CN2020140796W WO2021174977A1 WO 2021174977 A1 WO2021174977 A1 WO 2021174977A1 CN 2020140796 W CN2020140796 W CN 2020140796W WO 2021174977 A1 WO2021174977 A1 WO 2021174977A1
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Prior art keywords
layer
trench
groove
thin film
base substrate
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PCT/CN2020/140796
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English (en)
French (fr)
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宫奎
段献学
崔海峰
刘天真
张志海
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US17/418,218 priority Critical patent/US20240014225A1/en
Publication of WO2021174977A1 publication Critical patent/WO2021174977A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • This application relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display panel.
  • Thin film transistors can be used as pixel switching elements of flat panel displays.
  • the active layer of the thin film transistor may be mainly formed of amorphous silicon or polysilicon.
  • the amorphous silicon active layer is easier to deposit on a large area and easy to process at low temperature, but it has the disadvantage of low carrier mobility.
  • the polysilicon active layer has excellent electrical characteristics due to high carrier mobility, but requires high-temperature processing and is poor in reliability.
  • an oxide semiconductor such as IGZO
  • IGZO oxide semiconductor
  • the compositional characteristics of the oxide semiconductor active layer are easily affected by subsequent processes, resulting in poor TFT performance, which in turn leads to poor display products.
  • the present application discloses a display substrate, a preparation method thereof, and a display panel, with the purpose of improving the structure of the display substrate, improving the characteristics of thin film transistors, and improving the yield of display products.
  • a display substrate includes:
  • Thin film transistors located on the base substrate are Thin film transistors located on the base substrate;
  • the planarization layer is located on the side of the thin film transistor away from the base substrate, the planarization layer is provided with a trench arranged around the channel region of the thin film transistor, and the trench is on the base substrate There is no overlap between the orthographic projection of the channel region and the orthographic projection of the channel region on the base substrate.
  • the groove is an annular groove surrounding the channel region.
  • the groove includes a plurality of sections of groove bodies arranged at intervals around the channel region in sequence, and the plurality of sections of groove bodies are sequentially adjacent end to end but not connected.
  • the groove is a blind groove with a depth less than the thickness of the planarization layer.
  • the groove is a through groove passing through the thickness direction of the planarization layer.
  • the groove includes an annular main body portion and a plurality of protruding portions protruding relative to the side wall of the annular main body portion, and the orthographic projection of the protruding portion on the base substrate is located in the The orthographic projection of the ring-shaped body portion on the base substrate faces a side of the orthographic projection of the channel region on the base substrate.
  • the thin film transistor includes source and drain electrodes
  • the planarization layer further includes a first via hole for exposing the source and drain electrodes
  • the trench is in communication with the first via; the size of the first via is greater than the width of the trench.
  • the width of the groove is 1 ⁇ m-3 ⁇ m.
  • the display substrate further includes:
  • the first electrode layer is located on the side of the planarization layer away from the base substrate.
  • the first electrode layer includes a first portion located in the trench, and the first portion covers the bottom of the trench and Exposing the sidewall of the trench;
  • the first inorganic insulating layer is located on a side of the first electrode layer away from the base substrate, and the first inorganic insulating layer covers the bottom and sidewalls of the trench.
  • the slope angle of the sidewall of the trench is greater than 80 degrees.
  • a display panel comprising the display substrate according to any one of the above, and the groove is located in a non-opening area of the display panel.
  • a method for preparing a display substrate includes the following steps:
  • a planarization layer is prepared on the thin film transistor, the planarization layer is provided with a trench arranged around the channel region of the thin film transistor, and the orthographic projection of the trench on the base substrate and the trench The orthographic projection of the track area on the base substrate does not overlap.
  • preparing a planarization layer on the thin film transistor specifically includes:
  • the organic resin layer is processed through an ashing process, so that the blind groove becomes a through groove penetrating the thickness direction of the organic resin layer.
  • preparing a thin film transistor on a base substrate which specifically includes:
  • the active layer and the source and drain electrodes are sequentially prepared on the base substrate;
  • the preparation of a planarization layer on the thin film transistor specifically includes:
  • the blind groove is formed in the organic resin layer through an exposure and development process, and a first via for exposing the source and drain electrodes is formed in the organic resin layer at the same time.
  • the width of the blind groove is the same as that of the first via hole.
  • the ratio of the size of a via hole is in the range of 1/10-1/2.
  • processing the organic resin layer through an ashing process specifically includes:
  • O2 is used as a working gas, and the organic resin layer is bombarded and etched by a plasma etching device to remove the residue of the organic resin layer at the bottom of the blind groove.
  • the method further includes:
  • a first electrode layer is prepared on the planarization layer by magnetron sputtering.
  • the first electrode layer includes a first part located in the trench, and the first part covers the bottom of the trench and exposes it. The sidewall of the trench.
  • the method further includes:
  • An inorganic insulating layer is prepared on the first electrode layer by PECVD, and the inorganic insulating layer covers the bottom and sidewalls of the trench.
  • FIG. 1 is a schematic diagram of a partial plane structure of a display substrate provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a partial plane structure of a display substrate provided by another embodiment of the application.
  • FIG. 3 is a schematic diagram of a partial plane structure of a display substrate provided by another embodiment of the application.
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of the display substrate in FIG. 1 along the A1-A2 direction;
  • FIG. 5 is a schematic diagram of a partial cross-sectional structure of a display substrate after an organic resin layer is formed according to an embodiment of the application;
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of a display substrate after a blind groove is formed in an organic resin layer according to an embodiment of the application;
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of a display substrate after a through groove is formed in an organic resin layer according to an embodiment of the application;
  • FIG. 8 is a schematic diagram of a partial cross-sectional structure of the display substrate after the first electrode layer is formed according to an embodiment of the application;
  • FIG. 9 is a schematic diagram of a partial cross-sectional structure of a display substrate after forming a second inorganic insulating layer according to an embodiment of the application.
  • FIG. 10 is a schematic partial cross-sectional structure diagram of a display substrate according to an embodiment of the application after forming a second via hole penetrating the first inorganic insulating layer and the second inorganic insulating layer;
  • FIG. 11 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the application.
  • oxide semiconductor thin film transistors such as IGZO TFT
  • the switching voltage Vth is often small and does not reach the expected value, which will affect the reliability of oxide semiconductor thin film transistors. Negative impact. Among them, an important factor that affects the TFT switching voltage Vth is the organic insulating layer.
  • the organic insulating film layer is widely used on the TFT array substrates of high-end products because of its low dielectric constant and better surface flatness.
  • the organic insulating film layer can block the intrusion of external water vapor and protect the back channel of the TFT.
  • the water vapor and other exhaust gases (Outgas) released during the high-temperature process of the organic insulating film will also seriously affect the device characteristics of IGZO TFT.
  • reducing gases such as water vapor will be released.
  • these gases will also diffuse downward and penetrate into the active layer channel of the TFT, thereby causing the TFT
  • the overall right deviation of the transfer characteristic curve is even directly manifested as conductorization.
  • the embodiments of the present application disclose a display substrate and a preparation method thereof, a display panel, and a display device.
  • the purpose is to improve the structure of the display substrate and reduce the effect of the gas (Outgas) released by the organic insulating film layer in the high temperature process on IGZO.
  • the influence of the characteristics of TFT devices further improves the characteristics of thin film transistors and improves the yield of display products.
  • FIGS. 1 to 3 are schematic plan views of a pixel area of the display substrate, and FIG. 4 is a schematic cross-sectional structure view of FIG. 1 along the A-A direction.
  • the film layers are schematically shown in FIGS. 1 to 3, such as the gate 21, the active layer 23, the source and drain electrodes 24, the first electrode layer 4, and the pixel electrode 6, and there are also schematic drawings.
  • the trench 31 and the first via 32 in the planarization layer, the opening 40 of the first electrode layer 4 and other structures are shown, but in order to ensure the clear effect of the graphics, the planarization layer and the first inorganic insulation are not shown in the figure.
  • the film layers such as the second inorganic insulating layer and the second inorganic insulating layer, specifically, the respective film layers involved in FIGS. 1 to 3 and their positional relationship can be specifically referred to the cross-sectional view of FIG. 4.
  • an embodiment of the present application provides a display substrate, including:
  • the thin film transistor 2 is located on the base substrate 1;
  • the planarization layer 3 is located on the side of the thin film transistor 2 away from the base substrate 1.
  • the planarization layer 3 is provided with a trench 31 arranged around the channel region 230 of the thin film transistor 2, and the trench 31 is on the front side of the base substrate 1.
  • the projection and the orthographic projection of the channel region 230 on the base substrate 1 do not overlap.
  • a planarization layer 3 is provided above the thin film transistor (TFT) 2.
  • the planarization layer 3 can block the intrusion of external water vapor and the like, thereby protecting the channel region 230 of the TFT 2; and, the planarization layer 3 is provided with
  • the trench 31 provided around the channel region 230 of the TFT 2 is subsequently flattened in the high-temperature annealing process of the planarization layer 3 and/or the high-temperature annealing process of the electrode layer (for example, the first electrode layer 4) above the planarization layer 3
  • the oxide layer 3 releases water vapor and other reducing gases (Outgas).
  • the trench 31 can increase the path for these gases (Outgas) to be released outward, and prevent Outgas from diffusing down to the channel region 230 of the oxide TFT 2 to make the TFT 2 characteristic
  • the orthographic projection of the trench 31 and the orthographic projection of the TFT 2 channel region 230 do not overlap, that is, the TFT 2 channel region 230 still has a complete organic planarization film covering and protection, so the trench The setting of 31 will not affect the protective effect of the planarization layer 3 on the channel region 230 of the TFT 2.
  • the above-mentioned display substrate can reduce the influence of the gas (Outgas) released by the organic planarization layer in the high temperature process on the characteristics of the TFT device through the trench structure in the planarization layer above the thin film transistor (TFT), thereby improving the characteristics of the TFT device.
  • the characteristics of TFT devices improve the yield of display products.
  • the trench 31 may be an annular groove surrounding the channel region 230.
  • the annular groove may be a closed-loop groove or an open-loop groove.
  • the annular groove 31 can divide the planarization layer 3 into an independent part 301 covering the channel region 230 and an enclosing part surrounding the independent part 301, and the annular groove 31 divides the independent part 301 is separated from the surrounding part, which can prevent the water vapor generated in the high temperature process of the surrounding part from diffusing to the independent part 301 and the channel region 230.
  • the independent part 301 itself has a small area, and the water vapor generated in the high temperature process is very small, and The generated water vapor can diffuse outwards through the annular groove 31, so the water vapor eventually diffused to the channel region 230 is very small, and hardly affects the channel region 230.
  • the trench 31 may include a plurality of grooves (strip grooves 310 in the figure) arranged at intervals around the channel region 230. Specifically, the plurality of grooves are arranged in sequence. Adjacent end to end but not connected.
  • the above-mentioned multi-segment groove body surrounds the TFT channel, and the shape of the groove body is not limited, and specifically may be a circle, an ellipse, a square, a strip, and the like.
  • the trench 31 includes a plurality of strip-shaped grooves 310 arranged at intervals.
  • the plurality of strip-shaped grooves 310 are arranged in sequence around the channel region, and are adjacent but not connected end to end, and each segment of the strip groove 310 surrounds the groove.
  • Road area extension is provided.
  • the trench 31 surrounds the channel region 230 in a ring shape, specifically, it may be surrounded in a circular ring shape, or may be surrounded in an elliptical ring shape (as shown in FIGS. 1 and 3) or a square ring shape (such as (Shown in Figure 2), the surrounding shape is not limited here.
  • the trench 31 may be a blind trench with a depth less than the thickness of the planarization layer 3, such as the blind trench 71 shown in FIG. 6.
  • the groove 31 may be a through groove extending through the thickness direction of the planarization layer 3, as shown in FIG. 4.
  • the groove 31 may include an annular main body portion 311 and a plurality of protruding portions 312 protruding with respect to the side wall of the annular main body portion 311.
  • the protruding portions 312 are formed on the base substrate.
  • the orthographic projection is located on the side of the orthographic projection of the annular main body portion 311 on the base substrate toward the orthographic projection of the channel region 230 on the base substrate, that is, the protruding portion 312 is located inside the annular main body portion 311.
  • both the'annular main body portion 311' and the'protruding portion 312' are part of the groove 31, which are essentially grooves.
  • The'annular main body portion 311' is an annular groove, and the'protruding portion 312' 'Is the groove body opened on the inner side wall of the annular groove body.
  • the protruding portion 312 is added to the annular body portion 311 to increase the sidewall area of the trench 31, thereby increasing the release path of Outgas in the planarization layer, and reducing the diffusion of Outgas to the TFT channel region.
  • the thin film transistor 2 includes source and drain electrodes 24, and the planarization layer 3 further includes a first via 32 for exposing the source and drain electrodes 24.
  • the first via 32 may It is used for electrical connection between the pixel electrode 6 and the source and drain electrodes 24.
  • the trench 31 in the planarization layer 3 communicates with the first via 32.
  • the trench 31 and the first via 32 may also be two independent structures, which are not connected to each other, as shown in FIG. 2 for example. Which form to use can be determined according to actual needs.
  • the size of the first via hole 32 is larger than the width of the trench 31.
  • the first via hole 32 is generally prepared by an exposure and development process. Since the thickness of the planarization layer 3 is relatively thick, in order to prevent the planarization layer material from remaining in the first via hole 32 due to insufficient exposure, the planarization layer 3
  • the size of the first via 32 is generally larger. Exemplarily, the size of the first via hole 32 is generally greater than 7 ⁇ m, and may be, for example, 7 ⁇ m-10 ⁇ m.
  • the size of the trench 31 is designed to be small.
  • the size of the trench 31 may be 1 ⁇ m-5 ⁇ m, and further, may also be 1 ⁇ m-3 ⁇ m, so that the protection effect of the planarization layer 3 on the channel region 230 of the TFT 2 is not affected.
  • the "dimensions" of structures such as vias, trenches, and openings involved in this application refer to radial dimensions, which are related to the shape of the structure.
  • a circular via its'size' refers to the diameter of a circle
  • a square via its'size' refers to the diagonal of a square
  • a circular or square groove or opening
  • the size is the same as above; for a strip or ring groove, the'size' refers to the width of the strip or ring.
  • the display substrate further includes a first electrode layer 4, which is located on the side of the planarization layer 3 away from the base substrate 1, and includes The first part 41, the first part 41 covers the bottom of the trench 31 and exposes the sidewalls of the trench 31, that is, the first part 41 of the first electrode layer 4 in the trench 31 and the other parts of the first electrode layer 4 in the trench 31
  • the sidewalls are disconnected, so that Outgas in the planarization layer 3 can diffuse outward from the sidewalls of the trench 31, reducing the diffusion of Outgas to the channel region 230 of the TFT 2.
  • the slope angle of the sidewall of the trench 31 is greater than 80 degrees. Since the slope angle of the sidewall of the trench 31 is relatively steep, the coverage at the sidewall of the trench 31 is poor when the film is prepared by magnetron sputtering, so that the first electrode layer 4 can be positioned at the second position in the trench 31. The part 41 is easily disconnected from the rest at the sidewall of the trench 31.
  • the display substrate provided by the embodiment of the present application may be an array substrate of a liquid crystal display panel (LCD), the first electrode layer 4 may be a common electrode layer, and the material of the first electrode layer 4 is transparent indium tin oxide (ITO ).
  • LCD liquid crystal display panel
  • ITO transparent indium tin oxide
  • the display substrate further includes a first inorganic insulating layer 51.
  • the first inorganic insulating layer 51 is located on the side of the first electrode layer 4 away from the base substrate 1 and covers the groove 31. Bottom and side walls.
  • the first inorganic insulating layer 51 can be used as a passivation layer, and a silicon nitride material with strong moisture isolation ability can be selected to protect the first electrode layer 4.
  • the size of the trench 31 is small, and there is a first inorganic insulating layer 51 covering and protecting it. External water vapor cannot easily enter the planarization layer 3 through the trench 31. Therefore, the planarization layer 3 affects the channel region 230 of the TFT 2 The protective effect will not be affected.
  • the display substrate further includes a second inorganic insulating layer 52, which is located between the TFT 2 and the planarization layer 3 and is used to cover and protect the TFT 2.
  • the material of the second inorganic insulating layer 52 may be silicon oxide, or may be a multilayer composite such as silicon oxide/silicon nitride.
  • a second via 50 penetrating through the first inorganic insulating layer 51 and the second inorganic insulating layer 52 is also nested in the first via 32.
  • the first electrode layer 4 is provided with an opening 40 for exposing the first via hole, and the size of the opening 40 is larger than the size of the first via hole 32.
  • the display substrate further includes a pixel electrode 6.
  • the pixel electrode 6 is located on the side of the first inorganic insulating layer 51 away from the first electrode layer 4 and passes through the first via hole 32 and the first electrode layer 4.
  • the two via holes 50 are electrically connected to the source and drain electrodes 24.
  • the pixel electrode 6 may be made of transparent ITO material.
  • the thin film transistor 2 includes an active layer 23.
  • the active layer 23 may be an oxide semiconductor, such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the material of the active layer 23 is not Limited to this, it can also be other materials whose component characteristics are easily affected by Outgas.
  • the thin film transistor 2 further includes a gate (Gate) 21 and a gate insulating layer (GI) 22.
  • the thin film transistor 2 may include a gate (Gate) 21, a gate insulating layer (GI) 22, an oxide semiconductor active layer (Active) 23, and a metal Source drain electrode (SD) 24.
  • the gate electrode material can be Al, Cu, Au, Ag, Ti, Ta and other common metal materials.
  • the SD electrode can be a multilayer composite
  • the structure for example, can be Mo/Cu/Mo, MoNb/Cu/MoNb, and so on.
  • the display substrate provided in the present application is not limited to be used as an array substrate, but can also be used as a drive backplane for OLEDs.
  • the first electrode layer can also be a pixel electrode (anode), and the first inorganic insulating layer can also be It is the pixel defining structure, etc., which are not limited here.
  • the present application also provides a display panel.
  • the display panel includes any one of the above-mentioned display substrates.
  • the groove in the planarization layer is located in a non-opening area of the display panel.
  • the non-open area of the display panel is the area outside the open area.
  • the open area is defined by the light-shielding layer in the display panel, and the non-open area can be regarded as the area that is blocked by the light-shielding layer and does not emit light.
  • the trench 31 is arranged around the channel region 230 of the TFT, is located in the non-opening area, and has a small size, so it will not affect the aperture ratio of the display panel.
  • the above-mentioned display panel is an LCD
  • the display substrate is an array substrate.
  • the above-mentioned display panel is an OLED, and the display substrate is a driving backplane.
  • the present application also provides a display device, which includes any one of the above-mentioned display panels.
  • the above-mentioned display device can be applied to various electronic devices such as televisions, monitors, tablet computers, and smart phones.
  • the present application also provides a method for preparing the display substrate. As shown in FIG. 11, the method includes the following steps:
  • Step 101 preparing a thin film transistor on a base substrate
  • Step 102 prepare a planarization layer on the thin film transistor, the planarization layer is provided with a trench arranged around the channel region of the thin film transistor, the orthographic projection of the trench on the base substrate and the orthographic projection of the channel region on the base substrate The projections do not overlap.
  • step 102 preparing a planarization layer on the thin film transistor, may specifically include:
  • Step 201 coat an organic resin layer 7 on the thin film transistor 2; for example, the thickness of the organic resin layer 7 may be 2 ⁇ m-5 ⁇ m;
  • an annular blind groove 71 surrounding the channel region 230 of the thin film transistor 2 is formed in the organic resin layer 7 through an exposure and development process; for example, the depth of the blind groove 71 is equal to that of the organic resin layer 7
  • the ratio of the thickness is greater than 1/2, for example, the width of the blind groove 71 may be 1 ⁇ m-5 ⁇ m, and further, it may be 1 ⁇ m-3 ⁇ m;
  • Step 203 as shown in FIG. 7, the organic resin layer 7 is processed through an ashing process, so that the blind groove 71 becomes a through groove 70 penetrating the thickness direction of the organic resin layer 7.
  • the organic resin layer 7 is a photosensitive material, which can be used as a photoresist, and can be directly subjected to processing such as exposure, development, and ashing.
  • step 101 preparing a thin film transistor on a base substrate, specifically includes: as shown in FIG. 5, an active layer 23 and source and drain electrodes 24 are sequentially prepared on the base substrate 1.
  • step 101 in the step of preparing the thin film transistor 2 on the base substrate 1, before preparing the active layer 23, it further includes sequentially preparing a gate 21 and a gate insulating layer (GI) Step 22. Between step 101 and step 102, a step of preparing a second inorganic insulating layer 52 on the thin film transistor 2 may also be included.
  • step 102 preparing a planarization layer on the thin film transistor, may specifically include: as shown in FIG. 6, forming blind grooves 71 in the organic resin layer 7 through an exposure and development process, and at the same time forming a The first via 72 exposing the source and drain electrodes 24; for example, the ratio of the width of the blind groove 71 to the size of the first via 72 is in the range of 1/10-1/2; for example, the width of the blind groove 71 may be 1 ⁇ m-5 ⁇ m, for example, the width of the blind groove 71 may also be 1 ⁇ m-3 ⁇ m, and the size of the first via 72 may be 7 ⁇ m-10 ⁇ m.
  • the blind groove 71 and the first via 72 are simultaneously formed in the organic resin layer 7 through a single patterning process, or in other words, while the first via 72 in the organic resin layer 7 is formed through the patterning process, the surrounding
  • the blind groove 71 of the channel region 230 of the TFT 2 can form the blind groove 71 without adding any process steps, which can effectively simplify the manufacturing process and save costs.
  • the organic resin layer 7 is usually subjected to ashing treatment (Ashing ), after the ashing treatment, the electrode layer is coated.
  • Ashing ashing treatment
  • the ashing process for the organic resin layer 7 is used to etch and remove all the organic resin film layers in the blind groove 71, so that the blind groove 71 becomes a through groove 70 penetrating the thickness direction of the organic resin layer 7, such as As shown in FIG.
  • the area of the sidewall of the finally formed trench can be made larger, and the diffusion area and release path of Outgas in the organic resin layer 7 can be increased, thereby reducing the diffusion of Outgas to the channel region 230 of the TFT 2 and reducing The influence of small Outgas on the channel region 230 of the TFT 2.
  • the electrode layer covering the organic resin layer 7 (the first electrode layer 4 in FIG. 8) is easily disconnected at the side wall of the through groove 70 to ensure that Outgas can be released and diffused outward through the side wall of the through groove 70.
  • the groove formed in the final planarization layer may also be a blind groove.
  • the groove structure can also increase the release path of Outgas and reduce the effect of Outgas diffusion to the TFT channel region.
  • the size of the first via hole is generally larger.
  • the size of the first via hole is greater than 7 ⁇ m, for example, it may be 7 ⁇ m-10 ⁇ m.
  • the size of the through groove is designed to be small.
  • the size of the through groove may be 1 ⁇ m-5 ⁇ m, for example, may also be 1 ⁇ m-3 ⁇ m, so that the protective effect of the organic resin layer on the TFT channel region will not be affected.
  • the size of the trench (blind groove 71) that needs to be formed is relatively small (approximately controlled at 1 ⁇ m-3 ⁇ m), which is affected by the exposure machine As a result, the material of the organic resin layer 7 at the bottom cannot be sufficiently photosensitive during exposure, and the organic resin material remains at the bottom of the groove 31 after development, so that the blind groove 71 with the depth less than the thickness of the organic resin layer 7 will be prepared.
  • step 102 may also include the step of annealing the organic resin layer 7.
  • the annealing condition is a high temperature treatment at 250° C. for 30 minutes in an air atmosphere.
  • the reducing Outgas such as water vapor in the organic resin layer 7 will be released outwards.
  • the organic resin layer 7 is provided with a through groove 70 surrounding the channel region 230 of the TFT 2, the release path of the above-mentioned Outgas can be increased, such as As shown in FIG. 7, the internal water vapor in the organic resin layer 7 above the channel region 230 of the TFT 2 can be released outward through the sidewall of the through groove 70 to prevent the downward diffusion of Outgas from adversely affecting the channel region 230 of the TFT 2.
  • step 203 processing the organic resin layer through an ashing process, specifically includes:
  • O 2 as the working gas, plasma etching equipment is used to bombard and etch the organic resin layer to remove the residue of the organic resin layer at the bottom of the blind groove.
  • the ashing treatment by O 2 plasma can reduce the damage to the second inorganic insulating layer 52 under the organic resin layer 7, and the plasma etching equipment is used to etch with O 2 plasma.
  • the residue at the bottom of the blind groove is etched, it is easier to make a through groove 70 with a steep side wall slope angle.
  • the slope angle of the side wall of the through groove 70 may be greater than 80 degrees.
  • the above-mentioned ashing process can not only completely etch and remove the residue at the bottom of the blind trench, but also completely remove the film residue in the first via hole.
  • the preparation process of the trench does not require any additional procedures, the preparation process is simple, and the cost is very low.
  • step 102 that is, after preparing a planarization layer on the thin film transistor, the following steps may be further included:
  • Step 103 prepare a first electrode layer 4 on the planarization layer (that is, the organic resin layer 7) by magnetron sputtering.
  • the first electrode layer 4 includes a groove (that is, a through groove 70). Inside the first part 41, the first part 41 covers the bottom of the groove (through groove 70) and exposes the sidewall of the groove (through groove 70).
  • the first electrode layer is formed by magnetron sputtering. 4 will be broken at the side wall of the through groove 70, thereby forming the first part 41 in the through groove 70 and the remaining part outside the through groove 70.
  • the first electrode layer 4 may be a transparent ITO material.
  • the first electrode layer 4 needs to be subjected to a high-temperature annealing treatment.
  • the specific conditions may be: a high-temperature treatment at 230°C for 30 minutes in an N 2 atmosphere.
  • the reducing Outgas such as moisture in the organic resin layer 7 will be released outwards.
  • the organic resin layer 7 is provided with a through groove 70 surrounding the channel region 230 of the TFT 2 and the first electrode The layer 4 exposes the sidewalls of the through groove 70.
  • the reducing Outgas inside the organic resin layer 7 can be released through the sidewalls of the through groove 70 to prevent the downward diffusion of Outgas from causing adverse effects on the channel region 230 of the TFT 2 Influence.
  • step 103 that is, after the first electrode layer is prepared on the planarization layer by magnetron sputtering, the following steps may be further included:
  • Step 104 as shown in FIG. 9, a first inorganic insulating layer 51 is prepared on the first electrode layer 4 by means of chemical vapor deposition (PECVD), and the first inorganic insulating layer 51 covers the bottom of the trench (that is, the through groove 70) And side walls.
  • PECVD chemical vapor deposition
  • the PECVD method has better coverage of the sidewalls of the through groove 70, so the part of the first inorganic insulating layer 51 formed by the PECVD method in the through groove 70 can completely cover the through groove 70, thereby It is possible to prevent external water vapor from entering the organic resin layer 7 through the through groove 70 and affecting the channel region 230 of the TFT 2.
  • the first electrode layer 4 may be a common electrode, and the first inorganic insulating layer 51 is used to protect the first electrode layer 4.
  • the preparation method of the embodiment of the present application may further include the following steps: as shown in FIG. 10, through photolithography, etching, and other processes, the first inorganic insulating layer 51 and the second inorganic insulating layer 52 are made.
  • the second via 50 is nested in the first via 72 of the organic resin layer 7, and the bottom of the second via 50 exposes the upper surface of the SD electrode 24.
  • the preparation method of the embodiment of the present application may further include a step of preparing the pixel electrode 6 on the first inorganic insulating layer 51.
  • the aforementioned pixel electrode 6 passes through the first via 32 in the planarization layer 3 (that is, the first via 72 of the organic resin layer 7) and the second through the first inorganic insulating layer 51 and the second inorganic insulating layer 52.
  • the via 50 is electrically connected to the SD electrode 23.
  • the pixel electrode 6 may be a transparent ITO material, and specifically may be a comb-shaped electrode layer.
  • the preparation process of the method for preparing the display substrate may include: as shown in FIG. 4, a gate (Gate) 21, a gate insulating layer (GI) 22, Oxide semiconductor active layer (Active) 23 and metal source and drain electrodes (SD) 24-preparation of second inorganic insulating layer 52-preparation of planarization layer 3 (with trench 31)-preparation of first electrode layer 4 (common electrode) Layer)—preparation of the first inorganic insulating layer 51—preparation of the second electrode layer 6 (pixel electrode layer).
  • a gate Gate
  • GI gate insulating layer
  • Active Oxide semiconductor active layer
  • SD metal source and drain electrodes
  • the method for preparing the display substrate may further include more steps, which may be determined according to actual requirements.
  • the embodiments of the present disclosure do not limit this, and the detailed description and technology For the effect, please refer to the above description of the display substrate and the display panel, which will not be repeated here.
  • the process of'preparing a planarization layer on a thin film transistor' is not limited to the above-mentioned embodiments, and other methods and steps can also be used to prepare trenches.
  • the planarization layer please refer to the description of the planarization layer and the trench structure above for details, which will not be repeated here.

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Abstract

本申请涉及显示技术领域，公开了一种显示基板及其制备方法、显示面板，目的是改善显示基板的结构，提高薄膜晶体管的特性，提高显示产品良率。显示基板包括：衬底基板；薄膜晶体管，位于所述衬底基板上；平坦化层，位于所述薄膜晶体管背离所述衬底基板的一侧，所述平坦化层设有环绕所述薄膜晶体管的沟道区设置的沟槽，所述沟槽在所述衬底基板上的正投影与所述沟道区在所述衬底基板上的正投影没有交叠。

Description

显示基板及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及其制备方法、显示面板。
背景技术
薄膜晶体管(TFT)可用作平板显示器的像素开关元件。薄膜晶体管的有源层可主要由非晶硅或多晶硅形成。非晶硅有源层较容易沉积在大的区域上且容易在低温下加工，但是具有载流子迁移率低的缺点。多晶硅有源层由于载流子迁移率高而具有优异的电特性，但是需要高温加工且可靠性较差。
以氧化物半导体(例如IGZO)作为薄膜晶体管的有源层，可以同时具有非晶硅的能够在低温下加工的优点和多晶硅的高迁移率的优点。然而，氧化物半导体有源层的组分特性很容易受到后续工艺的影响，从而导致TFT性能不良，进而导致显示产品不良。
发明内容
本申请公开了一种显示基板及其制备方法、显示面板，目的是改善显示基板的结构，提高薄膜晶体管的特性，提高显示产品良率。
一种显示基板，包括：
衬底基板；
薄膜晶体管，位于所述衬底基板上；
平坦化层，位于所述薄膜晶体管背离所述衬底基板的一侧，所述平坦化层设有环绕所述薄膜晶体管的沟道区设置的沟槽，所述沟槽在所述衬底基板上的正投影与所述沟道区在所述衬底基板上的正投影没有交叠。
可选的，所述沟槽为包围所述沟道区的环状槽。
可选的，所述沟槽包括围绕所述沟道区且依次间隔设置的多段槽体，所 述多段槽体依次首尾相邻但不相连。
可选的，所述沟槽为深度小于所述平坦化层的厚度的盲槽。
可选的，所述沟槽为贯穿所述平坦化层厚度方向的通槽。
可选的，所述沟槽包括环形主体部和相对于所述环形主体部的侧壁凸出的多个凸出部，所述凸出部在所述衬底基板上的正投影位于所述环形主体部在所述衬底基板上的正投影朝向所述沟道区在所述衬底基板上的正投影的一侧。
可选的，所述薄膜晶体管包括源漏电极，所述平坦化层还包括用于暴露所述源漏电极的第一过孔；
所述沟槽与所述第一过孔连通；所述第一过孔的尺寸大于所述沟槽的宽度。
可选的，所述沟槽的宽度为1μm-3μm。
可选的，所述的显示基板，还包括：
第一电极层，位于所述平坦化层背离所述衬底基板的一侧，所述第一电极层包括位于所述沟槽内的第一部分，所述第一部分覆盖所述沟槽的底部并暴露所述沟槽的侧壁；
第一无机绝缘层，位于所述第一电极层背离所述衬底基板的一侧，所述第一无机绝缘层覆盖所述沟槽的底部和侧壁。
可选的，所述沟槽侧壁的坡度角大于80度。
一种显示面板，包括如上述任一项所述的显示基板，所述沟槽位于所述显示面板的非开口区域。
一种显示基板的制备方法，包括以下步骤：
在衬底基板上制备薄膜晶体管；
在所述薄膜晶体管上制备平坦化层，所述平坦化层设有环绕所述薄膜晶体管的沟道区设置的沟槽，所述沟槽在所述衬底基板上的正投影与所述沟道区在所述衬底基板上的正投影没有交叠。
可选的，在所述薄膜晶体管上制备平坦化层，具体包括：
在所述薄膜晶体管上涂覆有机树脂层；
通过曝光显影工艺在所述有机树脂层中形成包围所述薄膜晶体管的沟道区的环状盲槽，所述盲槽的深度与所述有机树脂层的厚度的比值大于1/2；
通过灰化工艺对所述有机树脂层进行处理，使得所述盲槽成为贯穿所述有机树脂层厚度方向的通槽。
可选的，在衬底基板上制备薄膜晶体管，具体包括：
在衬底基板依次制备有源层和源漏电极；
在所述薄膜晶体管上制备平坦化层，具体包括：
通过曝光显影工艺在所述有机树脂层中形成所述盲槽，同时在所述有机树脂层中形成用于暴露所述源漏电极的第一过孔，所述盲槽的宽度与所述第一过孔的尺寸的比值范围为1/10-1/2。
可选的，通过灰化工艺对所述有机树脂层进行处理，具体包括：
以O2为工作气体，利用等离子体刻蚀设备轰击刻蚀所述有机树脂层，以将所述盲槽底部的有机树脂层残留去除。
可选的，在所述薄膜晶体管上制备平坦化层之后，还包括：
通过磁控溅射的方式在所述平坦化层上制备第一电极层，所述第一电极层包括位于所述沟槽内的第一部分，所述第一部分覆盖所述沟槽的底部并暴露所述沟槽的侧壁。
可选的，通过磁控溅射的方式在所述平坦化层上制备第一电极层之后，还包括：
通过PECVD的方式在所述第一电极层上制备无机绝缘层，所述无机绝缘层覆盖所述沟槽的底部和侧壁。
附图说明
图1为本申请一实施例提供的一种显示基板的部分平面结构示意图；
图2为本申请另一实施例提供的一种显示基板的部分平面结构示意图；
图3为本申请另一实施例提供的一种显示基板的部分平面结构示意图；
图4为图1中的显示基板沿A1-A2方向的部分截面结构示意图；
图5为本申请一实施例的显示基板在形成有机树脂层后的部分截面结构示意图；
图6为本申请一实施例的显示基板在有机树脂层中形成盲槽后的部分截面结构示意图；
图7为本申请一实施例的显示基板在有机树脂层中形成通槽后的部分截面结构示意图；
图8为本申请一实施例的显示基板在形成第一电极层后的部分截面结构示意图；
图9为本申请一实施例的显示基板在形成第二无机绝缘层后的部分截面结构示意图；
图10为本申请一实施例的显示基板在形成贯穿第一无机绝缘层和第二无机绝缘层的第二过孔后的部分截面结构示意图；
图11为本申请一实施例提供的一种显示基板制备方法流程图。
具体实施方式
目前，氧化物半导体薄膜晶体管(例如IGZO TFT)在实际制作过程中，由于受到各种因素的影响，开关电压Vth往往较小，达不到期望值，这样会对氧化物半导体薄膜晶体管的信赖性造成负面影响。其中，影响TFT开关电压Vth的一个重要的因素就是有机绝缘层。
有机绝缘膜层因具有介电常数较小、表面平坦性较好等优点，被广泛应用在高端产品的TFT阵列基板上，有机绝缘膜层一方面可以阻挡外界水汽等侵入，保护TFT背沟道，另一方面，有机绝缘膜层在高温制程中释放的水汽等排放气体(Outgas)也会严重影响IGZO TFT的器件特性，例如，本申请的发明人发现，有机绝缘膜层在自身的高温退火工艺过程中或者在后续的电极层高温退火工艺中都会释放出水汽等还原性气体(Outgas)，这些气体除了向外部释放，也会向下扩散渗透到TFT的有源层沟道中，从而造成TFT的转移 特性曲线整体右偏甚至直接表现为导体化。
鉴于上述问题，本申请实施例公开一种显示基板及其制备方法、显示面板、显示装置，目的是通过改善显示基板的结构，降低有机绝缘膜层在高温制程中释放的气体(Outgas)对IGZO TFT器件特性的影响，进而提高薄膜晶体管的特性，提高显示产品良率。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1至图3为显示基板的一个像素区域的平面示意图，图4为图1沿A-A方向的截面结构示意图。具体的，图1至图3中仅示意性的表示出了部分膜层，例如栅极21、有源层23、源漏电极24、第一电极层4和像素电极6，另外还示意性画出了平坦化层中的沟槽31和第一过孔32、第一电极层4的开口40等结构，但是为了保证图形的清晰效果，图中没有具体示出平坦化层、第一无机绝缘层、第二无机绝缘层等膜层，具体的，图1至图3中所涉及的各膜层及其位置关系具体可以参考图4的截面图。
如图1至图4所示，本申请实施例提供一种显示基板，包括：
衬底基板1；
薄膜晶体管2，位于衬底基板1上；
平坦化层3，位于薄膜晶体管2背离衬底基板1的一侧，平坦化层3设有环绕薄膜晶体管2的沟道区230设置的沟槽31，沟槽31在衬底基板1上的正投影与沟道区230在衬底基板1上的正投影没有交叠。
上述显示基板中，在薄膜晶体管(TFT)2上方设有平坦化层3，该平坦化层3可以阻挡外界水汽等侵入，从而保护TFT 2沟道区230；并且，该平坦化层3设有环绕TFT 2沟道区230设置的沟槽31，后续在该平坦化层3的高温退火工序和/或平坦化层3上方的电极层(例如第一电极层4)的高温退火工序中，平坦化层3释放出水汽等还原性气体(Outgas)，上述沟槽31可以增 加这些气体(Outgas)往外释放的路径，避免Outgas向下扩散到氧化物TFT 2的沟道区230中使TFT 2特性劣化；同时，上述沟槽31的正投影与TFT 2沟道区230的正投影没有交叠，即TFT 2沟道区230的正上方仍然具有完整的有机平坦化膜层覆盖保护，因此沟槽31的设置不会影响平坦化层3对TFT 2沟道区230的保护作用。
综上所述，上述显示基板通过薄膜晶体管(TFT)上方的平坦化层中的沟槽结构，可以降低有机平坦化层在高温制程中释放的气体(Outgas)对TFT器件特性的影响，进而提高TFT器件的特性，提高显示产品良率。
一些实施例中，如图1和图3所示，沟槽31可以为包围沟道区230的环状槽。
示例性的，环状槽具体可以为闭环状的槽，也可以是开环状的槽。
如图1和图4所示，环状的沟槽31可以将平坦化层3划分为覆盖沟道区230的独立部分301和围绕独立部分301的包围部分，并且环状沟槽31将独立部分301和包围部分隔开，这样可以避免包围部分在高温制程中产生的水汽向独立部分301和沟道区230扩散，而独立部分301本身的面积很小，高温制程中产生的水汽很少，且产生的水汽可以通过环状沟槽31向外扩散，因此最终向沟道区230扩散的水汽非常少，几乎不会对沟道区230产生影响。
另一些实施例中，如图2所示，沟槽31可以包括围绕沟道区230且依次间隔设置的多段槽体(如图中的条形槽310)，具体的，所述多段槽体依次首尾相邻但不相连。
上述多段槽体环绕着TFT沟道，槽体的形状不限，具体可以为圆形、椭圆、方形以及条形等。例如，如图2所示，沟槽31包括多段间隔设置的条形槽310，多段条形槽310围绕沟道区依次设置，首尾相邻但不相连，且每段条形槽310围绕着沟道区延伸。
示例性的，沟槽31对沟道区230呈环形包围，具体可以是呈圆环形包围，也可以是呈椭圆环形包围(如图1和图3中所示)或者呈方环形包围(如图2中所示)，对于包围形状在此不做限定。
一些实施例中，沟槽31可以为深度小于平坦化层3的厚度的盲槽，例如图6中所示的盲槽71。
另一些实施例中，沟槽31可以为贯穿平坦化层3厚度方向的通槽，如4图所示。
一些实施例中，如图3所示，沟槽31可以包括环形主体部311和相对于环形主体部311的侧壁凸出的多个凸出部312，凸出部312在衬底基板上的正投影位于环形主体部311在衬底基板上的正投影朝向沟道区230在衬底基板上的正投影的一侧，即凸出部312位于环形主体部311的内侧。
值得注意的是，‘环形主体部311’和‘凸出部312’都是沟槽31的一部分，其本质上都是槽体，‘环形主体部311’为环形槽体，‘凸出部312’为在环形槽体的内侧壁上开设的槽体。
具体的，在环形主体部311上增设凸出部312，可以增加沟槽31的侧壁面积，从而增加平坦化层中Outgas的释放路径，减少Outgas向TFT沟道区的扩散。
一些实施例中，如图1和图4所示，薄膜晶体管2包括源漏电极24，平坦化层3还包括用于暴露源漏电极24的第一过孔32，该第一过孔32可以用于像素电极6与源漏电极24之间的电连接。
示例性的，如图1和图4所示，平坦化层3中的沟槽31与第一过孔32相连通。当然，沟槽31与第一过孔32也可以是独立的两个结构，彼此不连通，例如图2所示。具体采用哪种形式可根据实际需求决定。
示例性的，如图1和图4所示，第一过孔32的尺寸大于沟槽31的宽度。
具体的，第一过孔32一般采用曝光显影工艺制备，由于平坦化层3的厚度较厚，为防止因曝光不充分造成第一过孔32中有平坦化层材料残留，平坦化层3的第一过孔32的尺寸一般较大。示例性的，第一过孔32的尺寸一般大于7μm，例如可以为7μm-10μm。
具体的，为避免沟槽31的设置影响平坦化层3对TFT 2沟道区230的保护作用，沟槽31的尺寸设计较小。示例性的，沟槽31的尺寸可以为1μm-5μm， 进一步的，还可以是1μm-3μm，这样不会影响平坦化层3对TFT 2沟道区230的保护作用。
需要说明的是，本申请中所涉及的过孔或者沟槽、开口等结构的‘尺寸’，是指径向尺寸，其与结构的形状相关。例如，对于圆形的过孔，其‘尺寸’是指圆形的直径；对于方形的过孔，其‘尺寸’是指方形的对角线；圆形或方形的沟槽(或开口)的尺寸与上述同理；对于条形或者环形的沟槽，其‘尺寸’则是指条形或环形的宽度。
一些实施例中，如图1和图4所示，显示基板还包括第一电极层4，第一电极层4位于平坦化层3背离衬底基板1的一侧，包括位于沟槽31内的第一部分41，第一部分41覆盖沟槽31的底部并暴露沟槽31的侧壁，即第一电极层4位于沟槽31内的第一部分41与第一电极层4的其他部分在沟槽31侧壁处断开，这样，平坦化层3中Outgas可以从沟槽31侧壁向外扩散，减少Outgas向TFT 2沟道区230的扩散。
一些实施例中，如图4所示，沟槽31侧壁的坡度角大于80度。由于沟槽31侧壁坡度角较陡，采用磁控溅射成膜方式制备成膜时在沟槽31侧壁处覆盖性较差，因此可以使得第一电极层4处于沟槽31中的第一部分41很容易在沟槽31侧壁处与其余部分断开。
示例性的，本申请实施例提供的显示基板可以为液晶显示面板(LCD)的阵列基板，第一电极层4可以为公共电极层，第一电极层4的材质为透明铟锡氧化物(ITO)。
一些实施例中，如图4所示，显示基板还包括第一无机绝缘层51，该第一无机绝缘层51位于第一电极层4背离衬底基板1的一侧，并覆盖沟槽31的底部和侧壁。
具体的，第一无机绝缘层51可以用作钝化层，可选用隔离水汽能力较强的氮化硅材料，用于保护第一电极层4。
沟槽31的尺寸较小，并且上方还有第一无机绝缘层51覆盖保护，外界水汽不容易通过沟槽31进入到平坦化层3中，因此平坦化层3对TFT 2沟道 区230的保护作用不会受到影响。
一些实施例中，如图4所示，显示基板还包括第二无机绝缘层52，该第二无机绝缘层52位于TFT 2和平坦化层3之间，用于覆盖并保护TFT2。示例性的，第二无机绝缘层52的材质可以为氧化硅，也可以为氧化硅/氮化硅等多层复合而成。
具体的，在第一过孔32中还嵌套有贯穿第一无机绝缘层51和第二无机绝缘层52的第二过孔50。
进一步的，如图1所示，第一电极层4设有用于暴露第一过孔的开口40，该开口40尺寸大于第一过孔32的尺寸。
进一步的，如图1和图4所示，显示基板还包括像素电极6，该像素电极6位于第一无机绝缘层51背离第一电极层4的一侧，且通过第一过孔32和第二过孔50与源漏电极24电连接。示例性的，像素电极6可以为透明ITO材质。
一些实施例中，本申请提供的显示基板中，薄膜晶体管2包括有源层23，有源层23可以采用氧化物半导体，例如氧化铟镓锌(IGZO)，当然，有源层23材料并不限于此，也可以是组分特性容易受Outgas影响的其他材料。
具体的，如图1和图4所示，本申请提供的显示基板中，薄膜晶体管2还包括栅极(Gate)21和栅极绝缘层(GI)22。示例性的，沿远离衬底基板1的方向上，薄膜晶体管2可以包括依次设置的栅极(Gate)21、栅极绝缘层(GI)22、氧化物半导体有源层(Active)23以及金属源漏电极(SD)24。其中，Gate电极材料可以选用Al、Cu、Au、Ag、Ti、Ta等常见的金属材质，为防止SD电极刻蚀液损伤氧化物半导体有源层(例如IGZO)，SD电极可以选用多层复合结构，例如可以为Mo/Cu/Mo、MoNb/Cu/MoNb等等。
需要说明的是，本申请提供的显示基板并不限于用作阵列基板，也可以用作OLED的驱动背板，其中第一电极层也可以为像素电极(阳极)，第一无机绝缘层也可以是像素界定结构等，此处不做限定。
本申请还提供一种显示面板，该显示面板包括上述任一项的显示基板， 具体的，平坦化层中的沟槽位于显示面板的非开口区域。具体的，显示面板的非开口区域即开口区域以外的区域，一般显示面板中通过遮光层限定开口区域，则非开口区域可以认为是被遮光层遮挡且不出光的区域。
具体的，如图1所示，沟槽31环绕TFT的沟道区230设置，位于非开口区域内，且尺寸很小，因此对显示面板的开口率不会造成影响。
示例性的，上述显示面板为LCD，显示基板为阵列基板。
或者，上述显示面板为OLED，显示基板为驱动背板。
本申请还提供一种显示装置，该显示装置包括上述任一项的显示面板。
具体的，上述显示装置可以应用于电视、显示器、平板电脑、智能手机等各种电子设备。
另外，基于本申请提供的显示基板，本申请还提供一种显示基板的制备方法，如图11所示，该方法包括以下步骤：
步骤101，在衬底基板上制备薄膜晶体管；
步骤102，在薄膜晶体管上制备平坦化层，平坦化层设有环绕薄膜晶体管的沟道区设置的沟槽，沟槽在衬底基板上的正投影与沟道区在衬底基板上的正投影没有交叠。
一些实施例中，步骤102，在薄膜晶体管上制备平坦化层，具体可以包括：
步骤201，如图5所示，在薄膜晶体管2上涂覆有机树脂层7；示例性的，有机树脂层7的厚度可以为2μm-5μm；
步骤202，如图6所示，通过曝光显影工艺在有机树脂层7中形成包围薄膜晶体管2的沟道区230的环状盲槽71；示例性的，盲槽71的深度与有机树脂层7的厚度的比值大于1/2，例如，盲槽71的宽度可以为1μm-5μm，进一步的，还可以是1μm-3μm；
步骤203，如图7所示，通过灰化工艺对有机树脂层7进行处理，使得盲槽71成为贯穿有机树脂层7厚度方向的通槽70。
具体的，有机树脂层7为光敏性材料，可以作为光刻胶使用，能够直接 进行曝光、显影、灰化等工艺处理。
一些实施例中，步骤101，在衬底基板上制备薄膜晶体管，具体包括：如图5所示，在衬底基板1依次制备有源层23和源漏电极24。
进一步的，如图5所示，步骤101，在衬底基板1上制备薄膜晶体管2的步骤中，在制备有源层23之前，还包括依次制作栅极(Gate)21和栅极绝缘层(GI)22的步骤。在步骤101和步骤102之间，还可以包括在薄膜晶体管2上制备第二无机绝缘层52的步骤。这些都属于常规工艺流程，此处不再赘述。
进一步的，步骤102，在薄膜晶体管上制备平坦化层，具体可以包括：如图6所示，通过曝光显影工艺在有机树脂层7中形成盲槽71，同时在有机树脂层7中形成用于暴露源漏电极24的第一过孔72；示例性的，盲槽71的宽度与第一过孔72的尺寸的比值范围为1/10-1/2；例如，盲槽71的宽度可以为1μm-5μm，例如盲槽71的宽度还可以为1μm-3μm，第一过孔72的尺寸可以为7μm-10μm。即，通过一次构图工艺在有机树脂层7中同时形成盲槽71和第一过孔72，或者换句话说，在通过构图工艺形成有机树脂层7中的第一过孔72的同时，形成包围TFT 2沟道区230的盲槽71，这样无需增加任何工艺步骤即可以形成盲槽71，可以有效简化制备工艺，节约成本。
具体的，通常情况下，为了使最终形成的平坦化层表面平坦性更好，同时使得第一过孔72中膜层残留能够完全被去除，通常会对有机树脂层7进行灰化处理(Ashing)，灰化处理后再进行电极层的镀膜。本申请中，利用对有机树脂层7的灰化处理工艺，将上述盲槽71中的有机树脂膜层全部刻蚀去除，使得盲槽71成为贯穿有机树脂层7厚度方向的通槽70，如图7所示，这样，可以使得最终形成的沟槽侧壁的面积较大，可以增加有机树脂层7中Outgas的扩散面积和释放路径，从而减少Outgas向TFT 2沟道区230的扩散，减小Outgas对TFT 2沟道区230的影响。另外，通过灰化工艺容易制备形成尺寸较小且侧壁坡度角较大的通槽70结构，进而减小通槽70(即沟槽)对整个有机树脂层7(即平坦化层)的影响，同时使得有机树脂层7上方覆盖的电极层 (如图8中的第一电极层4)容易在通槽70侧壁处断开，保证Outgas能够通过通槽70侧壁向外释放扩散。
当然，也可以不将盲槽中残留的有机树脂材料全部刻蚀去除，即沟槽中也可以具有有机树脂材料的残留，或者换句话说，最终平坦化层中形成的沟槽也可以是盲槽结构，这样也能够实现增加Outgas的释放路径，减少Outgas向TFT沟道区扩散的效果。
具体的，因为上述有机树脂层的厚度较厚，为防止因曝光不充分造成第一过孔中有有机树脂材料残留，第一过孔的尺寸一般较大。示例性的，第一过孔的尺寸大于7μm，例如可以为7μm-10μm。
具体的，为避免通槽的设置影响有机树脂层对TFT沟道区的保护作用，通槽的尺寸设计较小。示例性的，通槽的尺寸可以为1μm-5μm，例如也可以为1μm-3μm，这样不会影响有机树脂层对TFT沟道区的保护作用。
在上述曝光工艺中，如图6所示，由于上述有机树脂层7的厚度较厚，而需要形成的沟槽(盲槽71)的尺寸较小(大致控制在1μm-3μm)，受曝光机精度影响，曝光时底部的有机树脂层7材料不能充分感光，显影后就会造成沟槽31底部有有机树脂材料残留，从而就会制备形成上述深度小于有机树脂层7的厚度的盲槽71。
具体的，步骤102，在薄膜晶体管上制备平坦化层，还可以包括对有机树脂层7进行退火处理的步骤。示例性的，退火条件为空气氛围下，250℃高温处理30min。退火时有机树脂层7中的水汽等还原性Outgas会向外释放，本申请中由于有机树脂层7中设有环绕TFT 2沟道区230的通槽70，可以增加上述Outgas的释放路径，如图7所示，TFT 2沟道区230上方的有机树脂层7内部水汽可以通过通槽70的侧壁向外释放，从而避免Outgas向下扩散对TFT 2沟道区230产生不良影响。
一些实施例中，步骤203，通过灰化工艺对有机树脂层进行处理，具体包括：
以O 2为工作气体，利用等离子体刻蚀设备轰击刻蚀有机树脂层，以将 盲槽底部的有机树脂层残留去除。
如图7所示，通过O 2等离子体进行灰化处理，可以减小对有机树脂层7下方的第二无机绝缘层52造成的损伤，且利用等离子体刻蚀设备，以O 2等离子体刻蚀盲槽底部的残留时，更容易制作出侧壁坡度角较陡的通槽70。示例性的，通槽70侧壁的坡度角可以大于80度。
具体的，采用上述的灰化工艺，不仅可以将盲槽底部的残留完全刻蚀去除，若第一过孔中存在膜层残留也将被完全去除。
具体的，本申请实施例中，沟槽的制备过程无需新增任何工序，制备工艺简单，成本很低。
一些实施例中，步骤102之后，即在薄膜晶体管上制备平坦化层之后，还可以包括以下步骤：
步骤103，如图8所示，通过磁控溅射的方式在平坦化层(即有机树脂层7)上制备第一电极层4，第一电极层4包括位于沟槽(即通槽70)内的第一部分41，第一部分41覆盖沟槽(通槽70)的底部并暴露沟槽(通槽70)的侧壁。
如图8所示，由于通槽70的侧壁坡度较陡，且磁控溅射成膜方式对通槽70侧壁的覆盖性较差，因此通过磁控溅射制备形成的第一电极层4会在通槽70侧壁处断开，从而形成位于通槽70中的第一部分41和处于通槽70外的其余部分。
示例性的，第一电极层4可以为透明ITO材料。具体的，为使第一电极层4结晶缺陷减少，需对上述第一电极层4进行高温退火处理，具体条件可以为：N 2氛围下，230℃高温处理30min。此次退火工艺过程中，有机树脂层7中的水汽等还原性Outgas会向外释放，本申请中由于有机树脂层7中设有环绕TFT 2沟道区230的通槽70，且第一电极层4暴露通槽70的侧壁，如图8所示，有机树脂层7内部还原性Outgas可以通过通槽70的侧壁向外释放，避免Outgas向下扩散对TFT 2沟道区230产生不良影响。
一些实施例中，步骤103之后，即通过磁控溅射的方式在平坦化层上制 备第一电极层之后，还可以包括以下步骤：
步骤104，如图9所示，通过化学气相沉积(PECVD)的方式在第一电极层4上制备第一无机绝缘层51，第一无机绝缘层51覆盖沟槽(即通槽70)的底部和侧壁。
如图9所示，PECVD成膜方式对通槽70侧壁的覆盖性较好，因此通过PECVD方式形成的第一无机绝缘层51位于通槽70中的部分可以将通槽70完全覆盖，从而可以防止外界水汽通过通槽70侵入有机树脂层7中影响TFT 2的沟道区230。
示例性的，第一电极层4可以为公共电极，第一无机绝缘层51用于保护第一电极层4。
具体的，本申请实施例的制备方法中，还可以包括以下步骤：如图10所示，通过光刻、刻蚀等工艺制程，制作出贯穿第一无机绝缘层51与第二无机绝缘层52的第二过孔50，上述第二过孔50嵌套于有机树脂层7的第一过孔72中，且上述第二过孔50的底部暴露出SD电极24的上表面。
进一步地，如图4所示，本申请实施例的制备方法中，还可以包括在第一无机绝缘层51上制备像素电极6的步骤。具体的，上述像素电极6通过平坦化层3中的第一过孔32(即有机树脂层7的第一过孔72)和贯穿第一无机绝缘层51与第二无机绝缘层52的第二过孔50实现与SD电极23电连接。
示例性的，像素电极6可以采用透明ITO材料，具体可以为梳状电极层。
示例性的，本申请实施例提供的显示基板的制备方法制备流程可以包括：如图4所示，在衬底基板1上依次制作栅极(Gate)21、栅极绝缘层(GI)22、氧化物半导体有源层(Active)23以及金属源漏电极(SD)24—制备第二无机绝缘层52—制备平坦化层3(设有沟槽31)—制备第一电极层4(公共电极层)—制备第一无机绝缘层51—制备第二电极层6(像素电极层)。
需要说明的是，本公开的一些实施例中，该显示基板的制备方法还可以包括更多的步骤，这可以根据实际需求而定，本公开的实施例对此不作限制，其详细说明和技术效果可以参考上文中关于显示基板和显示面板的描述，此 处不再赘述。另外，本公开实施例提供的显示基板制备方法中，关于‘在薄膜晶体管上制备平坦化层’的工艺过程并不限于上述实施例，也可以采用其他的方式和步骤制备形成设有沟槽的平坦化层，具体可以参考上文中关于平坦化层和沟槽结构的描述，此处不再赘述。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (17)

  1. 一种显示基板，包括：
    衬底基板；
    薄膜晶体管，位于所述衬底基板上；
    平坦化层，位于所述薄膜晶体管背离所述衬底基板的一侧，所述平坦化层设有环绕所述薄膜晶体管的沟道区设置的沟槽，所述沟槽在所述衬底基板上的正投影与所述沟道区在所述衬底基板上的正投影没有交叠。
  2. 如权利要求1所述的显示基板，其中，所述沟槽为包围所述沟道区的环状槽。
  3. 如权利要求1所述的显示基板，其中，所述沟槽包括围绕所述沟道区且依次间隔设置的多段槽体，所述多段槽体依次首尾相邻但不相连。
  4. 如权利要求1所述的显示基板，其中，所述沟槽为深度小于所述平坦化层的厚度的盲槽。
  5. 如权利要求1所述的显示基板，其中，所述沟槽为贯穿所述平坦化层厚度方向的通槽。
  6. 如权利要求2所述的显示基板，其中，所述沟槽包括环形主体部和相对于所述环形主体部的侧壁凸出的多个凸出部，所述凸出部在所述衬底基板上的正投影位于所述环形主体部在所述衬底基板上的正投影朝向所述沟道区在所述衬底基板上的正投影的一侧。
  7. 如权利要求2所述的显示基板，其中，所述薄膜晶体管包括源漏电极，所述平坦化层还包括用于暴露所述源漏电极的第一过孔；
    所述沟槽与所述第一过孔连通；所述第一过孔的尺寸大于所述沟槽的宽度。
  8. 如权利要求2所述的显示基板，其中，所述沟槽的宽度为1μm-3μm。
  9. 如权利要求1-8任一项所述的显示基板，其中，还包括：
    第一电极层，位于所述平坦化层背离所述衬底基板的一侧，所述第一电 极层包括位于所述沟槽内的第一部分，所述第一部分覆盖所述沟槽的底部并暴露所述沟槽的侧壁；
    第一无机绝缘层，位于所述第一电极层背离所述衬底基板的一侧，所述第一无机绝缘层覆盖所述沟槽的底部和侧壁。
  10. 如权利要求9所述的显示基板，其中，所述沟槽侧壁的坡度角大于80度。
  11. 一种显示面板，包括如权利要求1-10任一项所述的显示基板，所述沟槽位于所述显示面板的非开口区域。
  12. 一种显示基板的制备方法，包括以下步骤：
    在衬底基板上制备薄膜晶体管；
    在所述薄膜晶体管上制备平坦化层，所述平坦化层设有环绕所述薄膜晶体管的沟道区设置的沟槽，所述沟槽在所述衬底基板上的正投影与所述沟道区在所述衬底基板上的正投影没有交叠。
  13. 如权利要求12所述的制备方法，其中，在所述薄膜晶体管上制备平坦化层，具体包括：
    在所述薄膜晶体管上涂覆有机树脂层；
    通过曝光显影工艺在所述有机树脂层中形成包围所述薄膜晶体管的沟道区的环状盲槽，所述盲槽的深度与所述有机树脂层的厚度的比值大于1/2；
    通过灰化工艺对所述有机树脂层进行处理，使得所述盲槽成为贯穿所述有机树脂层厚度方向的通槽。
  14. 如权利要求13所述的制备方法，其中，
    在衬底基板上制备薄膜晶体管，具体包括：
    在衬底基板依次制备有源层和源漏电极；
    在所述薄膜晶体管上制备平坦化层，具体包括：
    通过曝光显影工艺在所述有机树脂层中形成所述盲槽，同时在所述有机树脂层中形成用于暴露所述源漏电极的第一过孔，所述盲槽的宽度与所述第一过孔的尺寸的比值范围为1/10-1/2。
  15. 如权利要求13所述的制备方法，其中，通过灰化工艺对所述有机树脂层进行处理，具体包括：
    以O 2为工作气体，利用等离子体刻蚀设备轰击刻蚀所述有机树脂层，以将所述盲槽底部的有机树脂层残留去除。
  16. 如权利要求12-15任一项所述的制备方法，其中，在所述薄膜晶体管上制备平坦化层之后，还包括：
    通过磁控溅射的方式在所述平坦化层上制备第一电极层，所述第一电极层包括位于所述沟槽内的第一部分，所述第一部分覆盖所述沟槽的底部并暴露所述沟槽的侧壁。
  17. 如权利要求16所述的制备方法，其中，通过磁控溅射的方式在所述平坦化层上制备第一电极层之后，还包括：
    通过PECVD的方式在所述第一电极层上制备无机绝缘层，所述无机绝缘层覆盖所述沟槽的底部和侧壁。
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