WO2021171084A1 - Mécanisme de réduction de trafic de bus et procédés de fonctionnement associés - Google Patents

Mécanisme de réduction de trafic de bus et procédés de fonctionnement associés Download PDF

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Publication number
WO2021171084A1
WO2021171084A1 PCT/IB2020/061923 IB2020061923W WO2021171084A1 WO 2021171084 A1 WO2021171084 A1 WO 2021171084A1 IB 2020061923 W IB2020061923 W IB 2020061923W WO 2021171084 A1 WO2021171084 A1 WO 2021171084A1
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WIPO (PCT)
Prior art keywords
symbol
content
signal processing
processing circuit
symbols
Prior art date
Application number
PCT/IB2020/061923
Other languages
English (en)
Inventor
Geng JIFENG
Yang HONGKUI
Original Assignee
Zeku Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zeku Inc. filed Critical Zeku Inc.
Priority to CN202080097800.3A priority Critical patent/CN115211039B/zh
Publication of WO2021171084A1 publication Critical patent/WO2021171084A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2666—Acquisition of further OFDM parameters, e.g. bandwidth, subcarrier spacing, or guard interval length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2602—Signal structure
    • H04L27/2605—Symbol extensions, e.g. Zero Tail, Unique Word [UW]
    • H04L27/2607—Cyclic extensions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2662—Symbol synchronisation

Definitions

  • This application relates to the communications field, and more specifically, to a wireless communications method and device.
  • Implementations of the present disclosure provide a wireless communications method and device to perform bus-traffic reduction.
  • One or more implementations provide a method for operating a communications device that may include a front-end circuit communicatively coupled to a signal processing circuit. The method may include: receiving a wireless signal at the communications device, wherein the wireless signal includes a content symbol and a corresponding prefix; at the front-end circuit, isolating the content symbol based on removing the corresponding prefix; and communicating the isolated content symbol to the signal processing circuit without the corresponding prefix. Communicating the isolated content symbol may include sending a set of bits that represent the content symbol to the signal processing circuit over a digital connection.
  • the front-end circuit may comprise a Radio Frequency Front-End (RFFE) chip
  • the signal processing circuit may comprise a baseband modem.
  • RFFE Radio Frequency Front-End
  • the method may include down-converting the received wireless signal at the front-end circuit; and generating a baseband bitstream based on sampling the down-converted wireless signal at the front-end circuit, wherein isolating the content symbol may include removing or blocking bits in the bit stream, wherein the removed or blocked bits may correspond to the prefix. Further, the method may further comprise receiving the isolated content symbol at the signal processing circuit; and at the signal processing circuit, implementing a Fourier Transform on the isolated content symbol.
  • the method may further comprise: sending a first message set from the front-end circuit to the signal processing circuit for an initial phase, wherein the first message set may include a first set of content symbols and corresponding prefixes; and transitioning from the initial phase to a subsequent phase based on a feedback message from the signal processing circuit, wherein the feedback message represents one or more timing details associated with the prefixes, wherein isolating the content symbol and communicating the isolated content symbol may comprise the subsequent phase, and the isolated content symbol may comprise a second set of content symbols that follow the first set of content symbols.
  • the method may further comprise: receiving the first message set at the signal processing circuit; at the signal processing circuit, determining the one or more timing details associated with the prefixes based on the first message set; and sending the feedback message to the front-end circuit, wherein the feedback message includes a timing for the symbol boundary, a set of prefix lengths, a current symbol position, a symbol length, or a combination thereof.
  • the method may further comprise receiving from the signal processing circuit information regarding a symbol boundary within the wireless signal, wherein isolating the content symbol includes removing or masking a set of bits that coincide with and/or immediately follow the symbol boundary.
  • the method may further comprise: at the front-end circuit, tracking a current symbol position within a communication data unit encompassing the content symbol; and determining a prefix length based on the current symbol position, wherein removing or masking the set of bits includes removing or masking the set of bits based on the determined prefix length.
  • the method may further comprise: at the front-end circuit, determining a symbol length based on information from the signal processing circuit, wherein the symbol length is representative of a duration associated with the content symbol according to a current communication setting, wherein isolating the content symbol includes retaining a set of bits that correspond to the symbol length.
  • One or more implementations provide a communications device that may include a front- end circuit and a signal processing circuit coupled thereto.
  • the communication device may be configured to implement one or more aspects/features of the method described above or combinations thereof.
  • the front-end circuit may be configured to: receive a wireless signal that includes a set of content symbols and corresponding prefixes; and isolate the set of content symbols based on removing or masking the corresponding prefixes.
  • the signal processing circuit may be configured to: receive the isolated set of content symbols; and recover content data based on the isolated set of content symbols.
  • the front-end circuit and the signal processing circuit may be physically separate and electrically coupled to each other by a digital connection.
  • the front-end circuit may comprise a Radio Frequency Front-End (RFFE) chip
  • the signal processing circuit may comprise a baseband chip.
  • the digital connection may include a feedback path for communicating information from the signal processing circuit back to the front-end circuit.
  • the signal processing circuit may further be configured to determine information regarding symbol boundary, and send the information regarding the symbol boundary to the front-end circuit over the feedback path.
  • the front-end circuit may be configured to remove a set of bits based on the received information regarding the symbol boundary, wherein the removed set of bits correspond to the prefixes associated with the set of content symbols.
  • the front-end circuit may include: a down converter configured to demodulate the received wireless signal to a baseband signal; a sampling circuit coupled to the down converter and configured to sample the baseband signal; and a prefix remover coupled to the sampling circuit and configured to isolate symbol bits in the sampled baseband signal by removing or masking prefix bits, the symbol bits correspond to the set of content symbols and the masking prefix bits correspond to the prefixes in the received wireless signal.
  • the front-end circuit may be configured to: receive the wireless signal that includes an initial set of content symbols and prefixes and a subsequent set of content symbols and prefixes, wherein the subsequent set of content symbols and prefixes includes the isolated set of content symbols; send the initial set of content symbols and prefixes to the signal processing circuit; receive a feedback message from the signal processing circuit, wherein the feedback message is at least partially derived based on the initial set of content symbols; and isolate the set of content symbols within the subsequent set of content symbols and prefixes based on removing or masking prefixes in the subsequent set of content symbols and prefixes.
  • the signal processing circuit may further be configured to: receive an initial set of content symbols and prefixes from the front-end circuit; determine information regarding a symbol boundary based on the received initial set of content symbols and prefixes; and send a feedback message to the front-end circuit for removing subsequent instances of the prefixes at the front- end circuit.
  • the signal processing circuit may further be configured to: remove prefixes in the initial set of content symbols and prefixes; implement a Fourier transform on a remaining set of content symbols from the initial set of content symbols and prefixes after the removal of the prefixes; and directly implement the Fourier transform on a set subsequently received content symbols without implementing a prefix removal process.
  • One or more implementations provide a tangible, non-transitory, computer-readable medium having processor instructions stored thereon that, when executed by one or more processors, cause the one or more processors to perform one or more aspects/features of the method described above or combinations thereof.
  • the stored processor instructions may be configured to implement the method comprising: receiving a wireless signal at the communications device, wherein the wireless signal includes a content symbol and a corresponding prefix; at the front-end circuit, isolating the content symbol based on removing the corresponding prefix; and communicating the isolated content symbol to the signal processing circuit without the corresponding prefix.
  • the method and/or the communication device may include one or more features described herein and/or various combinations thereof.
  • FIG. 1 is an illustration of a wireless communication system in accordance with one or more implementations of the present disclosure.
  • FIG. 2 is a block diagram of a mobile communication device in accordance with one or more implementations of the present disclosure.
  • FIG. 3 is a detailed block diagram of a downlink processing circuitry in accordance with one or more implementations of the present disclosure.
  • FIG. 4A is an illustration of a first example message in accordance with one or more implementations of the present disclosure.
  • FIG. 4B is an illustration of a second example message in accordance with one or more implementations of the present disclosure.
  • FIG. 4C is an illustration of data streams before and after processing in accordance with one or more implementations of the present disclosure.
  • FIG. 4D is a table illustrating example message configurations in accordance with one or more implementations of the present disclosure.
  • FIG. 5 is a flowchart of an example method in accordance with one or more implementations of the present disclosure.
  • FIG. 6 is a schematic block diagram of a terminal device in accordance with one or more implementations of the present disclosure.
  • FIG. 7 is a schematic block diagram of a system chip in accordance with one or more implementations of the present disclosure.
  • FIG. 8 is a schematic block diagram of a communications device in accordance with one or more implementations of the present disclosure.
  • a communications system includes interface circuitry configured to reduce the amount of data communicated between adjacent circuits, such as between a radio-frequency (RF) circuit (e.g., an RF chip) and a data processing circuitry (e.g., a baseband chip).
  • RF radio-frequency
  • a data processing circuitry e.g., a baseband chip
  • Some wireless communication protocols require each communicated symbol to be preceded by a Cyclic Prefix (CP).
  • the CP can provide a guard interval to eliminate inter-symbol interference caused by a preceding transmission/symbol.
  • the CP can function as a buffer region to protect subsequently following payload or data symbol.
  • the content of the CP can be a repetition of an end portion of the symbol.
  • the communicated message e.g., the content symbol and the CP
  • some wireless communication protocols can require different lengths for the CP according to a position/sequence ordinal of the symbol within a corresponding/encompassing communication unit (e.g., a subframe).
  • the CP is removed from the communicated or received data.
  • the received RF signal e.g., a combination of the CP and the payload symbol
  • a front-end circuitry e.g., the RF chip
  • a processing circuitry e.g., a baseband modem/chip.
  • the processing circuitry removes the CP or one or more portions thereof and processes the payload portion, such as by transforming the time-domain signals of the remaining symbol into a frequency domain signal (via, e.g., Fast Fourier Transform (FFT)).
  • FFT Fast Fourier Transform
  • One or more implementations of the present disclosure can include circuitry and/or processes to remove the CP at the front-end circuitry, thereby removing or not including the CP in the digital signal.
  • the communication system can provide reduced power consumption associated with the digital communication between the front-end circuitry and the processing circuitry.
  • the amount of removed data and the reduced power consumption can correspond to a length or size of the CP, which can account for up to 25% overhead. Given the large number of symbols communicated during a communication session (e.g., streaming applications and/or voice-calls), the removed data can provide significant power savings.
  • the front-end circuitry and the processing circuitry can operate according to and transition between two or more phases. For example, for an initial phase, the front-end circuitry can implement the down-conversion and sampling to generate a first set of messages that includes one or more instances of the CPs with the corresponding payload symbols.
  • the processing circuitry can receive and process the first set of messages to identify at least one symbol boundary (e.g., a separation between adjacent sets of CP-payload symbol combinations).
  • the processing circuitry can communicate information about the symbol boundary to the front-end circuitry as feedback during a transition between the phases (e.g., a handshake process between the front-end and processing circuits).
  • the front-end circuitry can use the symbol boundary to identify ends of each symbol segments in the time-domain signal.
  • the front- end circuitry can access a set of registers to identify an appropriate CP length, a symbol length, and/or a symbol position within a communicated unit (e.g., a subframe).
  • the processing circuitry can provide the CP lengths, the symbol length, and/or the symbol position to the front-end circuitry during the transition.
  • the front-end circuitry can use the symbol position to access an appropriate CP length (e.g., a long CP length for a first and/or a middle symbol or a normal CP length for other symbols).
  • the front-end circuitry can use the accessed CP length to remove or mask the corresponding CP portion within the sampled signal.
  • the front-end circuitry can update and track the symbol position as the corresponding symbols (e.g., without the corresponding CP) are communicated to the processing circuitry.
  • Removing the CP at the front-end circuitry instead of the processing circuitry provides reduction in the amount of data communicated to the processing circuitry.
  • Communication devices can include digital connections/buses between the front-end circuitry and the processing circuitry. As data rates and bandwidths increase for wireless communications, the data rate/amount for internal digital communication between the front-end circuitry and the processing circuitry also increases. By removing the CP at the front-end circuitry, the communication device can reduce the amount of internally communicated data without additional buffers. In some implementations, the front-end circuitry can adjust the bit rate for internally communicated data, such as by expanding the isolated bits to fill the duration opened by removing the CP.
  • the communication device can reduce the current/power consumed to communicate the CP. Further, by removing the CP at the front-end circuitry, the communication device can increase the throughput of the internal interface (by, e.g., up to 25%).
  • boundary information from the processing device to identify the CP locations in the digital stream, and tracking the symbol/CP length(s) and current symbol position provides relatively simple and fast mechanism/circuitry (e.g., a set or registers, removing/masking circuit, a counter, etc.) for implementing the CP removal at the front-end circuitry.
  • Instructions for executing computer- or processor-executable tasks can be stored in or on any suitable computer-readable medium, including hardware, firmware, or a combination of hardware and firmware. Instructions can be contained in any suitable memory device, including, for example, a flash drive and/or other suitable medium.
  • Coupled can be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular implementations, “connected” can be used to indicate that two or more elements are in direct contact with each other. Unless otherwise made apparent in the context, the term “coupled” can be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) contact with each other, or that the two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship, such as for signal transmission/reception or for function calls), or both.
  • FIG. 1 is an illustration of a wireless communication system in accordance with one or more implementations of the present disclosure.
  • the wireless communications system 100 can include a network device 110.
  • the network device 110 can include circuitry configured to provide communication coverage for a specific geographic area.
  • Some examples of the network device 110 can include: a base transceiver station (Base Transceiver Station, BTS), a NodeB (NodeB, NB), an evolved Node B (eNB or eNodeB), a Next Generation NodeB (gNB or gNode B), a Wireless Fidelity (Wi-Fi) access point (AP).
  • BTS Base Transceiver Station
  • NodeB NodeB
  • eNB or eNodeB evolved Node B
  • gNB or gNode B Next Generation NodeB
  • Wi-Fi Wireless Fidelity
  • the network device 110 can include a relay station, an access point, an in-vehicle device, a wearable device, and the like.
  • the network device 110 can include other wireless connection devices for communication networks such as: a Global System for Mobile Communications (GSM) network, a Code Division Multiple Access (CDMA) network, a Wideband CDMA (WCDMA) network, an LTE network, a cloud radio access network (Cloud Radio Access Network, CRAN), an Institute of Electrical and Electronics Engineers (IEEE) 802.11-based network (e.g., a Wi-Fi network), an Internet of Things (IoT) network, a device-to- device (D2D) network, a next-generation network (e.g., a 5G network), a future evolved public land mobile network (Public Land Mobile Network, PLMN), or the like.
  • a 5G system or network may be further referred to as a new radio (New Radio, NR) system or network.
  • the wireless communications system 100 can include a terminal device 120.
  • the terminal device 120 can be an end-user device configured to facilitate wireless communication.
  • the terminal device 120 can be configured to wirelessly connect to the network device 110 (via, e.g., a wireless channel 115) according to one or more corresponding communication protocols/standards.
  • the terminal device 120 may be mobile or fixed.
  • the terminal device 120 can be an access terminal, a UE, a user unit, a user station, a mobile site, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communications device, a user agent, or a user apparatus.
  • the terminal device 120 can include: a cellular phone, a smart phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device having a wireless communication function, a computing device or another processing device connected to a wireless modem, an in-vehicle device, a wearable device, an IoT device, a terminal device in a future 5G network, a terminal device in a future evolved PLMN, or the like.
  • SIP Session Initiation Protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • FIG. 1 illustrates the wireless communications system 100 via the network device 110 and the terminal device 120.
  • the wireless communications system 100 can include additional/other devices, such as additional instances of the network device 110 and/or the terminal device 120, a network controller, a mobility management entity, etc.
  • FIG. 2 is a block diagram of a mobile communication device 200 (e.g., the terminal device 120 of FIG. 1, the network device 110 of FIG. 1, and/or a portion therein) in accordance with one or more implementations of the present disclosure.
  • the mobile communication device 200 can include circuitry configured to communicate wireless signals with another device.
  • the terminal device 120 e.g., a UE
  • the mobile communication device 200 can include the mobile communication device 200 configured to exchange wireless signals with the network device 110 and/or other wirelessly coupled devices.
  • the mobile communication device 200 can include an antenna group 212 that includes a set of transmission and/or receiver antennas.
  • the antenna group 212 can be configured to utilize one or multiple antennas to exchange wireless signals with a corresponding device.
  • the antenna group 212 can be coupled to a filter bank 214 that includes a set of frequency-based filters.
  • the filter bank 214 can include a set of band-pass filters configured to isolate a specific frequency range utilized or targeted by the technology, standard, and/or context associated with the communication session.
  • the mobile communication device 200 can include a front-end circuit 202, such as a transceiver (e.g., an RF Front-End (RFFE) chip) configured to process various components of wireless signals.
  • the front-end circuit 202 can include an uplink module 222 (e.g., circuitry and/or function(s)) configured to synthesize and mix the I/Q data from the baseband into RF signal for transmission.
  • the front-end circuit 202 can include a downlink module 224 (e.g., circuitry and/or function(s)) configured to down-convert the incoming/received signal to complex representations (e.g., I/Q data).
  • the I/Q data can be processed/trimmed and then forwarded to a processing circuit (e.g., a baseband chip) for further processing.
  • the front-end circuit 202 can communicate baseband data (e.g., formatted content data prior to/after being modulated to one or more carrier frequencies) with a signal processing circuitry 204 using an internal connection 210.
  • the internal connection 210 can include a data connection/bus.
  • the internal connection 210 can be configured to communicate digital signals.
  • the downlink module 224 can send to the signal process circuitry 204 a sampled digital stream of the down-converted form of the wireless signals.
  • the portion of the internal connection 210 configured for the downlink signal processing can include a feedback path for communicating information from the signal processing circuit 204 back to the front-end circuit 202.
  • the signal processing circuitry 204 can send the digital baseband data to the uplink module 222 for up-conversion and digital-to-analog (D/A) conversion for wireless transmission.
  • the signal processing circuitry 204 can be implemented as a physically separate circuit (e.g., separate semiconductor chips).
  • the signal processing circuitry 204 can be configured to process/analyze baseband data with respect to the communicated/intended content.
  • the signal processing circuitry 204 can analyze and remove from the received wireless signal aspects/effects of the wireless channel 115 of FIG. 1 (e.g., inter-symbol interference, inter-carrier interference, inter-device interference, Doppler effect, multipath interference, fading, etc.) and/or device-internal noise to recover transmitted data.
  • the received wireless signal can be represented as:
  • the received wireless signal can be represented as ⁇ ', and the originally transmitted wireless signal can be represented as 'X'.
  • the noise introduced into the received wireless signal can be represented as 'N'.
  • the wireless channel 115 or the effect thereof on the transmitted signal can be represented as ⁇ .
  • the signal processing circuitry 204 can be configured to recover 'X' from ⁇ '.
  • the signal processing circuitry 204 can further include circuitry and/or functions configured to reverse the transmission processing, such as constellation mapping, interleaving, encoding, etc., to recover the intended content.
  • the signal processing circuitry 204 can implement the transmission formatting on the content data intended for transmission.
  • FIG. 3 is a detailed block diagram of a downlink processing circuitry (e.g., corresponding portion(s) of the front-end circuitry 202 of FIG. 2, such as the downlink module 224, and/or the signal processing circuitry 204 of FIG. 2) in accordance with one or more implementations of the present disclosure.
  • the downlink module 224 can include a downconverter 302 and a sampling circuit 304.
  • the downconverter 302 can be configured to demodulate the received wireless signal from carrier frequencies to baseband.
  • the sampling circuit 304 e.g., an analog-to-digital (A/D) converter
  • A/D analog-to-digital
  • the wireless communications system 100 of FIG. 1 can generate transmission messages according to a transmission scheme (e.g., Orthogonal Frequency Division Multiplexing (OFDM) scheme).
  • a transmission scheme e.g., Orthogonal Frequency Division Multiplexing (OFDM) scheme
  • the transceiver 216 can map the sequence of transmission bits to corresponding symbols of an OFDM symbol alphabet. The mapped symbols can be used to generate and transmit the wireless signal ('X') representative of the sequence of transmission bits.
  • the wireless communication system 100 can include a CP before or between each symbol.
  • Some wireless communication protocols require each communicated symbol to be preceded by a CP.
  • the CP can include a duplicate of an end portion of the symbol, which can be leveraged to reduce or eliminate inter- symbol interference and/or to enable linear processing (by, e.g., using circular convolution functions).
  • the downlink module 224 can generate the time-domain digital signal that, at least initially, includes digital representations of the symbols and the corresponding CPs.
  • the combination of the down converter 302 and the sampling circuit 304 can generate the time- domain digital signal that includes both the symbols and the CPs, which can be communicated to the signal processing circuitry 204 as a first message set 362 during an initial phase, such as for a first set of symbols communicated during a newly established communication session or following a rate adjustment or a synchronization adjustment.
  • the signal processing circuitry 204 can process the first message set 362 using circuits configured to (1) process the content of the first message set 362 and (2) coordinate removal of the CPs for subsequent messages.
  • the signal processing circuitry 204 can include a baseband (BB) boundary identifier 352 configured to identify the temporal boundaries between adjacent symbols.
  • the BB boundary identifier 352 can identify the timing when the CP preceding the corresponding symbol starts and/or when the prior/preceding symbol ends.
  • the BB boundary identifier 352 can identify the boundaries based on detecting synchronization signals (e.g., primary synchronization signal (PSS) and/or secondary synchronization signal (SSS)) in the first message set 362.
  • PSS primary synchronization signal
  • SSS secondary synchronization signal
  • the BB boundary identifier 352 can use a signal/pattem detection circuitry and/or function, such as a match filter.
  • the signal processing circuitry 204 can locally include a BB-CP remover 354 configured to remove the CPs from the first message set 362. Accordingly, the BB-CP remover 354 can isolate the symbols for subsequent processing by a downstream module 358.
  • the downstream module 358 can reverse the transmission formatting, such as by interleaving, decoding, etc., and recover the content data initially targeted by the transmitting device.
  • the signal processing circuitry 204 can also include a BB management module 356 configured to implement a transition from the initial phase where the signal processing circuitry 204 removes the CP to the subsequent phase where the front-end circuitry 202 removes the CP.
  • the BB management module 356 can include circuitry and/or functions configured to implement a handshake protocol with the front-end circuitry 202 for implementing the phase transition.
  • the BB management module 356 can provide over a feedback path 360 a feedback message 364 that includes the boundary information (e.g., a starting time and a frequency/rate) and/or a boundary signal (e.g., a clock/strobe signal) to the downlink module 224.
  • the BB management module 356 can include contextual/progress information for the communication in the feedback message 364.
  • the BB management module 356 can use the feedback message 364 to provide a sequence or a position of the currently processed symbol within an encompassing communication unit (e.g., a subframe) to the downlink module 224.
  • the BB management module 356 may further use the feedback message 364 to provide CP lengths and/or symbol length (e.g., a duration and/or a number of samples) according to the communication rate/setting of the session.
  • the downlink module 224 can include circuitry and/or functions configured to remove the CP during a subsequent phase.
  • the downlink module 224 can include an RF-boundary identifier 312.
  • the RF-boundary identifier 312 can include circuitry and/or functions configured to identify a symbol boundary 332 at the downlink module 224 based on the feedback message 364.
  • the RF-boundary identifier 312 can include a strobe circuit configured to generate an internal strobe signal according to the boundary information (e.g., a starting time and a frequency/rate).
  • the RF- boundary identifier 312 can include an interface circuit configured to receive the strobe signal in the feedback message 364 as the symbol boundary 332.
  • the downlink module 224 can include a tracking circuit 314, which can include circuitry and/or functions configured to access contextual information for removing the CP.
  • the downlink module 224 can include a set of registers configured to store one or more CP length data (e.g., a first length 334 and/or a second length 336), a symbol length 338, a symbol position 340, or a combination thereof.
  • the registers can be programmed by the signal processing circuitry 204 during the phase transition.
  • the registers can be preloaded with predetermined values, and the tracking circuit 314 can access the appropriate register according to a selection data in the feedback message 364 (e.g., a representation of session settings, such as data rate).
  • the symbol counter 316 can set the symbol position 340 based on the feedback message 364 during the phase transition. Accordingly, the symbol counter 316 can use the symbol boundary 332 for the subsequent portion(s) of the message to update/increment the symbol position 340.
  • the tracking circuit 314 can use the real-time tracked symbol position 340 to selectively access the appropriate CP length. For example, the tracking circuit 314 can access the first length 334 (e.g., representative of longer CPs) when the symbol position 340 corresponds to one or more predetermined positions (e.g., first and/or middle position) within the communication unit (e.g., the subframe). Also, the tracking circuit 314 can access the second length 336 when the symbol position 340 corresponds to other positions. The tracking circuit 314 can further access the symbol length 338 that corresponds to the communication setting.
  • the first length 334 e.g., representative of longer CPs
  • predetermined positions e.g., first and/or middle position
  • the tracking circuit 314 can access the second
  • the downlink module 224 can include an RF-CP remover 318 configured to remove the CP from the digitized signal at the front-end circuitry 202.
  • the RF-CP remover 318 can use the accessed/tracked values, such as the CP length and/or the symbol length 338, to identify the bits within the digitized signal that correspond to the CP.
  • the RF-CP remover 318 can remove or mask the identified bits that correspond to the CP (e.g., the overhead portion).
  • the RF-CP remover 318 can additionally or alternatively remove a portion within the symbol that has been repeated in the CP. Accordingly, the RF-CP remover 318 can isolate the bits that correspond to the symbols (e.g., the payload/content portion).
  • the downlink module 224 (via, e.g., the RF-CP remover 318) can update the timing, spacing, and/or arrangement of the remaining bits.
  • the downlink module 224 can combine or multiplex the isolated symbol bits to increase overall data throughput.
  • the downlink module 224 can spread the isolated symbol bits out over time, such as between the symbol boundary 332 and across the duration/timing corresponding to the removed CP.
  • the downlink module 224 can include an RF management module 320 configured to oversee and implement the phase operations and transition between the phases.
  • the RF management module 320 can interact with the BB management module 356 to oversee and implement the phase operations/transition.
  • the RF management module 320 can receive the feedback message 364 and initiate the transition between the phases.
  • the RF management module 320 can load the incoming values, such as the symbol boundary information, the symbol length 338, the CP lengths, and/or the symbol position 340, to corresponding registers.
  • the RF management module 320 can further activate the RF-boundary identifier 312, the tracking circuit 314, and/or the RF-CP remover 318 to remove the CPs.
  • the RF management module 320 can track and control a phase status 342. For example, the RF management module 320 can set the phase status 342 to represent the initial phase at the beginning of the communication session. The RF management module 320 can update the phase status 342 based on the transition/handshake process to represent a subsequent phase. In some implementations, the RF management module 320 can update the phase status 342 based on first receiving the feedback message 364, receiving a predetermined feedback content, and/or a predetermined period following a targeted content in the feedback message 364. Accordingly, the downlink module 224 can transition from outputting the first message set 362 to a second message set 366 that includes the isolated symbol bits without the CP bits.
  • FIG. 4A is an illustration of a first example message (e.g., a message/symbol unit in the first message set 362) in accordance with one or more implementations of the present disclosure.
  • the first message set 362 can include a CP 402 and a content 404.
  • the CP 402 can precede the corresponding content 404, which can include a symbol portion 412 and/or a repeated CP portion 414.
  • FIG. 4B is an illustration of a second example message (e.g., a message/symbol unit in the second message set 366) in accordance with one or more implementations of the present disclosure.
  • the front-end circuitry 202 can remove the CP 402 from the incoming/received message.
  • the second message set 366 can isolate the symbol portion 412 (e.g., a set of bits that correspond to the content/OFDM symbol) and remove the CP 402 and/or the repeated CP portion 414.
  • FIG. 4C is an illustration of data streams before and after processing in accordance with one or more implementations of the present disclosure.
  • the down converter 302 of FIG. 3 and/or the sampling circuit 304 of FIG. 3 can generate a first data stream 422 that includes a time-domain bit stream that represent the transmitted baseband message.
  • the first data stream can correspond to sequentially communicated instances of the first message set 362 of FIG. 3.
  • the first data stream 422 can include the CP 402 and the content 404 for each of the first message set 362.
  • the downlink module 224 of FIG. 2 can communicate the first data stream 422 to the signal processing circuitry 204 of FIG. 2 until the symbol boundary 332 is identified and the CP 402 is removed at the downlink module 224.
  • the downlink module 224 can remove the CP 402 and/or the repeated CP portion 414 at the downlink module 224. Accordingly, the downlink module 224 can communicate a second data stream 424 that includes a time-domain bit stream that represents the isolated content portion within the transmitted baseband message.
  • the second data stream 424 can include sequentially communicated instances of the symbol 412 of FIG. 4A.
  • the second data stream 424 can be processed according to the symbol boundary 332. Accordingly, the second data stream 424 can be temporally aligned with the symbol boundary 332.
  • FIG. 4D is a table 450 illustrating example message configurations (e.g., CP configurations) in accordance with one or more implementations of the present disclosure.
  • the table 450 can illustrate example configurations corresponding to different CP lengths and/or different subscriber spacing (SCS) associated with wireless communication protocols.
  • SCS subscriber spacing
  • each row of the table 450 can represent a unique combination of values/settings for a channel bandwidth, a SCS, a frequency band (FR), a normal CP length, and/or a long CP length.
  • the table 450 further illustrates an amount of resources (e.g., a percentage of the FFT size) required to process the corresponding CP lengths.
  • the resources required to process the CP can correspond to 7% to 25% of the overall resources. Accordingly, by removing the CP 402 at the downlink module 224, the signal processing circuitry 200 of FIG. 2 can reduce processing resources/overheads by corresponding amounts.
  • FIG. 5 is a flowchart of an example method 500 in accordance with one or more implementations of the present disclosure.
  • the method 500 can be for implementing the bus- traffic reduction mechanism.
  • the method 500 can be for operating the terminal device 120 of FIG. 1, the network device 110 of FIG. 1, the front-end circuitry 202 of FIG. 2, the signal processing circuitry 204 of FIG. 2, one or more portions thereof, or a combination thereof.
  • the front-end circuitry 202 can receive the wireless signal.
  • the antenna group 212 can receive the wireless signal ( ⁇ ') that corresponds to a signal ('X') transmitted by a counterpart device.
  • the received wireless signal can correspond to a wireless communication session (e.g., an initial portion thereof) between the transmitting device and the receiving device.
  • the front-end circuitry 202 can receive the wireless signal that includes a set of content symbols and a set of corresponding prefixes.
  • the front-end circuitry 202 can receive the set of content symbols and prefixes corresponding to an initial portion of the communication session.
  • the front-end circuitry 202 can convert the initially received wireless signal or portions thereof into baseband format.
  • the down converter 302 of FIG. 3 can down- convert the received wireless signal, such as by demodulating the wireless signal according to one or more predetermined signals/frequencies.
  • the sampling circuit 304 of FIG. 3 can sample the down-converted result of the wireless signal according to a predetermined sampling rate.
  • the downlink module 224 can generate a baseband bitstream (e.g., a time- domain bitstream) that corresponds to the down-converted and sampled result of the wireless signal.
  • the front-end circuitry 202 can communicate the first message set 362 of FIG. 3 (e.g., the converted baseband signal) to the signal processing circuitry 204.
  • the front-end circuitry 202 can send to the signal processing circuit 204 the first message set 362 resulting from the conversion.
  • the first message set 362 can correspond to an initial phase of the operation and/or the communication session.
  • the signal processing circuitry 204 can identify boundaries associated with each symbol within the baseband signal.
  • the signal processing circuitry 204 can receive the first message set 362 from the front-end circuitry 202.
  • the signal processing circuitry 204 can determine one or more timing details associated with the CP 402 of FIG. 4 within the first message set 362.
  • the BB boundary identifier 352 of FIG. 3 can determine the timing information based on detecting synchronization signals (via, e.g., a signal/pattern detection circuitry/function, such as a match filter) as described above.
  • the signal processing circuitry 204 can process the received baseband signal.
  • the signal processing circuitry 204 can process the first message set 362 to recover the content data (e.g., the transmitted signal 'X' and/or the initial content data).
  • the BB-CP remover 354 of FIG. 3 can remove the CP 402 from the first message set 362 to isolate the content portion 404 and/or the payload symbol 412).
  • the downstream module 358 of FIG. 3 can implement a Fourier Transform (e.g., FFT) on the isolated result (e.g., the content portion 404 and/or the payload symbol 412).
  • FFT Fourier Transform
  • the communication device e.g., the terminal device 120
  • can transition across phases e.g., from an initial phase to a subsequent phase.
  • the front-end circuitry 202 and the signal processing circuitry 204 can interact with each other to implement the transition (e.g., a handshake process).
  • the signal processing circuit 204 can send the feedback message 364 of FIG. 3 that represents one or more timing details associated with the CP 402 (e.g., a timing for the symbol boundaries, a set of prefix lengths, a current symbol position, a symbol length, or a combination thereof) to the front-end circuitry 202 as described above.
  • the front-end circuitry 202 can receive the information regarding the symbol boundaries and transition from the initial phase to the subsequent phase based on the feedback message 364.
  • the front-end circuitry 202 can remove the CP 402 from the received wireless signal for the subsequent phase.
  • the signal processing circuit 404 also transition to the subsequent phase and directly process the subsequently received signals (e.g., without removing the CP 402 at the signal processing circuit 404).
  • the communication device can set the initial states associated with the phase- based operations.
  • the front-end circuitry 202 can configure or set the tracking circuit 314 of FIG. 3 to store the first length 334 of FIG. 3, the second length 336 of FIG. 3, the symbol length 338 of FIG. 3, the current symbol position 340 of FIG. 3, or a combination thereof.
  • the front-end circuitry 202 can locally determine the symbol boundary 332 of FIG. 3 as described above.
  • the front-end circuitry 202 can convert subsequently received wireless signals or portions thereof.
  • the front-end circuitry 202 can receive the wireless signal as described above at block 502.
  • the front-end circuitry 202 can continue to convert the wireless signal received subsequent to the transition as described above at block 504.
  • the front-end circuitry 202 can down-convert the subsequently received symbols and CP to baseband.
  • the front-end circuitry 202 can sample the down-converted signal to generate a baseband bitstream (e.g., a time-domain bitstream).
  • the front-end circuitry 202 can identify the symbol boundaries for the baseband bitstream.
  • the front-end circuitry 202 can identify the symbol boundaries, such as based on a strobe or a timing signal corresponding to the symbol boundary 332. Accordingly, the front-end circuitry 202 can identify separations in the baseband bitstream for determining the different symbol-CP groupings within the wireless signal. In other words, the front-end circuitry 202 can identify bit groupings that each represent a set of the content portion 404 and the CP 402.
  • the front-end circuitry 202 can determine whether the currently processed symbol corresponds to a long CP.
  • the tracking circuit 314 can determine and track the symbol position 340.
  • the tracking circuit 314 and/or the RF-CP remover 318 of FIG. 3 can access the appropriate CP length according to the current symbol position 340.
  • the tracking circuit 314 can access the first length 334 when the current symbol position 340 indicates one or more predetermined positions (e.g., first symbol position and/or middle symbol position within each subframe) as illustrated at block 520.
  • the tracking circuit 314 can access the second length 336 for other positions as illustrated at block 522.
  • the front-end circuitry 202 can remove the CP 402 from the subsequently received wireless signal.
  • the RF-CP remover 318 and/or the tracking circuit 314 can determine the symbol length 338, such as by accessing the corresponding register.
  • the RF-CP remover 318 can remove the CP 402 based on the CP length and/or the symbol length 338.
  • the RF-CP remover 318 can remove or mask the bits starting with and lasting through the selected one of the first length 334 or the second length 336.
  • the RF-CP remover 318 can also retain and isolate the bits starting at or after the end of the CP length and lasting through the symbol length 338, such as the bits that make up or represent the CP 402. Accordingly, the RF-CP remover 318 can isolate bits that make up or represent the content portion 404 and/or the payload symbol 412.
  • the front-end circuitry 202 can communicate the second message set 366 of FIG. 3 (e.g., the content portion 404 of FIG. 4 and/or the payload symbol 412 of FIG. 4 isolated after removing the CP 402).
  • the front-end circuitry 202 can generate the second message set 366 based on isolating the content portion 404 and/or the payload symbol 412 from within the baseband digital bitstream.
  • the front-end circuitry 202 can send the second message set 366 (e.g., a set of bits that represent the isolated content symbols without the corresponding CPs 402) to the signal processing circuitry 404.
  • the front-end circuitry 202 can send the signal processing circuitry 404 over the digital bus (e.g., the internal bus 210 of FIG. 2).
  • the signal processing circuitry 204 can process the second message set 336.
  • the signal processing circuitry 204 can receive the second message set 336 (e.g., the isolated content symbol).
  • the signal processing circuitry 204 can process the second message set 336 as described above at block 554.
  • the signal processing circuitry 204 can recover the content data, such as based on implementing the Fourier Transform, based on the isolated set of content symbols.
  • the front-end circuitry 202 can update the symbol position (the current symbol position 340).
  • the symbol counter 316 can track the current symbol position 340 within a communication data unit (e.g., the subframe) encompassing the content symbol processed and sent to the signal processing circuitry 204.
  • the symbol counter 316 can track the current symbol position 340 based on incrementing the current symbol position 340 as each symbol is processed and communicated to the signal processing circuitry 204.
  • the signal processing circuitry 204 can determine whether processed message includes flags or triggers to adjust the timing associated with the wireless communication signal. When the content does not indicate the timing adjustment flags or triggers, the signal processing circuitry 204 can continue to process the incoming signal as illustrated by a feedback loop to block 556. Also, the signal processing circuitry 204 can process the incoming signals without sending any adjustment indication to the front-end circuitry 202. Accordingly, at decision block 530, the front-end circuitry 202 can determine that no timing adjustment feedback has been received from the signal processing circuitry 204. Thus, as represented by a feedback loop to block 514, the front-end circuitry 202 can continue to convert the received wireless signal, remove the CP 402, and send the isolated symbols or content portions to the signal processing circuitry 200.
  • the signal processing circuitry 204 can notify the front-end circuitry 202 of the timing adjustment as illustrated at block 560. Accordingly, at decision block 530, the front-end circuitry 202 can determine that the timing adjustment feedback has been received. In response to the determination, the front-end circuitry 202 can implement the transition between the phases to implement the new communication rate. Also, following the notification, the signal processing circuitry 204 can further identify new symbol boundaries according to the timing adjustment as illustrated by a feedback loop to block 552. Based on the updated instance of the boundaries, the front-end circuitry 202 and the signal processing circuitry 204 can implement the transition between phases as described above to implement the adjusted timing for subsequently arriving signals.
  • FIGS. 6-8 illustrate example devices and systems that include or incorporate the variable- complexity detector (e.g., the front-end circuitry 202 of FIG. 2 and/or the signal processing circuitry 204 of FIG. 2).
  • the variable- complexity detector e.g., the front-end circuitry 202 of FIG. 2 and/or the signal processing circuitry 204 of FIG. 2.
  • FIG. 6 is a schematic block diagram of a terminal device 600 (e.g., an instance of the terminal device 120 of FIG. 1) in accordance with one or more implementations of the present disclosure.
  • the terminal device 600 includes a processing unit 610 (e.g., a DSP, a CPU, a GPU, etc., functioning as the front-end circuitry 202, the signal processing circuitry 204, and/or a portion therein) and a memory 620.
  • the processing unit 610 can be configured to implement instructions that correspond to the method 500 of FIG. 5 and/or other aspects of the implementations described above.
  • FIG. 7 is a schematic block diagram of a system chip 700 (e.g., a component within the terminal device 120 of FIG. 1 and/or the network device 110 of FIG. 1) in accordance with one or more implementations of the present disclosure.
  • the system chip 700 in FIG. 7 includes an input interface 701, an output interface 702, a processor 703, and a memory 704 (e.g., a non- transitory, computer-readable medium) that may be connected through an internal communication connection line, where the processor 703 is configured to execute code in the memory 704.
  • the memory 704 can include code that corresponds to the method 500 of FIG. 5 and/or other aspects of the implementations described above. Accordingly, the processor 703 can implement the method 500 and/or other aspects of the implementations described above.
  • FIG. 8 is a schematic block diagram of a communications device 800 (e.g., an instance of the terminal device 120 of FIG. 1 and/or the network device 110 of FIG. 1) in accordance with one or more implementations of the present disclosure.
  • the communications device 800 may include a processor 810 and a memory 820.
  • the memory 820 may store program code, and the processor 810 may execute the program code stored in the memory 820.
  • the memory 820 can include code that corresponds to the method 500 of FIG. 5 and/or other aspects of the implementations described above. Accordingly, the processor 810 can implement the method 500 and/or other aspects of the implementations described above.
  • the communications device 800 can include a transceiver 830 (e.g., an instance of the front-end circuitry 202 of FIG. 2, the signal processing circuitry 204 of FIG. 2, and/or one or more portions thereof).
  • the transceiver 830 can be configured (via, e.g., hardware circuit, software code from the memory 820, and/or firmware) to implement the method 600 and/or other aspects of the implementations described above.
  • the processor in the implementations of this technology may be an integrated circuit chip and has a signal processing capability.
  • the steps in the foregoing method may be implemented by using an integrated logic circuit of hardware in the processor or an instruction in the form of software.
  • the processor may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a discrete gate or transistor logic device, and a discrete hardware component.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the methods, steps, and logic block diagrams disclosed in the implementations of this technology may be implemented or performed.
  • the general-purpose processor may be a microprocessor, or the processor may be alternatively any conventional processor or the like.
  • the steps in the methods disclosed with reference to the implementations of this technology may be directly performed or completed by a decoding processor implemented as hardware or performed or completed by using a combination of hardware and software modules in a decoding processor.
  • the software module may be located at a random-access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, or another mature storage medium in this field.
  • the storage medium is located at a memory, and the processor reads information in the memory and completes the steps in the foregoing methods in combination with the hardware thereof.
  • the memory in the implementations of this technology may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory.
  • the volatile memory may be a random-access memory (RAM) and is used as an external cache.
  • RAMs can be used, and are, for example, a static random-access memory (SRAM), a dynamic random-access memory (DRAM), a synchronous dynamic random-access memory (SDRAM), a double data rate synchronous dynamic random-access memory (DDR SDRAM), an enhanced synchronous dynamic random-access memory (ESDRAM), a synchronous link dynamic random-access memory (SLDRAM), and a direct Rambus random-access memory (DR RAM).
  • SRAM static random-access memory
  • DRAM dynamic random-access memory
  • SDRAM synchronous dynamic random-access memory
  • DDR SDRAM double data rate synchronous dynamic random-access memory
  • ESDRAM enhanced synchronous dynamic random-access memory
  • SLDRAM synchronous link dynamic random-access memory
  • DR RAM direct Rambus random-access memory
  • the feedback message 364, the RF-boundary identifier 312, the tracking circuit 314 (e.g., registers), the symbol counter 316, the RF-CP remover 318, corresponding functions, and/or a combination thereof enable practical removal of the CP 402 at the front-end circuitry 202.
  • the communication device can reduce data communicated between the front-end circuitry 202 and the signal processing circuitry 204, increase the throughput between the circuits, reduce power/current consumption associated with the internal communication, and/or reduce error rates by providing longer signal transition durations.

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Abstract

La présente invention concerne des circuits et des procédés de fonctionnement d'un récepteur dans un système de communication sans fil. Le récepteur supprime des préfixes cycliques (CP) au niveau d'un circuit frontal, ce qui permet d'isoler du contenu ou des symboles qui sont associés aux CP. Le circuit frontal envoie le contenu isolé sans les CP à une circuiterie de traitement de signal pour un traitement ultérieur.
PCT/IB2020/061923 2020-02-27 2020-12-15 Mécanisme de réduction de trafic de bus et procédés de fonctionnement associés WO2021171084A1 (fr)

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