WO2021169997A1 - 数字预失真电路、数字预失真系数获取方法及相关装置 - Google Patents

数字预失真电路、数字预失真系数获取方法及相关装置 Download PDF

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WO2021169997A1
WO2021169997A1 PCT/CN2021/077667 CN2021077667W WO2021169997A1 WO 2021169997 A1 WO2021169997 A1 WO 2021169997A1 CN 2021077667 W CN2021077667 W CN 2021077667W WO 2021169997 A1 WO2021169997 A1 WO 2021169997A1
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signal
output signal
band
circuit
dpd
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PCT/CN2021/077667
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English (en)
French (fr)
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刘乔
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This application relates to the field of communications, and in particular to a digital predistortion circuit, a digital predistortion coefficient acquisition method and related devices.
  • DPD Digital Pre-distortion
  • the embodiments of the application provide a digital predistortion circuit, a method for acquiring digital predistortion coefficients, and related devices, which can extract DPD coefficients through a band-limited DPD coefficient extraction circuit, reduce the bandwidth during DPD coefficient extraction, and thereby reduce the cost of DPD coefficient extraction. Power consumption.
  • an embodiment of the present application provides a digital predistortion circuit, which includes a digital predistortion DPD module, a power amplifier, a signal recovery circuit, and a band-limited DPD coefficient extraction circuit, wherein,
  • the output signal of the digital predistortion DPD module is input to the power amplifier, the output signal of the power amplifier is input to the signal recovery circuit, the output signal of the signal recovery circuit is input to the band-limited DPD coefficient extraction circuit, and the output signal of the band-limited DPD coefficient extraction circuit is input to Digital predistortion DPD module;
  • the band-limited DPD coefficient extraction circuit is used to determine the DPD coefficient according to the output signal of the signal recovery circuit and the first input signal.
  • the first input signal includes the input signal of the digital predistortion DPD module or the output signal of the digital predistortion DPD module.
  • the band-limited DPD coefficient extraction circuit performs DPD coefficient extraction according to the output signal of the signal recovery circuit and the input signal of the digital predistortion DPD module, and the output signal of the digital predistortion DPD module. Therefore, it is compared with the traditional solution.
  • the bandwidth of the output signal of the power amplifier is more than 5 times for DPD coefficient extraction, and the DPD coefficient can be extracted by the band-limited DPD coefficient extraction circuit, which can reduce the power consumption when extracting the DPD coefficient.
  • the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limited filter, and a signal restorer, where:
  • the input signal of the multiplier includes the output signal of the power amplifier and the output signal of the spread spectrum signal generator.
  • the output signal of the multiplier is input to the pre-band limiting filter, and the output signal of the pre-band limiting filter is input to the signal restorer, and the signal is restored.
  • the output signal of the converter is input to the band-limited DPD coefficient extraction circuit.
  • the spread spectrum signal can be filtered through the pre-band-limiting filter to obtain the filtered band-limited signal.
  • the signal restorer uses the band-limited signal for signal recovery, it does not need to be several times the bandwidth of the output signal of the power amplifier. Signal recovery reduces the energy consumption during signal recovery.
  • the circuit further includes an analog-to-digital converter, and the output signal of the pre-band limited filter is input to the signal restorer through the analog-to-digital converter.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor, where,
  • the input signal of the adder includes the output signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor.
  • the output signal of the adder is input to the band-limited DPD coefficient extractor, and the second of the band-limited DPD coefficient extractor
  • the output signal is input to the digital predistortion DPD module, and the output signal of the signal restorer is input to the band-limited DPD coefficient extractor;
  • the band-limited DPD coefficient extractor is used to determine the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor, where,
  • the input signal of the adder includes the input signal of the digital predistortion DPD module and the output signal of the signal restorer.
  • the output signal of the adder is input to the band-limited DPD coefficient extractor, and the output signal of the band-limited DPD coefficient extractor is input to the digital predistortion DPD module;
  • the band-limited DPD coefficient extractor is used to determine the DPD coefficient according to the output signal of the adder.
  • the analog-to-digital converter includes a low-speed analog-to-digital converter.
  • the pre-band limiting filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
  • the circuit further includes a coupler, and the output signal of the power amplifier is input to the signal recovery circuit through the coupler.
  • part of the energy can be coupled to the signal recovery circuit, so that signal coupling can be performed according to the requirements of the signal recovery circuit, which improves the practicability of the digital predistortion circuit.
  • the circuit further includes a digital-to-analog converter, and the output signal of the digital predistortion DPD module is input to the power amplifier through the digital-to-analog converter.
  • an embodiment of the present application provides a method for acquiring digital predistortion coefficients, which is characterized in that it is applied to a digital predistortion circuit, and the circuit includes a digital predistortion DPD module, a power amplifier, a signal recovery circuit, and band-limited DPD coefficient extraction Circuits, methods include:
  • the digital pre-distortion DPD module performs nonlinear correction on the input signal to obtain the output signal of the digital pre-distortion DPD module;
  • the power amplifier amplifies the output signal of the digital predistortion DPD module to obtain the output signal of the power amplifier
  • the signal recovery signal circuit recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit
  • the band-limited DPD coefficient extraction circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, and inputs the output signal including the DPD coefficient to the digital predistortion DPD module, and the first input signal includes the digital predistortion DPD module The input signal or the output signal of the digital predistortion DPD module.
  • the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limited filter, and a signal recovery device.
  • the signal recovery signal circuit recovers the output signal of the power amplifier, To obtain the output signal of the signal recovery signal circuit includes:
  • the multiplier multiplies the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain the output signal of the multiplier;
  • the pre-band limited filter filters the output signal of the multiplier to obtain a narrowband signal
  • the signal restorer restores the narrowband signal to obtain the restored signal, and inputs the restored signal to the band-limited DPD coefficient extraction circuit.
  • the circuit further includes an analog-to-digital converter, which performs analog-to-digital conversion on the narrowband signal to obtain a digital signal, and inputs the digital signal to the signal restorer.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor
  • the first input signal is the output signal of the digital predistortion DPD module
  • the band-limited DPD coefficient extraction circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, including:
  • the adder performs an addition operation according to the output signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain the output signal of the adder;
  • the band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor, the first input signal is the input signal of the digital predistortion DPD module, and the band-limited DPD coefficient extraction The circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, including:
  • the adder performs addition operation according to the input signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain the output signal of the adder;
  • the band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder.
  • the analog-to-digital converter includes a low-speed analog-to-digital converter.
  • the pre-band limiting filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
  • the circuit further includes a coupler, and the output signal of the power amplifier is input to the signal recovery circuit through the coupler.
  • the circuit further includes a digital-to-analog converter, and the output signal of the digital predistortion DPD module is input to the power amplifier through the digital-to-analog converter.
  • an embodiment of the present application provides a transmitter, and the transmitter includes an antenna and a digital predistortion circuit as in any one of the foregoing first aspect.
  • an embodiment of the present application provides a chip system, and the chip system includes a processor for supporting a digital predistortion circuit to implement any method as in the second aspect.
  • an embodiment of the present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, the computer program includes program instructions, and the program instructions cause the processor to execute when executed by the processor Such as the method of any one of the second aspect.
  • FIG. 1 is a schematic structural diagram of a digital predistortion circuit provided in an embodiment of the application
  • FIG. 2A provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of the present application
  • FIG. 2B provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of this application.
  • FIG. 3A provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of the present application.
  • FIG. 3B provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of the application.
  • FIG. 4A provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of the present application.
  • FIG. 4B provides a schematic structural diagram of another digital predistortion circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a method for acquiring digital predistortion coefficients according to an embodiment of this application
  • FIG. 6 provides a schematic structural diagram of a chip system provided in this application for an embodiment of this application.
  • the digital predistortion circuit aims to solve the problem of the large power consumption of the digital predistortion circuit that requires several times the bandwidth of the output signal of the power amplifier when extracting DPD coefficients in the existing solution.
  • the band-limited DPD coefficient extraction circuit in the circuit extracts the DPD coefficients without the need for several times the bandwidth of the output signal of the power amplifier to reduce the power consumption of the digital predistortion circuit.
  • FIG. 1 is a schematic structural diagram of a digital predistortion circuit provided in an embodiment of the application.
  • the digital predistortion circuit includes: a digital predistortion DPD module 110, a power amplifier PA120, a signal recovery circuit 130, and a band-limited DPD coefficient extraction circuit 140, wherein,
  • the output signal of the digital predistortion DPD module 110 is input to the power amplifier PA120, the output signal of the power amplifier PA120 is input to the signal recovery circuit 130, the output signal of the signal recovery circuit 130 is input to the band-limited DPD coefficient extraction circuit 140, and the band-limited DPD coefficient is extracted
  • the output signal of the circuit 140 is input to the digital predistortion DPD module 110;
  • the band-limited DPD coefficient extraction circuit 140 is used to determine the DPD coefficient according to the output signal of the signal recovery circuit 130 and the first input signal.
  • the first input signal includes the input signal of the digital predistortion DPD module 110 or the input signal of the digital predistortion DPD module 110 output signal.
  • the signal recovery circuit 130 is used to perform signal recovery according to the output signal of the power amplifier to obtain a recovered signal, and the recovered signal is a digital signal.
  • the digital predistortion DPD module 110 receives the DPD coefficients output by the band-limited DPD coefficient extraction circuit 140, it completes non-linear pre-correction in the digital domain.
  • the above-mentioned signal recovery circuit 130 and band-limited DPD coefficient extraction circuit 140 may also be referred to as a feedback channel.
  • the signal recovery circuit 130 includes a multiplier 131, a spread spectrum signal generator 132, a pre-band limit filter 133, and a signal restorer 134, where:
  • the input signal of the multiplier 131 includes the output signal of the power amplifier PA120 and the output signal of the spread spectrum signal generator 132.
  • the output signal of the multiplier 131 is input to the pre-band limit filter 133, and the output signal of the pre-band limit filter 133 is input to The signal restorer 134, and the output signal of the signal restorer 134 is input to the band-limited DPD coefficient extraction circuit 140.
  • the multiplier 131 is used to mix the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain a spread spectrum signal;
  • the pre-band limit filter 133 is used to filter the spread spectrum signal output by the multiplier 131 to obtain a narrowband signal with a preset bandwidth.
  • the preset bandwidth can be set according to the performance requirements when the DPD coefficient is extracted. For example, when the performance requirement is accuracy, the accuracy can also be understood as accuracy. The larger the preset bandwidth, the higher the accuracy, and the smaller the preset bandwidth, the lower the accuracy.
  • the narrowband signal is a sub-segment of the spread-spectrum wideband signal in the frequency domain, and the spectrum of the sub-segment can reflect the information characteristics of the output signal of the power amplifier PA120.
  • the signal recovery circuit 134 is used to perform signal recovery on the narrowband signal output by the pre-band limiting filter 133 to obtain a recovered signal, and the recovered signal is a digital signal.
  • the pre-band limit filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
  • the power amplifier can be a digital power amplifier or an analog power amplifier. If the power amplifier is a digital power amplifier, the signal recovery circuit is to recover the digital signal. If the power amplifier is an analog power amplifier, then The signal recovery circuit recovers the analog signal.
  • the digital predistortion circuit may also include an analog-to-digital converter, and the output signal of the pre-band limited filter is input to the signal restorer through the analog-to-digital converter.
  • the output signal of the pre-band-limiting filter undergoes analog-to-digital conversion to obtain an analog signal, and the analog signal is input to the signal restorer.
  • the analog-to-digital converter can be a low-speed analog-to-digital converter, and the low-speed analog-to-digital converter can be understood as an analog-to-digital converter with a lower sampling rate.
  • the signal can be sampled at a lower sampling rate, which eliminates the need for multiple times the bandwidth of the output signal of the power amplifier, which reduces energy consumption and reduces the difficulty of implementation , Improved practicality.
  • the digital predistortion circuit may further include a digital-to-analog converter for converting the output signal of the digital predistortion DPD module to obtain an analog signal, and inputting the analog signal to the power amplifier.
  • a digital-to-analog converter for converting the output signal of the digital predistortion DPD module to obtain an analog signal, and inputting the analog signal to the power amplifier.
  • the input signal of the digital-to-analog converter 150 is the output signal of the DPD module 110, and the output signal of the digital-to-analog converter 150 is input to the power Amplifier PA120;
  • the input signal of the analog-to-digital converter 135 is the output signal of the pre-band limiting filter 133, and the output signal of the analog-to-digital converter 135 is input to the signal restorer 134.
  • the output signal of the spread spectrum signal generator 132 may also be output to the signal restorer 134 for the signal restorer 134 to restore the signal.
  • the signal restorer can perform signal restoration according to the input signal through the signal restoration algorithm in the compressed sensing algorithm or the spectrum extrapolation algorithm, etc., to obtain the restored signal.
  • the band-limited DPD coefficient extraction circuit 140 includes an adder 141 and a band-limited DPD coefficient extractor 142, wherein,
  • the input signal of the adder 141 includes the output signal of the digital predistortion DPD module 110 and the first output signal of the band-limited DPD coefficient extractor 142.
  • the output signal of the adder 141 is input to the band-limited DPD coefficient extractor 142, and the band-limited DPD coefficient
  • the second output signal of the extractor 142 is input to the digital predistortion DPD module 110, and the output signal of the signal restorer 130 is input to the band-limited DPD coefficient extractor 142;
  • the band-limited DPD coefficient extractor 142 is used to determine the DPD coefficient according to the output signal of the adder 141 and the output signal of the signal restorer 130.
  • the band-limited DPD coefficient extraction circuit 140 includes an adder 141 and a band-limited DPD coefficient extractor 142, wherein,
  • the input signal of the adder 141 includes the input signal of the digital predistortion DPD module 110 and the output signal of the signal restorer 130, the output signal of the adder 141 is input to the band-limited DPD coefficient extractor 142, and the output of the band-limited DPD coefficient extractor 142 The signal is input to the digital predistortion DPD module 110;
  • the band-limited DPD coefficient extractor 142 is used to determine the DPD coefficient according to the output signal of the adder 141.
  • the digital predistortion circuit further includes a coupler 160.
  • the output signal of the power amplifier PA120 is input to the signal recovery circuit 130 through the coupler 160.
  • the power The output signal of the amplifier PA120 is coupled to the coupling port according to a preset ratio, that is, part of the energy of the output signal of the power amplifier PA120 is coupled to the signal recovery circuit 130.
  • the modules or circuits included in the signal recovery circuit and the band-limited DPD coefficient extraction circuit in the above embodiments may also be divided in other forms. This is only an example for illustration, for example, the spread spectrum signal generator in the signal recovery circuit It can be a sub-device in the band-limited DPD coefficient extraction circuit. When the spread-spectrum signal generator is a sub-device of the band-limited DPD coefficient extraction circuit, it cannot be a sub-device in the signal recovery circuit.
  • FIG. 5 provides a schematic flowchart of a method for acquiring digital predistortion coefficients.
  • the method for obtaining digital predistortion coefficients is applied to a digital predistortion circuit.
  • the digital predistortion circuit is the circuit shown in any one of the embodiments shown in FIGS. 1 to 4B, and the digital predistortion circuit includes digital predistortion.
  • the method for acquiring digital predistortion coefficients includes the following steps:
  • the digital predistortion DPD module performs nonlinear correction on the input signal to obtain an output signal of the digital predistortion DPD module.
  • the digital predistortion DPD module corrects the input signal, it needs to correct the input signal through the DPD coefficient, that is, after the digital predistortion circuit determines the DPD coefficient, the input signal is nonlinearly corrected.
  • the power amplifier amplifies the output signal of the digital predistortion DPD module to obtain the output signal of the power amplifier.
  • the power amplifier When the power amplifier amplifies the output signal of the digital predistortion DPD module, the power amplifier can work in the non-linear region.
  • the power amplifier can be an analog power amplifier or a digital power amplifier.
  • the signal recovery signal circuit recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit.
  • the output signal of the signal recovery circuit includes a digital signal.
  • the band-limited DPD coefficient extraction circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, and inputs the output signal including the DPD coefficient to the digital predistortion DPD module, the first input signal includes digital predistortion The input signal of the DPD module or the output signal of the digital predistortion DPD module.
  • the digital predistortion DPD module After receiving the DPD coefficient, the digital predistortion DPD module corrects the input signal according to the DPD coefficient to obtain a corrected signal.
  • the nonlinear distortion of the corrected signal is lower than that of the output signal amplified by the power amplifier. .
  • the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limited filter, and a signal restorer.
  • the signal recovery signal circuit restores the output signal of the power amplifier to obtain the signal recovery signal.
  • the multiplier multiplies the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain the output signal of the multiplier;
  • Multiplying the output signal of the power amplifier and the output signal of the spread-spectrum signal generator to obtain the output signal of the multiplier can also be a mixing of the output signal of the power amplifier.
  • the output signal of the multiplier is a broadband signal.
  • the pre-band limited filter filters the output signal of the multiplier to obtain a narrowband signal
  • the bandwidth of the narrowband signal can be set according to the performance requirements when the DPD coefficient is extracted.
  • the accuracy can also be understood as accuracy.
  • the signal restorer restores the narrowband signal to obtain the restored signal, and inputs the restored signal to the band-limited DPD coefficient extraction circuit.
  • the signal restorer can perform signal restoration according to the input signal through the signal restoration algorithm in the compressed sensing algorithm or the spectrum extrapolation algorithm, etc., to obtain the restored signal.
  • the circuit further includes an analog-to-digital converter, which performs analog-to-digital conversion on the narrowband signal to obtain a digital signal, and inputs the digital signal to the signal restorer.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor.
  • the method for determining the DPD coefficient may be:
  • the adder performs an addition operation according to the output signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain the output signal of the adder;
  • the band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
  • the DPD coefficient can be determined through an algorithm according to a preset nonlinear model.
  • the power amplifier is modeled by polynomials, and the mathematical model is as follows:
  • a km is the DPD coefficient (can also be called a non-linear parameter)
  • k is the degree of non-linearity
  • K is the order of non-linearity on which the power amplifier is modeled
  • m is the memory depth value
  • M is the power amplifier The maximum memory depth of the model.
  • the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor
  • the first input signal is the input signal of the digital predistortion DPD module
  • the method for determining the DPD coefficient includes:
  • the adder performs addition operation according to the input signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain the output signal of the adder;
  • the band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder.
  • the DPD coefficient When determining the DPD coefficient according to the output signal of the adder, it may specifically be a value corresponding to the minimum error value between the input signals of the first output signal digital predistortion DPD module of the band-limited DPD coefficient extractor.
  • the error value minimization can be determined according to different requirements, and different requirements can correspond to different error minimization values.
  • the analog-to-digital converter includes a low-speed analog-to-digital converter.
  • the pre-band limit filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
  • the digital predistortion circuit further includes a coupler, and the output signal of the power amplifier is input to the signal recovery circuit through the coupler.
  • the circuit further includes a digital-to-analog converter, and the output signal of the digital predistortion DPD module is input to the power amplifier through the digital-to-analog converter.
  • FIG. 6 provides a schematic structural diagram of a chip system provided by the present application for an embodiment of the present application.
  • the chip system 600 may include a processor 610 and one or more interfaces 620 coupled to the processor 610.
  • the processor 610 may be used to read and execute computer-readable instructions.
  • the processor 610 may mainly include a controller, an arithmetic unit, and a register.
  • the controller is mainly responsible for instruction decoding, and sends control signals for operations corresponding to the instructions.
  • the arithmetic unit is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations and logical operations, etc., and can also perform address operations and conversions.
  • the register is mainly responsible for storing the register operands and intermediate operation results temporarily stored during the execution of the instruction.
  • the hardware architecture of the processor 610 can be an application specific integrated circuit (ASIC) architecture, a microprocessor without interlocked pipeline stage architecture (microprocessor without interlocked piped stages architecture, MIPS) architecture, and advanced streamlining. Instruction set machine (advanced RISC machines, ARM) architecture or NP architecture, etc.
  • the processor 610 may be single-core or multi-core.
  • the interface 620 may be used to input data to be processed to the processor 610, and may output the processing result of the processor 610 externally.
  • the interface 620 may be a general purpose input output (GPIO) interface.
  • the interface 620 is connected to the processor 610 through the bus 630.
  • the processor 610 may be used to call the implementation program or data in the digital predistortion circuit of the method for acquiring the digital predistortion coefficient provided by one or more embodiments of the present application from the memory, so that the chip can Realize the method shown in Figure 6 above.
  • the memory may be integrated with the processor 610, or may be coupled to the communication chip 600 through the interface 620, that is to say, the memory may be a part of the communication chip 600 or may be independent of the communication chip 600.
  • the interface 620 may be used to output the execution result of the processor 610. In this application, the interface 620 may be specifically used to output the decoding result of the processor 610.
  • processor 610 and the interface 620 may be implemented through hardware design, may also be implemented through software design, or may be implemented through a combination of software and hardware, which is not limited here.
  • the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • Enhanced SDRAM, ESDRAM Synchronous Link Dynamic Random Access Memory
  • Sync Link DRAM SLDRAM
  • DR RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, transistor logic device, or discrete hardware component
  • the memory storage module
  • An embodiment of the present application also provides a transmitter, which includes an antenna and a digital predistortion circuit as shown in any one of the above-mentioned embodiments of FIG. 1 to FIG. 4B.
  • An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium may store a program, and the program includes part or all of the steps of any digital predistortion coefficient acquisition method recorded in the foregoing method embodiment when the program is executed.
  • the disclosed device may be implemented in other ways.
  • the device embodiments described above are only illustrative, for example, the division of units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated into Another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable memory.
  • the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory.
  • a number of instructions are included to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.
  • the program can be stored in a computer-readable memory, and the memory can include: flash disk, Read-only memory (English: Read-Only Memory, abbreviation: ROM), random access device (English: Random Access Memory, abbreviation: RAM), magnetic disk or optical disc, etc.

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Abstract

本申请公开了一种数字预失真电路、数字预失真系数获取方法及相关装置，其中，该电路包括：数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，其中，DPD模块的输出信号输入到功率放大器，功率放大器的输出信号输入到信号恢复电路，信号恢复电路的输出信号输入到带限DPD系数提取电路，带限DPD系数提取电路的输出信号输入到DPD模块；带限DPD系数提取电路，用于根据信号恢复电路的输出信号与第一输入信号，确定DPD系数，第一输入信号包括DPD模块的输入信号或DPD模块的输出信号，能够通过带限DPD系数提取电路提取DPD系数，降低DPD系数提取时的带宽，降低了DPD系数提取时的功耗。

Description

数字预失真电路、数字预失真系数获取方法及相关装置
本申请要求于2020年02月24日提交中国专利局、申请号为202010115969.9、申请名称为“数字预失真电路、数字预失真系数获取方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，尤其涉及一种数字预失真电路、数字预失真系数获取方法及相关装置。
背景技术
随着5G技术的快速发展，其频带扩展到了毫米波，在进行信号发射时由于功率放大器的工作在非线性区域，造成了带内信号的非线性失真，解决带内信号的非线性失真时通常会对信号进行数字预失真处理以调节带内信号的非线性失真。现有的数字预失真系统(Digital Pre-distortion，DPD)，其反馈通道通常需要功率放大器输出信号5倍以上的带宽进行信号恢复，在提取DPD系数时，通常会消耗功率放大器输出信号5倍以上的带宽，导致了DPD系数提取时的功耗较大。
发明内容
本申请实施例提供一种数字预失真电路、数字预失真系数获取方法及相关装置，能够通过带限DPD系数提取电路提取DPD系数，降低DPD系数提取时的带宽，从而降低了DPD系数提取时的功耗。
第一方面，本申请实施例提供了一种数字预失真电路，该电路包括：数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，其中，
数字预失真DPD模块的输出信号输入到功率放大器，功率放大器的输出信号输入到信号恢复电路，信号恢复电路的输出信号输入到带限DPD系数提取电路，带限DPD系数提取电路的输出信号输入到数字预失真DPD模块；
带限DPD系数提取电路，用于根据信号恢复电路的输出信号与第一输入信号，确定DPD系数，第一输入信号包括数字预失真DPD模块的输入信号或数字预失真DPD模块的输出信号。
本申请实施例中，带限DPD系数提取电路根据信号恢复电路的输出信号和数字预失真DPD模块的输入信号、数字预失真DPD模块的输出信号进行DPD系数提取，因此，相对于传统方案中采用功率放大器输出信号5倍以上的带宽进行DPD系数提取，能够通过带限DPD系数提取电路对DPD系数进行带限提取，从而可以降低DPD系数提取时的功耗。
结合第一方面，在一种可能的实现方式中，信号恢复电路包括乘法器、扩频信号生成器、预带限滤波器和信号恢复器，其中，
乘法器的输入信号包括功率放大器的输出信号和扩频信号生成器的输出信号，乘法器的输出信号输入到预带限滤波器，预带限滤波器的输出信号输入到信号恢复器，信号恢复 器的输出信号输入到带限DPD系数提取电路。
本示例中，可以通过预带限滤波器对扩频信号进行滤波，以得到滤波后的带限信号，信号恢复器采用带限信号进行信号恢复时，无需数倍于功率放大器输出信号的带宽进行信号恢复，降低了信号恢复时的能耗。
结合第一方面，在一种可能的实现方式中，电路还包括模数转换器，预带限滤波器的输出信号通过模数转换器输入到信号恢复器。
结合第一方面，在一种可能的实现方式中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，其中，
加法器的输入信号包括数字预失真DPD模块的输出信号和带限DPD系数提取器的第一输出信号，加法器的输出信号输入到带限DPD系数提取器，带限DPD系数提取器的第二输出信号输入到数字预失真DPD模块，信号恢复器的输出信号输入到带限DPD系数提取器；
带限DPD系数提取器，用于根据加法器的输出信号和信号恢复器的输出信号确定DPD系数。
结合第一方面，在一种可能的实现方式中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，其中，
加法器的输入信号包括数字预失真DPD模块的输入信号和信号恢复器的输出信号，加法器的输出信号输入到带限DPD系数提取器，带限DPD系数提取器的输出信号输入到数字预失真DPD模块；
带限DPD系数提取器，用于根据加法器的输出信号确定DPD系数。
结合第一方面，在一种可能的实现方式中，模数转换器包括低速模数转换器。
本示例中，通过采用低速模数转换器，相对于现有方案中采用高速模数转换器进行信号采样，能够降低电路实现的难度，同时也能降低采样时所需的能耗。
结合第一方面，在一种可能的实现方式中，预带限滤波器包括低通滤波器、高通滤波器或带通滤波器。
结合第一方面，在一种可能的实现方式中，电路还包括耦合器，功率放大器的输出信号通过耦合器输入到信号恢复电路。
本示例中，功率放大器的输出信号通过耦合器输入到信号恢复电路时，可以耦合部分能量到信号恢复电路，从而可以根据信号恢复电路的需求进行信号耦合，提升了数字预失真电路的实用性。
结合第一方面，在一种可能的实现方式中，电路还包括数模转换器，数字预失真DPD模块的输出信号通过数模转换器输入到功率放大器。
第二方面，本申请实施例提供了一种数字预失真系数获取方法，其特征在于，应用于数字预失真电路，电路包括数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，方法包括：
数字预失真DPD模块对输入信号进行非线性校正，以得到数字预失真DPD模块输出信号；
功率放大器对数字预失真DPD模块的输出信号进行放大，以得到功率放大器的输出信号；
信号恢复信号电路对功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号；
带限DPD系数提取电路根据信号恢复信号电路的输出信号和第一输入信号，确定DPD系数，以及将包括DPD系数的输出信号输入到数字预失真DPD模块，第一输入信号包括数字预失真DPD模块的输入信号或数字预失真DPD模块的输出信号。
结合第二方面，在一种可能的实现方式中，信号恢复电路包括乘法器、扩频信号生成器、预带限滤波器和信号恢复器，信号恢复信号电路对功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号包括：
乘法器对功率放大器的输出信号和扩频信号生成器的输出信号进行乘法运算，以得到乘法器的输出信号；
预带限滤波器对乘法器的输出信号进行滤波，以得到窄带信号；
信号恢复器根据窄带信号进行恢复，以得到恢复后的信号，以及将恢复后的信号输入到带限DPD系数提取电路。
结合第二方面，在一种可能的实现方式中，电路还包括模数转换器，模数转换器对窄带信号进行模数转换，以得到数字信号，以及将数字信号输入到信号恢复器。
结合第二方面，在一种可能的实现方式中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，第一输入信号为数字预失真DPD模块的输出信号，带限DPD系数提取电路根据信号恢复信号电路的输出信号和第一输入信号，确定DPD系数包括：
加法器根据数字预失真DPD模块的输出信号和带限DPD系数提取器的第一输出信号进行加法运算，以得到加法器的输出信号；
带限DPD系数提取器根据加法器的输出信号和信号恢复器的输出信号确定DPD系数。
结合第二方面，在一种可能的实现方式中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，第一输入信号为数字预失真DPD模块的输入信号，带限DPD系数提取电路根据信号恢复信号电路的输出信号和第一输入信号，确定DPD系数，包括：
加法器根据数字预失真DPD模块的输入信号和带限DPD系数提取器的第一输出信号进行加法运算，以得到加法器的输出信号；
带限DPD系数提取器根据加法器的输出信号确定DPD系数。
结合第二方面，在一种可能的实现方式中，模数转换器包括低速模数转换器。
结合第二方面，在一种可能的实现方式中，预带限滤波器包括低通滤波器、高通滤波器或带通滤波器。
结合第二方面，在一种可能的实现方式中，电路还包括耦合器，功率放大器的输出信号通过耦合器输入到信号恢复电路。
结合第二方面，在一种可能的实现方式中，电路还包括数模转换器，数字预失真DPD模块的输出信号通过数模转换器输入到功率放大器。
第三方面，本申请实施例提供了一种发射机，发射机包括天线和如上述第一方面任一项的数字预失真电路。
第四方面，本申请实施例提供了一种芯片系统，芯片系统包括处理器，用于支持数字预失真电路实现如第二方面任一项的方法。
第五方面，本申请实施例提供了一种计算机可读存储介质，其特征在于，计算机可读存储介质存储有计算机程序，计算机程序包括程序指令，程序指令当被处理器执行时使处理器执行如第二方面任一项的方法。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供了一种数字预失真电路的结构示意图；
图2A为本申请实施例提供了另一种数字预失真电路的结构示意图；
图2B为本申请实施例提供了另一种数字预失真电路的结构示意图；
图3A为本申请实施例提供了另一种数字预失真电路的结构示意图；
图3B为本申请实施例提供了另一种数字预失真电路的结构示意图；
图4A为本申请实施例提供了另一种数字预失真电路的结构示意图；
图4B为本申请实施例提供了另一种数字预失真电路的结构示意图；
图5为本申请实施例提供了一种数字预失真系数获取方法的流程示意图；
图6为本申请实施例提供了本申请提供的一种芯片系统的结构示意图。
具体实施方式
下面结合附图对本申请的实施例进行描述。
下面具体介绍数字预失真电路的具体结构。本申请提供的数字预失真电路，旨在解决现有方案中在DPD系数提取时需要数倍于功率放大器的输出信号的带宽，造成数字预失真电路的功耗较大的问题，通过数字预失真电路中的带限DPD系数提取电路来提取DPD系数，无需数倍于功率放大器输出信号的带宽，以降低数字预失真电路的功耗。
图1为本申请实施例提供了一种数字预失真电路的结构示意图。如图1所示，数字预失真电路包括：数字预失真DPD模块110、功率放大器PA120、信号恢复电路130和带限DPD系数提取电路140，其中，
数字预失真DPD模块110的输出信号输入到功率放大器PA120，功率放大器PA120的输出信号输入到信号恢复电路130，信号恢复电路130的输出信号输入到带限DPD系数提取电路140，带限DPD系数提取电路140的输出信号输入到数字预失真DPD模块110；
带限DPD系数提取电路140，用于根据信号恢复电路130的输出信号与第一输入信号，确定DPD系数，第一输入信号包括数字预失真DPD模块110的输入信号或数字预失真DPD模块110的输出信号。
信号恢复电路130，用于根据功率放大器的输出信号进行信号恢复，以得到恢复后的信号，恢复后的信号为数字信号。
数字预失真DPD模块110接收到带限DPD系数提取电路140输出的DPD系数后，在数字域完成非线性预校正。
上述信号恢复电路130和带限DPD系数提取电路140也可以称为反馈通道。
在一个可能的实施例中，如图2A所示，信号恢复电路130包括乘法器131、扩频信号生成器132、预带限滤波器133和信号恢复器134，其中，
乘法器131的输入信号包括功率放大器PA120的输出信号和扩频信号生成器132的输出信号，乘法器131的输出信号输入到预带限滤波器133，预带限滤波器133的输出信号输入到信号恢复器134，信号恢复器134的输出信号输入到带限DPD系数提取电路140。
乘法器131，用于对功率放大器的输出信号和扩频信号生成器的输出信号进行混频，以得到扩频信号；
预带限滤波器133，用于对乘法器131输出的扩频信号进行滤波，得到预设带宽的窄带信号。预设带宽可以根据DPD系数提取时的性能需求进行设定，例如性能需求为精度时，精度也可以理解为准确性，预设带宽越大则精度越高，预设带宽越小则精度越低。窄带信号在频域上是扩频宽带信号的一个子段，该子段频谱能反映功率放大器PA120的输出信号的信息特征。
信号恢复电路134，用于对预带限滤波器133输出的窄带信号进行信号恢复，得到恢复后的信号，恢复后的信号为数字信号。
在一个可能的实施例中，预带限滤波器包括低通滤波器、高通滤波器或带通滤波器。
在一个可能的实施例中，功率放大器可以为数字功率放大器也可以为模拟功率放大器，若功率放大器为数字功率放大器，则信号恢复电路为对数字信号进行恢复，若功率放大器为模拟功率放大器，则信号恢复电路对模拟信号进行恢复。
当功率放大器为模拟功率放大器时，数字预失真电路还可以包括模数转换器，预带限滤波器的输出信号通过模数转换器输入到信号恢复器，具体可以为：模数转换器用于将预带限滤波器的输出信号进行模数转换得到模拟信号，并将该模拟信号输入到信号恢复器。该模数转换器可以为低速模数转换器，低速模数转换器可以理解为较低的采样速率的模数转换器。采用低速模数转换器对信号进行模数转换，则可以采用较低的采样率对信号进行采样，从而无需数倍与功率放大器输出信号的带宽进行采用，降低了能耗，降低了实现的难度，提升了实用性。
数字预失真电路还可以包括数模转换器，该数模转换器用于将数字预失真DPD模块的输出信号进行转换得到模拟信号，并将该模拟信号输入到功率放大器。上述数模转换器和模数转换器的设置方式可以参见图2B所示，图2B中数模转换器150的输入信号为DPD模块110的输出信号，数模转换器150的输出信号输入到功率放大器PA120；模数转换器135的输入信号为预带限滤波器133的输出信号，模数转换器135的输出信号输入到信号恢复器134。
在一个可能的实施例中，扩频信号生成器132的输出信号还可以输出到信号恢复器134，用以信号恢复器134对信号进行恢复。信号恢复器可以通过压缩感知算法中的信号恢复算法或者频谱外推算法等，根据输入信号进行信号恢复，得到恢复后的信号。
在一个可能的实施例中，如图3A所示，带限DPD系数提取电路140包括加法器141和 带限DPD系数提取器142，其中，
加法器141的输入信号包括数字预失真DPD模块110的输出信号和带限DPD系数提取器142的第一输出信号，加法器141的输出信号输入到带限DPD系数提取器142，带限DPD系数提取器142的第二输出信号输入到数字预失真DPD模块110，信号恢复器130的输出信号输入到带限DPD系数提取器142；
带限DPD系数提取器142，用于根据加法器141的输出信号和信号恢复器130的输出信号确定DPD系数。
在一个可能的实施例中，如图3B所示，带限DPD系数提取电路140包括加法器141和带限DPD系数提取器142，其中，
加法器141的输入信号包括数字预失真DPD模块110的输入信号和信号恢复器130的输出信号，加法器141的输出信号输入到带限DPD系数提取器142，带限DPD系数提取器142的输出信号输入到数字预失真DPD模块110；
带限DPD系数提取器142，用于根据加法器141的输出信号确定DPD系数。
在一个可能的实施例中，如图4A和图4B所示，数字预失真电路还包括耦合器160，功率放大器PA120的输出信号通过耦合器160输入到信号恢复电路130，具体可以为，将功率放大器PA120的输出信号按照预设比例耦合到耦合端口，即为：将功率放大器PA120的输出信号，耦合部分能量到信号恢复电路130。
上述实施例中的信号恢复电路和带限DPD系数提取电路中包括的模块或电路还可以是以其它的形式进行划分，此处仅为举例说明，例如，信号恢复电路中的扩频信号生成器可以为带限DPD系数提取电路中的子器件，当该扩频信号生成器为带限DPD系数提取电路的子器件时，则其便不能为信号恢复电路中的子器件。
请参阅图5，图5提供了一种数字预失真系数获取方法的流程示意图。如图5所示，数字预失真系数获取方法应用于数字预失真电路，数字预失真电路为上述实施例如图1至图4B中任一实施例所示的电路，数字预失真电路包括数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，数字预失真系数获取方法包括如下步骤：
S510、数字预失真DPD模块对输入信号进行非线性校正，以得到数字预失真DPD模块输出信号。
数字预失真DPD模块对输入信号进行校正时，需要通过DPD系数对输入信号进行校正，即在数字预失真电路确定出DPD系数后，对输入信号进行非线性校正。
S502、功率放大器对数字预失真DPD模块输出信号进行放大，以得到功率放大器的输出信号。
功率放大器对数字预失真DPD模块的输出信号进行放大时，功率放大器可以工作在非线性区域。
功率放大器可以是模拟功率放大器，也可以是数字功率放大器。
S503、信号恢复信号电路对功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号。
信号恢复电路的输出信号包括数字信号。
S504、带限DPD系数提取电路根据信号恢复信号电路的输出信号和第一输入信号，确 定DPD系数，以及将包括DPD系数的输出信号输入到数字预失真DPD模块，第一输入信号包括数字预失真DPD模块的输入信号或数字预失真DPD模块的输出信号。
数字预失真DPD模块接收到DPD系数后，根据该DPD系数对输入信号进行校正，以得到校正后的信号，校正后的信号的非线性失真低于经过功率放大器放大后的输出信号的非线性失真。
在一个可能的实施例中，信号恢复电路包括乘法器、扩频信号生成器、预带限滤波器和信号恢复器，在信号恢复信号电路对功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号时，具体可以采用如下方法：
A1、乘法器对功率放大器的输出信号和扩频信号生成器的输出信号进行乘法运算，以得到乘法器的输出信号；
对功率放大器的输出信号和扩频信号生成器的输出信号进行乘法运算，以得到乘法器的输出信号也可以成为对功率放大器的输出信号进行混频。乘法器的输出信号为宽频信号。
A2、预带限滤波器对乘法器的输出信号进行滤波，以得到窄带信号；
窄带信号的带宽可以根据DPD系数提取时的性能需求进行设定，例如性能需求为精度时，精度也可以理解为准确性，预设带宽越大则精度越高，预设带宽越小则精度越低。
A3、信号恢复器根据窄带信号进行恢复，以得到恢复后的信号，以及将恢复后的信号输入到带限DPD系数提取电路。
信号恢复器可以通过压缩感知算法中的信号恢复算法或者频谱外推算法等，根据输入信号进行信号恢复，得到恢复后的信号。
在一个可能的实施例中，电路还包括模数转换器，模数转换器对窄带信号进行模数转换，以得到数字信号，以及将数字信号输入到信号恢复器。
在一个可能的实施例中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，第一输入信号为数字预失真DPD模块的输出信号时，确定DPD系数的方法可以为：
B1、加法器根据数字预失真DPD模块的输出信号和带限DPD系数提取器的第一输出信号进行加法运算，以得到加法器的输出信号；
B2、带限DPD系数提取器根据加法器的输出信号和信号恢复器的输出信号确定DPD系数。
带限DPD系数提取器根确定DPD系数时，可以按照预设的非线性模型，通过算法对DPD系数进行确定。例如，功率放大器用多项式建模，数学模型如下：
Figure PCTCN2021077667-appb-000001
其中，a km是DPD系数(也可以称为非线性参数)，k是非线性度，K是对功率放大器进行建模所依据的非线性度的阶数，m是记忆深度值，M是功率放大器模型的记忆深度的最大值。
在一个可能的实施例中，带限DPD系数提取电路包括加法器和带限DPD系数提取器，第一输入信号为数字预失真DPD模块的输入信号，确定DPD系数的方法包括：
C1、加法器根据数字预失真DPD模块的输入信号和带限DPD系数提取器的第一输出信号进行加法运算，以得到加法器的输出信号；
C2、带限DPD系数提取器根据加法器的输出信号确定DPD系数。
根据加法器的输出信号确定DPD系数时，具体可以为带限DPD系数提取器的第一输出信号数字预失真DPD模块的输入信号之间的误差值最小化所对应的值。误差值最小化可以根据不同的需求进行确定，不同的需求可以对应不同的误差最小化值。
在一个可能的实施例中，模数转换器包括低速模数转换器。
在一个可能的实施例中，预带限滤波器包括低通滤波器、高通滤波器或带通滤波器。
在一个可能的实施例中，数字预失真电路还包括耦合器，功率放大器的输出信号通过耦合器输入到信号恢复电路。
在一个可能的实施例中，电路还包括数模转换器，数字预失真DPD模块的输出信号通过数模转换器输入到功率放大器。
上述方法中的数字预失真电路的具体电路结构参见前述实施例图1至图4B任一实施例所示的电路，此处不再赘述。
参见图6，图6为本申请实施例提供了本申请提供的一种芯片系统的结构示意图。如图6所示，芯片系统600可包括：处理器610，以及耦合于处理器610的一个或多个接口620。示例性的：
处理器610可用于读取和执行计算机可读指令。具体实现中，处理器610可主要包括控制器、运算器和寄存器。示例性的，控制器主要负责指令译码，并为指令对应的操作发出控制信号。运算器主要负责执行定点或浮点算数运算操作、移位操作以及逻辑操作等，也可以执行地址运算和转换。寄存器主要负责保存指令执行过程中临时存放的寄存器操作数和中间操作结果等。具体实现中，处理器610的硬件架构可以是专用集成电路(application specific integrated circuits，ASIC)架构、无互锁管道阶段架构的微处理器(microprocessor without interlocked piped stages architecture，MIPS)架构、进阶精简指令集机器(advanced RISC machines，ARM)架构或者NP架构等等。处理器610可以是单核的，也可以是多核的。
示例性的，接口620可用于输入待处理的数据至处理器610，并且可以向外输出处理器610的处理结果。具体实现中，接口620可以是通用输入输出(general purpose input output，GPIO)接口。接口620通过总线630与处理器610相连。
一种可能的实现方式中，处理器610可用于从存储器中调用本申请的一个或多个实施例提供的数字预失真系数获取方法在数字预失真电路中的实现程序或者数据，使得该芯片可以实现前述图6所示的法。存储器可以和处理器610集成在一起，也可以通过接口620与通信芯片600相耦合，也就是说存储器可以是通信芯片600的一部分，也可以独立于该通信芯片600。接口620可用于输出处理器610的执行结果。本申请中，接口620可具体用于输出处理器610的译码结果。关于本申请的一个或多个实施例提供的数字预失真系数获取方可参考前述各个实施例，这里不再赘述。
需要说明的，处理器610、接口620各自对应的功能既可以通过硬件设计实现，也可以通过软件设计来实现，还可以通过软硬件结合的方式来实现，这里不作限制。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Sync Link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
本申请实施例还提供一种发射机，该发射机包括天线和如上述图1至图4B任一实施例所示的数字预失真电路。
本申请实施例还提供一种计算机存储介质，其中，该计算机存储介质可存储有程序，该程序执行时包括上述方法实施例中记载的任何一种数字预失真系数获取方法的部分或全部步骤。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存 储在一个计算机可读取存储器中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。
[根据细则26改正26.04.2021]　
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上上述，本说明书内容不应理解为对本申请的限制。

Claims (17)

  1. 一种数字预失真电路，其特征在于，所述电路包括：数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，其中，
    所述数字预失真DPD模块的输出信号输入到所述功率放大器，所述功率放大器的输出信号输入到所述信号恢复电路，所述信号恢复电路的输出信号输入到所述带限DPD系数提取电路，所述带限DPD系数提取电路的输出信号输入到所述数字预失真DPD模块；
    所述带限DPD系数提取电路，用于根据所述信号恢复电路的输出信号与第一输入信号，确定DPD系数，所述第一输入信号包括所述数字预失真DPD模块的输入信号或所述数字预失真DPD模块的输出信号。
  2. 根据权利要求1所述的数字预失真电路，其特征在于，所述信号恢复电路包括乘法器、扩频信号生成器、预带限滤波器和信号恢复器，其中，
    所述乘法器的输入信号包括所述功率放大器的输出信号和所述扩频信号生成器的输出信号，所述乘法器的输出信号输入到所述预带限滤波器，所述预带限滤波器的输出信号输入到所述信号恢复器，所述信号恢复器的输出信号输入到所述带限DPD系数提取电路。
  3. 根据权利要求2所述的数字预失真电路，其特征在于，所述电路还包括模数转换器，所述预带限滤波器的输出信号通过所述模数转换器输入到所述信号恢复器。
  4. 根据权利要求2或3所述的数字预失真电路，其特征在于，所述带限DPD系数提取电路包括加法器和带限DPD系数提取器，其中，
    所述加法器的输入信号包括所述数字预失真DPD模块的输出信号和所述带限DPD系数提取器的第一输出信号，所述加法器的输出信号输入到所述带限DPD系数提取器，所述带限DPD系数提取器的第二输出信号输入到所述数字预失真DPD模块，所述信号恢复器的输出信号输入到所述带限DPD系数提取器；
    所述带限DPD系数提取器，用于根据所述加法器的输出信号和所述信号恢复器的输出信号确定所述DPD系数。
  5. 根据权利要求2或3所述的数字预失真电路，其特征在于，所述带限DPD系数提取电路包括加法器和带限DPD系数提取器，其中，
    所述加法器的输入信号包括所述数字预失真DPD模块的输入信号和所述信号恢复器的输出信号，所述加法器的输出信号输入到所述带限DPD系数提取器，所述带限DPD系数提取器的输出信号输入到所述数字预失真DPD模块；
    所述带限DPD系数提取器，用于根据所述加法器的输出信号确定所述DPD系数。
  6. 根据权利要求3至5任一项所述数字预失真电路，其特征在于，所述模数转换器包括低速模数转换器。
  7. 根据权利要求2至6任一项所述数字预失真电路，其特征在于，所述预带限滤波器包括低通滤波器、高通滤波器或带通滤波器。
  8. 根据权利要求1至7任一项所述的数字预失真电路，其特征在于，所述电路还包括耦合器，所述功率放大器的输出信号通过所述耦合器输入到所述信号恢复电路。
  9. 根据权利要求1至8任一项所述的数字预失真电路，其特征在于，所述电路还包括数模转换器，所述数字预失真DPD模块的输出信号通过所述数模转换器输入到所述功率放 大器。
  10. 一种数字预失真系数获取方法，其特征在于，应用于数字预失真电路，所述电路包括数字预失真DPD模块、功率放大器、信号恢复电路和带限DPD系数提取电路，所述方法包括：
    所述数字预失真DPD模块对输入信号进行非线性校正，以得到所述数字预失真DPD模块输出信号；
    所述功率放大器对所述数字预失真DPD模块的输出信号进行放大，以得到所述功率放大器的输出信号；
    所述信号恢复信号电路对所述功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号；
    所述带限DPD系数提取电路根据所述信号恢复信号电路的输出信号和第一输入信号，确定DPD系数，以及将包括所述DPD系数的输出信号输入到所述数字预失真DPD模块，所述第一输入信号包括所述数字预失真DPD模块的输入信号或所述数字预失真DPD模块的输出信号。
  11. 根据权利要求10所述的方法，其特征在于，所述信号恢复电路包括乘法器、扩频信号生成器、预带限滤波器和信号恢复器，所述信号恢复信号电路对所述功率放大器的输出信号进行恢复，以得到信号恢复信号电路的输出信号包括：
    所述乘法器对所述功率放大器的输出信号和所述扩频信号生成器的输出信号进行乘法运算，以得到所述乘法器的输出信号；
    所述预带限滤波器对所述乘法器的输出信号进行滤波，以得到窄带信号；
    所述信号恢复器根据所述窄带信号进行恢复，以得到恢复后的信号，以及将所述恢复后的信号输入到所述带限DPD系数提取电路。
  12. 根据权利要求11所述的方法，其特征在于，所述电路还包括模数转换器，所述模数转换器对所述窄带信号进行模数转换，以得到数字信号，以及将所述数字信号输入到所述信号恢复器。
  13. 根据权利要求11或12所述的方法，其特征在于，所述带限DPD系数提取电路包括加法器和带限DPD系数提取器，所述第一输入信号为所述数字预失真DPD模块的输出信号，所述带限DPD系数提取电路根据所述信号恢复信号电路的输出信号和第一输入信号，确定DPD系数包括：
    所述加法器根据所述数字预失真DPD模块的输出信号和所述带限DPD系数提取器的第一输出信号进行加法运算，以得到所述加法器的输出信号；
    所述带限DPD系数提取器根据所述加法器的输出信号和所述信号恢复器的输出信号确定所述DPD系数。
  14. 根据权利要求11或12所述的方法，其特征在于，所述带限DPD系数提取电路包括加法器和带限DPD系数提取器，所述第一输入信号为所述数字预失真DPD模块的输入信号，所述带限DPD系数提取电路根据所述信号恢复信号电路的输出信号和第一输入信号，确定DPD系数，包括：
    所述加法器根据所述数字预失真DPD模块的输入信号和所述带限DPD系数提取器的第 一输出信号进行加法运算，以得到所述加法器的输出信号；
    所述带限DPD系数提取器根据所述加法器的输出信号确定所述DPD系数。
  15. 一种发射机，其特征在于，所述发射机包括天线和如权利要求1至9任一项所述的数字预失真电路。
  16. 一种芯片系统，其特征在于，所述芯片系统包括处理器，用于支持数字预失真电路实现如权利要求10至14任一项所述的方法。
  17. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序包括程序指令，所述程序指令当被处理器执行时使所述处理器执行如权利要求10至14任一项所述的方法。
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