WO2021169755A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2021169755A1
WO2021169755A1 PCT/CN2021/074936 CN2021074936W WO2021169755A1 WO 2021169755 A1 WO2021169755 A1 WO 2021169755A1 CN 2021074936 W CN2021074936 W CN 2021074936W WO 2021169755 A1 WO2021169755 A1 WO 2021169755A1
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WIPO (PCT)
Prior art keywords
sub
pixel
touch
array substrate
pixels
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Application number
PCT/CN2021/074936
Other languages
English (en)
French (fr)
Inventor
冯博
王世君
王洋
魏旃
穆文凯
刘屹
田丽
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21760015.4A priority Critical patent/EP4113205A4/en
Priority to US17/427,348 priority patent/US11934060B2/en
Publication of WO2021169755A1 publication Critical patent/WO2021169755A1/zh
Priority to US18/434,968 priority patent/US20240231139A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • the application relates to an array substrate and a display device.
  • a full-screen display device has a relatively high screen occupancy (generally reaching 80% or even more than 90%), so it can provide a larger size display screen without increasing the overall size of the display device.
  • the embodiment of the present application provides an array substrate and a display device. It can solve the technical problem of poor display effect of the existing array substrate prepared by the dual-gate line technology after being assembled into the liquid crystal display panel, and the technical solution is as follows:
  • an array substrate including:
  • the plurality of first extension parts and the plurality of second extension parts are alternately arranged one by one, and the extension direction of any two connected first extension parts and the extension direction of the second extension parts Intersect, and any two adjacent first extensions in the same data line and a second extension between the two adjacent first extensions form a bending structure, and the bending structure
  • the enclosed area includes at least one of the first pixel areas;
  • Two sub-pixels located in the first pixel area the two sub-pixels are arranged along the extending direction of the gate line, and the two sub-pixels are respectively adjacent to two of the first pixel area A data line is connected, and the sub-pixel is connected to one of the two gate lines adjacent to the sub-pixel;
  • the plurality of first pixel regions are also arranged in a plurality of columns, one column of the first pixel region includes two columns of the sub-pixels, the The touch signal line is located between the two columns of the sub-pixels in the first pixel area in the same column.
  • the plurality of first extension portions and the plurality of second extension portions in the same data line constitute a plurality of the bending structures, and the bending structures have openings and are arbitrarily adjacent to each other. The directions of the openings of the two bending structures are opposite.
  • the extension direction of the first extension is the same as the extension direction of the gate line
  • the extension direction of the second extension is perpendicular to the extension direction of the gate line
  • the extension of the touch signal line The direction is perpendicular to the extending direction of the gate line.
  • the orthographic projection of the first extension portion on the base substrate is staggered from the orthographic projection of the grid line on the substrate.
  • the first extension portion is located between the two gate lines between two adjacent rows of the first pixel regions.
  • the data line and the gate line further define a plurality of second pixel regions on the base substrate, and the plurality of second pixel regions are arranged in two columns, and the first The pixel area is located between the two columns of the second pixel area, and the array substrate further includes a sub-pixel located in the second pixel area.
  • the touch signal line includes: a first touch line segment and a second touch line segment arranged at intervals, the first touch line segment and the second touch line segment are arranged in different layers, and adjacent The first touch line segment is connected to the second touch line segment, the first touch line segment is arranged in the same layer as the data line, and the orthographic projection of the second touch line segment on the base substrate Cross with the orthographic projection of the data line on the base substrate.
  • the array substrate further includes: a first insulating layer located in the first touch line segment and the second touch line segment, the first insulating layer has a plurality of first via holes, adjacent The first touch line segment and the second touch line segment are connected by at least one of the first via holes.
  • the multiple touch signal lines are arranged in the same layer, and are arranged in a different layer from the data lines.
  • the array substrate further includes: a plurality of touch electrodes, and the plurality of touch electrodes are connected to the plurality of touch signal lines in a one-to-one correspondence.
  • the touch electrodes and the plurality of touch signal lines are arranged in different layers, and the array substrate further includes a second insulating layer located between the touch electrodes and the plurality of touch signal lines
  • the second insulating layer has a plurality of second via holes, and each of the touch electrodes and the corresponding touch signal line are connected through at least one of the second via holes.
  • the touch electrodes are reused for common electrodes in the array substrate, and the touch signal lines are reused for common electrode lines in the array substrate.
  • the touch electrodes are block-shaped electrodes
  • the sub-pixels include pixel electrodes
  • the orthographic projection of one touch electrode on the base substrate covers a plurality of pixel electrodes on the substrate. Orthographic projection on the bottom substrate.
  • multiple columns of the first pixel area correspond to the multiple touch signal lines one-to-one, and each of the touch signal lines is located in a column corresponding to the touch signal line
  • the array substrate includes: a first conductive layer, a gate insulating layer, an active layer, a second conductive layer, a pixel electrode layer, and a second conductive layer sequentially stacked in a direction perpendicular to and away from the base substrate.
  • the first conductive layer includes: the gate line and the gate
  • the second conductive layer includes: the data line, the first touch line segment, source and drain
  • the third conductive layer includes: the second touch line segment
  • the fourth conductive layer includes: the touch electrode
  • the array substrate includes: a first conductive layer, a gate insulating layer, an active layer, a second conductive layer, a pixel electrode layer, and a second conductive layer sequentially stacked in a direction perpendicular to and away from the base substrate.
  • the first conductive layer includes: the gate line and the gate
  • the second conductive layer includes: the data line, source and drain
  • the third conductive layer includes: the touch signal Line
  • the fourth conductive layer includes: touch electrodes.
  • the area enclosed by the bending structure includes a plurality of the first pixel regions, and the arrangement direction of the plurality of the first pixel regions is perpendicular to the extension direction of the gate line.
  • the two sub-pixels in the first pixel area are respectively: two sub-pixels among a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • the green sub-pixels and the blue sub-pixels are sequentially and periodically arranged, and the colors of the sub-pixels in the same column are the same.
  • the sub-pixel includes: a thin film transistor and a pixel electrode
  • the thin film transistor includes: a first electrode, a second electrode, and a gate; the first electrode is connected to one of the data lines, and the second The electrode is connected to the pixel electrode, and the gate is connected to one of the gate lines.
  • a display device including: any one of the above-mentioned array substrates, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate prepared by dual-gate line technology provided by related technologies
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by another embodiment of the application.
  • Figure 7 is a cross-sectional view of Figure 6 at A-A';
  • Figure 8 is a cross-sectional view of Figure 5 at A-A';
  • FIG. 9 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the full-screen display device is made of a liquid crystal display panel, it is necessary to adopt the dual gate technology to prepare the array substrate in the liquid crystal display panel.
  • FIG. 1 is a schematic structural diagram of an array substrate prepared by dual-gate line technology provided by the related art.
  • the array substrate 00 may include a plurality of data lines 01, a plurality of gate lines 02, and a plurality of sub-pixels 03, the gate lines 02 extend in a first direction x, and the data lines 01 extend in a second direction y.
  • the data line 01 and the gate line 02 can define a plurality of pixel regions 00a, and each pixel region 00a has two sub-pixels 03 arranged along the first direction x.
  • the plurality of pixel areas 00a may be arranged in multiple rows along the first direction x, and may also be arranged in multiple columns along the second direction y, and each column of the pixel area 00a includes two columns of sub-pixels 03.
  • Two gate lines 02 are arranged between any two adjacent rows of pixel regions 00a, and a data line 01 is arranged between any two adjacent columns of pixel regions 00a.
  • the array substrate prepared by the double-gate line technology reduces the number of data lines 01 by doubling the number of gate lines 02, so that the data leads that are electrically connected to the data lines 01 in the non-display area of the array substrate.
  • the liquid crystal display panel is prone to shaking head patterns during display, and the reasons are as follows:
  • the two sub-pixels 03 are respectively connected to the two adjacent gate lines 02 of the pixel area 00a, and are also connected to the pixels respectively.
  • Two adjacent data lines 01 in the area 00a are connected.
  • the two sub-pixels 03 are two of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B, respectively.
  • the sub-pixels in the same row are periodically arranged in the order of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B, and the sub-pixels in the same column are all the first sub-pixel R, the second sub-pixel G, or the third sub-pixel B .
  • the first sub-pixel R can emit red light
  • the second sub-pixel G can emit green light
  • the third sub-pixel B can emit blue light. .
  • the liquid crystal display panel displays images, it is necessary to ensure that the voltage polarities of any two adjacent data lines in the array substrate 00 are opposite. Therefore, the voltage polarities of the two sub-pixels 03 in the same pixel area 00a are opposite, and the voltage polarities of the sub-pixels 03 in the same column are the same. In this way, spatially, in each row of pixel regions, the voltage polarity of all the first sub-pixels R is arranged in a cycle of "+--+", and the voltage polarity of all the second sub-pixels G is "++--" ”, the voltage polarity of all third sub-pixels B is cyclically arranged with “-++-”.
  • the probability that the voltage polarity between any two adjacent sub-pixels is the same is nearly 50%, and for each column of sub-pixels, the voltage polarity of each sub-pixel is the same.
  • the voltage polarity of the same seed pixel in the same frame of image is averaged, and visually, there will be bright and dark stripes, which also presents the undesirable phenomenon of shaking head patterns.
  • the display effect of the liquid crystal display panel is poor.
  • the array substrate 100 may include a base substrate 10, a plurality of gate lines 20, a plurality of data lines 30 and a plurality of sub-pixels 40 on the base substrate 10.
  • the gate line 20 and the data line 30 can define a plurality of first pixel regions 10 a on the base substrate 10.
  • the plurality of first pixel regions 10a may be arranged in multiple rows or in multiple columns. Wherein, two gate lines 20 are arranged between any two adjacent rows of first pixel regions 10a.
  • the data line 30 has a plurality of first extending portions 301 and a plurality of second extending portions 302 connected, and the plurality of first extending portions 301 and the plurality of second extending portions are alternately arranged one by one.
  • the extension direction of any two connected first extension portions 301 and the extension direction of the second extension portion 302 intersect.
  • Any two adjacent first extension portions 301 and the second extension portion 302 between the two adjacent first extension portions 301 in the same data line 30 constitute a bending structure 303, and the bending structure 303
  • the enclosed area 303a may include at least one first pixel area 10a. For example, as shown in FIG. 2, FIG.
  • FIG. 2 schematically illustrates an example in which the area 303 a enclosed by the bending structure 303 includes a first pixel area 10 a.
  • FIG. 3 schematically illustrates an example in which the area 303a enclosed by the bending structure 303 includes four first pixel areas 10a. It should be noted that when the area 303a enclosed by the bending structure 303 includes a plurality of first pixel regions 10a, the arrangement direction of the plurality of first pixel regions 10a may be perpendicular to the extending direction of the gate line 20.
  • Two sub-pixels 40 are arranged in each first pixel area 10a along the extending direction of the gate line 20, and the two sub-pixels 40 are respectively connected to two adjacent data lines 30 of the first pixel area 10a, and each sub-pixel 40 is connected to one of the two gate lines 20 adjacent to the sub-pixel 40.
  • the two sub-pixels 40 are two of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B.
  • the sub-pixels in the same row are periodically arranged in the order of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B, and the sub-pixels in the same column are all the first sub-pixel R, the second sub-pixel G, or the third sub-pixel B .
  • the first sub-pixel R can emit red light
  • the second sub-pixel G can emit green light
  • the third sub-pixel B can emit blue light. .
  • the first sub-pixel R may also be referred to as a red sub-pixel
  • the second sub-pixel G may also be referred to as a green sub-pixel
  • the third sub-pixel B may also be referred to as a blue sub-pixel.
  • the colors of the sub-pixels in the same column are the same.
  • the array substrate 100 is assembled in a liquid crystal display panel.
  • any two adjacent data lines 30 among the plurality of data lines 30 in the array substrate 100 need to be loaded with polarity. Opposite voltage. In this way, even for the same seed pixel in the first pixel area of each row, the probability of the voltage polarity between any two adjacent sub-pixels is still close to 50%. However, in each column of sub-pixels, they belong to two sub-pixels. The voltage polarities between two sub-pixels in adjacent first pixel regions 10a are opposite.
  • the voltage polarity between any two adjacent sub-pixels 40 in each column of sub-pixels is opposite.
  • the voltage polarity of the same seed pixel in the same frame of image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head patterns, and effectively improving the display effect of the liquid crystal display panel.
  • the above-mentioned array substrate 100 may further include: a plurality of touch signal lines 50 located on the base substrate 10.
  • Each column of the first pixel regions 10a in the plurality of columns of first pixel regions 10a includes two columns of sub-pixels 40, and the touch signal line 50 is located between the two columns of sub-pixels 40 in the same column of the first pixel regions 10a.
  • the liquid crystal display panel prepared by using the array substrate 100 has a touch function. In this way, it is possible to enable the liquid crystal display panel to have the touch function without separately assembling the touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with the touch function.
  • the array substrate provided by the embodiments of the present application includes a base substrate, and multiple gate lines, multiple data lines, multiple sub-pixels, and multiple touch signal lines on the base substrate.
  • the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel performs display, even for the same seed pixel in the first pixel area of each row, the probability that the voltage polarity between any two adjacent sub-pixels is the same It is still nearly 50%, but in each column of sub-pixels, the voltage polarities between the two sub-pixels belonging to two adjacent first pixel regions are opposite.
  • the voltage polarity of the same seed pixel in the same frame of image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head patterns, and effectively improving the display effect of the liquid crystal display panel.
  • the liquid crystal display panel can be provided with a touch function without separately assembling the touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with the touch function.
  • FIG. 4 is a schematic structural diagram of another array substrate provided by the embodiment of the present application.
  • the data line 30 and the gate line 20 may also define a plurality of second pixel regions 10b on the base substrate 10.
  • the plurality of second pixel regions 10b are arranged in two columns, and the plurality of columns of first pixel regions 10a are located between the two columns of second pixel regions 10b.
  • a sub-pixel 40 is arranged in each second pixel region 10b, and the sub-pixel 40 is connected to a data line 30, and the sub-pixel 40 is connected to one of the two adjacent gate lines 20.
  • the plurality of data lines 30 in the array substrate 100 can be divided into a plurality of first data lines 30a and two data lines 30b, and the plurality of first data lines 30a are located between the two second data lines 30b.
  • each second extension portion 302 can connect two adjacent sub-pixels 40, and the two adjacent sub-pixels 40 are located in two different first data lines.
  • a pixel area 10a Within a pixel area 10a.
  • a part of the second extension portion 302 is connected to two adjacent sub-pixels 40, and one of the two adjacent sub-pixels 40 is located in the first pixel In the area 10a, the other is located in the second pixel area 10b; the other second extension portion 302 is not connected to the sub-pixel 40.
  • the second extension portion 302 connected to the sub-pixel 40 and the second extension portion 302 not connected to the sub-pixel 40 are alternately arranged.
  • the length of the first extension 301 in the first data line 30a needs to be greater than the length of the first extension 301 in the second data line 30b.
  • the length of the first extension 301 in the first data line 30a is greater than the total width of two adjacent sub-pixels 40; and the length of the first extension 301 in the second data line 30b is greater than the width of one sub-pixel 40 , But less than the total width of two adjacent sub-pixels 40.
  • the length direction of the first extension portion 301 is parallel to the width direction of the sub-pixel 40.
  • FIG. 5 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • the multiple first extension portions 301 and the multiple second extension portions 302 in the same data line 30 can form multiple bending structures 303.
  • Each bending structure 303 has an opening 303b, and the directions of the openings 303b of any two adjacent bending structures 303 are opposite.
  • the nth data line, the n+1th data line, and the n+2th data line are three adjacent data lines 30.
  • the first extension A1 and the second The opening 303b of the bending structure formed by the extension B1 and the first extension A2 faces the n+2th data line, and the bending formed by the first extension A2, the second extension B2, and the first extension A3
  • the opening 303b of the structure faces the nth data line.
  • the extension direction of the first extension portion 301 in the data line 30 is the same as the extension direction of the gate line 20, and the extension direction of the second extension portion 302 in the data line 30 is perpendicular to the extension direction of the gate line 20. Since the extending direction of the gate line 20 is generally parallel to the row direction of the plurality of first pixel regions 10a (that is, the first direction x), and perpendicular to the column direction of the plurality of first pixel regions 10a (that is, the second direction y) . Therefore, the first extension 301 may extend in the first direction x, and the second extension 302 may extend in the second direction y.
  • the first extension 301 in the data line 30 is located between the two gate lines 20 between two adjacent rows of first pixel regions, and the second extension 302 is on the base substrate 10
  • the orthographic projection of the grid line 20 is staggered from the orthographic projection of the grid line 20 on the base substrate. In this way, the parasitic capacitance generated between the data line 30 and the gate line 20 can be effectively reduced.
  • each sub-pixel 40 may include: a thin film transistor 401 and a pixel electrode 402.
  • the pixel electrode 402 may be an electrode made of a transparent conductive material.
  • the thin film transistor 401 may include a first electrode, a second electrode and a gate electrode.
  • the first electrode can be connected to a data line 30, the gate can be connected to a gate line 20, and the second electrode can be connected to the pixel electrode 402.
  • the first electrode is one of the source and the drain, and the second electrode is the other of the source and the drain.
  • each bending structure 303 includes a first pixel area 10a.
  • the nth data line is in accordance with the first sub-pixel R, the third sub-pixel B, the first sub-pixel R, and the second sub-pixel.
  • the sequence of the sub-pixel G periodically drives the two columns of sub-pixels connected to it; the n+1th data line is periodically cycled in the sequence of the third sub-pixel B, the second sub-pixel G, the first sub-pixel R, and the third sub-pixel B
  • the two columns of sub-pixels connected to it are driven linearly; the n+2th data line is periodically driven in the order of the first sub-pixel R, the second sub-pixel G, the third sub-pixel B, and the second sub-pixel G. Two columns of sub-pixels.
  • FIG. 6 is a schematic structural diagram of another array substrate provided by another embodiment of the application.
  • the touch signal line 50 in the array substrate 100 includes: a first touch line segment 501 and a second touch line segment 502 arranged at intervals.
  • the extension direction of the first touch line segment 501 is the same as the extension direction of the second touch line segment 502, and the adjacent first touch line segment 501 and the second touch line segment 502 are connected.
  • the first touch line segment 501 and the data line 30 are arranged in the same layer, and the orthographic projection of the first touch line segment 501 on the base substrate 10 and the orthographic projection of the data line 30 on the base substrate 10 are staggered.
  • the orthographic projection of the second touch line segment 502 on the base substrate 10 crosses the orthographic projection of the data line 30 (the first extension 301 in the data line 30) on the base substrate 10. Therefore, in order to avoid a short circuit between the touch signal line 50 and the data line 30, it is necessary to ensure that the second touch line 502 and the data line 50 are arranged in different layers, that is, the second touch line segment 502 and the first touch The line segment 501 is arranged in different layers.
  • the arrangement of the first touch line segment 501 and the data line 30 in the same layer means that the first touch line segment 501 and the data line 30 are formed by the same patterning process.
  • the arrangement of the second touch line 502 and the data line 50 in different layers means that the second touch line 502 and the data line 50 are not in the same film layer, and there is an insulating layer between the second touch line 502 and the data line 50 .
  • the array substrate 100 may further include: a first insulating layer 60 located between the first touch line segment 501 and the second touch line segment 502.
  • the first insulating layer 60 has a plurality of first via holes 601, and adjacent first touch line segments 501 and second touch line segments 502 are connected by at least one first via hole 601.
  • the material of the second touch line segment 502 may include a transparent conductive material. In this way, the aperture ratio of each sub-pixel 30 can be increased.
  • the multiple touch signal lines 50 in the array substrate 100 are arranged in the same layer, and the touch signal lines 50 and the data lines 30 are arranged in different layers.
  • the arrangement of the multiple touch signal lines 50 in the same layer refers to: the multiple touch signal lines 50 are formed through the same patterning process; the touch signal lines 50 and the data lines 30 are arranged in different layers. It is: the touch signal line 50 and the data line 30 are not in the same film layer, and there is an insulating layer between the touch signal line 50 and the data line 30.
  • Fig. 8 is a cross-sectional view of Fig. 5 at A-A'.
  • the array substrate 100 may further include: a first insulating layer 60 located between the touch signal line 50 and the data line 30.
  • the material of the touch signal line 50 may include a metal material. Since the touch signal line 50 and the data line 30 are arranged in different layers in the second achievable manner, there is no need to provide the first via hole on the first insulating layer 60. In this way, the aperture ratio of each sub-pixel 30 can be increased.
  • the material of the touch signal line 50 in the second achievable manner is a metal material, it has higher conductivity and lower resistivity than the transparent conductive material, which effectively improves the touch signal line
  • the signal amount of the touch signal in 50 further improves the touch performance of the array substrate 100.
  • the array substrate 100 may further include a plurality of touch electrodes 70.
  • the multiple touch electrodes 70 are connected to the multiple touch signal lines 50 in a one-to-one correspondence.
  • the touch electrode 70 may be an electrode made of a transparent conductive material. It should be noted that the touch mode in the array substrate 100 in the present application belongs to self-capacitive touch, and the related touch principle can refer to the related technology, which will not be repeated here.
  • the touch electrode 70 and the multiple touch signal lines 50 are arranged in different layers. It should be noted that the arrangement of the touch electrode 70 and the multiple touch signal lines 50 in different layers means that the touch electrode 70 and the multiple touch signal lines 50 are not in the same film layer, and the touch electrode 70 and the multiple touch signal lines 50 are not in the same layer. There is an insulating layer between the plurality of touch signal lines 50.
  • the array substrate 100 may further include a second insulating layer 80 between the touch electrode 70 and the plurality of touch signal lines 50.
  • the second insulating layer 80 has a plurality of second via holes 801, and each touch The control electrode 70 and the corresponding touch signal line 50 are connected through at least one second via 801.
  • each touch electrode 70 is a block-shaped electrode, and the orthographic projection of each touch electrode 70 on the base substrate 10 covers the orthographic projection of a plurality of pixel electrodes 402 on the base substrate 10.
  • the orthographic projection of each touch electrode 70 on the base substrate covers j ⁇ j pixel electrodes 402.
  • the array substrate 100 may further include: a common electrode and a common electrode line.
  • the touch electrode 70 in the array substrate 100 can be reused for the common electrode
  • the touch signal line 50 in the array substrate 100 can be reused for the common electrode line. That is, the touch electrode 70 and the common electrode in the array substrate 100 are the same electrode, and the touch signal line 50 and the common electrode line are the same signal line.
  • the liquid crystal display panel prepared by using the array substrate 100 if the liquid crystal display panel is required to display, it is necessary to load a common electrode signal on the touch signal line 50, so that the touch electrode 70 can be formed with the pixel electrode 402.
  • the extension direction of the touch signal line 50 is perpendicular to the extension direction of the gate line 20. That is, the touch signal line 50 extends along the second direction y.
  • multiple columns of first pixel regions 10a correspond to multiple touch signal lines 50 one-to-one, and each touch signal line 50 is located in a column corresponding to the touch signal line 50 Between two columns of sub-pixels 40 in the first pixel area 10a.
  • the array substrate 100 includes: a first conductive layer, a gate insulating layer 90, an active layer (not shown in the figure), a second conductive layer, and a pixel electrode, which are sequentially stacked in a direction perpendicular to and away from the base substrate 10. Layer, a first insulating layer 60, a third conductive layer, a second insulating layer 80, and a fourth conductive layer.
  • the first conductive layer includes: the gate line 20 and the gate of the thin film transistor 402; the second conductive layer includes: the data line 30, the first touch line segment 501, and the source and drain of the thin film transistor 402;
  • the pixel electrode layer includes: a plurality of pixel electrodes 401; the third conductive layer includes: a second touch line segment 502; and the fourth conductive layer includes: a touch electrode 70.
  • the array substrate 100 includes: a first conductive layer, a gate insulating layer 90, an active layer (not shown in the figure), a second conductive layer, and a pixel electrode, which are sequentially stacked in a direction perpendicular to and away from the base substrate 10. Layer, a first insulating layer 60, a third conductive layer, a second insulating layer 80, and a fourth conductive layer.
  • the first conductive layer includes: the gate line 20 and the gate of the thin film transistor 402; the second conductive layer includes: the data line 30 and the source and drain of the thin film transistor 402; the third conductive layer includes: the touch signal line 50; The fourth conductive layer includes: touch electrodes 70.
  • the array substrate provided by the embodiments of the present application includes a base substrate, and multiple gate lines, multiple data lines, multiple sub-pixels, and multiple touch signal lines on the base substrate.
  • the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel performs display, even for the same seed pixel in the first pixel area of each row, the probability that the voltage polarity between any two adjacent sub-pixels is the same It is still nearly 50%, but in each column of sub-pixels, the voltage polarities between the two sub-pixels belonging to two adjacent first pixel regions are opposite.
  • the voltage polarity of the same seed pixel in the same frame of image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head patterns, and effectively improving the display effect of the liquid crystal display panel.
  • the liquid crystal display panel can be provided with a touch function without separately assembling the touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with the touch function.
  • the embodiment of the present application also provides a manufacturing method of an array substrate, and the manufacturing method of the array substrate is used to manufacture the array substrate 100 shown in FIG. 2, FIG. 3, FIG. 4, FIG. 5, or FIG.
  • the manufacturing method of the array substrate 100 may include:
  • a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a plurality of touch signal lines are formed on the base substrate.
  • the data line and the gate line define a plurality of first pixel regions on the base substrate.
  • the plurality of first pixel regions are arranged in multiple rows, and two gate lines are arranged between any two adjacent rows of first pixel regions.
  • the data line has a plurality of first extension portions and a plurality of second extension portions connected, and the plurality of first extension portions and the plurality of second extension portions are alternately arranged one by one.
  • the extension direction of any two connected first extension portions intersects the extension direction of the second extension portion.
  • any two adjacent first extensions in the same data line and a second extension between two adjacent first extensions constitute a bending structure, and the area enclosed by the bending structure includes at least A first pixel area. Any two adjacent data lines are used to load voltages with opposite polarities.
  • Two sub-pixels are arranged in each first pixel area along the extending direction of the gate line, and the two sub-pixels are respectively connected to two data lines adjacent to the first pixel area, and each sub-pixel is connected to two adjacent sub-pixels.
  • One of the gate lines is connected.
  • the plurality of first pixel regions are also arranged in multiple columns, each column of the first pixel region includes two columns of sub-pixels, and the touch signal line is located between the two columns of sub-pixels in the same column of the first pixel region.
  • a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a plurality of touch signal lines are formed on a base substrate.
  • the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel performs display, even for the same seed pixel in the first pixel area of each row, the probability that the voltage polarity between any two adjacent sub-pixels is the same It is still nearly 50%, but in each column of sub-pixels, the voltage polarities between the two sub-pixels belonging to two adjacent first pixel regions are opposite.
  • the voltage polarity of the same seed pixel in the same frame of image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head patterns, and effectively improving the display effect of the liquid crystal display panel.
  • the liquid crystal display panel can be provided with a touch function without separately assembling the touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with the touch function.
  • FIG. 9 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present application.
  • the manufacturing method of the array substrate is used to manufacture the array substrate shown in FIG. 5 or FIG. 6.
  • the manufacturing method of the array substrate may include:
  • Step S1 forming a first conductive layer, a gate insulating layer and an active layer on the base substrate.
  • the material of the first conductive layer may include metallic materials such as metallic molybdenum (abbreviated as: Mo), metallic copper (abbreviated as: Cu), metallic aluminum (abbreviated as: Al), or alloys.
  • the material of the gate insulating layer may include silicon dioxide, silicon nitride, or a mixed material of silicon dioxide and silicon nitride.
  • the material of the active layer may include polysilicon.
  • the first conductive material layer can be formed on the base substrate by any of a variety of methods such as deposition, coating, sputtering, etc., and a patterning process is performed on the first conductive material layer to form the first conductive material layer.
  • the first conductive layer may include a gate electrode and a gate line.
  • a gate insulating layer and an active material layer are sequentially formed on the base substrate on which the first conductive layer is formed by deposition, coating, sputtering, etc., and the active material layer A patterning process is performed once to form the active layer.
  • Step S2 forming a second conductive layer and a pixel electrode layer on the active layer.
  • the material of the second conductive layer may include: metallic materials such as metallic Mo, metallic copper Cu, metallic aluminum Al or alloys.
  • the material of the pixel electrode layer may include: a transparent conductive material, for example, it may be ITO.
  • the second electrode material layer can be formed on the active layer by any of a variety of methods such as deposition, coating, sputtering, etc., and a patterning process is performed on the second conductive material layer to form a second electrode material layer.
  • the second conductive layer may include a source electrode, a drain electrode, and a data line.
  • the pixel electrode material layer can be formed on the second conductive layer by any of a variety of methods such as deposition, coating, sputtering, and the pixel electrode material layer is subjected to a patterning process to form the pixel electrode layer.
  • the pixel electrode layer may include: a plurality of pixel electrodes.
  • Step S3 forming a first insulating layer and a third conductive layer on the pixel electrode layer.
  • the first insulating layer may also be referred to as a flat layer, and its material may include materials such as acrylic resin or epoxy resin.
  • the material of the third conductive layer includes a transparent conductive material, for example, it may be ITO.
  • the second conductive layer formed in step S2 further includes: a first touch line segment.
  • the first insulating layer can be formed on the pixel electrode layer by any of a variety of methods such as deposition, coating, and sputtering, and a patterning process is performed on the first insulating layer to form a first insulating layer with multiple first passes. The first insulating layer of the hole.
  • a third conductive material layer can be formed on the base substrate on which the first insulating layer is formed by deposition, coating, sputtering, etc., and the third conductive material layer can be patterned once.
  • the process forms a third conductive layer.
  • the third conductive layer may include: a second touch line segment, and the second touch line segment can be connected to the first touch line segment through at least one first via hole, and the second touch line segment and the first touch line segment can be Form the touch signal line.
  • the material of the third conductive layer includes: such as metal Mo, metal copper Cu, metal aluminum Al or Metal materials such as alloys.
  • the first insulating layer and the third conductive material layer can be sequentially formed on the pixel electrode layer by any of a variety of methods such as deposition, coating, and sputtering, and the third conductive material layer can be The material layer undergoes a patterning process to form a third conductive layer.
  • the third conductive layer may include: touch signal lines.
  • Step S4 forming a second insulating layer and a fourth conductive layer on the third conductive layer.
  • the second insulating layer may also be referred to as a flat layer, and its material may include materials such as acrylic resin or epoxy resin.
  • the material of the fourth conductive layer includes: a transparent conductive material, for example, it may be ITO.
  • the second insulating layer and the fourth conductive material layer can be sequentially formed on the third conductive layer by any of a variety of methods such as deposition, coating, and sputtering, and the fourth conductive material layer A patterning process is performed once to form the fourth conductive layer.
  • the third conductive layer may include: touch electrodes.
  • each patterning process in the foregoing embodiment may include: photoresist coating, exposure, development, etching, and photoresist stripping.
  • a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels, and a plurality of touch signal lines are formed on a base substrate.
  • the array substrate is used to prepare a liquid crystal display panel, if the liquid crystal display panel performs display, even for the same seed pixel in the first pixel area of each row, the probability that the voltage polarity between any two adjacent sub-pixels is the same It is still nearly 50%, but in each column of sub-pixels, the voltage polarities between the two sub-pixels belonging to two adjacent first pixel regions are opposite.
  • the voltage polarity of the same seed pixel in the same frame of image can be effectively averaged on a spatial scale, thereby reducing the probability of shaking head patterns, and effectively improving the display effect of the liquid crystal display panel.
  • the liquid crystal display panel can be provided with a touch function without separately assembling the touch panel on the liquid crystal display panel, which effectively reduces the thickness of the liquid crystal display panel with the touch function.
  • the embodiment of the present application also provides a display device.
  • the display device may be a liquid crystal display device, which includes a liquid crystal display panel.
  • the liquid crystal display panel may include: the array substrate shown in FIG. 2, FIG. 3, FIG. 4, FIG. 5, or FIG. 6, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.
  • the display device can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, or wearable device.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device includes the above-mentioned liquid crystal display panel, and the display area of the liquid crystal display panel includes sub-pixel regions Px arranged in rows and columns.
  • the data line in the above-mentioned display area may be between two adjacent sub-pixel areas Px to transmit the accessed data signal to each sub-pixel area Px.

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Abstract

一种阵列基板（100）及显示装置，阵列基板（100）包括：衬底基板（10），以及位于衬底基板（10）上的多条栅线（20）、多条数据线（30）、多个子像素（40）和多条触控信号线（50）。数据线（30）具有交替排布的多个第一延伸部（301）和多个第二延伸部（302）。当采用阵列基板（100）制备液晶显示面板时，若液晶显示面板进行显示，在每列子像素（40）中，分别属于两个相邻的第一像素区域中的两个子像素（40）间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素（40）的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了液晶显示面板的显示效果。

Description

阵列基板及显示装置
本申请要求于2020年02月28日提交的申请号为202010127377.9、发明名称为“阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种阵列基板及显示装置。
背景技术
全面屏显示装置由于其屏占比较高(一般能够达到80％甚至90％以上)，因此能够在不增加显示装置整体尺寸的前提下，提供更大尺寸的显示屏幕。
发明内容
本申请实施例提供了一种阵列基板及显示装置。可以解决现有的采用双栅线技术制备的阵列基板在装配到液晶显示面板中后，该液晶显示面板的显示效果较差的技术问题，所述技术方案如下：
一方面，提供了一种阵列基板，包括：
衬底基板；
位于所述衬底基板上的多条栅线和多条数据线，所述数据线与所述栅线在所述衬底基板上限定出多个第一像素区域，所述多个第一像素区域排布为多行，且任意相邻的两行第一像素区域之间排布有两条所述栅线，所述数据线具有相连接的多个第一延伸部和多个第二延伸部，所述多个第一延伸部和所述多个第二延伸部一一交替排布，任意两个相连接的所述第一延伸部的延伸方向与所述第二延伸部的延伸方向相交，且同一条所述数据线中任意相邻的两个第一延伸部与所述相邻的两个第一延伸部之间的第二延伸部构成一个折弯结构，所述折弯结构所围成的区域包括至少一个所述第一像素区域；
位于所述第一像素区域内的两个子像素，所述两个子像素沿所述栅线的延伸方向排布，且所述两个子像素分别与所述第一像素区域相邻的两条所述数据 线连接，所述子像素与所述子像素相邻的两条所述栅线中的一条所述栅线连接；
以及，位于所述衬底基板上的多条触控信号线，所述多个第一像素区域还排布为多列，一列所述第一像素区域中包括两列所述子像素，所述触控信号线位于同一列所述第一像素区域中的两列所述子像素之间。
可选的，同一条所述数据线中所述多个第一延伸部和所述多个第二延伸部构成多个所述折弯结构，所述折弯结构具有开口，且任意相邻的两个所述折弯结构的开口的方向相反。
可选的，所述第一延伸部的延伸方向与所述栅线的延伸方向相同，所述第二延伸部的延伸方向与所述栅线的延伸方向垂直，所述触控信号线的延伸方向与所述栅线的延伸方向垂直。
可选的，所述第一延伸部在所述衬底基板上的正投影与所述栅线在所述衬底上的正投影错开。
可选的，所述第一延伸部位于相邻的两行所述第一像素区域之间的两条所述栅线之间。
可选的，所述数据线与所述栅线还在所述衬底基板上限定出多个第二像素区域，所述多个第二像素区域排布为两列，多列所述第一像素区域位于两列所述第二像素区域之间，所述阵列基板还包括位于所述第二像素区域内的一个子像素。
可选的，所述触控信号线包括：间隔排布的第一触控线段和第二触控线段，所述第一触控线段和所述第二触控线段异层设置，相邻的所述第一触控线段与所述第二触控线段连接，所述第一触控线段与所述数据线同层设置，所述第二触控线段在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影交叉。
可选的，所述阵列基板还包括：位于所述第一触控线段和所述第二触控线段的第一绝缘层，所述第一绝缘层具有多个第一过孔，相邻的所述第一触控线段与所述第二触控线段通过至少一个所述第一过孔连接。
可选的，所述多条触控信号线同层设置，且与所述数据线异层设置。
可选的，所述阵列基板还包括：多个触控电极，所述多个触控电极与所述多条触控信号线一一对应连接。
可选的，所述触控电极与所述多条触控信号线异层设置，所述阵列基板还 包括位于所述触控电极与所述多条触控信号线之间的第二绝缘层，所述第二绝缘层具有多个第二过孔，每个所述触控电极和对应的触控信号线通过至少一个所述第二过孔连接。
可选的，所述触控电极复用于所述阵列基板中的公共电极，所述触控信号线复用于所述阵列基板中的公共电极线。
可选的，所述触控电极为块状的电极，所述子像素包括像素电极，一个所述触控电极在所述衬底基板上的正投影覆盖多个所述像素电极在所述衬底基板上的正投影。
可选的，多列所述第一像素区域与所述多条触控信号线一一对应，每条所述触控信号线位于与所述触控信号线对应的一列
所述第一像素区域中的两列子像素之间。
可选的，所述阵列基板包括：沿垂直且远离所述衬底基板的方向依次叠层设置的第一导电层、栅极绝缘层、有源层、第二导电层、像素电极层、第一绝缘层、第三导电层、第二绝缘层和第四导电层；
其中，所述第一导电层包括：所述栅线和栅极，所述第二导电层包括：所述数据线、所述第一触控线段、源极和漏极，所述第三导电层包括：所述第二触控线段，所述第四导电层包括：触控电极。
可选的，所述阵列基板包括：沿垂直且远离所述衬底基板的方向依次叠层设置的第一导电层、栅极绝缘层、有源层、第二导电层、像素电极层、第一绝缘层、第三导电层、第二绝缘层和第四导电层；
其中，所述第一导电层包括：所述栅线和栅极，所述第二导电层包括：所述数据线、源极和漏极，所述第三导电层包括：所述触控信号线，所述第四导电层包括：触控电极。
可选的，所述折弯结构所围成的区域包括多个所述第一像素区域，且多个所述第一像素区域的排布方向与所述栅线的延伸方向垂直。
可选的，所述第一像素区域内的两个子像素分别为：红色子像素、绿色子像素和蓝色子像素中的两个子像素，同一行所述子像素按照所述红色子像素、所述绿色子像素和所述蓝色子像素的顺序周期排布，同一列所述子像素的颜色相同。
可选的，所述子像素包括：薄膜晶体管和像素电极，所述薄膜晶体管包括： 第一极、第二极和栅极，所述第一极与一条所述数据线连接，所述第二极与所述像素电极连接，所述栅极与一条所述栅线连接。
另一方面，提供了一种显示装置，包括：上述任一所述阵列基板、彩膜基板以及位于所述阵列基板和所述彩膜基板之间的液晶层。
附图说明
图1是相关技术提供的一种采用双栅线技术制备的阵列基板的结构示意图；
图2是本申请实施例提供的一种阵列基板的结构示意图；
图3是本申请实施例提供的另一种阵列基板的结构示意图；
图4是本申请实施例提供的又一种阵列基板的结构示意图；
图5是本申请另一实施例提供的一种阵列基板的结构示意图；
图6本是申请另一实施例提供的另一种阵列基板的结构示意图；
图7是图6在A-A’处的截面图；
图8是图5在A-A’处的截面图；
图9是本申请实施例提供的一种阵列基板的制造方法的流程图；
图10是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
目前，若全面屏显示装置采用液晶显示面板制备，则需要采用双栅线(Dual Gate)技术制备液晶显示面板中的阵列基板。
请参考图1，图1是相关技术提供的一种采用双栅线技术制备的阵列基板的结构示意图。该阵列基板00可以包括：多条数据线01、多条栅线02和多个子像素03，该栅线02沿第一方向x延伸，数据线01沿第二方向y延伸。该数据线01与栅线02能够限定出多个像素区域00a，每个像素区域00a内沿第一方向x排布有两个子像素03。该多个像素区域00a可以沿第一方向x排布为多行，且也可以沿第二方向y排布为多列，每列像素区域00a中包括两列子像素03。任意相邻的两行像素区域00a之间排布有两条栅线02，任意相邻的两列像素区域00a之间排布有一条数据线01。
采用双栅线技术制备的阵列基板，通过增加一倍数量的栅线02，以减少数据线01的数量，使得位于该阵列基板中的非显示区域内的与该数据线01电连接的数据引线的数量较少，进而使得该阵列基板中的非显示区域的宽度较小，以保证采用该阵列基板制备出的液晶显示面板的屏占比较高。
然而，采用双栅线技术制备的阵列基板在装配到液晶显示面板中后，该液晶显示面板在显示时极易出现摇头纹的现象，原因如下：
在采用双栅线技术制备的阵列基板中，对于同一个像素区域00a内的两个子像素03，该两个子像素03分别与像素区域00a相邻的两条栅线02连接，且还分别与像素区域00a相邻的两条数据线01连接。该两个子像素03分别为第一子像素R、第二子像素G和第三子像素B中的两种。同一行子像素按照第一子像素R、第二子像素G和第三子像素B的顺序周期排布，同一列子像素都为第一子像素R、第二子像素G或第三子像素B。示例的，假设该阵列基板00装配到液晶显示面板中，则该第一子像素R能够发出红色的光线，第二子像素G能够发出绿色的光线，第三子像素B能够发出蓝色的光线。
由于液晶显示面板在显示画面时，需要保证阵列基板00中的任意相邻的两条数据线的电压极性相反。因此，同一像素区域00a内的两个子像素03的电压极性相反，且同一列子像素03的电压极性相同。如此，在空间上，每一行像素区域中，所有第一子像素R的电压极性为“+--+”的循环排布，所有第二子像素G的电压极性为“++--”的循环排布，所有第三子像素B的电压极性为“-++-”的循环排布。对于每行像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率近乎50％，并且对于每列子像素而言，每个子像素的电压极性均相同，无法在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，在视觉上会出现的亮暗相间的条纹，也就呈现出摇头纹的不良现象。
因此，采用双栅线技术制备的阵列基板在装配到液晶显示面板中后，该液晶显示面板的显示效果较差。
请参考图2，图2是本申请实施例提供的一种阵列基板的结构示意图。该阵列基板100可以包括：衬底基板10，位于衬底基板10上的多条栅线20、多条数据线30和多个子像素40。
栅线20与数据线30在衬底基板10上能够限定出多个第一像素区域10a。 该多个第一像素区域10a可以排布为多行，也可以排布为多列。其中，任意相邻的两行第一像素区域10a之间排布有两条栅线20。
数据线30具有相连接的多个第一延伸部301和多个第二延伸部302，该多个第一延伸部301和多个第二延伸部一一交替排布。任意两个相连接的该第一延伸部301的延伸方向与第二延伸部302的延伸方向相交。同一条数据线30中任意相邻的两个第一延伸部301与该相邻的两个第一延伸部301之间的第二延伸部302构成一个折弯结构303，该折弯结构303所围成的区域303a可以包括至少一个第一像素区域10a。示例的，如图2所示，图2是以该折弯结构303所围成的区域303a包括一个第一像素区域10a为例进行示意性说明的。在其他可选的实现方式中，如图3所示，图3是以该折弯结构303所围成的区域303a包括4个第一像素区域10a为例进行示意性说明的。需要说明的是，当折弯结构303所围成的区域303a包括多个第一像素区域10a时，该多个第一像素区域10a的排布方向可以与栅线20的延伸方向垂直。
每个第一像素区域10a内沿栅线20的延伸方向排布有两个子像素40，且该两个子像素40分别与该第一像素区域10a相邻的两条数据线30连接，每个子像素40与该子像素40相邻的两条栅线20中的一条栅线20连接。
在本申请实施例中，对于同一个第一像素区域10a内的两个子像素40，该两个子像素40为第一子像素R、第二子像素G和第三子像素B中的两种。同一行子像素按照第一子像素R、第二子像素G和第三子像素B的顺序周期排布，同一列子像素都为第一子像素R、第二子像素G或第三子像素B。示例的，假设该阵列基板100装配到液晶显示面板中，则该第一子像素R能够发出红色的光线，第二子像素G能够发出绿色的光线，第三子像素B能够发出蓝色的光线。需要说明的是，该第一子像素R也可以称为红色子像素，该第二子像素G也可以称为绿色子像素，该第三子像素B也可以称为蓝色子像素。在这种情况下，同一列子像素的颜色相同。
在本申请中，假设该阵列基板100装配到液晶显示面板中，在该液晶显示面板进行显示时，阵列基板100中的多条数据线30中任意相邻的两条数据线30需要加载极性相反的电压。如此，即使对于每行第一像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率任然近乎50％，但是，在每列子像素中，分别属于两个相邻的第一像素区域10a中的两个子像素间的 电压极性相反。例如，若折弯结构303所围成的区域303a包括一个第一像素区域10a，则每列子像素中任意两个相邻的子像素40间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了该液晶显示面板的显示效果。
如图2所示，上述阵列基板100还可以包括：位于衬底基板10上的多条触控信号线50。多列第一像素区域10a中的每列第一像素区域10a包括两列子像素40，该触控信号线50位于同一列第一像素区域10a中的两列子像素40之间。在本申请中，通过阵列基板100中的多条触控信号线50，使得采用该阵列基板100制备出的液晶显示面板具有触控功能。如此，无需在液晶显示面板上单独装配触控面板便能够使液晶显示面板具有触控功能，有效的降低了具有触控功能的液晶显示面板的厚度。
综上所述，本申请实施例提供的阵列基板，包括：衬底基板，以及位于衬底基板上的多条栅线、多条数据线、多个子像素和多条触控信号线。当采用该阵列基板制备液晶显示面板时，若该液晶显示面板进行显示，则即使对于每行第一像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率任然近乎50％，但是，在每列子像素中，分别属于两个相邻的第一像素区域中的两个子像素间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了该液晶显示面板的显示效果。并且，通过多条触控信号线无需在该液晶显示面板上单独装配触控面板便能够使液晶显示面板具有触控功能，有效的降低了具有触控功能的液晶显示面板的厚度。
在本申请实施例中，如图4所示，图4是本申请实施例提供的又一种阵列基板的结构示意图。数据线30与栅线20还可以在衬底基板10上限定出多个第二像素区域10b。该多个第二像素区域10b排布为两列，且多列第一像素区域10a位于该两列第二像素区域10b之间。每个第二像素区域10b内排布有一个子像素40，该子像素40与一条数据线30连接，且该子像素40与其相邻的两条栅线20中的一条栅线20连接。
该阵列基板100中的多条数据线30，其能够划分为多条第一数据线30a和两条的数据线30b，该多条第一数据线30a位于两条第二数据线30b之间。
对于第一数据线30a中的多个第二延伸部302，每个第二延伸部302可以连 接两个相邻的子像素40，且这两个相邻的子像素40位于两个不同的第一像素区域10a内。
对于第二数据线30b中的多个第二延伸部302，一部分第二延伸部302与两个相邻的子像素40连接，且这两个相邻的子像素40中的一个位于第一像素区域10a内，另一个位于第二像素区域10b内；另一部第二延伸部302未与子像素40连接。其中，在该第二数据线30b中，与子像素40连接的第二延伸部302和未与子像素连40接的第二延伸部302交替排布。
在本申请中，第一数据线30a中的第一延伸部301的长度需要大于第二数据线30b中的第一延伸部301的长度。示例的，第一数据线30a中的第一延伸部301的长度大于相邻两个子像素40的总宽度；而第二数据线30b中的第一延伸部301的长度大于一个子像素40的宽度，但小于相邻两个子像素40的总宽度。需要说明的是，该第一延伸部301的长度方向平行于子像素40的宽度方向。
在本申请实施例中，如图5所示，图5是本申请另一实施例提供的一种阵列基板的结构示意图。同一条数据线30中多个第一延伸部301和多个第二延伸部302能够构成多个弯折结构303。每个弯折结构303具有开口303b，且任意相邻的两个弯折结构303的开口303b的方向相反。例如，第n条数据线、第n+1条数据线和第n+2条数据线为相邻的三条数据线30，对于第n+1条数据线中，第一延伸部A1、第二延伸部B1和第一延伸部A2所构成的弯折结构的开口303b朝向第n+2条数据线，而第一延伸部A2、第二延伸部B2和第一延伸部A3所构成的弯折结构的开口303b朝向第n条数据线。
可选的，数据线30中的第一延伸部301的延伸方向与栅线20的延伸方向相同，数据线30中的第二延伸部302的延伸方向与栅线20的延伸方向垂直。由于栅线20的延伸方向通常平行于多个第一像素区域10a的行方向(也即第一方向x)，且垂直于多个第一像素区域10a的列方向(也即第二方向y)。因此，第一延伸部301可以沿第一方向x延伸，第二延伸部302可以沿第二方向y延伸。
在本申请实施例中，数据线30中的第一延伸部301位于相邻的两行第一像素区域之间的两条栅线20之间，且该第二延伸部302在衬底基板10上的正投影与栅线20在衬底基板上的正投影错开。如此，可以有效的减小数据线30与栅线20之间产生的寄生电容。
可选的，每个子像素40可以包括：薄膜晶体管401和像素电极402。该像素电极402可以为由透明导电材料制备的电极。该薄膜晶体管401可以包括：第一极、第二极和栅极。该第一极可以与一条数据线30连接，栅极可以与一条栅线20连接，第二极与像素电极402连接。其中，该第一极为源极和漏极中的一个，第二极为源极和漏极中的另一个。
假设，每个弯折结构303所围成的区域303a包括一个第一像素区域10a。且，在该阵列基板100装配到液晶显示面板后，若该液晶显示面板需要进行显示，则第n条数据线按照第一子像素R、第三子像素B、第一子像素R和第二子像素G的顺序周期性的驱动与其相连的两列子像素；第n+1条数据线按照第三子像素B、第二子像素G、第一子像素R和第三子像素B的顺序周期性的驱动与其相连的两列子像素；第n+2条数据线按照第一子像素R、第二子像素G、第三子像素B和第二子像素G的顺序周期性的驱动与其相连的两列子像素。
在本申请实施例中，阵列基板100中的触控信号线50的结构有多种，本申请实施例以以下两种可实现方式为例进行示意性的说明。
在第一种可实现方式中，如图6所述，图6本是申请另一实施例提供的另一种阵列基板的结构示意图。该阵列基板100中的触控信号线50包括：间隔排布的第一触控线段501和第二触控线段502。该第一触控线段501的延伸方向与第二触控线段502的延伸方向相同，且相邻的第一触控线段501和第二触控线段502连接。第一触控线段501与数据线30同层设置，且该第一触控线段501在衬底基板10上的正投影与数据线30在衬底基板10上的正投影错开。由于第二触控线段502在衬底基板10上的正投影与数据线30(该数据线30中的第一延伸部301)在衬底基板10的正投影交叉。因此，为了避免触控信号线50与数据线30之间存在短路现象，需要保证第二触控线502与数据线50异层设置，也即是，第二触控线段502与第一触控线段501异层设置。
需要说明的是，该第一触控线段501与数据线30同层设置指的是：第一触控线段501与数据线30是通过同一次构图工艺形成的。第二触控线502与数据线50异层设置指的是：第二触控线502与数据线50不在同一膜层中，且该第二触控线502与数据线50之间具有绝缘层。
示例的，请参考图7，图7是图6在A-A’处的截面图。该阵列基板100还可以包括：位于第一触控线段501与第二触控线段502之间的第一绝缘层60。 该第一绝缘层60具有多个第一过孔601，相邻的第一触控线段501与第二触控线段502通过至少一个第一过孔601连接。
可选的，第二触控线段502的材料可以包括透明导电材料。如此，可以增大每个子像素30的开口率。
在第二种可实现方式中，如图5所示，阵列基板100中的多条触控信号线50同层设置，且该触控信号线50与数据线30异层设置。需要说明的是，该多条触控信号线50同层设置指的是：多条触控信号线50是通过同一次构图工艺形成的；该触控信号线50与数据线30异层设置指的是：触控信号线50与数据线30不在同一膜层中，且该触控信号线50与数据线30之间具有绝缘层。
示例的，如图8所述，图8是图5在A-A’处的截面图。该阵列基板100还可以包括：位于触控信号线50与数据线30之间的第一绝缘层60。可选的，该触控信号线50的材料可以包括金属材料。由于在第二种可实现方式中触控信号线50与数据线30异层设置，因此无需在第一绝缘层60上设置第一过孔，如此，可以提高每个子像素30的开口率。并且，又由于在第二种可实现方式中触控信号线50的材料为金属材料，其相对于透明导电材料具有较高的导电性和较低的电阻率，有效的提高了触控信号线50中的触控信号的信号量，进而提高了该阵列基板100的触控性能。
可选的，如图7和图8所示，该阵列基板100还可以包括：多个触控电极70。该多个触控电极70与多条触控信号线50一一对应连接。该触控电极70可以为由透明导电材料制备的电极。需要说明的是，本申请中的阵列基板100中的触控方式属于自容式的触控，相关的触控原理可以参考相关技术，在此不做赘述。
示例的，触控电极70与多条触控信号线50异层设置。需要说明的是，该触控电极70与多条触控信号线50异层设置指的是：触控电极70与多条触控信号线50不在同一膜层中，且该触控电极70与多条触控信号线50之间具有绝缘层。示例的，该阵列基板100还可以包括位于触控电极70与多条触控信号线50之间的第二绝缘层80，该第二绝缘层80具有多个第二过孔801，每个触控电极70和对应的触控信号线50通过至少一个第二过孔801连接。
可选的，每个触控电极70为块状的电极，每个触控电极70在衬底基板10上的正投影覆盖多个像素电极402在衬底基板10上的正投影。例如，假设阵列 基板10中的多个子像素可以均匀的分为k个子像素组，每个子像素组包括j×j个子像素，则每个触控电极70在衬底基板上的正投影覆盖j×j个像素电极402。
在本申请实施例中，阵列基板100还可以包括：公共电极和公共电极线。为了减少该阵列基板100的结构的复杂度，可以使阵列基板100中的触控电极70复用于该公共电极，阵列基板100中的触控信号线50复用于该公共电极线。也即是，阵列基板100中的触控电极70与公共电极是同一个电极，触控信号线50与公共电极线为同一根信号线。
如此，在采用该阵列基板100制备的液晶显示面板中，若需要该液晶显示面板进行显示，则需要对触控信号线50加载公共电极信号，使得该触控电极70能够与像素电极402形成使液晶偏振的压差；若需要该液晶显示面板进行触控，则需要对该触控信号线50加载触控信号，使得该触控电极70能够检测到触控位置。
可选的，如图5或图6所述，触控信号线50的延伸方向与栅线20的延伸方向垂直。也即是，该触控信号线50沿第二方向y延伸。
可选的，如图5或图6所述，多列第一像素区域10a与多条触控信号线50一一对应，每条触控信号线50位于与该触控信号线50对应的一列第一像素区域10a中的两列子像素40之间。
对于上述第一种可实现方式中的阵列基板100，也即是，图6示出的阵列基板100。该阵列基板100包括：沿垂直且远离衬底基板10的方向依次叠层设置的第一导电层、栅极绝缘层90、有源层(图中未画出)、第二导电层、像素电极层、第一绝缘层60、第三导电层、第二绝缘层80和第四导电层。其中，该第一导电层包括：栅线20和薄膜晶体管402中的栅极；第二导电层包括：数据线30、第一触控线段501，以及薄膜晶体管402中的源极和漏极；像素电极层包括：多个像素电极401；第三导电层包括：第二触控线段502；第四导电层包括：触控电极70。
对于上述第二种可实现方式中的阵列基板100，也即是，对于图5示出的阵列基板100。该阵列基板100包括：沿垂直且远离衬底基板10的方向依次叠层设置的第一导电层、栅极绝缘层90、有源层(图中未画出)、第二导电层、像素电极层、第一绝缘层60、第三导电层、第二绝缘层80和第四导电层。其中，第一导电层包括：栅线20和薄膜晶体管402中栅极；第二导电层包括：数据线 30以及薄膜晶体管402中的源极和漏极；第三导电层包括：触控信号线50；第四导电层包括：触控电极70。
综上所述，本申请实施例提供的阵列基板，包括：衬底基板，以及位于衬底基板上的多条栅线、多条数据线、多个子像素和多条触控信号线。当采用该阵列基板制备液晶显示面板时，若该液晶显示面板进行显示，则即使对于每行第一像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率任然近乎50％，但是，在每列子像素中，分别属于两个相邻的第一像素区域中的两个子像素间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了该液晶显示面板的显示效果。并且，通过多条触控信号线无需在该液晶显示面板上单独装配触控面板便能够使液晶显示面板具有触控功能，有效的降低了具有触控功能的液晶显示面板的厚度。
本申请实施例还提供了一种阵列基板的制造方法，该阵列基板的制造方法用于制造图2、图3、图4、图5或图6示出的阵列基板100。该阵列基板100的制造方法可以包括：
在衬底基板上形成多条栅线、多条数据线、多个子像素和多条触控信号线。
其中，数据线与栅线在衬底基板上限定出多个第一像素区域。该多个第一像素区域排布为多行，且任意相邻的两行第一像素区域之间排布有两条栅线。数据线具有相连接的多个第一延伸部和多个第二延伸部，该多个第一延伸部和多个第二延伸部一一交替排布。任意两个相连接的第一延伸部的延伸方向与第二延伸部的延伸方向相交。且同一条数据线中任意相邻的两个第一延伸部与相邻的两个第一延伸部之间的第二延伸部构成一个折弯结构，该折弯结构所围成的区域包括至少一个第一像素区域。任意相邻的两条数据线用于加载极性相反的电压。每个第一像素区域内沿栅线的延伸方向排布有两个子像素，且两个子像素分别与第一像素区域相邻的两条数据线连接，每个子像素与子像素相邻的两条栅线中的一条栅线连接。多个第一像素区域还排布为多列，每列第一像素区域中包括两列子像素，触控信号线位于同一列第一像素区域中的两列子像素之间。
综上所述，本申请实施例提供的阵列基板的制造方法，在衬底基板上形成 多条栅线、多条数据线、多个子像素和多条触控信号线。当采用该阵列基板制备液晶显示面板时，若该液晶显示面板进行显示，则即使对于每行第一像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率任然近乎50％，但是，在每列子像素中，分别属于两个相邻的第一像素区域中的两个子像素间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了该液晶显示面板的显示效果。并且，通过多条触控信号线无需在该液晶显示面板上单独装配触控面板便能够使液晶显示面板具有触控功能，有效的降低了具有触控功能的液晶显示面板的厚度。
可选的，请参考图9，图9是本申请实施例提供的一种阵列基板的制造方法的流程图。该阵列基板的制造方法用于制造图5或图6示出的阵列基板。该阵列基板制造方法可以包括：
步骤S1、在衬底基板上形成第一导电层、栅极绝缘层和有源层。
可选的，该第一导电层的材料可以包括：诸如金属钼(简称：Mo)、金属铜(简称：Cu)、金属铝(简称：Al)或合金等金属材料。该栅极绝缘层的材料可以包括：二氧化硅、氮化硅或者二氧化硅和氮化硅的混合材料。该有源层的材料可以包括：多晶硅。
示例的，首先，可以在衬底基板上通过沉积、涂敷、溅射等多种方式中的任一种形成第一导电材质层，并对该第一导电材质层进行一次构图工艺形成第一导电层。该第一导电层可以包括：栅极和栅线。
然后，在形成有第一导电层的衬底基板上通过沉积、涂敷、溅射等多种方式中的任一种依次形成栅极绝缘层和有源材质层，并对该有源材质层进行一次构图工艺形成有源层。
步骤S2、在有源层上形成第二导电层和像素电极层。
可选的，该第二导电层的材料可以包括：诸如金属Mo、金属铜Cu、金属铝Al或合金等金属材料。像素电极层的材料可以包括：透明导电材料，例如，其可以为ITO。
示例的，首先，可以在有源层上通过沉积、涂敷、溅射等多种方式中的任一种形成第二电极材质层，并对该第二导电材质层进行一次构图工艺形成第二导电层。该第二导电层可以包括：源极、漏极和数据线。
然后，可以在第二导电层上通过沉积、涂敷、溅射等多种方式中的任一种形成像素电极材质层，并对该像素电极材质层进行一次构图工艺形成像素电极层。该像素电极层可以包括：多个像素电极。
步骤S3、在像素电极层上形成第一绝缘层和第三导电层。
可选的，该第一绝缘层也可以称为平坦层，其材料可以包括：丙烯酸树脂或者环氧树脂等材料。
在一种可实现方式中，若该衬底基板的制造方法用于制造图5示出的阵列基板，则第三导电层的材料包括：透明导电材料，例如，其可以为ITO。
在这种情况下，步骤S2形成的第二导电层还包括：第一触控线段。首先，可以在像素电极层上通过沉积、涂敷、溅射等多种方式中的任一种形成第一绝缘层，并对该第一绝缘层进行一次构图工艺形成带有多个第一过孔的第一绝缘层。
然后，可以在形成有第一绝缘层的衬底基板上通过沉积、涂敷、溅射等多种方式中的任一种形成第三导电材质层，并对该第三导电材质层进行一次构图工艺形成第三导电层。该第三导电层可以包括：第二触控线段，且该第二触控线段能够通过至少一个第一过孔与第一触控线段连接，该第二触控线段与第一触控线段能够构成触控信号线。
在另一种可实现方式中，若该衬底基板的制造方法用于制造图6示出的阵列基板，则该第三导电层的材料包括：诸如金属Mo、金属铜Cu、金属铝Al或合金等金属材料。
在这种情况下，首先，可以在像素电极层上通过沉积、涂敷、溅射等多种方式中的任一种依次形成第一绝缘层和第三导电材质层，并对该第三导电材质层进行一次构图工艺形成第三导电层。该第三导电层可以包括：触控信号线。
步骤S4、在第三导电层上形成第二绝缘层和第四导电层。
可选的，该第二绝缘层也可以称为平坦层，其材料可以包括：丙烯酸树脂或者环氧树脂等材料。该第四导电层的材料包括：透明导电材料，例如，其可以为ITO。
示例的，首先，可以在第三导电层上通过沉积、涂敷、溅射等多种方式中的任一种依次形成第二绝缘层和第四导电材质层，并对该第四导电材质层进行一次构图工艺形成第四导电层。该第三导电层可以包括：触控电极。
需要说明的是，上述实施例中的每次构图工艺均可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的阵列基板具体原理，可以参考前述阵列基板的结构的实施例中的对应内容，在此不再赘述。
综上所述，本申请实施例提供的阵列基板的制造方法，在衬底基板上形成多条栅线、多条数据线、多个子像素和多条触控信号线。当采用该阵列基板制备液晶显示面板时，若该液晶显示面板进行显示，则即使对于每行第一像素区域中的同一种子像素而言，任意相邻的两个子像素间电压极性相同的概率任然近乎50％，但是，在每列子像素中，分别属于两个相邻的第一像素区域中的两个子像素间的电压极性相反。可以有效的在空间尺度上对同一帧图像中同种子像素的电压极性进行平均，从而降低了出现摇头纹的概率，进而有效的提高了该液晶显示面板的显示效果。并且，通过多条触控信号线无需在该液晶显示面板上单独装配触控面板便能够使液晶显示面板具有触控功能，有效的降低了具有触控功能的液晶显示面板的厚度。
本申请实施例还提供了一种显示装置。该显示装置可以为液晶显示装置，其包括液晶显示面板。该液晶显示面板可以包括：图2、图3、图4、图5或图6示出的阵列基板、彩膜基板以及位于阵列基板和彩膜基板之间的液晶层。
该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪或可穿戴设备等任何具有显示功能的产品或部件。作为一种示例，图10是本申请实施例提供的一种显示装置的结构示意图。该显示装置包括上述的液晶显示面板，该液晶显示面板的显示区内包括行列设置的子像素区域Px。上述显示区中的数据线可以在两个相邻的子像素区域Px之间，以将所接入的数据信号传输至每个子像素区域Px之中。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中 间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本申请中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。
以上所述仅为本申请的可选的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板上的多条栅线和多条数据线，所述多条数据线与所述多条栅线在所述衬底基板上限定出多个第一像素区域，所述多个第一像素区域排布为多行，且任意相邻的两行第一像素区域之间排布有两条所述栅线，所述数据线具有相连接的多个第一延伸部和多个第二延伸部，所述多个第一延伸部和所述多个第二延伸部一一交替排布，任意两个相连接的所述第一延伸部的延伸方向与所述第二延伸部的延伸方向相交，且同一条所述数据线中任意相邻的两个第一延伸部与所述相邻的两个第一延伸部之间的第二延伸部构成一个折弯结构，所述折弯结构所围成的区域包括至少一个所述第一像素区域；
    位于所述第一像素区域内的两个子像素，所述两个子像素沿所述栅线的延伸方向排布，且所述两个子像素分别与所述第一像素区域相邻的两条所述数据线连接，所述子像素与所述子像素相邻的两条所述栅线中的一条所述栅线连接；
    以及，位于所述衬底基板上的多条触控信号线，所述多个第一像素区域还排布为多列，一列所述第一像素区域中包括两列所述子像素，所述触控信号线位于同一列所述第一像素区域中的两列所述子像素之间。
  2. 根据权利要求1所述的阵列基板，同一条所述数据线中所述多个第一延伸部和所述多个第二延伸部构成多个所述折弯结构，所述折弯结构具有开口，且任意相邻的两个所述折弯结构的开口的方向相反。
  3. 根据权利要求1所述的阵列基板，所述第一延伸部的延伸方向与所述栅线的延伸方向相同，所述第二延伸部的延伸方向与所述栅线的延伸方向垂直，所述触控信号线的延伸方向与所述栅线的延伸方向垂直。
  4. 根据权利要求3所述的阵列基板，所述第一延伸部在所述衬底基板上的正投影与所述栅线在所述衬底上的正投影错开。
  5. 根据权利要求4所述的阵列基板，所述第一延伸部位于相邻的两行所述第一像素区域之间的两条所述栅线之间。
  6. 根据权利要求1所述的阵列基板，所述多条数据线与所述多条栅线还在所述衬底基板上限定出多个第二像素区域，所述多个第二像素区域排布为两列，多列所述第一像素区域位于两列所述第二像素区域之间，所述阵列基板还包括位于所述第二像素区域内的一个子像素。
  7. 根据权利要求1所述的阵列基板，所述触控信号线包括：间隔排布的第一触控线段和第二触控线段，所述第一触控线段和所述第二触控线段异层设置，相邻的所述第一触控线段与所述第二触控线段连接，所述第一触控线段与所述数据线同层设置，所述第二触控线段在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影交叉。
  8. 根据权利要求7所述的阵列基板，所述阵列基板还包括：位于所述第一触控线段和所述第二触控线段的第一绝缘层，所述第一绝缘层具有多个第一过孔，相邻的所述第一触控线段与所述第二触控线段通过至少一个所述第一过孔连接。
  9. 根据权利要求1所述的阵列基板，所述多条触控信号线同层设置，且与所述数据线异层设置。
  10. 根据权利要求1至9任一所述的阵列基板，所述阵列基板还包括：多个触控电极，所述多个触控电极与所述多条触控信号线一一对应连接。
  11. 根据权利要求10所述的阵列基板，所述触控电极与所述多条触控信号线异层设置，所述阵列基板还包括位于所述触控电极与所述多条触控信号线之间的第二绝缘层，所述第二绝缘层具有多个第二过孔，每个所述触控电极和对应的触控信号线通过至少一个所述第二过孔连接。
  12. 根据权利要求10所述的阵列基板，所述触控电极复用于所述阵列基板中的公共电极，所述触控信号线复用于所述阵列基板中的公共电极线。
  13. 根据权利要求11或12所述的阵列基板，所述触控电极为块状的电极，所述子像素包括像素电极，一个所述触控电极在所述衬底基板上的正投影覆盖多个所述像素电极在所述衬底基板上的正投影。
  14. 根据权利要求1至9任一所述的阵列基板，多列所述第一像素区域与所述多条触控信号线一一对应，每条所述触控信号线位于与所述触控信号线对应的一列所述第一像素区域中的两列子像素之间。
  15. 据权利要求7或8所述的阵列基板，所述阵列基板包括：沿垂直且远离所述衬底基板的方向依次叠层设置的第一导电层、栅极绝缘层、有源层、第二导电层、像素电极层、第一绝缘层、第三导电层、第二绝缘层和第四导电层；
    其中，所述第一导电层包括：所述栅线和栅极，所述第二导电层包括：所述数据线、所述第一触控线段、源极和漏极，所述第三导电层包括：所述第二触控线段，所述第四导电层包括：触控电极。
  16. 根据权利要求9所述的阵列基板，所述阵列基板包括：沿垂直且远离所述衬底基板的方向依次叠层设置的第一导电层、栅极绝缘层、有源层、第二导电层、像素电极层、第一绝缘层、第三导电层、第二绝缘层和第四导电层；
    其中，所述第一导电层包括：所述栅线和栅极，所述第二导电层包括：所述数据线、源极和漏极，所述第三导电层包括：所述触控信号线，所述第四导电层包括：触控电极。
  17. 根据权利要求1至9任一所述的阵列基板，所述折弯结构所围成的区域包括多个所述第一像素区域，且多个所述第一像素区域的排布方向与所述栅线的延伸方向垂直。
  18. 根据权利要求1至9任一所述的阵列基板，所述第一像素区域内的两 个子像素分别为：红色子像素、绿色子像素和蓝色子像素中的两个子像素，同一行所述子像素按照所述红色子像素、所述绿色子像素和所述蓝色子像素的顺序周期排布，同一列所述子像素的颜色相同。
  19. 根据权利要求1至9任一所述的阵列基板，所述子像素包括：薄膜晶体管和像素电极，所述薄膜晶体管包括：第一极、第二极和栅极，所述第一极与一条所述数据线连接，所述第二极与所述像素电极连接，所述栅极与一条所述栅线连接。
  20. 一种显示装置，包括：权利要求1至19任一所述阵列基板、彩膜基板以及位于所述阵列基板和所述彩膜基板之间的液晶层。
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