WO2021169302A1 - 先进制程下最小化时延和溢出的通孔柱感知层分配器 - Google Patents

先进制程下最小化时延和溢出的通孔柱感知层分配器 Download PDF

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WO2021169302A1
WO2021169302A1 PCT/CN2020/119326 CN2020119326W WO2021169302A1 WO 2021169302 A1 WO2021169302 A1 WO 2021169302A1 CN 2020119326 W CN2020119326 W CN 2020119326W WO 2021169302 A1 WO2021169302 A1 WO 2021169302A1
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line
hole
congestion
time delay
lines
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PCT/CN2020/119326
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French (fr)
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郭文忠
张星海
刘耿耿
黄兴
陈国龙
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福州大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

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  • the invention belongs to the technical field of integrated circuit computer-aided design, and specifically relates to a through-hole column sensing layer distributor that minimizes time delay and overflow under an advanced manufacturing process.
  • the line network delay mainly includes line delay and through-hole delay.
  • the line resistance and the through-hole resistance increase significantly, which directly leads to an increase in the network delay.
  • the upper layer has a larger line width and line spacing than the lower layer, so the resistance of the upper line is smaller. Therefore, assigning the timing critical line segment to the upper layer is beneficial to reduce the time delay.
  • this method alone is not enough to greatly reduce the time delay, so it is necessary to introduce new technologies in the advanced manufacturing process to further optimize the time delay.
  • the through-hole post includes a plurality of conventional through-holes and has various forms.
  • Figure 1 shows a type of through-hole column structure.
  • the size of the via and the capacity of the wiring unit should be considered.
  • considering the size of the through hole and the capacity of the wiring unit is also beneficial to reduce the degree of mismatch between the overall wiring and the detailed wiring.
  • non-default regular lines As another important technology under the advanced manufacturing process, the application of non-default regular lines is an important way to reduce line resistance.
  • the non-default regular lines In the lower layer of the wiring area in the advanced manufacturing process, due to the limitation of the manufacturing process, the non-default regular lines can only be realized in the form of parallel lines. In other wiring layers, non-default regular lines are implemented in the form of wide lines.
  • the line width of the wide line is greater than the default line width and is given in advance.
  • the wiring resources of each wiring layer have an upper limit. If too many lines are allocated to the upper layer, or through-hole posts and non-default regular lines are excessively used, the routableness will deteriorate and the line density will increase. Due to the coupling effect, the increase in line density will lead to an increase in the coupling capacitance, which in turn leads to an increase in time delay, which has a negative impact on the timing characteristics of the circuit. Therefore, routing resources, through-hole posts, and non-default ruled lines should be used reasonably.
  • the purpose of the present invention is to provide a via post sensing layer distributor that minimizes time delay and overflow under an advanced manufacturing process.
  • the via post sensing layer distributor can take into account via congestion, line congestion, and coupling effects. Optimize delay and overflow.
  • the technical solution adopted by the present invention is: a through-hole column sensing layer distributor that minimizes time delay and overflow under an advanced manufacturing process, and the through-hole column sensing layer distributor performs the layer distribution scheme according to the following steps Fully automatic design:
  • step S1 the specific method for applying a multi-angle congestion relaxation strategy to assess congestion is as follows:
  • the multi-angle congestion relaxation strategy considers the relationship between objects occupying wiring resources and wiring areas that provide wiring resources from multiple perspectives, specifically: the wiring resources of the wiring area include side tracks and the area of the wiring unit. Wiring resources can be occupied by lines, vias, and obstacles. Taking these factors into consideration, the congestion cost function is defined as follows:
  • segment congestion cost cong(s) includes obstacle congestion cost cong(o), via congestion cost cong(v) and line Congestion cost cong(w); if s is a through hole, v represents the through hole and cong(w) is 0; if s is a line segment, then w represents the line segment and cong(v) is 0; e and g are respectively Represents the edge and wiring unit that the line segment s passes through; tc(e) and tc(g) represent the edge capacity of e and the area capacity of g respectively; dc(e o ), dc(e v ) and dc(e w ) Respectively represent the number of tracks in e occupied by obstacles, vias and lines; dc(g o ), dc(g v ) and dc(g w ) represent the area of g occupied by obstacles, via
  • the specific method of applying the guidance layer allocation based on the negotiation idea is: if the currently allocated segment is allocated to an edge with no remaining available routing tracks, the cost of using the edge is increased to Guide subsequent allocated segments to avoid using this edge.
  • the wire net healing algorithm guides the timing non-critical wire net to release the wiring resources shared with the timing critical wire net, so as to provide more space and flexibility for the reallocation of the timing critical wire net, and then Reduce the maximum delay.
  • the through-hole column optimization method is used to combine the through-hole column and the non-default regular line.
  • the type of the through-hole column and the line type are considered, The type of through-hole column depends on the type of wiring that the through-hole column is connected to.
  • the setting method of the type of through-hole pillars is as follows: a connection parallel line and default rules
  • the through-hole post of the line is of 2 ⁇ 1 type; a through-hole post connecting two pairs of parallel lines is of 2 ⁇ 2 type; a through-hole post connecting wide line and default regular line is 3 ⁇ 1 type; one connecting wide line and The via post of the parallel line is 3 ⁇ 2 type; a via post connecting two wide lines is 3 ⁇ 3 type; if a via post is connected to the default regular line, the via post will be converted into a regular via; If a via column is not connected to a line on a certain layer, the type of the via column depends on the default ruled line of the layer; for the via segment that is directly connected to the signal source of the timing critical line network, use 2 ⁇ 2 types of through hole columns.
  • the present invention has the following beneficial effects: it proposes a through-hole column sensing layer distributor that minimizes time delay and overflow under the advanced manufacturing process considering the size of the through-hole and the coupling effect, and the through-hole column sensing
  • the layer distributor adopts a congestion relaxation strategy to reduce overflow, a line network healing algorithm that optimizes the maximum delay, and a through-hole column optimization method that effectively combines through-hole columns and non-default regular lines.
  • Optimizing time delay and overflow under the premise has strong practicability and broad application prospects.
  • Fig. 1 is a schematic diagram of a conventional through-hole column structure.
  • Fig. 2 is a comparison diagram of a non-default ruled line and a default ruled line in an embodiment of the present invention.
  • Fig. 3 is a schematic diagram of a conventional through hole model in an embodiment of the present invention.
  • Fig. 4 is a schematic diagram showing the occupation of wiring resources by vias, lines, and obstacles in an embodiment of the present invention.
  • Fig. 5 is a schematic diagram of the types of through-hole posts in an embodiment of the present invention.
  • Fig. 6 is a schematic diagram of an optimized layer allocation scheme using a wire net healing algorithm in an embodiment of the present invention.
  • Fig. 7 is a flow chart of implementing the layer allocation scheme design of the through-hole column sensing layer distributor according to the embodiment of the present invention.
  • the line width of the non-default ruled line is different from the default line width. Specifically, the default line widths of different wiring layers are different. The default line width of the upper layer is usually greater than the default line width of the lower layer.
  • the comparison between the non-default ruled line and the default ruled line is shown in Figure 2.
  • the two pins are respectively connected with a parallel line and a default regular line, where the default regular line occupies one wiring track and the parallel line occupies two wiring tracks.
  • a wide line and a default regular line are used to connect two pins respectively, where the default regular line occupies one wiring track and the wide line occupies three wiring tracks.
  • the non-default ruled line can reduce the line resistance and optimize the delay.
  • a through hole column contains a plurality of conventional through holes.
  • the horizontal projection of a conventional through hole is a rectangle.
  • the length and width of the rectangle depend on the line width and spacing of two lines located in different layers connected to the through hole, as shown in FIG. 3. If a conventional through hole has no line connected to the through hole in a certain layer, the length or width of the horizontal projection of the conventional through hole depends on the default line width and spacing of the layer.
  • the via post Compared with the conventional via, the via post has a smaller resistance and a larger capacitance. Therefore, the reasonable application of through-hole posts can reduce the time delay, otherwise it may increase the time delay. For example, for a wire network, only using the through hole column technology for the downstream through hole section will cause the delay of each upstream section to increase, and ultimately lead to an increase in the wire network delay. In addition, compared with conventional vias, via posts may occupy more wiring resources, which may worsen circuit congestion. Therefore, through-hole posts should be used rationally to optimize the time delay while ensuring good routing.
  • the wiring area includes wiring units and edges.
  • the present invention not only considers the side capacity, line width and spacing, but also considers the area of the wiring unit and the size of the through hole. Specifically, the area of the wiring unit is determined by the length and width of the wiring unit, and the capacity of a side is determined by the number of tracks included in the side. As shown in Figure 4, the area of the wiring unit and the wiring track can be occupied by the through holes and lines of the wire net, as well as obstacles. The uppermost track in Figure 4, because it is occupied by through holes, cannot be used by other wire nets, and is called an unusable track.
  • the area occupied by the wire net and obstacles to the wiring unit is greater than the area capacity of the wiring unit, the area of the wiring unit will overflow. If the line network and obstacles occupy more than the track capacity of the side, side overflow will occur.
  • the calculation methods of the overflow of(g) of the wiring unit g and the overflow of(e) of the edge e are as follows:
  • u(g) and c(g) respectively represent the current area usage and capacity of g.
  • u(e) and c(e) represent e's current orbit usage and capacity, respectively.
  • the area overflow and edge overflow of the wiring unit can be attributed to the occupation of the wiring resources by the through holes and the occupation of the wire-to-wiring resources.
  • the present invention provides a through-hole column sensing layer distributor that minimizes time delay and overflow under an advanced manufacturing process considering the size of the through-hole and the coupling effect.
  • the through-hole column sensing layer distributor follows the following steps Fully automatic design of layer distribution scheme:
  • the present invention adopts a multi-angle congestion relaxation strategy to optimize congestion and thereby improve the routable.
  • the multi-angle congestion relaxation strategy considers the relationship between objects occupying wiring resources and wiring areas that provide wiring resources from multiple perspectives.
  • the wiring resources of the wiring area include the side track and the area of the wiring unit, and these wiring resources can be occupied by wires, vias, and obstacles. Considering these factors comprehensively, the congestion cost function is defined as follows:
  • segment congestion cost cong(s) includes obstacle congestion cost cong(o), via congestion cost cong(v) and line Congestion cost cong(w); if s is a through hole, v represents the through hole and cong(w) is 0; if s is a line segment, then w represents the line segment and cong(v) is 0; e and g are respectively Represents the edge and wiring unit that the line segment s passes through; tc(e) and tc(g) represent the edge capacity of e and the area capacity of g respectively; dc(e o ), dc(e v ) and dc(e w ) Respectively represent the number of tracks in e occupied by obstacles, vias and lines; dc(g o ), dc(g v ) and dc(g w ) represent the area of g occupied by obstacles, via
  • ⁇ is a user-defined parameter, which is set to 0.05 in the present invention.
  • the multi-angle congestion relaxation strategy can optimize the congestion in the routing area to reduce the overflow caused by lines and vias, while ensuring good timing characteristics.
  • This strategy quantifies the pros and cons of each alternative as a cost through a more detailed analysis of the alternatives. If the scheme is better, the cost corresponding to the scheme is low, and if the scheme is poor, the cost corresponding to the scheme is high. Finally, a low-cost solution is selected to guide the allocation of layers.
  • the maximum delay is an important factor affecting chip performance. Therefore, the present invention proposes a network healing algorithm to reduce the maximum time delay.
  • the wire net healing algorithm guides the timing non-critical wire net to release the wiring resources shared with the timing critical wire net, and provides more space and flexibility for the redistribution of the timing critical wire net, thereby reducing the maximum time delay.
  • Fig. 6 gives an example to explain the wire net healing algorithm.
  • n 1 is a timing non-critical network
  • n 2 is the maximum delay network.
  • the order of layer allocation is n 1 , n 2 .
  • FIG 6 (a) is n 1 and n 2D wiring scheme 2, can be seen from FIG. 6 (a), n 1 and n 2 are competing routing resources.
  • the capacity of each side is 1, and the line resistance of the upper layer is smaller than the line resistance of the lower layer.
  • the maximum delay line network should have the priority of using wiring resources.
  • FIG. 6(c) is the 3D wiring scheme of n 1 and n 2 when the wire net healing algorithm is used. Under the guidance of the online net healing algorithm, the layer allocation plan of n 2 is adjusted to the layer allocation plan shown in Fig. 6(c). In order to ensure good wiringability, the layer allocation scheme of n 1 is adjusted to the layer allocation scheme shown in Fig. 6(d). Figure 6(d) shows the final layer allocation scheme of n 1 and n 2 after using the wire net healing algorithm.
  • the through-hole column optimization method combines the through-hole column and non-default regular lines to further reduce the time delay and produce a final layer distribution scheme with good timing characteristics and routing.
  • the present invention reasonably uses the through-hole column to reduce the network delay without causing congestion deterioration.
  • the through hole column optimization method of the present invention reasonably combines the through hole column and the non-default regular line.
  • the use of through-hole posts for each wire net is not only unnecessary but also causes deterioration of the wiringability.
  • the time delay of the critical timing net is one of the important factors that affect the performance of the chip, and the line length of the critical timing net is usually very large. Therefore, if the via column is used downstream of the timing critical line network, the downstream capacitance of each segment of the timing critical line network will increase, which will lead to an increase in the line network delay. Therefore, the via post should be used in the timing critical section close to the signal source in the timing critical network to effectively reduce the time delay.
  • the present invention fully considers the type of the via column and the type of the line, and the type of the via column depends on the type of connection of the via column. Specifically, since parallel lines occupies two wiring tracks and wide lines occupies three wiring tracks, the type of through-hole post is set as follows:
  • a through-hole column connecting parallel lines and the default regular line is a 2 ⁇ 1 type; as shown in Figure 5(b), a through-hole column connecting two pairs of parallel lines is 2 ⁇ 2 Type; as shown in Figure 5(c), a through-hole post connecting wide lines and default ruled lines is a 3 ⁇ 1 type; as shown in Figure 5(d), a through-hole post connecting wide lines and parallel lines is 3 ⁇ 2 type.
  • a through-hole column connecting two wide lines is a 3 ⁇ 3 type; in addition, if a through-hole column is connected to the default ruled line, the through-hole column is transformed into one as shown in Figure 3.
  • the present invention uses a 2 ⁇ 2 type through-hole column for the through-hole section.

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Abstract

一种先进制程下最小化时延和溢出的通孔柱感知层分配器，所述通孔柱感知层分配器按如下步骤设计层分配方案：S1)为后续阶段产生一个初始解；应用多角度拥塞松弛策略评估拥塞进而调整层分配方案；S2)在初始解的基础上，应用基于协商思想引导层分配；S3)采用线网治愈算法优化当前层分配方案的最大时延；S4)将所有线网根据时延大小排序后重分配；优先处理时延大的线网即时序关键线网，同时对靠前的时序关键线网使用通孔柱优化方法，结合通孔柱和非默认规则线，以进一步降低时延，产生最终的层分配方案。所述通孔柱感知层分配器能够在考虑通孔拥塞、线拥塞和耦合效应的前提下优化时延和溢出。

Description

先进制程下最小化时延和溢出的通孔柱感知层分配器 技术领域
本发明属于集成电路计算机辅助设计技术领域，具体涉及一种先进制程下最小化时延和溢出的通孔柱感知层分配器。
背景技术
作为影响芯片性能的重要因素之一，互连时延是层分配中的一个重要优化目标。线网时延主要包括线时延和通孔时延。然而，随着电路规模的扩大，线电阻和通孔电阻显著增大，这直接导致线网时延增大。在先进制程中，上层具有比下层更大的线宽和线间距，因而上层线的电阻较小。故将时序关键线网段分配给上层有利于减小时延。但仅通过这一方式不足以大幅度降低时延，因此有必要引入先进制程中的新技术进一步优化时延。
通孔柱(via pillar)作为先进制程中的一项重要技术，能够有效降低通孔电阻。通孔柱包含多个常规通孔，并且具有多种形式。图1展示了一种通孔柱结构类型。为了区分通孔柱和常规通孔对布线资源的影响，通孔的尺寸和布线单元的容量应当被考虑。此外，考虑通孔的尺寸和布线单元的容量还有利于降低总体布线和详细布线的不匹配程度。
作为先进制程下的另一项重要技术，非默认规则线的应用是降低线电阻的重要方式。非默认规则线有两种类型：并行线和宽线。在先进制程中布线区域的下层，由于制造工艺的限制，非默认规则线只能以并行线的形式实现。而在其他布线层，非默认规则线以宽线形式实现。宽线的线宽大于默认线宽并且是预先给定的。
技术问题
每一布线层的布线资源都有上限。若分配过多的线到上层，或者过度使用通孔柱、非默认规则线，可布线性将恶化并且线密度将增大。由于耦合效应，线密度增大将导致耦合电容增大，进而导致时延增大，这对电路的时序特性有 负面影响。因此，布线资源、通孔柱以及非默认规则线应当被合理使用。
技术解决方案
本发明的目的在于提供一种先进制程下最小化时延和溢出的通孔柱感知层分配器，所述通孔柱感知层分配器能够在考虑通孔拥塞、线拥塞和耦合效应的前提下优化时延和溢出。
为实现上述目的，本发明采用的技术方案是：一种先进制程下最小化时延和溢出的通孔柱感知层分配器，所述通孔柱感知层分配器按如下步骤进行层分配方案的全自动设计：
S1)为后续阶段产生一个初始解；应用多角度拥塞松弛策略评估拥塞进而调整层分配方案，在保障良好时序特性的同时，减少溢出；
S2)在初始解的基础上，应用基于协商思想引导层分配；
S3)采用线网治愈算法优化当前层分配方案的最大时延；在此过程中，可以使用非默认规则线；并且，采用段区分方法，根据段与信号源的距离给段赋值，以区分时序关键线网中的时序关键段与时序非关键段；
S4)将所有线网根据时延大小排序后重分配；优先处理时延大的线网即时序关键线网，同时对靠前的时序关键线网使用通孔柱优化方法，结合通孔柱和非默认规则线，以进一步降低时延，产生最终的层分配方案。
进一步地，所述步骤S1中，应用多角度拥塞松弛策略评估拥塞的具体方法为：
所述多角度拥塞松弛策略从多个角度考虑占用布线资源的物体与提供布线资源的布线区域之间的相互关系，具体为：布线区域的布线资源包括边的轨道和布线单元的面积，所述布线资源可以被线、通孔和障碍物占用，综合考虑这些因素，定义拥塞代价函数如下：
cong(s)＝cong(o)+cong(v)+cong(w)
Figure PCTCN2020119326-appb-000001
Figure PCTCN2020119326-appb-000002
Figure PCTCN2020119326-appb-000003
其中s表示一个线网段；o、v和w分别表示障碍物、通孔和线；段拥塞代价cong(s)包括障碍物拥塞代价cong(o)、通孔拥塞代价cong(v)和线拥塞代价cong(w)；若s是一通孔，则v表示该通孔且cong(w)为0；若s是一线段，则w表示该线段且cong(v)为0；e和g分别表示线网段s经过的边和布线单元；tc(e)和tc(g)分别表示e的边容量和g的面积容量；dc(e o)、dc(e v)和dc(e w)分别表示被障碍物、通孔和线占用的e中轨道的数量；dc(g o)、dc(g v)和dc(g w)分别表示被障碍物、通孔和线占用的g的面积；of(e w)是发生线溢出时的额外拥塞代价；h e是历史代价，其计算方式如下：
Figure PCTCN2020119326-appb-000004
其中
Figure PCTCN2020119326-appb-000005
和
Figure PCTCN2020119326-appb-000006
分别表示e的第i次历史代价和第i+1次历史代价；ρ是定义的参数。
进一步地，所述步骤S2中，应用基于协商思想引导层分配的具体方法为：若当前被分配的段被分配到一条无剩余可用布线轨道数的边，则增大使用该边的代价，以引导后续被分配的段避免使用该边。
进一步地，所述步骤S3中，所述线网治愈算法引导时序非关键线网释放与时序关键线网共享的布线资源，以为时序关键线网的重分配提供更多的空间和灵活性，进而降低最大时延。
进一步地，所述步骤S4中，使用通孔柱优化方法将通孔柱和非默认规则线相结合，在结合通孔柱和非默认规则线时，考虑通孔柱的类型和线的类型，通孔柱的类型取决于该通孔柱所连线的类型，由于并行线占用两个布线轨道，宽线占用三个布线轨道，通孔柱类型的设置方法如下：一个连接并行线和默认规则线的通孔柱是2×1类型；一个连接两对并行线的通孔柱是2×2类型；一个连接宽线和默认规则线的通孔柱是3×1类型；一个连接宽线和并行线的通孔柱是3×2类型；一个连接两条宽线的通孔柱是3×3类型；若一个通孔柱连接默认规则线，则该通孔柱转变为一个常规通孔；若一个通孔柱在某一层上没有与线相连，则该通孔柱的类型取决于该层的默认规则线；对与时序关键线网的信号源直接相连的通孔段，使用2×2类型的通孔柱。
有益效果
相较于现有技术，本发明具有以下有益效果：提出了一种考虑通孔尺寸和耦合效应的先进制程下最小化时延和溢出的通孔柱感知层分配器，所述通孔柱感知层分配器通过减少溢出的拥塞松弛策略、优化最大时延的线网治愈算法以及有效结合通孔柱和非默认规则线的通孔柱优化方法，在考虑通孔拥塞、线拥塞和耦合效应的前提下优化时延和溢出，具有很强的实用性和广阔的应用前景。
附图说明
图1是现有的一种通孔柱结构示意图。
图2是本发明实施例中非默认规则线与默认规则线的对比图。
图3是本发明实施例中常规通孔模型示意图。
图4是本发明实施例中通孔、线和障碍物占用布线资源示意图。
图5是本发明实施例中各通孔柱类型示意图。
图6是本发明实施例中采用线网治愈算法优化层分配方案示意图。
图7是本发明实施例的通孔柱感知层分配器进行层分配方案设计的实现流程图。
本发明的实施方式
下面结合附图及具体实施例对本发明作进一步的详细说明。
非默认规则线：
非默认规则线的线宽不同于默认线宽。具体地说，不同布线层的默认线宽是不同的。上层的默认线宽通常大于下层的默认线宽。非默认规则线与默认规则线的对比如图2所示。在图2(a)中，分别使用并行线和默认规则线连接两个引脚，其中默认规则线占用一个布线轨道而并行线占用两个布线轨道。在图2(b)中，分别使用宽线和默认规则线连接两个引脚，其中默认规则线占用一个布线轨道而宽线占用三个布线轨道。与默认规则线相比，虽然非默认规则线占用更多的布线资源，但非默认规则线能够降低线电阻进而优化时延。
通孔柱：
一个通孔柱包含多个常规通孔。一个常规通孔的水平投影是一个矩形。该矩形的长和宽取决于与该通孔相连的、位于不同层的两条线的线宽和间距，如图3所示。若一个常规通孔在某层没有线与该通孔相连，则该常规通孔的水平投影的长或宽取决于该层的默认线宽和间距。
与常规通孔相比，通孔柱的电阻更小而电容更大。因此合理应用通孔柱可以减小时延，否则可能增大时延。例如对于一个线网，仅对下游的通孔段使用通孔柱技术，将会导致上游各段的时延增大，并最终导致线网时延增大。此外，与常规通孔相比，通孔柱可能会占用更多的布线资源，这会使得电路的拥塞恶化。因此，应当合理地使用通孔柱，以在优化时延的同时保障良好的可布线性。
布线拥塞：
在总体布线中，布线区域包括布线单元和边。为了减小总体布线和详细布线的不匹配程度，本发明不仅考虑了边容量、线宽和间距，还考虑了布线单元的面积和通孔的尺寸。具体地说，布线单元的面积由该布线单元的长与宽决定，边的容量由该边包含的轨道数决定。如图4所示，布线单元面积和布线轨道可以被线网的通孔和线，以及障碍物所占用。图4中最上方的轨道，由于被通孔占用，因而不能被其他线网使用，称为不可用的轨道。
若线网和障碍物对布线单元的面积占用量大于该布线单元的面积容量，则会发生布线单元面积溢出。若线网和障碍物对轨道的占用量大于该边的轨道容量，则会发生边溢出。布线单元g溢出of(g)和边e溢出of(e)的计算方式如下：
Figure PCTCN2020119326-appb-000007
Figure PCTCN2020119326-appb-000008
其中u(g)和c(g)分别表示g的当前面积使用量和容量。u(e)和c(e)分别表示e的当前轨道使用量和容量。布线单元面积溢出和边溢出可以归结于通孔对布线资源的占用和线对布线资源的占用。
本发明提供了一种考虑通孔尺寸和耦合效应的先进制程下最小化时延和溢出的通孔柱感知层分配器，如图7所示，所述通孔柱感知层分配器按如下步骤进行层分配方案的全自动设计：
S1)为后续阶段产生一个初始解；应用多角度拥塞松弛策略评估拥塞进而调整层分配方案，在保障良好时序特性的同时，减少溢出。
多角度拥塞松弛策略：
本发明采用多角度拥塞松弛策略优化拥塞进而改善可布线性。为了降低总体布线和详细布线之间的不匹配程度，所述多角度拥塞松弛策略从多个角度考虑占用布线资源的物体与提供布线资源的布线区域之间的相互关系。具体地说，布线区域的布线资源包括边的轨道和布线单元的面积，该些布线资源可以被线、通孔和障碍物占用。综合考虑这些因素，定义拥塞代价函数如下：
cong(s)＝cong(o)+cong(v)+cong(w)
Figure PCTCN2020119326-appb-000009
Figure PCTCN2020119326-appb-000010
Figure PCTCN2020119326-appb-000011
其中s表示一个线网段；o、v和w分别表示障碍物、通孔和线；段拥塞代价cong(s)包括障碍物拥塞代价cong(o)、通孔拥塞代价cong(v)和线拥塞代价cong(w)；若s是一通孔，则v表示该通孔且cong(w)为0；若s是一线段，则w表示该线段且cong(v)为0；e和g分别表示线网段s经过的边和布线单元；tc(e)和tc(g)分别表示e的边容量和g的面积容量；dc(e o)、dc(e v)和dc(e w)分别表示被障碍物、通孔和线占用的e中轨道的数量；dc(g o)、dc(g v)和dc(g w)分别表示被障碍物、通孔和线占用的g的面积；of(e w)是发生线溢出时的额外拥塞代价；h e是历史代价，其计算方式如下：
Figure PCTCN2020119326-appb-000012
其中
Figure PCTCN2020119326-appb-000013
和
Figure PCTCN2020119326-appb-000014
分别表示e的第i次历史代价和第i+1次历史代价；ρ是用户定义的参数，在本发明中设置为0.05。
多角度拥塞松弛策略能够优化布线区域的拥塞以降低线和通孔造成的溢出，同时保障良好时序特性。该策略通过对可选的方案进行更加细致的分析，量化各可选方案的优劣性作为代价。方案较优则该方案对应的代价低，方案较劣则该方案对应的代价高。最终选出代价低的方案引导层分配。
S2)在初始解的基础上，应用基于协商思想引导层分配。具体方法为：若当前被分配的段被分配到一条无剩余可用布线轨道数的边，则增大使用该边的 代价，以引导后续被分配的段避免使用该边。
S3)采用线网治愈算法优化当前层分配方案的最大时延；在此过程中，可以使用非默认规则线；并且，为了区分时序关键线网中的时序关键段与时序非关键段，采用段区分方法，根据段与信号源的距离给段赋值。靠近信号源的段为时序关键段，被赋予较大的值；远离信号源的段为时序非关键段，被赋予较小的值。通过这种方式将时序关键线网中时序关键段和时序非关键段进行区分。
线网治愈算法：
最大时延是影响芯片性能的重要因素。因此，本发明提出线网治愈算法降低最大时延。所述线网治愈算法引导时序非关键线网释放与时序关键线网共享的布线资源，为时序关键线网的重分配提供更多的空间和灵活性，进而降低最大时延。
图6给出一个示例用于解释所述线网治愈算法。n 1是一个时序非关键线网，n 2是最大时延线网。层分配顺序是n 1，n 2。图6(a)是n 1和n 2的2D布线方案，由图6(a)可知，n 1和n 2相互竞争布线资源。在3D布线区域中，每条边的容量是1，且上层的线电阻小于下层的线电阻。为了降低最大时延，最大时延线网应当具有使用布线资源的优先权。在使用线网治愈算法之前，n 1和n 2的原始层分配方案如图6(b)所示。图6(c)是使用线网治愈算法时n 1和n 2的3D布线方案，在线网治愈算法的引导下，n 2的层分配方案调整为图6(c)所示的层分配方案。为了保障良好的可布线性，n 1的层分配方案被调整为图6(d)所示的层分配方案。图6(d)给出了使用线网治愈算法之后n 1和n 2的最终层分配方案。
S4)将所有线网根据时延大小排序后重分配；优先处理时延大的线网即时序关键线网，同时对靠前(在本实施例中取前5％)的时序关键线网使用通孔柱优化方法，结合通孔柱和非默认规则线，以进一步降低时延，产生最终的具有良好时序特性和可布线性的层分配方案。
通孔柱优化方法：
为了提高层分配方案的质量，本发明合理地使用通孔柱降低线网时延并且 不引起拥塞恶化。具体地说，为了充分考虑线网时延、拥塞、线的类型和时序关键段，本发明通孔柱优化方法将通孔柱和非默认规则线合理地结合。
由于层分配中涉及的线网数量大，对每个线网使用通孔柱不仅没有必要而且会引起可布线性恶化。时序关键线网的时延是影响芯片性能的重要因素之一，并且时序关键线网的线长通常很大。因此，若将通孔柱用于时序关键线网的下游，时序关键线网上游各段的下游电容会增大，进而导致线网时延增大。所以，通孔柱应当被用于时序关键线网中靠近信号源的时序关键段以有效降低时延。
为了避免拥塞恶化，在结合通孔柱和非默认规则线时，本发明充分考虑通孔柱的类型和线的类型，通孔柱的类型取决于该通孔柱所连线的类型。具体地说，由于并行线占用两个布线轨道，宽线占用三个布线轨道，通孔柱类型的设置如下：
如图5(a)所示，一个连接并行线和默认规则线的通孔柱是2×1类型；如图5(b)所示，一个连接两对并行线的通孔柱是2×2类型；如图5(c)所示，一个连接宽线和默认规则线的通孔柱是3×1类型；如图5(d)所示，一个连接宽线和并行线的通孔柱是3×2类型。如图5(e)所示，一个连接两条宽线的通孔柱是3×3类型；此外，若一个通孔柱连接默认规则线，则该通孔柱转变为一个如图3所示的常规通孔；若一个通孔柱在某一层上没有与线相连，则该通孔柱的类型取决于该层的默认规则线；此外，考虑到与时序关键线网的信号源直接相连的通孔段的下游电容很大，为了恰当地协调时序和可布线性，本发明对该通孔段使用2×2类型的通孔柱。
以上是本发明的较佳实施例，凡依本发明技术方案所作的改变，所产生的功能作用未超出本发明技术方案的范围时，均属于本发明的保护范围。

Claims (5)

  1. 一种先进制程下最小化时延和溢出的通孔柱感知层分配器，其特征在于，所述通孔柱感知层分配器按如下步骤进行层分配方案的全自动设计：
    S1)为后续阶段产生一个初始解；应用多角度拥塞松弛策略评估拥塞进而调整层分配方案，在保障良好时序特性的同时，减少溢出；
    S2)在初始解的基础上，应用基于协商思想引导层分配；
    S3)采用线网治愈算法优化当前层分配方案的最大时延；在此过程中，可以使用非默认规则线；并且，采用段区分方法，根据段与信号源的距离给段赋值，以区分时序关键线网中的时序关键段与时序非关键段；
    S4)将所有线网根据时延大小排序后重分配；优先处理时延大的线网即时序关键线网，同时对靠前的时序关键线网使用通孔柱优化方法，结合通孔柱和非默认规则线，以进一步降低时延，产生最终的层分配方案。
  2. 根据权利要求1所述的先进制程下最小化时延和溢出的通孔柱感知层分配器，其特征在于，所述步骤S1中，应用多角度拥塞松弛策略评估拥塞的具体方法为：
    所述多角度拥塞松弛策略从多个角度考虑占用布线资源的物体与提供布线资源的布线区域之间的相互关系，具体为：布线区域的布线资源包括边的轨道和布线单元的面积，所述布线资源可以被线、通孔和障碍物占用，综合考虑这些因素，定义拥塞代价函数如下：
    cong(s)＝cong(o)+cong(v)+cong(w)
    Figure PCTCN2020119326-appb-100001
    Figure PCTCN2020119326-appb-100002
    Figure PCTCN2020119326-appb-100003
    其中s表示一个线网段；o、v和w分别表示障碍物、通孔和线；段拥塞代价cong(s)包括障碍物拥塞代价cong(o)、通孔拥塞代价cong(v)和线拥塞代价cong(w)；若s是一通孔，则v表示该通孔且cong(w)为0；若s是一线段，则w表示该线段且cong(v)为0；e和g分别表示线网段s经过的边和布线单元；tc(e)和tc(g)分别表示e的边容量和g的面积容量；dc(e o)、dc(e v)和dc(e w)分别表示被障碍物、通孔和线占用的e中轨道的数量；dc(g o)、dc(g v)和dc(g w)分别表示被障碍物、通孔和线占用的g的面积；of(e w)是发生线溢出时的额外拥塞代价；h e是历史代价，其计算方式如下：
    Figure PCTCN2020119326-appb-100004
    其中
    Figure PCTCN2020119326-appb-100005
    和
    Figure PCTCN2020119326-appb-100006
    分别表示e的第i次历史代价和第i+1次历史代价；ρ是定义的参数。
  3. 根据权利要求1所述的先进制程下最小化时延和溢出的通孔柱感知层分配器，其特征在于，所述步骤S2中，应用基于协商思想引导层分配的具体方法为：若当前被分配的段被分配到一条无剩余可用布线轨道数的边，则增大使用该边的代价，以引导后续被分配的段避免使用该边。
  4. 根据权利要求1所述的先进制程下最小化时延和溢出的通孔柱感知层分配器，其特征在于，所述步骤S3中，所述线网治愈算法引导时序非关键线网释放与时序关键线网共享的布线资源，以为时序关键线网的重分配提供更多的空间和灵活性，进而降低最大时延。
  5. 根据权利要求1所述的先进制程下最小化时延和溢出的通孔柱感知层分配器，其特征在于，所述步骤S4中，使用通孔柱优化方法将通孔柱和非默认规 则线相结合，在结合通孔柱和非默认规则线时，考虑通孔柱的类型和线的类型，通孔柱的类型取决于该通孔柱所连线的类型，由于并行线占用两个布线轨道，宽线占用三个布线轨道，通孔柱类型的设置方法如下：一个连接并行线和默认规则线的通孔柱是2×1类型；一个连接两对并行线的通孔柱是2×2类型；一个连接宽线和默认规则线的通孔柱是3×1类型；一个连接宽线和并行线的通孔柱是3×2类型；一个连接两条宽线的通孔柱是3×3类型；若一个通孔柱连接默认规则线，则该通孔柱转变为一个常规通孔；若一个通孔柱在某一层上没有与线相连，则该通孔柱的类型取决于该层的默认规则线；对与时序关键线网的信号源直接相连的通孔段，使用2×2类型的通孔柱。
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