WO2021168842A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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WO2021168842A1
WO2021168842A1 PCT/CN2020/077300 CN2020077300W WO2021168842A1 WO 2021168842 A1 WO2021168842 A1 WO 2021168842A1 CN 2020077300 W CN2020077300 W CN 2020077300W WO 2021168842 A1 WO2021168842 A1 WO 2021168842A1
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Prior art keywords
electrode
compensation
array substrate
gate
area
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PCT/CN2020/077300
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English (en)
French (fr)
Inventor
王洋
冯博
魏旃
王世君
穆文凯
刘屹
田丽
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to CN202080000203.4A priority Critical patent/CN113678056B/zh
Priority to CN202310063814.9A priority patent/CN115951528B/zh
Priority to PCT/CN2020/077300 priority patent/WO2021168842A1/zh
Publication of WO2021168842A1 publication Critical patent/WO2021168842A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the liquid crystal display mainly includes an array substrate and a color filter substrate arranged oppositely, and a liquid crystal layer located between the array substrate and the color filter substrate.
  • the array substrate is provided with thin film transistors, pixel electrodes, data lines and gates. During the preparation of the array substrate, the source and drain electrode layers of the thin film transistor will shift due to process fluctuations during sputtering, which will cause the Ioff and Cgs of the thin film transistor to fluctuate, thereby affecting the performance of the thin film transistor.
  • the embodiments of the present disclosure provide an array substrate and a liquid crystal display panel, and the specific solutions are as follows:
  • An embodiment of the present disclosure provides an array substrate, wherein the array substrate includes a plurality of pixel electrodes arranged in a matrix, a pixel transistor connected to each of the pixel electrodes, a plurality of scan lines and a plurality of data lines;
  • the gate of the pixel transistor is connected to the scan line, the first electrode of the pixel transistor is connected to the pixel electrode, and the second electrode of the pixel transistor is connected to the data line;
  • the pixel transistor further includes: a compensation gate connected to the scan line and a compensation electrode connected to the first electrode;
  • the compensation electrode and the first electrode are arranged side by side along the extension direction of the scan line;
  • the compensation gate and the gate are arranged side by side and spaced apart along the extension direction of the scan line;
  • the compensation grid and the compensation electrode are located on the same side of the grid.
  • the compensation electrode and the first electrode are an integral structure.
  • the compensation gate and the gate are provided in the same layer.
  • the distance between the compensation gate and the gate along the scan line direction is smaller than the width of the compensation electrode along the scan line direction.
  • the orthographic projection of the compensation gate and the compensation electrode on the array substrate at least partially overlap.
  • the overlap area of the compensation grid and the compensation electrode on the orthographic projection of the array substrate is a first area
  • the grid and the The overlapping area of the orthographic projection of the first electrode on the array substrate is the second area
  • the sum of the first area and the second area is greater than or the area of the first electrode and less than or equal to 1.3 times the area of the first electrode.
  • the compensation electrode includes a strip portion extending along the extension direction of the scan line
  • the first electrode is electrically connected to the pixel electrode through the complementary strip-shaped portion.
  • the compensation electrode further includes a protrusion located on a side of the strip portion close to the pixel electrode and protruding along the extending direction of the data line;
  • the width of the strip portion along the extending direction of the data line is smaller than the width of the compensation gate along the extending direction of the data line;
  • the width of the protruding portion and the bar-shaped portion along the extending direction of the data line is greater than or equal to the width of the compensation gate along the extending direction of the data line.
  • the area of the compensation gate is smaller than the area of the gate.
  • an embodiment of the present disclosure also provides a liquid crystal display panel, including an array substrate and a counter substrate that are arranged oppositely, and a liquid crystal layer located between the array substrate and the counter substrate; wherein the array The substrate is any of the above-mentioned array substrates provided by the embodiments of the present invention.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a pixel transistor provided by an embodiment of the disclosure when there is no deviation in alignment
  • FIG. 3 is a schematic diagram of the structure of the pixel transistor shown in FIG. 2 when the alignment shift occurs;
  • FIG. 4 is a schematic diagram of the structure of the first electrode, the second electrode and the compensation electrode of the pixel transistor shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the structure of the compensation gate and the gate of the pixel transistor shown in FIG. 2;
  • FIG. 6 is a schematic structural diagram of another pixel transistor provided by an embodiment of the disclosure when there is no deviation in alignment
  • FIG. 7 is a schematic diagram of the structure of the pixel transistor shown in FIG. 6 when the alignment shift occurs;
  • FIG. 8 is a schematic diagram of the structure of the first electrode, the second electrode and the compensation electrode of the pixel transistor shown in FIG. 6;
  • FIG. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the disclosure.
  • the array substrate includes a plurality of pixel electrodes 01 arranged in a matrix, a pixel transistor 02 connected to each pixel electrode 01, a plurality of scan lines G1, and a plurality of data lines. D1; Among them, the gate 023 of the pixel transistor 02 is connected to the scan line G1, the first electrode 021 of the pixel transistor 02 is connected to the pixel electrode 01, and the second electrode 022 of the pixel transistor 02 is connected to the data line D1;
  • the pixel transistor 02 further includes: a compensation gate 024 connected to the scan line G1 and a compensation electrode 025 connected to the first electrode 021;
  • the compensation electrode 025 and the first electrode 021 are arranged side by side along the extension direction of the scan line G1;
  • the compensation gate 024 and the gate 023 are arranged side by side and spaced apart along the extension direction of the scan line G1;
  • the compensation grid 024 and the compensation electrode 025 are located on the same side of the grid 023.
  • the pixel transistor further includes a compensation gate 024 connected to the scan line G1 and a compensation electrode 025 connected to the first electrode 021; the compensation electrode 025 and the first electrode 021 extend along the scan line G1
  • the extension direction is arranged side by side; the compensation gate 024 and the gate 023 are arranged side by side and spaced along the extension direction of the scan line G1; the compensation gate 024 and the compensation electrode 025 are located on the same side of the gate 023.
  • the alignment offset causes the compensation gate 024 to overlap the compensation electrode 025, so that the overlap area of the compensation gate 024 and the compensation electrode 025 is used to compensate the gate 023, the first electrode 021 and the second electrode due to the alignment offset.
  • the reduction of the overlapping area of 022 avoids changes in the performance of Cgs, Ioff, etc. caused by the change of the overlapped panel of the gate 023, the first electrode 021 and the second electrode 022, thereby stabilizing the performance of the pixel transistor.
  • the pixel transistor may be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor). Make a limit.
  • TFT Thin Film Transistor
  • MOS metal oxide semiconductor field effect transistor
  • the first electrode of the pixel transistor may be the source and the second electrode may be the drain, or the first electrode of the pixel transistor may be the drain and the second electrode may be the source, which is not used here. Specific distinction.
  • the compensation electrode 025 and the first electrode 021 have an integral structure, so that no new construction process is required, thereby avoiding an increase in production cost. .
  • the compensation gate 024 and the gate 023 are arranged in the same layer, so that there is no need to add a new construction process, thereby avoiding an increase in production costs. .
  • the distance s2 between the compensation gate 024 and the gate 023 along the direction of the scan line G1 is smaller than the distance s2 of the compensation electrode 025 along the direction of the scan line G1. Width s1.
  • the orthographic projection of the compensation gate 024 and the compensation electrode 025 on the array substrate at least partially overlap.
  • the overlapping area of the compensation gate 024 and the compensation electrode 025 is small so as not to affect the performance of the pixel transistor.
  • the compensation gate 024 and the compensation electrode becomes larger, which can ensure that changes in the performance of Cgs, Ioff, etc. caused by the change of the gate 023 and the first electrode overlapped panel can be avoided, thereby stabilizing the performance of the pixel transistor.
  • the overlap area of the compensation grid and the compensation electrode on the orthographic projection of the array substrate is the first area, and the overlap area of the grid and the first electrode on the orthographic projection of the array substrate Is the second area;
  • the sum of the first area and the second area is greater than the area of the first electrode and less than or equal to 1.3 times the area of the first electrode.
  • the sum of the first area and the second area is always within a certain range to avoid the occurrence of the sum of the first area and the second area. Too much fluctuation.
  • the area of the first electrode is A1, and the sum of the first area and the second area may be 1.05A1, 1.1A1, 1.15A1, 1.2A1, 1.25A1, or 1.3A1.
  • the compensation electrode 025 includes a strip portion 0251 extending along the extension direction of the scan line G1;
  • the first electrode 021 is electrically connected to the pixel electrode 01 through the strip portion 0251.
  • the gap between the first electrode 021 and the pixel electrode 01 is used to set the compensation electrode 025 to minimize the impact on the pixel aperture ratio.
  • the compensation electrode 025 further includes a protrusion located on the side of the strip portion 0251 close to the pixel electrode 01 and protruding along the extension direction of the data line D1 Department 0252;
  • the width w1 of the strip portion 0251 along the extending direction of the data line D1 is smaller than the width w0 of the compensation gate 024 along the extending direction of the data line D1;
  • the width w2 of the protruding portion 0252 and the stripe portion 0251 along the extending direction of the data line D1 is greater than or equal to the width w0 of the compensation gate 024 along the extending direction of the data line D1.
  • the protrusion 0252 of the compensation electrode 025 is located between the gate 023 and the compensation gate 024. That is, using the protrusion 0252 to increase the area of the compensation electrode 025 can ensure that when the gate 023 is offset from the first electrode 021, the overlap area of the compensation electrode 025 and the compensation gate 024 is increased.
  • the protrusion 0252 of the compensation electrode 025 is located between the gate 023 and the compensation gate 024, which can ensure that the gate 023 and the first electrode When there is no deviation in the alignment between the 021 and the second electrode 022, the compensation grid 024 does not overlap the protrusion 0252.
  • the area of the compensation gate 024 is smaller than the area of the gate 023, thereby avoiding the influence of the area of the compensation gate 024 being too large.
  • the overall aperture ratio of the array substrate is smaller than the area of the gate 023, thereby avoiding the influence of the area of the compensation gate 024 being too large.
  • each row of pixel electrodes 01 corresponds to a scan line G1
  • each column of pixel electrodes 01 corresponds to a data line D1.
  • each row of pixel electrodes 01 is provided with one scan line G1 on both sides, and two adjacent rows of pixel electrodes 01 are provided with two scan lines G1.
  • the array substrate has a double-gate structure, which can reduce the data lines D1 by half, thereby helping to improve the resolution of the display panel.
  • the data line D1 zigzags in a "bow" shape along the column direction.
  • embodiments of the present disclosure also provide a liquid crystal display panel, including an array substrate and an opposite substrate, and a liquid crystal layer located between the array substrate and the opposite substrate; wherein the array substrate is Any of the above-mentioned array substrates provided by the embodiments of the invention. Since the principle of solving the problem of the liquid crystal display panel is similar to that of the aforementioned array substrate, the implementation of the liquid crystal display panel can refer to the implementation of the aforementioned array substrate, and the repetition will not be repeated.
  • the pixel transistor further includes a compensation gate connected to the scan line and a compensation electrode connected to the first electrode; the compensation electrode and the first electrode extend along the scan line The direction is arranged side by side; the compensation grid and the grid are arranged side by side and spaced along the extension direction of the scan line; the compensation grid and the compensation electrode are located on the same side of the grid.
  • the offset of the alignment makes the compensation grid and the compensation electrode Overlap, so as to use the overlap area of the compensation grid and the compensation electrode to compensate for the decrease in the overlap area of the grid and the first electrode and the second electrode caused by the alignment shift, and avoid the problem of the grid and the first electrode and the second electrode. Changes in the performance of Cgs, Ioff, etc. caused by the change of the two-electrode overlapping panel, thereby stabilizing the performance of the pixel transistor.

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Abstract

一种阵列基板及液晶显示面板，由于像素晶体管（02）中还包括与扫描线（G1）连接的补偿栅极（024）以及与第一电极（021）连接的补偿电极（025）；补偿电极（025）与第一电极（021）沿扫描线（G1）的延伸方向并排设置；补偿栅极（024）与栅极（023）沿扫描线（G1）的延伸方向并排且间隔设置；补偿栅极（024）与补偿电极（025）位于栅极（023）同一侧。在制备阵列基板时，当栅极（023）在沿扫描线（G1）方向发生对位误差时，虽然栅极（032）与第一电极（021）和第二电极（022）的重叠面积变小，但是由于对位偏移使补偿栅极（024）与补偿电极（025）重叠，从而利用补偿栅极（024）与补偿电极（025）的重叠面积来补偿因对位偏移而导致的栅极（023）与第一电极（021）和第二电极（022）的重叠面积的变小，从而稳定像素晶体管（02）的性能。

Description

阵列基板及液晶显示面板 技术领域
本公开涉及显示技术领域，尤指一种阵列基板及液晶显示面板。
背景技术
在平板显示装置中，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有体积小、功耗低、制造成本相对较低和无辐射等特点，在当前的平板显示器市场占据了主导地位。常见的液晶显示器可用作手机显示屏、Note Book显示屏、GPS显示屏、液晶电视的显示屏等。
液晶显示器主要包括相对设置的阵列基板和彩膜基板以及位于阵列基板和彩膜基板之间的液晶层。其中阵列基板中设置有薄膜晶体管、像素电极、数据线以及栅极。阵列基板在制备时，薄膜晶体管中源漏电极层在溅镀时由于工艺波动会导致源漏电极发生偏移，从而使薄膜晶体管的Ioff，Cgs等发生波动，从而影响薄膜晶体管的性能。
发明内容
本公开实施例提供了一种阵列基板及液晶显示面板，具体方案如下：
本公开实施例提供的一种阵列基板，其中，所述阵列基板包括矩阵排列的多个像素电极以及与个所述像素电极连接的像素晶体管，多条扫描线以及多条数据线；其中，所述像素晶体管的栅极与所述扫描线连接，所述像素晶体管的第一电极像素电极连接，所述像素晶体管的第二电极与所述数据线连接；
所述像素晶体管还包括：与所述扫描线连接的补偿栅极以及与所述第一电极连接的补偿电极；
所述补偿电极与所述第一电极沿所述扫描线的延伸方向并排设置；
所述补偿栅极与所述栅极沿所述扫描线的延伸方向并排且间隔设置；
所述补偿栅极与所述补偿电极位于所述栅极同一侧。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿电极与所述第一电极为一体结构。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿栅极与所述栅极同层设置。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿栅极与所述栅极沿所述扫描线方向的距离小于所述补偿电极沿所述扫描线方向的宽度。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿栅极与所述补偿电极在所述阵列基板的正投影至少部分重叠。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿栅极与所述补偿电极在所述阵列基板的正投影的重叠面积为第一面积，所述栅极与所述第一电极在所述阵列基板的正投影的重叠面积为第二面积；
所述第一面积与所述第二面积之和大于或所述第一电极的面积且小于或等于所述第一电极的面积的1.3倍。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿电极包括沿所述扫描线延伸方向延伸的条形部；
所述第一电极通过所述补条形部与所述像素电极电连接。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿电极还包括位于所述条形部靠近所述像素电极一侧且沿所述数据线延伸方向突出的突出部；
所述条形部沿所述数据线延伸方向的宽度小于所述补偿栅极沿所述数据线延伸方向的宽度；
所述突出部和所述条形部沿所述数据线延伸方向的宽度大于或等于所述补偿栅极沿所述数据线延伸方向的宽度。
可选地，在本公开实施例提供的阵列基板中，其中，所述补偿栅极的面积小于所述栅极的面积。
相应地，本公开实施例还提供了一种液晶显示面板，包括相对设置的阵 列基板和对向基板，以及位于所述阵列基板和所述对向基板之间的液晶层；其中，所述阵列基板为本发明实施例提供的上述任一种阵列基板。
附图说明
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的一种像素晶体管在对位无偏差时的结构示意图；
图3为图2所示的像素晶体管在发生对位偏移时的结构示意图；
图4为图2所示的像素晶体管的第一电极、第二电极和补偿电极的结构示意图；
图5为图2所示的像素晶体管的补偿栅极和栅极的结构示意图；
图6为本公开实施例提供的另一种像素晶体管在对位无偏差时的结构示意图；
图7为图6所示的像素晶体管在发生对位偏移时的结构示意图；
图8为图6所示的像素晶体管的第一电极、第二电极和补偿电极的结构示意图；
图9为本公开实施例提供的另一种阵列基板的结构示意图；
图10为本公开实施例提供的又一种阵列基板的结构示意图。
具体实施方式
为使本公开的上述目的、特征和优点能够更为明显易懂，下面将结合附图和实施例对本公开做进一步说明。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开更全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本公开中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本公开保护范围内。 本公开的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是，在以下描述中阐述了具体细节以便于充分理解本公开。但是本公开能够以多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本公开内涵的情况下做类似推广。因此本公开不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式，然所述描述乃以说明本申请的一般原则为目的，并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
下面结合附图，对本公开实施例提供的阵列基板及液晶显示面板进行具体说明。
本公开实施例提供的一种阵列基板，如图1所示，阵列基板包括矩阵排列的多个像素电极01以及与个像素电极01连接的像素晶体管02，多条扫描线G1以及多条数据线D1；其中，像素晶体管02的栅极023与扫描线G1连接，像素晶体管02的第一电极021与像素电极01连接，像素晶体管02的第二电极022与数据线D1连接；
如图2至图5所示，像素晶体管02还包括：与扫描线G1连接的补偿栅极024以及与第一电极021连接的补偿电极025；
补偿电极025与第一电极021沿扫描线G1的延伸方向并排设置；
补偿栅极024与栅极023沿扫描线G1的延伸方向并排且间隔设置；
补偿栅极024与补偿电极025位于栅极023同一侧。
本公开实施例提供的阵列基板，由于像素晶体管中还包括与扫描线G1连接的补偿栅极024以及与第一电极021连接的补偿电极025；补偿电极025与第一电极021沿扫描线G1的延伸方向并排设置；补偿栅极024与栅极023沿扫描线G1的延伸方向并排且间隔设置；补偿栅极024与补偿电极025位于栅极023同一侧。在制备阵列基板时，如图3所示，当栅极023在沿扫描线G1方向发生对位误差时，虽然栅极023与第一电极021和第二电极022的重叠面积变小，但是由于对位偏移使补偿栅极024与补偿电极025重叠，从而利用补偿栅极024与补偿电极025的重叠面积来补偿因对位偏移而导致的栅极 023与第一电极021和第二电极022的重叠面积的变小，避免因为栅极023与第一电极021和第二电极022重叠面板发生变化而引起的Cgs、Ioff等性能的变动，从而稳定像素晶体管的性能。
在具体实施时，本公开实施例提供的阵列基板中，像素晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不做限定。
在本公开实施例中，像素晶体管的第一电极可以为源极，第二电极可以为漏极，或者，像素晶体管的第一电极可以为漏极，第二电极可以为源极，在此不作具体区分。
可选地，在本公开实施例提供的阵列基板中，如图2和图4所示，补偿电极025与第一电极021为一体结构，这样可以不用增加新的构工艺，从而避免增加生产成本。
可选地，在本公开实施例提供的阵列基板中，如图2和图5所示，补偿栅极024与栅极023同层设置，这样可以不用增加新的构工艺，从而避免增加生产成本。
可选地，在本公开实施例提供的阵列基板中，如图4和图5所示，补偿栅极024与栅极023沿扫描线G1方向的距离s2小于补偿电极025沿扫描线G1方向的宽度s1。
可选地，在本公开实施例提供的阵列基板中，如图2所示，补偿栅极024与补偿电极025在阵列基板的正投影至少部分重叠。具体地，如图2所示，当栅极023与第一电极021和第二电极022对位无偏差时，补偿栅极024和补偿电极025的重叠面积较小从而不影响像素晶体管的性能。如图3所示，当栅极023在沿扫描线G1方向发生对位误差时，虽然栅极023与第一电极021和第二电极022的重叠面积变小，但是补偿栅极024与补偿电极025的交叠面积变大，从而可以保证避免因为栅极023与第一电极重叠面板发生变化而引起的Cgs、Ioff等性能的变动，从而稳定像素晶体管的性能。
可选地，在本公开实施例提供的阵列基板中，补偿栅极与补偿电极在阵 列基板的正投影的重叠面积为第一面积，栅极与第一电极在阵列基板的正投影的重叠面积为第二面积；
第一面积与第二面积之和大于第一电极的面积且小于或等于第一电极的面积的1.3倍。
即保证当栅极与第一电极沿扫描线方向的对位偏移在一定范围内时，第一面积与第二面积之和始终在一定范围内，避免第一面积与第二面积之和发生太大波动。
在具体实施时，例如第一电极的面积为A1，第一面积和第二面积之和可以为1.05A1，1.1A1、1.15A1、1.2A1、1.25A1或1.3A1等。
可选地，在本公开实施例提供的阵列基板中，如图2和图4所示，补偿电极025包括沿扫描线G1延伸方向延伸的条形部0251；
第一电极021通过条形部0251与像素电极01电连接。
即利用第一电极021与像素电极01之间的间隙设置补偿电极025，尽可能的减小对像素开口率的影响。
可选地，在本公开实施例提供的阵列基板中，如图6至图8所示，补偿电极025还包括位于条形部0251靠近像素电极01一侧且沿数据线D1延伸方向突出的突出部0252；
如图5和图8所示，条形部0251沿数据线D1延伸方向的宽度w1小于补偿栅极024沿数据线D1延伸方向的宽度w0；
突出部0252和条形部0251沿数据线D1延伸方向的宽度w2大于或等于补偿栅极024沿数据线D1延伸方向的宽度w0。
在具体实施时，当栅极023与第一电极021和第二电极022对位无偏差时，补偿电极025的突出部0252位于栅极023与补偿栅极024之间。即利用突出部0252增加补偿电极025的面积可以保证当栅极023与第一电极021对位发生偏移时，增大补偿电极025与补偿栅极024的重叠面积。而当栅极023与第一电极021和第二电极022对位无偏差时，补偿电极025的突出部0252位于栅极023与补偿栅极024之间，可以保证当栅极023与第一电极021和 第二电极022对位无偏差时，补偿栅极024与突出部0252不重叠。
可选地，在本公开实施例提供的阵列基板中，如图2、图5和图6所示，补偿栅极024的面积小于栅极023的面积，从而避免补偿栅极024面积太大影响阵列基板的整体开口率。
在具体实施时，在本公开实施例提供的阵列基板中，如图1所示，每行像素电极01分别对应一条扫描线G1，每一列像素电极01分别对应一条数据线D1。
可选地，在本公开实施例提供的阵列基板中，如图9所示，每行像素电极01的两侧分别设置有一条扫描线G1，且相邻两行像素电极01之间设置有两条扫描线G1；
位于同一行相邻的两个像素电极01共用同一数据线D1。即阵列基板为双栅结构，这样可以减少一半数据线D1，从而有利于提高显示面板的分辨率。
进一步地，在本公开实施例提供的阵列基板中，如图10所示，数据线D1沿列方向呈“弓”字型曲折延伸。
基于同一发明构思，本公开实施例还提供了一种液晶显示面板，包括相对设置的阵列基板和对向基板，以及位于阵列基板和对向基板之间的液晶层；其中，该阵列基板为本发明实施例提供的上述任一种阵列基板。由于该液晶显示面板解决问题的原理与前述一种阵列基板相似，因此该液晶显示面板的实施可以参见前述阵列基板的实施，重复之处不再赘述。
本公开实施例提供的一种阵列基板及液晶显示面板，由于像素晶体管中还包括与扫描线连接的补偿栅极以及与第一电极连接的补偿电极；补偿电极与第一电极沿扫描线的延伸方向并排设置；补偿栅极与栅极沿扫描线的延伸方向并排且间隔设置；补偿栅极与补偿电极位于栅极同一侧。在制备阵列基板时，当栅极在沿扫描线方向发生对位误差时，虽然栅极与第一电极和第二电极的重叠面积变小，但是由于对位偏移使补偿栅极与补偿电极重叠，从而利用补偿栅极与补偿电极的重叠面积来补偿因对位偏移而导致的栅极与第一电极和第二电极的重叠面积的变小，避免因为栅极与第一电极和第二电极重 叠面板发生变化而引起的Cgs、Ioff等性能的变动，从而稳定像素晶体管的性能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种阵列基板，其中，所述阵列基板包括矩阵排列的多个像素电极以及与个所述像素电极连接的像素晶体管，多条扫描线以及多条数据线；其中，所述像素晶体管的栅极与所述扫描线连接，所述像素晶体管的第一电极与像素电极连接，所述像素晶体管的第二电极与所述数据线连接；
    所述像素晶体管还包括：与所述扫描线连接的补偿栅极以及与所述第一电极连接的补偿电极；
    所述补偿电极与所述第一电极沿所述扫描线的延伸方向并排设置；
    所述补偿栅极与所述栅极沿所述扫描线的延伸方向并排且间隔设置；
    所述补偿栅极与所述补偿电极位于所述栅极同一侧。
  2. 如权利要求1所述的阵列基板，其中，所述补偿电极与所述第一电极为一体结构。
  3. 如权利要求1所述的阵列基板，其中，所述补偿栅极与所述栅极同层设置。
  4. 如权利要求1所述的阵列基板，其中，所述补偿栅极与所述栅极沿所述扫描线方向的距离小于所述补偿电极沿所述扫描线方向的宽度。
  5. 如权利要求4所述的阵列基板，其中，所述补偿栅极与所述补偿电极在所述阵列基板的正投影至少部分重叠。
  6. 如权利要求5所述的阵列基板，其中，所述补偿栅极与所述补偿电极在所述阵列基板的正投影的重叠面积为第一面积，所述栅极与所述第一电极在所述阵列基板的正投影的重叠面积为第二面积；
    所述第一面积与所述第二面积之和大于或所述第一电极的面积且小于或等于所述第一电极的面积的1.3倍。
  7. 如权利要求5所述的阵列基板，其中，所述补偿电极包括沿所述扫描线延伸方向延伸的条形部；
    所述第一电极通过所述条形部与所述像素电极电连接。
  8. 如权利要求7所述的阵列基板，其中，所述补偿电极还包括位于所述条形部靠近所述像素电极一侧且沿所述数据线延伸方向突出的突出部；
    所述条形部沿所述数据线延伸方向的宽度小于所述补偿栅极沿所述数据线延伸方向的宽度；
    所述突出部和所述条形部沿所述数据线延伸方向的宽度大于或等于所述补偿栅极沿所述数据线延伸方向的宽度。
  9. 如权利要求1所述的阵列基板，其中，所述补偿栅极的面积小于所述栅极的面积。
  10. 一种液晶显示面板，包括相对设置的阵列基板和对向基板，以及位于所述阵列基板和所述对向基板之间的液晶层；其中，所述阵列基板为如权利要求1-9任一项所述的阵列基板。
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