CN110689854A - 薄膜晶体管阵列基板及应用其的显示面板 - Google Patents

薄膜晶体管阵列基板及应用其的显示面板 Download PDF

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CN110689854A
CN110689854A CN201810731337.8A CN201810731337A CN110689854A CN 110689854 A CN110689854 A CN 110689854A CN 201810731337 A CN201810731337 A CN 201810731337A CN 110689854 A CN110689854 A CN 110689854A
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film transistor
thin film
sub
pixel
electrode
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熊园
方宁
柳智忠
王明宗
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Century Technology Shenzhen Corp Ltd
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Century Technology Shenzhen Corp Ltd
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Priority to CN201810731337.8A priority Critical patent/CN110689854A/zh
Priority to TW107123991A priority patent/TWI676166B/zh
Priority to US16/170,502 priority patent/US20200013363A1/en
Publication of CN110689854A publication Critical patent/CN110689854A/zh
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Abstract

一种薄膜晶体管阵列基板，包括多对扫描线组、多条数据线、多个像素单元以及一源极驱动器。每一对扫描线组包括沿第一方向延伸的第一扫描线和第二扫描线。多条数据线沿与所述第一方向交叉的第二方向延伸，并与所述多对扫描线组交叉。每一像素单元包括分别第一子像素和第二子像素。所述第一子像素电性连接第一扫描线，第二子像素电性连接第二扫描线。第一子像素和第二子像素分别位于同一数据线的相对的两侧并电性连接该数据线。多条数据线分别与源极驱动器电性连接，源极驱动器通过多条数据线为第一子像素输入的数据电压大于源极驱动器为第二子像素输入的数据电压。还提供应用上述薄膜晶体管阵列基板的显示面板。

Description

薄膜晶体管阵列基板及应用其的显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管阵列基板及应用其的显示面板。
背景技术
现行液晶显示技术中，扫描线驱动分为IC驱动和GOP(Gate on panel)驱动，两者之间的区别是一般的GOP驱动都存在预充电(Pre_charging)，而在双扫描线(Dual Gate)设计情况下，扫描线数量增加一倍，若使用GOP驱动，为保证画素能够充饱，会采用预充电这样的充电方式。
由于是双扫描线设计，扫描线数量增加一倍，导致充电时间缩短，在搭配2点反转(2dot inversion)或1+2点反转(1+2dot inversion)的情况下，出现奇偶列像素充电率的差异，以致奇偶列充同样电位时出现不同的亮度，在点灯观察纯画面时会出现明暗相间的竖条纹(V-line)，放大观察显示奇偶两列像素亮度上存在明显差异。
发明内容
一种薄膜晶体管阵列基板，包括：
多对扫描线组，每一对扫描线组包括沿第一方向延伸的第一扫描线和第二扫描线；
多条数据线，沿与所述第一方向交叉的第二方向延伸，并与所述多对扫描线组交叉；
多个像素单元，每一像素单元包括分别位于同一扫描线组的相对的两侧的第一子像素和第二子像素，所述第一子像素电性连接所述第一扫描线，所述第二子像素电性连接所述第二扫描线，所述第一子像素和所述第二子像素分别位于同一数据线的相对的两侧并电性连接该数据线；以及
一源极驱动器，所述多条数据线分别与所述源极驱动器电性连接，所述源极驱动器通过所述多条数据线为所述第一子像素输入的数据电压大于所述源极驱动器为所述第二子像素输入的数据电压。
一种显示面板，所述显示面板包括彩色滤光片基板、液晶层以及上述的薄膜晶体管阵列基板，所述液晶层夹设于所述彩色滤光片基板与所述薄膜晶体管阵列基板之间。
本发明实施例提供的显示面板，通过调整源极驱动器为第一子像素和第二子像素输入数据电压的大小，以使第一子像素和第二子像素充电完成后，第一子像素的实际的像素电压和第二子像素的实际的像素电压趋于一致，进而减小第一子像素所在列和第二子像素所在列的像素充电率的差异，避免明暗相间的竖条纹现象，改善显示质量。
附图说明
图1为本发明较佳实施方式的显示面板的剖面示意图。
图2为本发明较佳实施方式的薄膜晶体管阵列基板的电路布局示意图。
图3A和图3B为本发明较佳实施方式的薄膜晶体管阵列基板的时序图。
图4A和图4B为实验测得的本发明较佳实施方式的薄膜晶体管阵列基板的时序图。
图5为本发明较佳实施方式的薄膜晶体管阵列基板的局部剖面图。
图6A和图6B为实验测得的本发明较佳实施方式的薄膜晶体管阵列基板的时序图。
主要元件符号说明
Figure BDA0001720967550000021
Figure BDA0001720967550000031
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
如图1所示，本发明较佳实施方式的显示面板100包括彩色滤光片(Color Filter，CF)基板120、液晶层130以及薄膜晶体管阵列(Thin Film Transistor，TFT)基板110。所述彩色滤光片基板120和所述薄膜晶体管阵列基板110相对设置，所述液晶层130夹设于所述彩色滤光片基板120与所述薄膜晶体管阵列基板110之间。
如图2所示，薄膜晶体管阵列基板110包括多对扫描线组30、多条数据线D1-Dn以及多个像素单元40。每一对扫描线组30包括沿第一方向X延伸的第一扫描线G1和第二扫描线G2。每一条数据线Dn沿与所述第一方向X交叉的第二方向Y延伸，并与所述多对扫描线组30交叉。每一像素单元40包括分别位于同一扫描线组30的相对的两侧的第一子像素50和第二子像素60。所述第一子像素50电性连接所述第一扫描线G1，所述第二子像素60电性连接所述第二扫描线G2，所述第一子像素50和所述第二子像素60分别位于同一数据线Dn的相对的两侧并电性连接同一数据线Dn。
如图2所示，所述薄膜晶体管阵列基板110还包括栅极驱动器20和源极驱动器10。多条第一扫描线G1和多条第二扫描线G2分别与所述栅极驱动器20电性连接。多条数据线D1-Dn分别与所述源极驱动器10电性连接。所述栅极驱动器20用于驱动多条第一扫描线G1和多条第二扫描线G2。所述源极驱动器10通过所述多条数据线D1-Dn为所述第一子像素50和所述第二子像素60输入数据电压。
如图2所示，所述第一子像素50包括一第一子像素电极52(如图5所示)、一第一薄膜晶体管M1以及与所述第一薄膜晶体管M1对应连接的一第一液晶电容和一第一储存电容。所述第一薄膜晶体管M1包括一栅极54、一源极56以及一漏极58。所述第一薄膜晶体管M1的栅极54电性连接所述第一扫描线G1。所述第一薄膜晶体管M1的源极56电性连接所述数据线Dn。所述第一薄膜晶体管M1的漏极58电性连接所述第一液晶电容和一第一储存电容的一端。所述源极驱动器10通过所述数据线Dn传输一数据电压至第一薄膜晶体管M1。所述第一扫描线G1控制第一薄膜晶体管M1接收该数据电压，进而控制所述第一液晶电容的充放电。第一储存电容用来维持第一液晶电容两端的电位差，以防第一液晶电容漏电的情况发生。
如图2所示，所述第二子像素60包括一第二子像素电极62(如图5所示)、一第二薄膜晶体管M2以及与所述第二薄膜晶体管M2对应连接的一第二液晶电容和一第二储存电容。所述第二薄膜晶体管M2包括一栅极64、一源极66以及一漏极68。所述第二薄膜晶体管M2的栅极64电性连接所述第二扫描线G2。所述第二薄膜晶体管M2的源极66电性连接所述数据线Dn。所述第二薄膜晶体管M2的漏极68电性连接所述第二液晶电容和所述第二储存电容的一端。所述源极驱动器10通过所述数据线Dn传输一数据电压至所述第二薄膜晶体管M2。所述第二扫描线G2控制第二薄膜晶体管M2接收该数据电压，进而控制所述第二液晶电容的充放电。第二储存电容用来维持第二液晶电容两端的电位差，以防第二液晶电容漏电的情况发生。
如图3A和图3B所示，同一像素单元40中，数据线Dn的有效时段(如高电平)分为第一子驱动时段Ta和第二子驱动时段Tb。在第一子驱动时段Ta，所述源极驱动器10通过数据线Dn为第一子像素50输入的数据电压。在第二子驱动时段Tb，所述源极驱动器10通过数据线Dn为第二子像素60输入的数据电压。
如图3A和图3B所示，第一子驱动时段Ta包括第一充电时段T1和第一OE(OutputEnable)时段T2，第二子驱动时段Tb包括第二充电时段T1’和第二OE时段T2’。本实施例中，在第一充电时段T1，所述源极驱动器10通过数据线Dn为第一子像素50输入的数据电压。在第一OE时段T2，第一扫描线G1上的信号和OE信号在逻辑上作AND，提前将该第一扫描线G1关闭。在第二充电时段T1’，所述源极驱动器10通过数据线Dn为第二子像素60输入的数据电压。在第二OE时段T2’，第二扫描线G2上的信号和OE信号在逻辑上作AND，提前将该第二扫描线G2关闭。
如图3A所示，在第一子驱动时段Ta的第一充电时段T1，第一扫描线G1上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第一扫描线G1上的多个第一子像素50输入数据电压。在第一子驱动时段Ta的第一OE时段T2，第一扫描线G1上的信号无效(如为低电平)，该第一扫描线G1上的信号和OE信号(此时段OE信号为高电平)在逻辑上作AND，提前将该第一扫描线G1关闭。
如图3B所示，在第二子驱动时段Tb的第一充电时段T1’，第二扫描线G2上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第二扫描线G2上的多个第二子像素60输入数据电压。在第二子驱动时段Tb的第一OE时段T2’，第二扫描线G2上的信号无效(如为低电平)，该第二扫描线G2上的信号和OE信号(此时段OE信号为高电平)在逻辑上作AND，提前将该第二扫描线G2关闭。
本实施例中，在第一子驱动时段Ta的第一充电时段T1，数据线Dn为电性连接于第一扫描线G1上的多个第一子像素50输入数据电压大于其为电性连接于第二扫描线G2上的多个第二子像素60输入数据电压。
如图4A所示，在第一子驱动时段Ta，第一扫描线G1上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第一扫描线G1上的第一子像素50输入数据电压。其中，第一子像素50充电完成后，第一子像素50上的实际的像素电压V1(如a点所示)大致为9.97193V。
如图4B所示，在第二子驱动时段Tb，第二扫描线G2上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第二扫描线G2上的多个多个第二子像素60输入数据电压。结合图4A可知，数据线Dn为电性连接于第一扫描线G1上的第一子像素50输入数据电压大于数据线Dn为电性连接于第二扫描线G2上的多个第二子像素60输入数据电压。其中，第二子像素60充电完成后，第二子像素60的实际的像素电压V2(如b点所示)大致为10.00977V，其与第一像素的实际的像素电压V1基本趋于一致。
本实施例中，在搭配2点反转(2dot inversion)的情况下，通过提高所述源极驱动器10为所述第一子像素50输入的数据电压，使其大于所述源极驱动器10为所述第二子像素60输入的数据电压，使得第一子像素50和第二子像素60充电完成后，第一子像素50的实际的像素电压V1和第二子像素60的实际的像素电压V2趋于一致，减小了第一子像素50所在列和第二子像素60所在列的像素充电率的差异，进而避免明暗相间的竖条纹现象，改善显示质量。
可以理解地，在搭配1+2点反转(1+2dot inversion)，可通过提高所述源极驱动器10为所述第二子像素50输入的数据电压，使其大于所述源极驱动器10为所述第一子像素60输入的数据电压，使得第一子像素50和第二子像素60充电完成后，第一子像素50的实际的像素电压V1和第二子像素60的实际的像素电压V2趋于一致，减小了第一子像素50所在列和第二子像素60所在列的像素充电率的差异，进而避免明暗相间的竖条纹现象，改善显示质量。
如图5所示，所述第一薄膜晶体管M1的源极56、所述第二薄膜晶体管M2的源极66均大致呈一U形结构。所述第一薄膜晶体管M1的漏极58包括延伸至所述第一薄膜晶体管M1的源极56的开口中的第一插入部582和电性连接所述第一插入部582与所述第一子像素电极52的第一漏极连接部584。所述第二薄膜晶体管M2的漏极68包括延伸至所述第二薄膜晶体管M2的源极66的开口中的第二插入部682和电性连接所述第二插入部682与所述第二子像素电极62的第二漏极连接部684。
本实施例中，所述第一薄膜晶体管M1的源极56与所述第一插入部582定义第一U形沟道588。所述第二薄膜晶体管M2的源极66与所述第二插入部682定义第二U形沟道688。
本实施例中，定义第一U形沟道588的沟道宽度W为(W1+W2)/2,定义第二U形沟道688的沟道宽度W’为(W1’+W2’)/2。其中，W1为第一U形沟道588的外侧壁延伸长度(第一U形沟道588的外侧壁为所述第一U形沟道588远离第一薄膜晶体管M1的漏极58的侧壁)，W2为第一U形沟道588的内侧壁延伸长度(第一U形沟道588的内侧壁为所述第一U形沟道588靠近第一薄膜晶体管M1的漏极58的侧壁)。W1’为第二U形沟道688的外侧壁延伸长度，W2’为第二U形沟道688的内侧壁长度。定义第一U形沟道588的沟道长度L为第一U形沟道588沿平行第一方向X的最短延伸长度。定义第一U形沟道588的沟道长度L为第一U形沟道588沿平行第一方向X的最短延伸长度。定义第二U形沟道688的沟道长度L’为第二U形沟道688沿平行第一方向X的最短延伸长度。
如图5所示，所述第二U形沟道688的沟道宽度W’小于所述第一U形沟道588的沟道宽度W(即，W’<W)。所述第一U形沟道588的沟道长度L等于所述第二U形沟道688的沟道长度L’(即，L’＝L)。因此，本实施例中，第二薄膜晶体管M2的沟道的宽长比小于第一薄膜晶体管M1的沟道的宽长比(即，W’/L’<W/L)。而薄膜晶体管的充电电流的大小与其沟道的宽长比呈正比。本实施例中，通过将第一薄膜晶体管M1和第二薄膜晶体管M2的沟道宽度差异化，可降低第二子像素60的充电率。从而第一子像素50和第二子像素60充电完成后，第一子像素50的实际的像素电压V1和第二子像素60的实际的像素电压V2趋于一致，减小了第一子像素50所在列和第二子像素60所在列的像素充电率的差异，进而避免明暗相间的竖条纹现象，改善显示质量。
如图6A所示，在第一子驱动时段Ta，第一扫描线G1上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第一扫描线G1上的第一子像素50输入数据电压。其中，第一子像素50充电完成后，第一子像素50上的实际的像素电压V1(如a点所示)大致为9.34025V。
如图6B所示，在第二子驱动时段Tb，第二扫描线G2上的信号有效(如为高电平)，数据线Dn上的信号有效(如为高电平)。此时，数据线Dn为电性连接于第二扫描线G2上的多个第二子像素60输入数据电压。其中，第二子像素60充电完成后，第二子像素60的实际的像素电压V2(如b点所示)大致为9.36259V，结合图6A可知，其与第一像素的实际的像素电压V1基本趋于一致。
可以理解地，在搭配1+2点反转(1+2dot inversion)，可通过设计所述第一U形沟道588的沟道宽度W小于第二U形沟道688的沟道宽度W’(即，W<W’)。所述第一U形沟道588的沟道长度L等于所述第二U形沟道688的沟道长度L’(即，L’＝L)。即，第一薄膜晶体管M1的沟道的宽长比小于第二薄膜晶体管M2的沟道的宽长比(即，W/L<W’/L’)，降低第一子像素50的充电率，使得第一子像素50和第二子像素60充电完成后，第一子像素50的实际的像素电压V1和第二子像素60的实际的像素电压V2趋于一致，减小了第一子像素50所在列和第二子像素60所在列的像素充电率的差异，进而避免明暗相间的竖条纹现象，改善显示质量。
本实施例中，所述第一扫描线G1、所述第二扫描线G2、所述第一薄膜晶体管M1的栅极54、所述第二薄膜晶体管M2的栅极64由第一导电层形成。所述数据线Dn、所述第一薄膜晶体管M1的源极56、所述第一薄膜晶体管M1的漏极58、所述第二薄膜晶体管M2的源极66、所述第二薄膜晶体管M2的漏极68由第二导电层形成。
本实施例中，所述薄膜晶体管阵列基板110还包括补偿结构，当所述第一导电层与第二导电层存在对位偏差而导致所述第一导电层与第二导电层的重叠面积增加或减少时，所述补偿结构相应地减少或增加所述第一导电层与第二导电层的重叠面积。
如图5所示，所述补偿结构包括第一漏极补偿结构586和第二漏极补偿结构686。所述第一漏极补偿结构586为由所述第一薄膜晶体管M1的漏极58延伸而出的分支。所述第一漏极补偿结构586自所述第一薄膜晶体管M1的漏极58向远离所述第一薄膜晶体管M1的源极56的一侧延伸至邻近的第一扫描线G1，并与所述第一扫描线G1绝缘且部分层叠设置。
如图5所示，所述第二漏极补偿结构686为由所述第二薄膜晶体管M2的漏极68延伸而出的分支。所述第二漏极补偿结构686自所述第二薄膜晶体管M2的漏极68向远离所述第二薄膜晶体管M2的源极66的一侧延伸至邻近的第二扫描线G2，并与所述第二扫描线G2绝缘且部分层叠设置。所述第一漏极补偿结构586为由所述第一漏极连接部584向远离所述第一插入部582的一侧延伸而出的分支。所述第二漏极补偿结构686为由所述第二漏极连接部684向远离所述第二插入部682的一侧延伸而出的分支。
如图5所示，所述第一薄膜晶体管M1的漏极58与所述第一薄膜晶体管M1的栅极54层叠且绝缘设置并定义形成第一栅漏电容。所述第二薄膜晶体管M2的漏极68与所述第二薄膜晶体管M2的栅极64层叠且绝缘设置并定义形成第二栅漏电容。本实施例中，第一栅漏电容等于第二栅漏电容。
如图5所示，所述补偿结构还包括第一栅极补偿结构542和第二栅极补偿结构642。所述第一栅极补偿结构542为由所述第一扫描线G1向远离所述第一扫描线G1的方向延伸的凸起。所述第一漏极补偿结构586与所述第一栅极补偿结构542绝缘且部分层叠设置。所述第二栅极补偿结构642为由所述第二扫描线G2向远离所述第二扫描线G2的方向延伸的凸起。所述第二漏极补偿结构686与所述第二栅极补偿结构642绝缘且部分层叠设置。
以上实施方式仅用以说明本发明的技术方案而非限制，尽管参照较佳实施方式对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。

Claims (10)

1.一种薄膜晶体管阵列基板，包括：
多对扫描线组，每一对扫描线组包括沿第一方向延伸的第一扫描线和第二扫描线；
多条数据线，沿与所述第一方向交叉的第二方向延伸，并与所述多对扫描线组交叉；
多个像素单元，每一像素单元包括分别位于同一扫描线组的相对的两侧的第一子像素和第二子像素，所述第一子像素电性连接所述第一扫描线，所述第二子像素电性连接所述第二扫描线，所述第一子像素和所述第二子像素分别位于同一数据线的相对的两侧并电性连接该数据线；以及
一源极驱动器，所述多条数据线分别与所述源极驱动器电性连接，其特征在于，所述源极驱动器通过所述多条数据线为所述第一子像素输入的数据电压大于所述源极驱动器为所述第二子像素输入的数据电压。
2.如权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述第一子像素包括一第一子像素电极以及一第一薄膜晶体管，所述第二子像素包括一第二子像素电极以及一第二薄膜晶体管，所述第一薄膜晶体管和所述第二薄膜晶体管各包括一栅极、一源极以及一漏极；
所述第一薄膜晶体管的栅极电性连接所述第一扫描线，所述第一薄膜晶体管的源极电性连接所述数据线，所述第一薄膜晶体管的漏极电性连接所述第一子像素电极；
所述第二薄膜晶体管的栅极电性连接所述第二扫描线，所述第二薄膜晶体管的源极电性连接所述数据线，所述第二薄膜晶体管的漏极电性连接所述第二子像素电极。
3.如权利要求2所述的薄膜晶体管阵列基板，其特征在于，所述第一薄膜晶体管的源极、所述第二薄膜晶体管的源极均大致呈一U形结构；
所述第一薄膜晶体管的漏极包括延伸至所述第一薄膜晶体管的源极的开口中的第一插入部和电性连接所述第一插入部与所述第一子像素电极的第一漏极连接部；
所述第二薄膜晶体管的漏极包括延伸至所述第二薄膜晶体管的源极的开口中的第二插入部和电性连接所述第二插入部与所述第二子像素电极的第二漏极连接部。
4.如权利要求3所述的薄膜晶体管阵列基板，其特征在于，所述第一薄膜晶体管的源极与所述第一插入部定义第一U形沟道；
所述第二薄膜晶体管的源极与所述第二插入部定义第二U形沟道；
定义所述第一U形沟道的沟道宽度为所述第一U形沟道的外侧壁延伸长度和所述第一U形沟道的内侧壁延伸长度之和的一半；
定义所述第二U形沟道的沟道宽度为所述第二U形沟道的外侧壁延伸长度和所述第二U形沟道的内侧壁延伸长度之和的一半；
所述第一U形沟道的沟道宽度大于所述第二U形沟道的沟道宽度。
5.如权利要求4所述的薄膜晶体管阵列基板，其特征在于，所述第一扫描线、一第二扫描线、所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极由第一导电层形成；
所述数据线、所述第一薄膜晶体管的源极、所述第一薄膜晶体管的漏极、所述第二薄膜晶体管的源极、所述第二薄膜晶体管的漏极由第二导电层形成。
6.如权利要求5所述的薄膜晶体管阵列基板，其特征在于，所述薄膜晶体管阵列基板还包括补偿结构，当所述第一导电层与第二导电层存在对位偏差而导致所述第一导电层与第二导电层的重叠面积增加或减少时，所述补偿结构相应地减少或增加所述第一导电层与第二导电层的重叠面积。
7.如权利要求6所述的薄膜晶体管阵列基板，其特征在于，所述补偿结构包括第一漏极补偿结构和第二漏极补偿结构；
所述第一漏极补偿结构为由所述第一薄膜晶体管的漏极延伸而出的分支，所述第一漏极补偿结构自所述第一薄膜晶体管的漏极向远离所述第一薄膜晶体管的源极的一侧延伸至邻近的第一扫描线，并与所述第一扫描线绝缘且部分层叠设置；
所述第二漏极补偿结构为由所述第二薄膜晶体管的漏极延伸而出的分支，所述第二漏极补偿结构自所述第二薄膜晶体管的漏极向远离所述第二薄膜晶体管的源极的一侧延伸至邻近的第二扫描线，并与所述第二扫描线绝缘且部分层叠设置。
8.如权利要求7所述的薄膜晶体管阵列基板，其特征在于，所述第一漏极补偿结构为由所述第一漏极连接部向远离所述第一插入部的一侧延伸而出的分支；
所述第二漏极补偿结构为由所述第二漏极连接部向远离所述第二插入部的一侧延伸而出的分支。
9.如权利要求7所述的薄膜晶体管阵列基板，其特征在于，所述补偿结构还包括第一栅极补偿结构和第二栅极补偿结构；
所述第一栅极补偿结构为由所述第一扫描线向远离所述第一扫描线的方向延伸的凸起，所述第一漏极补偿结构与所述第一栅极补偿结构绝缘且部分层叠设置；
所述第二栅极补偿结构为由所述第二扫描线向远离所述第二扫描线的方向延伸的凸起，所述第二漏极补偿结构与所述第二栅极补偿结构绝缘且部分层叠设置。
10.一种显示面板，包括彩色滤光片基板、液晶层以及薄膜晶体管阵列基板，所述液晶层夹设于所述彩色滤光片基板与所述薄膜晶体管阵列基板之间，其特征在于，所述薄膜晶体管阵列基板为如权利要求1至9中任意一项所述的薄膜晶体管阵列基板。
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