WO2021163976A1 - 显示面板、其驱动方法及显示装置 - Google Patents

显示面板、其驱动方法及显示装置 Download PDF

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Publication number
WO2021163976A1
WO2021163976A1 PCT/CN2020/076078 CN2020076078W WO2021163976A1 WO 2021163976 A1 WO2021163976 A1 WO 2021163976A1 CN 2020076078 W CN2020076078 W CN 2020076078W WO 2021163976 A1 WO2021163976 A1 WO 2021163976A1
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WIPO (PCT)
Prior art keywords
sub
base substrate
orthographic projection
pixel
area
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PCT/CN2020/076078
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English (en)
French (fr)
Inventor
秦相磊
林坚
张勇
张丽敏
孙泽鹏
杨智超
唐亮珍
段智龙
金红贵
安亚帅
乜玲芳
王建
田丽
庞净
宋雪超
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000156.3A priority Critical patent/CN113728375B/zh
Priority to PCT/CN2020/076078 priority patent/WO2021163976A1/zh
Priority to US17/755,302 priority patent/US11942053B2/en
Publication of WO2021163976A1 publication Critical patent/WO2021163976A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device.
  • transflective display panels have been widely used in display devices such as mobile phones and tablet computers due to their advantages of low power consumption and strong environmental adaptability.
  • a plurality of sub-pixels are arranged on the base substrate, and at least one of the plurality of sub-pixels includes a pixel electrode;
  • a plurality of transistors, the plurality of transistors include a plurality of first transistors, a plurality of second transistors, and a plurality of third transistors;
  • a plurality of data lines are arranged on the base substrate at intervals;
  • a plurality of gate lines are arranged on the base substrate at intervals; and the plurality of gate lines include a plurality of first gate lines, a plurality of second gate lines, and a plurality of third gate lines;
  • the row group has a first sub-row group and a second sub-row group arranged in a column direction;
  • the pixel electrode includes a first pixel electrode and a second pixel electrode;
  • One sub-pixel in the first sub-row group includes one first transistor and one first pixel electrode; wherein the gate of the first transistor in the first sub-row group is electrically connected to one of the A first gate line; and, in the same sub-pixel, the second electrode of the first transistor is electrically connected to the first pixel electrode;
  • One sub-pixel in the second sub-row group includes one second transistor and one second pixel electrode; wherein the gate of the second transistor in the second sub-row group is electrically connected to one of the A second gate line; and, in the same sub-pixel, the second electrode of the second transistor is electrically connected to the second pixel electrode;
  • two adjacent sub-pixels in the column direction share one third transistor; wherein the gate of the third transistor in the row group is electrically connected to one third gate line;
  • the first transistor and the second transistor in a column of sub-pixels are electrically connected to one of the data lines through a shared third transistor.
  • two adjacent sub-pixels in the column direction form a sub-pixel group
  • the sub-pixel group is configured to display at least a partial area of one pixel in the screen.
  • the active layer of the third transistor includes a first source region, a first drain region, a second drain region, a first channel region, and a second channel region
  • the first channel region is located between the first source region and the first drain region
  • the second channel region is located between the first source region and the second drain region
  • the first source region is electrically connected to the data line
  • the first drain region is electrically connected to the first electrode of the first transistor
  • the second drain region is electrically connected to the first electrode of the second transistor.
  • the display panel further includes:
  • the source conductive layer is located on the base substrate, and the source conductive layer includes the plurality of spaced data lines, a plurality of source connection portions, a plurality of first source portions, and a plurality of second source portions Wherein, one said source connection part, one said first source part and one said second source part are located in one said sub-pixel group;
  • the first source portion serves as the first electrode of the first transistor, and the second source portion serves as the first electrode of the second transistor;
  • the first source portion is electrically connected to the first drain region
  • the second source portion is electrically connected to the second drain region
  • the first source The area is electrically connected to the source connection part
  • the source connection part is electrically connected to one of the data lines.
  • the source connection portion includes: a first sub-source connection portion and a second sub-source connection portion that are electrically connected to each other; wherein, the first sub-source connection portion extends in a row direction , The second sub-source connection portion extends along the column direction; and, the first sub-source connection portion is electrically connected to the data line, and the second sub-source connection portion is electrically connected to the first source region .
  • the pixel electrode is configured as a reflective electrode; the first pixel electrode is provided with a first through hole, the second pixel electrode is provided with a second through hole, and the first pixel electrode is provided with a second through hole.
  • the area of the through hole is different from the area of the second through hole.
  • the base substrate has: a first partition and a second partition; wherein, the first partition covers one sub-pixel in the sub-pixel group, and the second partition Covering another sub-pixel of the sub-pixel group;
  • the display panel also includes:
  • the opposite substrate is arranged opposite to the base substrate;
  • the color resist layer is located between the base substrate and the opposite substrate, and the color resist layer includes: a sub-color resist layer located in each of the sub-pixels;
  • the sub-color resist layer has a first sub-color resist area and a second sub-color resist area, and in a direction perpendicular to the plane of the base substrate, the first sub-area covers the first sub-color resist Area, the second sub-area covers the second sub-color resistance area.
  • the first pixel electrode and the sub-color resist layer located in the first sub-color resist region have a first facing area
  • the second pixel electrode and the sub-color-resist layer located in the second sub-color-resist region have a second facing area
  • the first facing area is different from the second facing area.
  • the area of the first pixel electrode and the area of the second pixel electrode are approximately the same, and the area of the first sub-color resist region Smaller than the area of the second sub-color resistance region.
  • the sub-color resist layer located in the first partition is provided with a first via hole, and the first via hole penetrates the sub-color resist layer;
  • the orthographic projection of the first via on the base substrate and the orthographic projection of the first through hole on the base substrate do not overlap.
  • the area of the first pixel electrode is smaller than the area of the second pixel electrode, and the area of the first sub-color resist region is smaller than or Roughly equal to the area of the second sub-color resistance region.
  • the orthographic projection of the first through hole on the base substrate is not intersected with the orthographic projection of the source conductive layer and the gate conductive layer on the base substrate.
  • the orthographic projection of the second through hole on the base substrate does not overlap with the orthographic projection of the source conductive layer and the gate conductive layer on the base substrate, respectively.
  • the first gate line and the first pixel electrode that are electrically connected to the first transistor are on the base substrate.
  • the orthographic projection and the orthographic projection of the first pixel electrode on the base substrate respectively have overlapping areas; and/or,
  • the orthographic projections of the second gate line and the second transistor on the base substrate are respectively aligned with the second pixel electrode.
  • the orthographic projection of the base substrate has an overlapping area; and/or,
  • the first pixel electrode is provided with a first through hole
  • the second through hole includes a first sub-through hole and a second sub-through hole arranged at intervals
  • the orthographic projection of the first sub-via on the base substrate is closer to the data that the sub-pixels are electrically connected to the orthographic projection of the second sub-via on the base substrate The orthographic projection of the line on the base substrate; and/or,
  • the orthographic projection of the second sub-through hole on the base substrate is farther away from the data that the sub-pixel is electrically connected to the orthographic projection of the first sub-through hole on the base substrate The orthographic projection of the line on the base substrate.
  • the orthographic projection of the first sub-via on the base substrate is located at the orthographic projection of the first sub-source connection portion on the base substrate and the data line Between the orthographic projections of the base substrate, and the orthographic projection of the first sub-via on the base substrate is located between the orthographic projection of the second sub-source connecting portion on the base substrate and the The third grid line is between the orthographic projections of the base substrate.
  • the display panel further includes: a transparent conductive layer located on a side of the pixel electrode away from the base substrate;
  • the transparent conductive layer includes a plurality of first sub-transparent conductive parts arranged at intervals; wherein, the orthographic projection of one of the first sub-transparent conductive parts on the base substrate is located in one of the first sub-regions; the same In the first partition, the orthographic projection of the first sub-transparent conductive portion on the base substrate covers the orthographic projection of the first through hole on the base substrate, and the first sub-transparent conductive portion is located at all The orthographic projection of the base substrate is located within the orthographic projection of the first pixel electrode on the base substrate; and/or,
  • the transparent conductive layer includes a plurality of second sub-transparent conductive parts arranged at intervals; wherein, the orthographic projection of one second sub-transparent conductive part on the base substrate is located in one of the second sub-regions; the same In the second partition, the orthographic projection of the second sub-transparent conductive portion on the base substrate covers the orthographic projection of the second through hole on the base substrate, and the second sub-transparent conductive portion is located at all The orthographic projection of the base substrate is located within the orthographic projection of the second pixel electrode on the base substrate.
  • the display panel further includes:
  • the first planarization layer is located between the layer where the reflective electrode is located and the base substrate;
  • An auxiliary electrode layer located between the first planarization layer and the layer where the reflective electrode is located;
  • the second planarization layer is located between the auxiliary electrode layer and the layer where the reflective electrode is located;
  • the auxiliary electrode layer includes a plurality of first auxiliary electrodes arranged at intervals; wherein an orthographic projection of one of the first auxiliary electrodes on the base substrate is located in one of the first partitions; in the same first partition , The orthographic projection of the first pixel electrode on the base substrate covers the orthographic projection of the first auxiliary electrode on the base substrate; and/or,
  • the auxiliary electrode layer includes a plurality of second auxiliary electrodes arranged at intervals; wherein, the orthographic projection of one second auxiliary electrode on the base substrate is located in one of the second partitions; and in the same second partition The orthographic projection of the second pixel electrode on the base substrate covers the orthographic projection of the second auxiliary electrode on the base substrate.
  • the display panel further includes:
  • a gate insulating layer located between the source conductive layer and the base substrate;
  • the gate conductive layer further includes: a plurality of first compensation electrodes arranged at intervals; wherein, the orthographic projection of one of the first compensation electrodes on the base substrate is located in one of the first sub-regions; In the sub-area, the orthographic projection of the first pixel electrode on the base substrate covers the orthographic projection of the first compensation electrode on the base substrate, and the first compensation electrode is on the front of the base substrate.
  • the projection and the first drain portion of the first transistor have an overlapping area on the orthographic projection of the base substrate; and/or,
  • the gate conductive layer further includes: a plurality of second compensation electrodes arranged at intervals; wherein the orthographic projection of one second compensation electrode on the base substrate is located in one of the second sub-regions; In the sub-area, the orthographic projection of the second pixel electrode on the base substrate covers the orthographic projection of the second compensation electrode on the base substrate, and the second compensation electrode is on the front of the base substrate.
  • the projection and the orthographic projection of the second drain portion of the second transistor on the base substrate have an overlapping area.
  • An embodiment of the present disclosure provides a display device including the above-mentioned display panel.
  • the embodiment of the present disclosure provides a driving method of the above-mentioned display panel, including:
  • driving the sub-pixels in one row group in one data writing stage includes:
  • a gate-on signal is applied to the first gate line electrically connected to the sub-pixels of the first sub-row group in the row group, and the gate line is applied to the second gate line electrically connected to the sub-pixels of the first sub-row group to turn off Signal, apply a gate turn-on signal to the third gate line electrically connected to the sub-pixels of the first sub-row group, apply a data signal to each data line, and make the first pixel electrode of the first sub-row group input a data signal ;
  • a gate-off signal is applied to the first gate line electrically connected to the sub-pixels of the second sub-row group in the row group, and the gate is applied to the second gate line electrically connected to the sub-pixels of the second sub-row group to turn on Signal, apply a gate-on signal to the third gate line electrically connected to the sub-pixels of the second sub-row group, apply a data signal to each data line, and make the second pixel electrode of the second sub-row group input a data signal .
  • FIG. 1 is a schematic diagram of the structure of some display panels provided by the embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of some circuit structures provided by the embodiments of the disclosure.
  • FIG. 3 is a schematic diagram of some layout structures provided by the embodiments of the disclosure.
  • Fig. 4a is a schematic sectional view of the structure along the AA' direction in the schematic diagram shown in Fig. 3;
  • Fig. 4b is a schematic diagram of other cross-sectional structures along the AA' direction in the schematic diagram shown in Fig. 3;
  • FIG. 5 is a schematic structural diagram of other display panels provided by the embodiments of the present disclosure.
  • Fig. 6a is a schematic sectional view of the structure along the AA' direction in the schematic diagram shown in Fig. 5;
  • Fig. 6b is a schematic sectional view of the structure along the BB' direction in the schematic diagram shown in Fig. 5;
  • Fig. 6c is a schematic sectional view of the structure along the CC' direction in the schematic diagram shown in Fig. 5;
  • FIG. 7 is a schematic diagram of the structure of some sub-color resist layers provided by the embodiments of the disclosure.
  • FIG. 8 is a schematic diagram of the structure of other pixel electrodes provided by the embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of the structure of still other pixel electrodes provided by the embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of the structure of other sub-color resist layers provided by the embodiments of the present disclosure.
  • FIG. 11 is a flowchart of some driving methods provided by the embodiments of the disclosure.
  • FIG. 12 is a timing diagram of some signals provided by the embodiments of the disclosure.
  • FIG. 13 is a schematic structural diagram of still other display panels provided by the embodiments of the present disclosure.
  • the display area of a transflective display panel can be divided into a reflective area and a transmissive area.
  • the external ambient light is strong, the external ambient light is reflected by the reflective area to provide a light source for the transflective display panel to make It displays the image.
  • the backlight in the transflective display panel works, and the light emitted from the backlight passes through the transmissive area to provide a light source for the transflective display panel to display image.
  • An embodiment of the present disclosure provides a display panel, as shown in FIGS. 1 to 6c, which may include: a base substrate 100, a plurality of sub-pixels arranged on the base substrate 100, and a plurality of transistors arranged at intervals on the substrate
  • the multiple data lines DA on the substrate 100 are arranged at intervals on the multiple gate lines on the base substrate 100.
  • at least one of the plurality of sub-pixels may include a pixel electrode.
  • row group PXZ-n (1 ⁇ n ⁇ N, n and N are integers, and N is the total number of row groups.
  • the row group PXZ-n has a first sub-row group Z1-n and a second sub-row group Z2-n arranged along the column direction F2. For example, taking the 4 rows of sub-pixels in Fig.
  • the first row of sub-pixels and the second row of sub-pixels are the first row group PXZ-1, and the first row of sub-pixels are regarded as the first row group PXZ-1
  • the second row of sub-pixels are used as the second row group Z2-1 in the first row group PXZ-1.
  • the third row of sub-pixels and the fourth row of sub-pixels are the second row group PXZ-2, and the third row of sub-pixels are regarded as the first sub row group Z1-2 in the second row group PXZ-2, and the fourth row
  • the sub-pixels serve as the second sub-row group Z2-2 in the second row group PXZ-2.
  • the plurality of transistors may include a plurality of first transistors T1, a plurality of second transistors T2, and a plurality of third transistors T3.
  • the plurality of gate lines may include a plurality of first gate lines G1-n, a plurality of second gate lines G2-n, and a plurality of third gate lines G3-n;
  • the pixel electrode may include a first pixel electrode 110- 1 and the second pixel electrode 110-2.
  • one sub-pixel in the first sub-row group Z1-n may include one first transistor T1 and one first pixel electrode 110-1; wherein, the first sub-row group Z1-n The gate of the first transistor T1 is electrically connected to one of the first gate lines G1-n; and, in the same sub-pixel, the second electrode of the first transistor T1 is electrically connected to the first pixel electrode 110 -1.
  • One sub-pixel in the second sub-row group Z2-n may include one second transistor T2 and one second pixel electrode 110-2; wherein, one sub-pixel in the second sub-row group Z2-n
  • the gate of the second transistor T2 is electrically connected to one of the second gate lines G2-n; and, in the same sub-pixel, the second electrode of the second transistor T2 is electrically connected to the second pixel electrode 110-2 .
  • two adjacent sub-pixels in the column direction F2 share one third transistor T3; wherein, the gate of the third transistor T3 in the row group PXZ-n is electrically connected One of the third gate lines G3-n.
  • the first transistor T1 and the second transistor T2 in a column of sub-pixels are electrically connected to one data line DA through a shared third transistor T3.
  • the first transistor and the third transistor when the first transistor and the third transistor are both turned on, the data signal transmitted on the data line can be provided to the first pixel electrode.
  • the first transistor and the third transistor can be combined into a double-gate thin film transistor (TFT).
  • TFT thin film transistor
  • the first transistor and the third transistor can jointly control the signal flow between the data line and the first pixel electrode, thereby increasing the on-state current of the transistor, reducing the off-state current of the transistor, and reducing power consumption and improving stability. sex.
  • the second transistor and the third transistor when the second transistor and the third transistor are both turned on, the data signal transmitted on the data line can be provided to the second pixel electrode.
  • the second transistor and the third transistor can be combined into a double-gate TFT. Therefore, the second transistor and the third transistor can jointly control the signal flow between the data line and the second pixel electrode, thereby increasing the on-state current of the transistor, reducing the off-state current of the transistor, and reducing the power consumption and improving the stability. sex.
  • the first transistor T1 when the first gate line G1-n is loaded with a gate-on signal, the first transistor T1 can be controlled to be turned on. When the first gate line G1-n is loaded with a gate-off signal, the first transistor T1 can be controlled to be turned off.
  • the gate-on signal when the first transistor T1 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the gate-on signal when the first transistor T1 is a P-type transistor, the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • the second transistor T2 when the second gate line G2-n is loaded with a gate-on signal, the second transistor T2 can be controlled to be turned on. When the gate-off signal is applied to the second gate line G2-n, the second transistor T2 can be controlled to be turned off.
  • the gate-on signal when the second transistor T2 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the second transistor T2 when the second transistor T2 is a P-type transistor, the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • the third transistor T3 when the third gate line G3-n is loaded with a gate-on signal, the third transistor T3 can be controlled to be turned on. When the third gate line G3-n is loaded with a gate off signal, the third transistor T3 can be controlled to be turned off.
  • the gate-on signal when the third transistor T3 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the gate-on signal when the third transistor T3 is a P-type transistor, the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • two adjacent sub-pixels along the column direction F2 may form a sub-pixel group.
  • two sub-pixels sharing the same third transistor T3 can be used as a sub-pixel group.
  • the sub-pixel group may be configured to display at least a partial area of one pixel in the screen.
  • the sub-pixel group can be configured as a pixel in the display screen.
  • the sub-pixel group can also be configured as a partial area of one pixel in the display screen.
  • the specific implementation of the sub-pixel group can be designed and determined according to the requirements of the actual application environment, which is not limited here.
  • the display panel may include a plurality of pixel units PX.
  • the pixel unit PX may include a plurality of sub-pixel groups, and each sub-pixel group is arranged in an array.
  • the pixel unit PX may include a first color sub-pixel group spx-1, a second color sub-pixel group spx-2, and a third color sub-pixel group spx-3 that are sequentially arranged along the row direction F1.
  • the first color, the second color, and the third color can be arbitrarily selected from red, green, and blue.
  • the first color can be set to red
  • the second color is set to green
  • the third color is set to blue
  • the first color sub-pixel group spx-1 has two red sub-pixels
  • the group spx-2 has two green sub-pixels
  • the third color sub-pixel group spx-3 has two blue sub-pixels.
  • red, green and blue can be mixed to form a pixel in the display screen, thereby making the display panel Achieve display effects.
  • the pixel unit in the embodiment of the present disclosure can be used as a pixel in the display screen
  • the sub-pixel group can be used as a partial area of a pixel in the display screen.
  • the specific implementation of the pixel unit can be designed according to the actual application environment, which is not limited here.
  • description will be made by taking the pixel unit including a red sub-pixel group, a green sub-pixel group, and a blue sub-pixel group sequentially arranged along the row direction F1 as an example.
  • the display panel may further include:
  • the first planarization layer 312 is located between the layer where the reflective electrode is located and the base substrate 100;
  • the source conductive layer 1300 is located between the first planarization layer 312 and the base substrate 100, and the source conductive layer 1300 may include a plurality of data lines DA arranged at intervals;
  • the gate insulating layer 311 is located between the source conductive layer 1300 and the base substrate 100;
  • the gate conductive layer 1200 is located between the gate insulating layer 311 and the base substrate 100, and the gate conductive layer 1200 may include a plurality of first gate lines G1-n, a plurality of second gate lines G2-n, and a plurality of The third gate line G3-n.
  • the sub-pixels in the first sub-row group Z1-n of a row are electrically connected to a first gate line G1-n
  • the sub-pixels in the second sub-row group Z2-n of a row are electrically connected to a second gate line G2-n
  • One column of sub-pixels is electrically connected to one data line DA.
  • a semiconductor layer is further provided between the gate insulating layer 311 and the source conductive layer 1300.
  • the semiconductor layer may include an active layer forming each transistor.
  • the active layer has a channel region.
  • the gate conductive layer 1200 may further include a gate forming each transistor.
  • the first transistor T1 may include: a gate 1321 and a gate 1321
  • the active layer 1322 is insulated from the gate 1321 and is electrically connected to the active layer 1322 and the first source portion 1323 and the first drain portion 1324, as well as the first pixel electrode 110-1 and the second pixel Electrode 110-2.
  • the gate 1321 is located between the active layer 1322 and the base substrate 100.
  • the layer where the first source portion 1323 and the first drain portion 1324 are located is on the side of the active layer 1322 away from the base substrate 100.
  • a gate insulating layer 311 is provided between the gate 1321 and the active layer 1322.
  • the first source portion 1323 and the first drain portion 1324 directly overlap the active layer 1322 respectively.
  • a first planarization layer 312 is provided between the layer where the first source portion 1323 and the first drain portion 1324 are located and the layer where the first pixel electrode 110-1 and the second pixel electrode 110-2 are located.
  • the first pixel electrode 110-1 is electrically connected to the first drain portion 1324 through a via 3121 penetrating the first planarization layer 312.
  • the structure of the second transistor T2 and the third transistor T3 is substantially the same as that of the first transistor T1, and the second pixel electrode 110-2 passes through the via hole 3122 penetrating the first planarization layer 312 and the second transistor T2
  • the poles are electrically connected, and the rest of the structure will not be repeated here.
  • the active layer of the third transistor T3 includes a first source region ts-S, a first drain region ts-D1, a second drain region ts-D2, The first channel region ts-A1 and the second channel region ts-A2; wherein, the first channel region ts-A1 is located between the first source region ts-S and the first drain region ts-D1.
  • the second channel region ts-A2 is located between the first source region ts-S and the second drain region ts-D2.
  • the first source region ts-S is electrically connected to the corresponding data line DA
  • the first drain region ts-D1 is electrically connected to the first electrode of the first transistor T1
  • the second drain region ts-D2 is electrically connected to the second electrode of the first transistor T1.
  • the first electrode of the transistor T2 is electrically connected.
  • the source conductive layer 1300 may further include: a plurality of source connection portions 1523, a plurality of first source portions 1323, a plurality of second source portions 1423, and a plurality of first source portions.
  • the part 1424 is located in a sub-pixel group.
  • a first source portion 1323 serves as a first electrode of a first transistor T1
  • a first drain portion 1324 serves as a second electrode of a first transistor T1.
  • a second source portion 1423 serves as a first electrode of a second transistor T2, and a second drain portion 1424 serves as a second electrode of a second transistor T2. Moreover, in the same sub-pixel group, the first source portion 1323 is electrically connected to the first drain region ts-D1, and the second source portion 1423 is electrically connected to the second drain region ts-D2. Connected, the first source region ts-S is electrically connected to the source connecting portion 1523, and the source connecting portion 1523 is electrically connected to one of the data lines DA.
  • the present disclosure includes but is not limited to this.
  • the source connection portion 1523 may include: a first sub-source connection portion 15231 and a second sub-source connection portion 15232 that are electrically connected to each other; wherein, the first sub-source connection portion 15231 is along the row direction F1 Extending, the second sub-source connecting portion 15232 extends along the column direction F2; and, the first sub-source connecting portion 15231 is electrically connected to the data line DA, and the second sub-source connecting portion 15232 is electrically connected to the first source region ts-S, That is, the second sub-source connecting portion 15232 is electrically connected to the third transistor T3.
  • the source connecting portion 1523 can be arranged in a broken line shape.
  • the present disclosure includes but is not limited to this.
  • the pixel electrode may be configured as a reflective electrode.
  • the first pixel electrode 110-1 is provided with a first through hole 111
  • the second pixel electrode 110-2 is provided with a second through hole 112.
  • the area of the first through hole 111 is equal to that of the first through hole 111.
  • the areas of the two through holes 112 are different.
  • the through hole can be used to transmit the backlight; the reflective electrode can be used to reflect the light incident on the reflective electrode.
  • the through holes and the reflective electrodes can also implement functions in other display panels, which are not limited here.
  • a first through hole penetrating is provided in the first reflective electrode, and a second through hole penetrating is provided in the second reflective electrode.
  • the display panel can be in the reflective mode, which can make the external ambient light reflect by the reflective electrode to provide a light source for the display panel so that the display panel can display images.
  • the backlight can be turned off to reduce power consumption.
  • the display panel can be in see-through mode.
  • the backlight source work, the light emitted from the backlight source passes through the first through hole and the second through hole to provide a light source for the display panel.
  • the display panel displays the image. Therefore, the above-mentioned display panel provided by the embodiments of the present disclosure can realize a transflective display panel.
  • the base substrate may have a first partition Q-1 and a second partition Q-2, wherein the first The partition covers one sub-pixel in the sub-pixel group, and the second partition covers another sub-pixel in the sub-pixel group.
  • the orthographic projection of a first pixel electrode 110-1 and a first transistor T1 on the base substrate 100 is located in a first subarea Q-1.
  • the orthographic projection of a second pixel electrode 110-2 and a second transistor T2 on the base substrate 100 is located in a second subarea Q-2.
  • the display panel may further include a counter substrate 200 disposed opposite to the base substrate 100, and a color resist layer located between the base substrate 100 and the counter substrate 200.
  • the color resist layer may include: a sub-color resist layer located in each sub-pixel.
  • the sub-color resistance layer may have a first sub-color resistance region S-1 and a second sub-color resistance region S-2. In the direction perpendicular to the plane where the base substrate 100 is located, the first sub-region Q-1 covers the first sub-color resistance region S-1, and the second sub-region Q-2 covers the second sub-color resistance region S-2. In this way, the same sub-pixel can realize multi-gray-scale display, thereby improving the display effect.
  • the display panel may further include a liquid crystal layer 300 packaged between the base substrate 100 and the counter substrate 200.
  • the counter substrate 200 is provided with a common electrode
  • the base substrate 100 is also provided with a thin film transistor (TFT) located in each subarea.
  • the display panel may also include multiple gate lines and multiple data lines DA.
  • the gates of the TFTs in the same sub-pixel of a row can be electrically connected to one gate line, and the source of the TFTs in a column of sub-pixels can be connected to one
  • the data line DA is electrically connected, and the drain of the TFT may be electrically connected to the reflective electrode.
  • the data signal transmitted on the data line DA can be input to the reflective electrode, so that the reflective electrode can input the voltage of the data signal for display.
  • a corresponding voltage is also applied to the common electrode, so that an electric field can be provided between the reflective electrode and the common electrode to control the deflection of liquid crystal molecules, and the light source is combined to achieve a display effect.
  • the first pixel electrode 110-1 and the sub-color resist layer located in the first sub-color resist region S-1 may have a first opposite Area
  • the second pixel electrode 110-2 and the sub-color resist layer located in the second sub-color resist region S-2 may have a second facing area.
  • the first facing area is different from the second facing area.
  • the light-emitting brightness of the area where the first facing area is located is different from the light-emitting brightness of the area where the second facing area is located, so that the sub-pixel group can achieve different grayscale brightness.
  • the orthographic projection of the first pixel electrode 110-1 on the base substrate 100 and the orthographic projection of the sub-color resist layer located in the first sub-color resist region S-1 on the base substrate 100 may have a first overlap. Area, the area of the first overlapping area may be used as the first facing area.
  • the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 and the orthographic projection of the sub-color resist layer located in the second sub-color resist region S-2 on the base substrate 100 may have a second overlapping area, the second The area of the overlapping area can be used as the second facing area.
  • the area of the first pixel electrode 110-1 and the area of the second pixel electrode 110-2 may be The area of is approximately the same, and the area of the first sub-color resistance region S-1 is smaller than the area of the second sub-color resistance region S-2.
  • the display panel is in the reflective mode, since the area of the first sub-color-resist region S-1 and the area of the second sub-color-resist region S-2 are different, the brightness of the first sub-region Q-1 and the second sub-region Q can be changed.
  • the brightness of -2 is different, so that the same color sub-pixel group can realize the brightness of 4 gray scales.
  • the display panel is in the see-through mode, since the area of the first sub-color-resist region S-1 and the area of the second sub-color-resist region S-2 are different, the brightness of the first sub-region Q-1 and the second sub-region Q- can be changed.
  • the brightness of 2 is different, so that the same color sub-pixel group can realize the brightness of 4 gray scales.
  • the red sub-pixel is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects the external ambient light to make the display panel display.
  • red is used as the first gray level H1.
  • red is used as the second gray level H2.
  • red is used as the third gray level H3.
  • red is used as the fourth gray level H4.
  • the sub-color resist layer located in the first subarea Q-1 may be provided with a first via, and the first via Through the sub-color resist layer, the sub-color resist layer located in the second partition Q-2 is not provided with the first via hole.
  • the orthographic projection of the first via hole on the base substrate 100 and the orthographic projection of the first through hole 111 on the base substrate 100 do not overlap.
  • the sum of the area of the sub-color resist layer in the first partition Q-1 and the area of the first via hole may be the same as the area of the sub-color resist layer in the second partition Q-2. . In this way, by providing the first via hole, the area occupied by the sub-color resist layer in the first partition Q-1 can be made smaller than the area occupied by the sub-color resist layer in the second partition Q-2.
  • the area of the first through hole and the area of the second through hole in the same sub-pixel group may be different.
  • the area of the second through hole 112 may be set to be N times the area of the first through hole 111.
  • 1 ⁇ N ⁇ 5 can be set.
  • 2 ⁇ N ⁇ 3 can be set.
  • the area of the second through hole 112 can also be set to 3 times the area of the first through hole 111, so that the transmitted light of the second partition Q-2 can be The intensity is 3 times the intensity of the transmitted light of the first partition Q-1.
  • the area of the first through hole 111 may be approximately the same.
  • the area of the second through hole 112 is approximately the same. It should be noted that in practical applications, the area of the second through hole 112 and the area of the first through hole 111 and the value of N can be designed and determined according to the actual application environment, which is not limited here.
  • the area of the second through hole 112 is set to be twice the area of the first through hole 111.
  • the area where the sub-pixel group is located can be roughly mirror-symmetrical according to the central axis extending along the row direction F1.
  • the width of the first pixel electrode 110-1 in the row direction F1 and the width of the second pixel electrode 110-2 in the row direction F1 can be approximately the same, and the width of the second pixel electrode 110-2 in the column direction F2 is larger than the width of the second pixel electrode 110-2 in the column direction F2.
  • the width of a pixel electrode 110-1 in the column direction F2. The center of the area composed of the first pixel electrode 110-1 and the first through hole 111 is taken as the first center, and the center of the area composed of the second pixel electrode 110-2 and the second through hole 112 is taken as the second center.
  • the center is closer to the aforementioned central axis than the second center, so that in the same sub-pixel group, the area of the first pixel electrode 110-1 and the area of the second pixel electrode 110-2 can be the same.
  • the area of the first through hole 111 in the same sub-pixel group, can also be set to X times the area of the second through hole 112; Let 1 ⁇ X ⁇ 5.
  • 2 ⁇ X ⁇ 3 can be set.
  • the area of the first through hole 111 may be approximately the same.
  • the area of the second through hole 112 is approximately the same. It should be noted that in practical applications, the area of the second through hole 112 and the area of the first through hole 111 and the value of X can be designed and determined according to the actual application environment, which is not limited here.
  • the area of the first through hole 111 is set to be twice the area of the second through hole 112.
  • the area where the sub-pixel group is located can be roughly mirror-symmetrical according to the central axis extending along the row direction F1.
  • the width of the first pixel electrode 110-1 in the row direction F1 and the width of the second pixel electrode 110-2 in the row direction F1 can be approximately the same, and the width of the first pixel electrode 110-1 in the column direction F2 is greater than The width of the two pixel electrodes 110-2 along the column direction F2.
  • the center of the area composed of the first pixel electrode 110-1 and the first through hole 111 is taken as the first center, and the center of the area composed of the second pixel electrode 110-2 and the second through hole 112 is taken as the second center.
  • the center is closer to the aforementioned central axis than the first center, so that in the same sub-pixel group, the area of the first pixel electrode 110-1 and the area of the second pixel electrode 110-2 can be the same.
  • the red sub-pixel is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If within one frame of display time, in a red sub-pixel group, both the first partition Q-1 and the second partition Q-2 do not emit light, then red is used as the first gray level H1. If only the first sub-pixel group Q-1 emits light in one red sub-pixel group within one frame of display time, then red is used as the second gray level H2. If only the second sub-pixel group Q-2 emits light in one red sub-pixel group within one frame of display time, then red is used as the third gray level H3.
  • red is used as the fourth gray level H4.
  • a transparent conductive layer may be provided on the side of the reflective electrode away from the base substrate.
  • the transparent conductive layer may include a plurality of first sub transparent conductive parts 310 arranged at intervals.
  • the orthographic projection of one first sub-transparent conductive part 310 on the base substrate 100 may be located in a first zone Q-1, that is, one first sub-transparent conductive part 310 is provided in one first zone Q-1.
  • One first through hole 111 corresponds to one first sub-transparent conductive portion 310, and in the same first zone Q-1, the orthographic projection of the first sub-transparent conductive portion 310 on the base substrate 100 covers the first through hole 111 on the substrate. Orthographic projection of the substrate 100. Moreover, the orthographic projection of the first sub-transparent conductive portion 310 on the base substrate 100 is located within the orthographic projection of the first pixel electrode 110-1 on the base substrate 100. Further, the first sub-transparent conductive portion 310 is directly electrically connected to the first pixel electrode 110-1. For example, the transparent conductive layer is directly prepared on the reflective electrode. In this way, the first through hole can be blocked by the first sub-transparent conductive part, and an electric field can also exist in the first through hole area, thereby improving the display effect.
  • a transparent conductive layer may be provided on the side of the reflective electrode away from the base substrate.
  • the transparent conductive layer includes a plurality of second transparent conductive sub-parts 320 arranged at intervals.
  • the orthographic projection of a second sub-transparent conductive portion 320 on the base substrate 100 is located in a second subarea Q-2. That is, one second sub-transparent conductive part 320 is provided in one second partition Q-2.
  • One second through hole 112 corresponds to one second sub-transparent conductive portion 320, and in the same second partition Q-2, the orthographic projection of the second sub-transparent conductive portion 320 on the base substrate 100 covers the second through hole 112 in the substrate Orthographic projection of the substrate 100. Moreover, the orthographic projection of the second sub-transparent conductive portion 320 on the base substrate 100 is located within the orthographic projection of the second pixel electrode 110-2 on the base substrate 100. Further, the second sub-transparent conductive portion 320 is directly electrically connected to the second pixel electrode 110-2. For example, the transparent conductive layer is directly prepared on the reflective electrode. In this way, the second through hole 112 can be blocked by the second sub-transparent conductive portion 320, so that an electric field can also exist in the second through hole area, thereby improving the display effect.
  • an auxiliary electrode layer 400 may be provided between the layer where the reflective electrode is located and the first planarization layer 312, and a second planarization layer 313 may be provided between the auxiliary electrode layer 400 and the layer where the reflective electrode is located.
  • the first pixel electrode 110-1 is electrically connected to the first drain portion 1324 through a via 3121 penetrating the first planarization layer 312 and the second planarization layer 313.
  • the second pixel electrode 110-2 is electrically connected to the second electrode of the second transistor T2 through the via hole 3122 penetrating the first planarization layer 312 and the second planarization layer 313, and the rest of the structure is not described here.
  • the auxiliary electrode layer 400 may include a plurality of first auxiliary electrodes 410 arranged at intervals.
  • the orthographic projection of a first auxiliary electrode 410 on the base substrate 100 is located in a first subarea Q-1, that is, the first subarea Q-1 is provided with a first auxiliary electrode 410, and a first pixel electrode 110-1 corresponds to One first auxiliary electrode 410, and in the same first zone Q-1, the orthographic projection of the first pixel electrode 110-1 on the base substrate 100 covers the orthographic projection of the first auxiliary electrode 410 on the base substrate 100.
  • the first pixel electrode 110-1 and the first auxiliary electrode 410 can have an area facing each other to form the capacitor structure C11.
  • the auxiliary electrode layer 400 may include a plurality of second auxiliary electrodes 420 arranged at intervals.
  • the orthographic projection of a second auxiliary electrode 420 on the base substrate 100 is located in a second subarea Q-2, that is, a second subarea Q-2 is provided with a second auxiliary electrode 420, and a first pixel electrode 110-1 Corresponds to one first auxiliary electrode 410.
  • the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 covers the orthographic projection of the second auxiliary electrode 420 on the base substrate 100. In this way, a facing area between the second pixel electrode 110-2 and the second auxiliary electrode 420 can be provided to form the capacitor structure C12.
  • the gate conductive layer may further include: a plurality of first compensation electrodes 510 arranged at intervals; that is, a plurality of first compensation electrodes 510 may be arranged in the layer where the gate 1321 is located;
  • the orthographic projection of the compensation electrode 510 on the base substrate 100 is located in a first subarea Q-1, that is, one first pixel electrode 110-1 corresponds to one first compensation electrode 510.
  • the orthographic projection of the first pixel electrode 110-1 on the base substrate 100 covers the orthographic projection of the first compensation electrode 510 on the base substrate 100, and the first compensation electrode 510 is on the substrate 100.
  • the orthographic projection of the substrate 100 and the orthographic projection of the first drain portion 1324 of the first transistor T1 on the base substrate 100 have an overlapping area. In this way, an area facing the first compensation electrode 510 and the first drain portion 1324 of the first transistor T1 can be formed to form a capacitor structure C21.
  • the gate conductive layer 1200 may further include a plurality of second compensation electrodes 520 arranged at intervals.
  • the orthographic projection of a second compensation electrode 520 on the base substrate 100 is located in a second zone Q-2. That is, one second pixel electrode 110-2 corresponds to one second auxiliary electrode 420.
  • the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 covers the orthographic projection of the second compensation electrode 520 on the base substrate 100, and the second compensation electrode 520 is on the substrate 100.
  • the orthographic projection of the substrate 100 and the orthographic projection of the second drain portion 1424 of the second transistor T2 on the base substrate 100 have an overlapping area. In this way, an area facing the second compensation electrode 520 and the second drain portion 1424 of the second transistor T2 can be provided to form a capacitor structure C22.
  • the capacitor structures C11 and C21 can be formed in a parallel relationship to increase the capacitance value of the first pixel electrode.
  • the capacitor structures C12 and C22 are connected in parallel to increase the capacitance value of the second pixel electrode.
  • the sum of the capacitance values of the first pixel electrode and the sum of the capacitance values of the second pixel electrode may be approximately the same.
  • the capacitance value of the capacitor structure C11 and the capacitance value of the capacitor structure C21 may be approximately the same, and the capacitance value of the capacitor structure C12 and the capacitance value of the capacitor structure C22 may be approximately the same.
  • the specific structural forms of the capacitor structures C11, C12, C21, and C22 can be designed and determined according to the actual application environment, which is not limited here.
  • the source conductive layer and the gate conductive layer are made of metal materials. Metal materials are generally opaque. Therefore, in order to prevent the source conductive layer and the gate conductive layer from blocking the first through hole, in a specific implementation, in an embodiment of the present disclosure, in conjunction with FIG. 3 to FIG. 4b, it is possible to make The orthographic projections of the first through holes 111 on the base substrate 100 and the orthographic projections of the source conductive layer and gate conductive layer on the base substrate are not overlapped, respectively. This can prevent the source conductive layer and the gate conductive layer from blocking the light of the first through hole.
  • the orthographic projection of the second through hole 112 on the base substrate 100 can be made to be the same as those of the source conductive layer and gate conductive layer on the base substrate.
  • the orthographic projections do not overlap. This can prevent the source conductive layer and the gate conductive layer from blocking the light of the second through hole.
  • the first gate line G1 and the first pixel electrode 110-1 that are electrically connected to the first transistor T1
  • the first gate line G1 and the first transistor respectively have overlapping areas.
  • the orthographic projection of the first pixel electrode 110-1 on the base substrate 100 covers the orthographic projection of the first transistor T1 on the base substrate 100
  • the orthographic projection of the line G1 on the base substrate 100 has an overlapping area.
  • the film layer where the first gate line G1 and the first transistor T1 are located is between the first pixel electrode 110-1 and the base substrate 100, and the orthographic projection of the first gate line G1 on the base substrate 100 and the first pixel electrode
  • the orthographic projection of 110-1 and the first transistor T1 on the base substrate 100 has an overlapping area, so that the first pixel electrode 110-1 can be used to shield the first gate line G1 and the first transistor T1 to increase the first pixel electrode.
  • the area occupied by 110-1 in the sub-pixel can increase the pixel aperture ratio.
  • the second gate line G2 and the second pixel electrode 110-2 electrically connected to the second transistor T2 the second gate line G2 and the second transistor
  • the orthographic projection of T2 on the base substrate 100 and the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 respectively have overlapping areas.
  • the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 covers the orthographic projection of the second transistor T2 on the base substrate 100, and the orthographic projection of the second pixel electrode 110-2 on the base substrate 100 and the second gate
  • the line G2 has an overlapping area on the orthographic projection of the base substrate 100.
  • the film layer where the second gate line G2 and the second transistor T2 are located is between the second pixel electrode 110-2 and the base substrate 100, and the orthographic projection of the second gate line G2 on the base substrate 100 and the second pixel electrode
  • the orthographic projection of 110-2 and the second transistor T2 on the base substrate 100 has an overlapping area, so that the second pixel electrode 110-2 can be used to shield the second gate line G2 and the second transistor T2 to increase the second pixel electrode.
  • the area occupied by 110-2 in the sub-pixel can increase the pixel aperture ratio.
  • the orthographic projection of the third gate line G3 on the base substrate 100 is electrically connected to the third transistor T3, the first pixel electrode 110-1 and the second pixel electrode 110-1.
  • the orthographic projection of the pixel electrode 110-2 on the base substrate 100 has an overlapping area, and the orthographic projection of the first through hole 111 and the second through hole 112 on the base substrate 100 is the same as the source conductive layer and gate conductive layer on the base substrate.
  • the orthographic projections of 100 also do not overlap. This can prevent the third gate line G3 and the third transistor T3 from blocking the first through hole 111 and the second through hole 112, and reduce the influence of the third gate line G3 and the third transistor T3 on the display effect.
  • the first pixel electrode 110-1 may be provided with a first through hole 111.
  • the area of the first through hole 111 may be set to 208.377 ⁇ m 2 .
  • the shape of the first through hole 111 may be set as a rectangle, the long side of the rectangle may extend in the row direction F1, the short side of the rectangle may extend in the column direction F2, and the width of the long side may be the same as that of the short side. 2 to 3 times the width.
  • the length of the long side and the short side of the first through hole 111 can be set according to the requirements of the actual application, which is not limited here.
  • the source connecting portion 1523 can be set in the form of a curve or a broken line.
  • the second through hole 112 may include a first sub-through hole 112-1 and a second sub-through hole 112-2 arranged at intervals, that is, the second pixel electrode 110-2 may be provided with one first sub-through hole 112-1 and one The second through-hole 112-2 can divide the second through-hole into two so as to be scattered in the second pixel electrode 110-2.
  • the areas of the first sub-through hole 112-1 and the second sub-through hole 112-2 may be substantially the same.
  • the area of the first sub-via 112-1 may be set to 4.008 ⁇ m 2 .
  • the shape of the first sub-through hole 112-1 may be a rectangle, the long side of the rectangle may extend in the column direction F2, the short side of the rectangle may extend in the row direction F1, and the width of the long side may be short. 1.5 to 2 times the width of the side.
  • the shape of the second sub-through hole 112-2 may be a rectangle, the long side of the rectangle may extend along the column direction F2, and the short side of the rectangle may extend along the row direction F1.
  • the long sides and short sides of the first through-hole 112-1 and the short side of the second through-hole 112-2 can be designed according to the requirements of the actual application environment, which is not limited here.
  • the second through hole 112 includes the first sub-through hole 112-1 and the second sub-through hole 112-2
  • the orthographic projection of 112-2 on the base substrate 100 is located between the orthographic projections of the second grid line G2 and the third grid line G3 on the base substrate 100.
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 is relative to the second sub-via
  • the orthographic projection of 112-2 on the base substrate 100 is close to the orthographic projection of the data line DA on the base substrate 100.
  • the orthographic projection of the first sub-through hole 112-1 on the base substrate 100 is closer to the data line DA than the orthographic projection of the second sub-through hole 112-2 on the base substrate 100.
  • the orthographic projection of the second sub-through hole 112-2 on the base substrate 100 is farther than the orthographic projection of the first sub-through hole 112-1 on the base substrate 100.
  • the data line DA to which the sub-pixels are electrically connected is orthographically projected on the base substrate 100.
  • the first sub-via 112-1 is arranged close to the data line DA electrically connected to the sub-pixel, and the second sub-via 112-2 is away from the sub-pixel data line DA.
  • the first sub-through holes 112-1 and the second sub-through holes 112-2 in the second partition Q-2 can be dispersedly arranged, so that the first sub-through holes can be adjusted according to the space in the second partition Q-2.
  • the through hole 112-1 and the second sub-through hole 112-2 are flexibly arranged.
  • the orthographic projection of the third gate line G3 on the base substrate 100 is located between the orthographic projection of the first gate line G1 on the base substrate 100 and the second gate line G2. Between the orthographic projections of the base substrate 100.
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 may be located at the orthographic projection of the first sub-source connection portion 15231 on the base substrate 100 and the data line DA in the liner. Between the orthographic projections of the base substrate 100, and the orthographic projection of the first sub-via 112-1 on the base substrate 100 is located between the orthographic projection of the second sub-source connection portion 15232 on the base substrate 100 and the third grid line G3 on the base substrate 100. Between the orthographic projection of the base substrate 100.
  • the orthographic projection of the first sub-through hole 112-1 on the base substrate 100 is located at the orthographic projection of the source connection portion 1523 on the base substrate 100 and is close to the data line DA on the base substrate 100.
  • the orthographic projection of the second source portion 1423 on the base substrate 100 is located at the orthographic projection of the source connection portion 1523 on the base substrate 100 away from the orthographic projection of the data line DA on the base substrate 100
  • the orthographic projection of the second sub-via 112-2 on the base substrate 100 is located on the side of the orthographic projection of the second source portion 1423 on the base substrate 100 away from the source connection portion 1523 on the orthographic projection of the base substrate 100 .
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 may be located at the orthographic projection of the first sub-source connection portion 15231 on the base substrate 100 and the data line DA in the liner. Between the orthographic projections of the base substrate 100, and the orthographic projection of the first sub-via 112-1 on the base substrate 100 is located at the orthographic projection of the second sub-source connection portion 15232 on the base substrate 100 and the first grid line G1 is in line Between the orthographic projection of the base substrate 100.
  • the sub-color resist layer located in the first partition Q-1 is provided with a A via hole 121, and the first via hole 121 penetrates the sub-color resist layer 120-1.
  • the sub-color resist layer located in the first partition Q-1 is provided with a first via 122 , The first via hole 122 penetrates the sub-color resist layer 120-2.
  • the sub-color resist layer located in the first partition Q-1 is provided with a first via hole 123.
  • the first via hole 123 penetrates the sub-color resist layer 120-3.
  • the human eye has different sensitivity to different colors of light. For example, the human eye has the highest sensitivity to green, followed by red sensitivity, and the lowest sensitivity to blue. If the areas of the first via holes in the sub-pixels of different colors are set to be the same, the human eyes will feel that the image is greenish when viewing the image displayed on the display panel. In order to improve the display effect, the size of the first via holes in the sub-pixels of different colors can be designed according to the sensitivity of human eyes to red, green, and blue. In a specific implementation, as shown in FIG.
  • the area of the first via hole 122 in the second color sub-pixel group spx-2 may be greater than the area of the first via hole 121 in the first color sub-pixel group spx-1 ,
  • the area of the first via hole 121 in the first color sub-pixel group spx-1 can be made larger than the area of the first via hole 123 in the third color sub-pixel group spx-3.
  • the area of the first via hole in the green sub-pixel group may be larger than the area of the first via hole in the red sub-pixel group, and the area of the first via hole in the red sub-pixel group may be larger than that of the blue sub-pixel.
  • the area of the first via in the group In this way, the green light emission of the green sub-pixel group can be reduced, so that the problem of the greenish picture can be improved.
  • the first color sub-pixel group spx-1 may have a first side C1 and a second side C2 opposite to each other; wherein, the first side C1 And the second side C2 are arranged along the row direction F1.
  • the first via 121 in the first color sub-pixel group spx-1 may include a first sub via 121-1 and a second sub via 121-2; the first sub via 121-1 is located on the first side C1, The second sub-via 121-2 is located on the second side C2. In this way, the first sub-via 121-1 and the second sub-via 121-2 can be respectively arranged on the edge of the sub-color resist layer.
  • the area of the first sub-via 121-1 and the area of the second sub-via 121-2 can be substantially the same.
  • the first sub-via 121-1 and the second sub-via 121-2 can be uniformly prepared, which reduces the difficulty of process preparation.
  • the shape of the orthographic projection of the first sub-via 121-1 on the base substrate 100 and the shape of the orthographic projection of the second sub-via 121-2 on the base substrate 100 can be approximately the same, and the first sub-via The area of the orthographic projection of the hole 121-1 on the base substrate 100 and the area of the orthographic projection of the second sub-via 121-2 on the base substrate 100 are approximately the same.
  • the shape of the first sub-via 121-1 and the second sub-via 121-2 can be set to a rectangle, the long side of the rectangle extends in the column direction F2, and the short side of the rectangle extends in the row direction F1.
  • the area of the rectangle can be set to 200 ⁇ m 2 .
  • the long side of the rectangle may be 2 to 3 times the short side.
  • the areas of the first sub-via 121-1 and the second sub-via 121-2 can be designed according to the actual application environment, which is not limited herein.
  • the second color sub-pixel group spx-2 has a third side C3 and a fourth side C4 opposite to each other; wherein, the third side C3 and The fourth side C4 is arranged along the row direction F1.
  • the orthographic projection of the first via hole in the second color sub-pixel group spx-2 on the base substrate 100 extends from the third side C3 to the fourth side C4.
  • the first via hole in the second color sub-pixel group spx-2 may be configured as a rectangle, the long side of the rectangle extends along the row direction F1, and the short side of the rectangle extends along the column direction F2.
  • the area of the rectangle can be set to 812 ⁇ m 2 .
  • the width of the long side of the rectangle may be 2 to 3 times the width of the short side.
  • the first via holes in the second color sub-pixel group spx-2 can be designed according to the actual application environment, which is not limited here.
  • the third color sub-pixel group spx-3 has a fifth side C5 and a sixth side C6 opposite to each other; among them, the fifth side C5 and The sixth side C6 is arranged along the row direction F1.
  • the first via in the third color sub-pixel group spx-3 may include a third sub-via 123-1 and a fourth sub-via 123-2; the third sub-via 123-1 is located on the fifth side C5 , The fourth sub-via 123-2 is located on the sixth side C6. In this way, the third sub-via 123-1 and the fourth sub-via 123-2 can be respectively arranged on the edge of the sub-color resist layer.
  • the area of the third sub-via 123-1 can be substantially the same as the area of the fourth sub-via 123-2.
  • the third sub-via 123-1 and the fourth sub-via 123-2 can be uniformly prepared, which reduces the difficulty of process preparation.
  • the shape of the orthographic projection of the third sub-via 123-1 on the base substrate 100 and the shape of the orthographic projection of the fourth sub-via 123-2 on the base substrate 100 may be approximately the same, and the third sub-via The area of the orthographic projection of the hole 123-1 on the base substrate 100 and the area of the orthographic projection of the fourth sub-via 123-2 on the base substrate 100 are approximately the same.
  • the shape of the third sub-via 123-1 and the fourth sub-via 123-2 can be set to a rectangle, the long side of the rectangle extends along the column direction F2, and the short side of the rectangle extends along the row direction F1.
  • the area of the rectangle can be set to 157 ⁇ m 2 .
  • the length of the long side can be set to 2 to 3 times the length of the short side.
  • the third sub-via 123-1 and the fourth sub-via 123-2 can be designed according to the actual application environment, which is not limited here.
  • the center of the first via hole in the first color sub-pixel group spx-1 can be set to be the center of the first via hole in the second color sub-pixel group spx-2.
  • the center of a via hole and the center of the first via hole in the third color sub-pixel group spx-3 are arranged on the same straight line L0 along the row direction F1. This can reduce the design difficulty of these first vias.
  • the sub-color resist layers in every two adjacent sub-pixel groups may have overlapping regions or be adjacent to each other. As shown in FIG.
  • the first sub-via 121- in the first color sub-pixel group spx-1 The long side of 1 may coincide with the long side of the fourth sub-via 123-2 in the third color sub-pixel group spx-3.
  • the long side of the second sub-via 121-2 in the first color sub-pixel group spx-1 may coincide with the short side of the first via on the third side C3 in the second color sub-pixel group spx-2.
  • the short side of the second sub-via 121-2 located on the fourth side C4 in the first color sub-pixel group spx-1 may be the same as that of the third sub-via 123-1 in the third color sub-pixel group spx-3.
  • the long sides coincide.
  • the row direction F1 may be the row direction of the sub-pixels
  • the column direction F2 may be the column direction of the sub-pixels.
  • the row direction F1 may also be the column direction of the sub-pixels
  • the column direction F2 may be the row direction of the sub-pixels. In actual applications, it can be designed and determined according to the actual application environment, which is not limited here.
  • the above-mentioned features are not completely the same, and there may be some deviations. Therefore, the same relationship between the above-mentioned features as long as the above-mentioned conditions are substantially satisfied. That is, all belong to the protection scope of the present disclosure.
  • the above-mentioned sameness may be the same as allowed within the allowable error range.
  • An embodiment of the present disclosure also provides a driving method of the above-mentioned display panel, which may include: driving one sub-pixel in the row group in each data input stage of one frame time.
  • driving the sub-pixels in one row group in one data writing stage, as shown in FIG. 11, may include the following steps:
  • One frame of display time may include: n data input stages t0-n, wherein the nth data input stage t0-n includes: stages t1-n and t2-n.
  • the first gate line G1-n and the third gate line G3-n electrically connected to the sub-pixel group in the nth row input gate turn-on signals, respectively.
  • the second gate line G2-n and the third gate line G3-n that are electrically connected to the sub-pixel group in the nth row input gate turn-on signals, respectively.
  • the following is the first sub-row group (for example, the first row of sub-pixels) and the second sub-row group (for example, the second row of sub-pixels) in the first row group PXZ-1, and the second row group PXZ-2.
  • the first sub-row group (for example, the third row of sub-pixels) and the second sub-row group (for example, the fourth row of sub-pixels) are taken as examples for description.
  • the first data input stage t0-1 includes: stages t1-1 and t2-1.
  • the second data input stage t0-2 includes stages t1-2 and t2-2.
  • g1-1 is a signal input from the first gate line G1-1 electrically connected to the sub-pixels in the first row
  • g2-1 is a signal input from the second gate line G2-1 electrically connected to the sub-pixels in the second row.
  • g3-1 is the signal input by the third gate line G3-1 of the first row group PXZ-1.
  • g1-2 is a signal input from the first gate line G1-2 electrically connected to the sub-pixels in the third row
  • g2-2 is a signal input from the second gate line G2-2 electrically connected to the sub-pixels in the fourth row.
  • g3-2 is the signal input by the third gate line G3-2 of the second row group PXZ-2.
  • the second gate line G2-1 electrically connected to the second row of sub-pixels inputs a low-level signal to control the second transistors T2 in the second row of sub-pixels to be turned off.
  • the first gate line G1-2 electrically connected to the third row of sub-pixels inputs a low-level signal to control the first transistors T1 in the third row of sub-pixels to be turned off.
  • the second gate line G2-2 electrically connected to the sub-pixels in the fourth row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the fourth row to be turned off.
  • the third gate line G3-2 of the second row group PXZ-2 inputs a low-level signal to control the third transistors T3 in the second row group PXZ-2 to be turned off.
  • the first gate line G1-1 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned on.
  • the third gate line G3 of the first row group PXZ-1 inputs a high-level signal to control the third transistors T3 in the second row group PXZ-2 to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first pixel electrode 110-1 in the first row of sub-pixels.
  • the first gate line G1-1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2-1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the first gate line G1-2 electrically connected to the third row of sub-pixels inputs a low-level signal to control the first transistors T1 in the third row of sub-pixels to be turned off.
  • the third gate line G3 of the second row group PXZ-2 inputs a low-level signal to control the third transistors T3 in the second row group PXZ-2 to be all turned off.
  • the second gate line G2-1 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned on.
  • the third gate line G3 of the first row group PXZ-1 inputs a high-level signal to control the third transistors T3 in the first row group PXZ-1 to be turned on.
  • each data line DA is loaded with a data signal
  • the second pixel electrode 110-2 in the second row of sub-pixels is input with a data signal.
  • the first gate line G1-1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2-1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the second gate line G2-2 electrically connected to the sub-pixels in the fourth row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the fourth row to be turned off.
  • the third gate line G3 of the second row group PXZ-2 inputs a low-level signal to control the third transistors T3 in the second row group PXZ-2 to be all turned off.
  • the first gate line G1-2 electrically connected to the sub-pixels in the third row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the third row to be turned on.
  • the third gate line G3-2 of the second row group PXZ-2 inputs a high-level signal to control the third transistors T3 in the second row group PXZ-2 to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first pixel electrode 110-1 in the third row of sub-pixels.
  • the first gate line G1-1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2-1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the first gate line G1-2 electrically connected to the third row of sub-pixels inputs a low-level signal to control the first transistors T1 in the third row of sub-pixels to be turned off.
  • the third gate line G3-1 of the first row group PXZ-1 inputs a low-level signal to control the third transistors T3 in the first row group PXZ-1 to be turned off.
  • the second gate line G2-2 electrically connected to the sub-pixels in the fourth row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the fourth row to be turned on.
  • the third gate line G3-2 of the second row group PXZ-2 inputs a high-level signal to control the third transistors T3 in the second row group PXZ-2 to be turned on.
  • each data line DA is loaded with a data signal
  • the second pixel electrode 110-2 in the fourth row of sub-pixels is input with a data signal.
  • the red sub-pixel group is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects the external ambient light to make the display panel display. If the data signals input by the reflective electrodes in the first subarea Q-1 and the second subarea Q-2 cannot control the inversion of the liquid crystal molecules within the display time of one frame, the first subarea Q-1 and the second subarea Q-2 are not Glow, then red is used as the first gray level H1.
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the inversion of the liquid crystal molecules, the data input by the second reflective electrode 110-2 in the second subarea Q-2 If the signal cannot control the driving molecule to flip, the first reflective electrode 110-1 in the first subarea Q-1 can reflect the incident light, so that only the first subarea Q-1 emits light, then red is used as the second gray scale H2.
  • the data signal input by the first reflective electrode 110-1 in the first zone Q-1 cannot control the flipping of the driving molecule
  • the data input by the second reflective electrode 110-2 in the second zone Q-2 The signal can control the driving molecule to flip, and the second reflective electrode 110-2 in the second subarea Q-2 can reflect the incident light, so that only the second subarea Q-2 emits light, and then red is used as the third gray level H3 .
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2
  • the signal can also control the driving molecule to flip, so the first reflective electrode 110-1 in the first subarea Q-1 can reflect the incident light, and the second reflective electrode 110-2 in the second subarea Q-2 also The incident light can be reflected out, so that both the first subarea Q-1 and the second subarea Q-2 emit light, and the red color is used as the fourth gray level H4.
  • the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the red sub-pixel group is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If the data signals input by the reflective electrodes in the first subarea Q-1 and the second subarea Q-2 cannot control the inversion of the liquid crystal molecules within the display time of one frame, the first subarea Q-1 and the second subarea Q-2 are not Glow, then red is used as the first gray level H1.
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2 If the signal cannot control the driving molecule to flip, the light of the backlight can pass through the first through hole 111 and be emitted through the first subarea Q-1, so that only the first subarea Q-1 emits light, and then red is used as the second gray scale. H2.
  • the data signal input by the first reflective electrode 110-1 in the first zone Q-1 cannot control the flipping of the driving molecule
  • the data input by the second reflective electrode 110-2 in the second zone Q-2 The signal can control the driving molecule to flip, then the light of the backlight source can pass through the second through hole 112 and be emitted through the second partition Q-2, so that only the second partition Q-2 emits light, then red is used as the third gray level H3 .
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2
  • the signal can also control the driving molecule to flip, so the light of the backlight can pass through the first through hole 111 and be emitted through the first partition Q-1, and the light of the backlight can pass through the second through hole 112 and pass through the second partition.
  • Q-2 is emitted, so that both the first subarea Q-1 and the second subarea Q-2 emit light, and the red color is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4.
  • H1 may be the lowest gray level of red
  • H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state. Similarly, in a pixel unit, the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the embodiments of the present disclosure further provide some display panels, the structural diagram of which is shown in FIG. 13, which is modified with respect to the implementation of the foregoing embodiment.
  • FIG. 13 is modified with respect to the implementation of the foregoing embodiment.
  • the area of the first pixel electrode 110-1 can be made smaller than the area of the second pixel electrode 110-2, and the area of the first sub-color resist region S-1 The area is approximately equal to the area of the second sub-color resistance region S-2.
  • the area of the first pixel electrode 110-1 is smaller than the area of the second pixel electrode 110-2, and the first sub-color resist region S The area of -1 is approximately equal to the area of the second sub-color resistance region S-2.
  • each second color sub-pixel group spx-2 the area of the first pixel electrode 110-1 is smaller than the area of the second pixel electrode 110-2, and the area of the first sub-color resist region S-1 is substantially equal to the second sub-color The area of the resistance zone S-2.
  • the area of the first pixel electrode 110-1 is smaller than the area of the second pixel electrode 110-2, and the area of the first sub-color resistance region S-1 is substantially equal to the second sub-color The area of the resistance zone S-2.
  • the display panel when the display panel is in the reflective mode, since the area of the first pixel electrode 110-1 is smaller than the area of the second pixel electrode 110-2, the brightness of the first zone Q-1 can be made smaller than that of the second zone Q- 2 brightness, which can make the display panel achieve 64 gray scales.
  • the red sub-pixel group is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects the external ambient light to make the display panel display. If neither the first subarea Q-1 nor the second subarea Q-2 emit light within one frame of display time, then red is used as the first gray level H1.
  • red is used as the second gray level H2. If only the second subarea Q-2 emits light during one frame of display time, then red is used as the third gray level H3. If the first zone Q-1 and the second zone Q-2 both emit light within one frame of display time, then red is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4. That is, H1 may be the lowest gray level of red, and H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state
  • the blue part can also have 4 gray levels from the dark state to the bright state.
  • a pixel unit can display 64 gray levels of colors.
  • the implementation manners of the second through hole 112 and the first through hole 111 can refer to the above-mentioned implementation manners, and details are not described herein.
  • the display panel when the display panel is in the transmissive mode, since the area of the first pixel electrode 110-1 and the area of the second pixel electrode 110-2 are different, the brightness of the first reflective area and the brightness of the second reflective area can be changed. Different, so that the display panel can achieve 64 gray scales.
  • the red sub-pixel group is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If neither the first subarea Q-1 nor the second subarea Q-2 emit light within one frame of display time, then red is used as the first gray level H1.
  • red is used as the second gray level H2. If only the second subarea Q-2 emits light within one frame of display time, then red is used as the third gray level H3. If the first zone Q-1 and the second zone Q-2 both emit light within one frame of display time, then red is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4. That is, H1 may be the lowest gray level of red, and H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state
  • the blue part can also have 4 gray levels from the dark state to the bright state.
  • a pixel unit can display 64 gray levels of colors.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetition is not repeated here.
  • the display device may further include a backlight source.
  • the backlight source may be located on the side of the base substrate away from the opposite substrate.
  • the backlight source may be a direct-type backlight source or an edge-type backlight source, and the specific setting method may be designed and determined according to the actual application environment, which is not limited herein.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

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Abstract

一种显示面板、其驱动方法及显示装置，以相邻的两行子像素为一个行组(PXZ-n)，行组(PXZ-n)具有沿列方向(F2)排列的第一子行组(Z1-n)和第二子行组(Z2-n)；像素电极包括第一像素电极(110-1)和第二像素电极(110-2)；第一子行组(Z1-n)中的第一晶体管(T1)的栅极电连接一条第一栅线(G1-n)；第一晶体管(T1)的第二极电连接第一像素电极(110-1)；第二子行组(Z2-n)中的第二晶体管(T2)的栅极电连接一条第二栅线(G2-n)；第二晶体管(T2)的第二极电连接第二像素电极(110-2)；沿列方向(F2)上相邻的两个子像素共用一个第三晶体管(T3)；行组(PXZ-n)中的第三晶体管(T3)的栅极电连接一条第三栅线(G3-n)；一列子像素中的第一晶体管(T1)和第二晶体管(T2)通过共用的第三晶体管(T3)与一条数据线(DA)电连接。

Description

显示面板、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板、其驱动方法及显示装置。
背景技术
随着显示技术的不断发展，半透半反式显示面板因其具有功耗低、环境适应性强等优点，在手机、平板电脑等显示装置中得到了广泛应用。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板；
多个子像素，设置于所述衬底基板上，所述多个子像素中的至少一个包括像素电极；
多个晶体管，所述多个晶体管包括多个第一晶体管、多个第二晶体管、多个第三晶体管；
多条数据线，间隔设置于所述衬底基板上；
多条栅线，间隔设置于所述衬底基板上；且所述多条栅线包括多条第一栅线、多条第二栅线以及多条第三栅线；
其中，以相邻的两行子像素为一个行组，所述行组具有沿列方向排列的第一子行组和第二子行组；所述像素电极包括第一像素电极和第二像素电极；
所述第一子行组中的一个子像素包括一个所述第一晶体管和一个所述第一像素电极；其中，所述第一子行组中的第一晶体管的栅极电连接一条所述第一栅线；并且，同一所述子像素中，所述第一晶体管的第二极电连接所述第一像素电极；
所述第二子行组中的一个子像素包括一个所述第二晶体管和一个所述第二像素电极；其中，所述第二子行组中的第二晶体管的栅极电连接一条所述 第二栅线；并且，同一所述子像素中，所述第二晶体管的第二极电连接所述第二像素电极；
同一所述行组中，沿列方向上相邻的两个子像素共用一个所述第三晶体管；其中，所述行组中的第三晶体管的栅极电连接一条所述第三栅线；
一列子像素中的第一晶体管和第二晶体管通过共用的第三晶体管与一条所述数据线电连接。
可选地，在本公开实施例中，同一所述行组中，沿所述列方向上相邻的两个子像素组成一个子像素组；
所述子像素组被配置为显示画面中的一个像素点的至少部分区域。
可选地，在本公开实施例中，所述第三晶体管的有源层包括第一源极区、第一漏极区、第二漏极区、第一沟道区以及第二沟道区；其中，所述第一沟道区位于所述第一源极区和所述第一漏极区之间，所述第二沟道区位于所述第一源极区和所述第二漏极区之间；
所述第一源极区与所述数据线电连接，所述第一漏极区与所述第一晶体管的第一极电连接，所述第二漏极区与所述第二晶体管的第一极电连接。
可选地，在本公开实施例中，所述显示面板还包括：
源导电层，位于所述衬底基板上，且所述源导电层包括所述多条间隔设置的数据线、多个源连接部、多个第一源极部和多个第二源极部；其中，一个所述源连接部、一个所述第一源极部以及一个所述第二源极部位于一个所述子像素组中；
所述第一源极部作为所述第一晶体管的第一极，所述第二源极部作为所述第二晶体管的第一极；
同一所述子像素组中，所述第一源极部与所述第一漏极区电连接，所述第二源极部与所述第二漏极区电连接，所述第一源极区与所述源连接部电连接，所述源连接部与一条所述数据线电连接。
可选地，在本公开实施例中，所述源连接部包括：相互电连接的第一子源连接部和第二子源连接部；其中，所述第一子源连接部沿行方向延伸，所 述第二子源连接部沿列方向延伸；并且，所述第一子源连接部与所述数据线电连接，所述第二子源连接部与所述第一源极区电连接。
可选地，在本公开实施例中，所述像素电极设置为反射电极；所述第一像素电极设置有第一通孔，所述第二像素电极设置有第二通孔，所述第一通孔的面积与所述第二通孔的面积不同。
可选地，在本公开实施例中，所述衬底基板具有：第一分区和第二分区；其中，所述第一分区覆盖所述子像素组中的一个子像素，所述第二分区覆盖所述子像素组的另一个子像素；
所述显示面板还包括：
对向基板，与所述衬底基板相对设置；
色阻层，位于所述衬底基板与所述对向基板之间，并且，所述色阻层包括：位于各所述子像素的子色阻层；
其中，所述子色阻层具有第一子色阻区和第二子色阻区，在垂直于所述衬底基板所在平面的方向上，所述第一分区覆盖所述第一子色阻区，所述第二分区覆盖所述第二子色阻区。
可选地，在本公开实施例中，所述第一像素电极与位于所述第一子色阻区的子色阻层具有第一正对面积；
所述第二像素电极与位于所述第二子色阻区的子色阻层具有第二正对面积；
同一所述子像素组中，所述第一正对面积与所述第二正对面积不同。
可选地，在本公开实施例中，同一所述子像素组中，所述第一像素电极的面积和所述第二像素电极的面积大致相同，且所述第一子色阻区的面积小于所述第二子色阻区的面积。
可选地，在本公开实施例中，位于所述第一分区内的所述子色阻层设置有第一过孔，所述第一过孔贯穿所述子色阻层；
所述第一过孔在所述衬底基板的正投影与所述第一通孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，同一所述子像素组中，所述第一像素电极的面积小于所述第二像素电极的面积，且所述第一子色阻区的面积小于或大致等于所述第二子色阻区的面积。
可选地，在本公开实施例中，所述第一通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠；
所述第二通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，针对与所述第一晶体管电连接的第一栅线和第一像素电极，所述第一栅线和所述第一晶体管在所述衬底基板的正投影分别与所述第一像素电极在所述衬底基板的正投影具有交叠区域；和/或，
针对与所述第二晶体管电连接的第二栅线和第二像素电极，所述第二栅线和所述第二晶体管在所述衬底基板的正投影分别与所述第二像素电极在所述衬底基板的正投影具有交叠区域；和/或，
所述第三栅线在所述衬底基板的正投影与电连接的所述第三晶体管、所述第一像素电极和所述第二像素电极在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述第一像素电极设置有一个第一通孔，所述第二通孔包括间隔设置的第一子通孔和第二子通孔；
针对一个所述子像素组，所述第一子通孔在所述衬底基板的正投影相对所述第二子通孔在所述衬底基板的正投影靠近所述子像素电连接的数据线在所述衬底基板的正投影；和/或，
针对一个所述子像素组，所述第二子通孔在所述衬底基板的正投影相对所述第一子通孔在所述衬底基板的正投影远离所述子像素电连接的数据线在所述衬底基板的正投影。
可选地，在本公开实施例中，所述第一子通孔在所述衬底基板的正投影位于所述第一子源连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影之间，且所述第一子通孔在所述衬底基板的正投影位于所述第二子源连接部在所述衬底基板的正投影与所述第三栅线在所述衬底基板的正 投影之间。
可选地，在本公开实施例中，所述显示面板还包括：透明导电层，位于所述像素电极背离所述衬底基板一侧；
所述透明导电层包括间隔设置的多个第一子透明导电部；其中，一个所述第一子透明导电部在所述衬底基板的正投影位于一个所述第一分区内；同一所述第一分区内，所述第一子透明导电部在所述衬底基板的正投影覆盖所述第一通孔在所述衬底基板的正投影，且所述第一子透明导电部在所述衬底基板的正投影位于所述第一像素电极在所述衬底基板的正投影内；和/或，
所述透明导电层包括间隔设置的多个第二子透明导电部；其中，一个所述第二子透明导电部在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二子透明导电部在所述衬底基板的正投影覆盖所述第二通孔在所述衬底基板的正投影，且所述第二子透明导电部在所述衬底基板的正投影位于所述第二像素电极在所述衬底基板的正投影内。
可选地，在本公开实施例中，所述显示面板还包括：
第一平坦化层，位于所述反射电极所在层与所述衬底基板之间；
辅助电极层，位于所述第一平坦化层与所述反射电极所在层之间；
第二平坦化层，位于所述辅助电极层与所述反射电极所在层之间；
所述辅助电极层包括间隔设置的多个第一辅助电极；其中，一个所述第一辅助电极在所述衬底基板的正投影位于一个所述第一分区内；同一所述第一分区内，所述第一像素电极在所述衬底基板的正投影覆盖所述第一辅助电极在所述衬底基板的正投影；和/或，
所述辅助电极层包括间隔设置的多个第二辅助电极；其中，一个所述第二辅助电极在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二像素电极在所述衬底基板的正投影覆盖所述第二辅助电极在所述衬底基板的正投影。
可选地，在本公开实施例中，所述显示面板还包括：
栅绝缘层，位于所述源导电层与所述衬底基板之间；
栅导电层，位于所述栅绝缘层与所述衬底基板之间；且所述栅导电层包括多条第一栅线、多条第二栅线以及多条第三栅线；
所述栅导电层还包括：间隔设置的多个第一补偿电极；其中，一个所述第一补偿电极在所述衬底基板的正投影位于一个所述第一分区内；同一所述第一分区内，所述第一像素电极在所述衬底基板的正投影覆盖所述第一补偿电极在所述衬底基板的正投影，且所述第一补偿电极在所述衬底基板的正投影与所述第一晶体管的第一漏极部在所述衬底基板的正投影具有交叠区域；和/或，
所述栅导电层还包括：间隔设置的多个第二补偿电极；其中，一个所述第二补偿电极在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二像素电极在所述衬底基板的正投影覆盖所述第二补偿电极在所述衬底基板的正投影，且所述第二补偿电极在所述衬底基板的正投影与所述第二晶体管的第二漏极部在所述衬底基板的正投影具有交叠区域。
本公开实施例提供了一种显示装置，包括上述显示面板。
本公开实施例提供了一种上述显示面板的驱动方法，包括：
在一帧时间的各数据输入阶段中驱动一个所述行组中的子像素；
其中，在一个所述数据写入阶段中驱动一个所述行组中的子像素，包括：
对所述行组中的第一子行组的子像素电连接的第一栅线加载栅极开启信号，对所述第一子行组的子像素电连接的第二栅线加载栅极关闭信号，对所述第一子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使所述第一子行组的第一像素电极输入数据信号；
对所述行组中的第二子行组的子像素电连接的第一栅线加载栅极关闭信号，对所述第二子行组的子像素电连接的第二栅线加载栅极开启信号，对所述第二子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使所述第二子行组的第二像素电极输入数据信号。
附图说明
图1为本公开实施例提供的一些显示面板的结构示意图；
图2为本公开实施例提供的一些电路结构示意图；
图3为本公开实施例提供的一些布局结构示意图；
图4a为图3所示的示意图中沿AA’方向上的剖视结构示意图；
图4b为图3所示的示意图中沿AA’方向上的另一些剖视结构示意图；
图5为本公开实施例提供的另一些显示面板的结构示意图；
图6a为图5所示的示意图中沿AA’方向上的剖视结构示意图；
图6b为图5所示的示意图中沿BB’方向上的剖视结构示意图；
图6c为图5所示的示意图中沿CC’方向上的剖视结构示意图；
图7为本公开实施例提供的一些子色阻层的结构示意图；
图8为本公开实施例提供的另一些像素电极的结构示意图；
图9为本公开实施例提供的又一些像素电极的结构示意图；
图10为本公开实施例提供的另一些子色阻层的结构示意图；
图11为本公开实施例提供的一些驱动方法的流程图；
图12为本公开实施例提供的一些信号时序图；
图13为本公开实施例提供的又一些显示面板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第 二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
一般半透半反式显示面板的显示区域可划分为反射区域和透射区域，在外部环境光较强时，外部环境光线通过反射区域的反射，为半透半反式显示面板提供光源，以使其显示图像。而在外部无光或弱光的环境下，半透半反式显示面板中的背光源工作，背光源的出射光线穿过透射区域，为半透半反式显示面板提供光源，以使其显示图像。
本公开实施例提供一种显示面板，如图1至图6c所示，可以包括：衬底基板100，设置于衬底基板100上的多个子像素，多个晶体管，间隔设置于所述衬底基板100上的多条数据线DA，间隔设置于衬底基板100上的多条栅线。并且，多个子像素中的至少一个可以包括像素电极。
其中，以相邻的两行子像素为一个行组PXZ-n(1≤n≤N，n和N为整数，且N为行组的总数。图1和图2以N＝2为例)，所述行组PXZ-n具有沿列方向F2排列的第一子行组Z1-n和第二子行组Z2-n。例如，以图1中的4行子像素为例，第一行子像素和第二行子像素为第一个行组PXZ-1，则第一行子像素作为第一个行组PXZ-1中的第一子行组Z1-1，第二行子像素作为第一个行组PXZ-1中的第二子行组Z2-1。第三行子像素和第四行子像素为第二个行组PXZ-2，则第三行子像素作为第二个行组PXZ-2中的第一子行组Z1-2，第四行子像素作为第二个行组PXZ-2中的第二子行组Z2-2。
并且，所述多个晶体管可以包括多个第一晶体管T1、多个第二晶体管T2、多个第三晶体管T3。所述多条栅线可以包括多条第一栅线G1-n、多条第二栅 线G2-n以及多条第三栅线G3-n；所述像素电极可以包括第一像素电极110-1和第二像素电极110-2。其中，所述第一子行组Z1-n中的一个子像素可以包括一个所述第一晶体管T1和一个所述第一像素电极110-1；其中，所述第一子行组Z1-n中的第一晶体管T1的栅极电连接一条所述第一栅线G1-n；并且，同一所述子像素中，所述第一晶体管T1的第二极电连接所述第一像素电极110-1。所述第二子行组Z2-n中的一个子像素可以包括一个所述第二晶体管T2和一个所述第二像素电极110-2；其中，所述第二子行组Z2-n中的第二晶体管T2的栅极电连接一条所述第二栅线G2-n；并且，同一所述子像素中，所述第二晶体管T2的第二极电连接所述第二像素电极110-2。同一所述行组PXZ-n中，沿列方向F2上相邻的两个子像素共用一个所述第三晶体管T3；其中，所述行组PXZ-n中的第三晶体管T3的栅极电连接一条所述第三栅线G3-n。并且，一列子像素中的第一晶体管T1和第二晶体管T2通过共用的第三晶体管T3与一条所述数据线DA电连接。
本公开实施例提供的上述显示面板，通过设置第三晶体管，在第一晶体管和第三晶体管均导通时，可以将数据线上传输的数据信号提供给第一像素电极。这样可以使第一晶体管和第三晶体管组合为双栅型薄膜晶体管(Thin Film Transistor，TFT)。从而可以使第一晶体管和第三晶体管共同控制数据线与第一像素电极之间的信号流通，进而可以增大晶体管的开态电流，降低晶体管的关态电流，以及降低功耗，提高的稳定性。并且，在第二晶体管和第三晶体管均导通时，可以将数据线上传输的数据信号提供给第二像素电极。这样可以使第二晶体管和第三晶体管组合为双栅型TFT。从而可以使第二晶体管和第三晶体管共同控制数据线与第二像素电极之间的信号流通，进而可以增大晶体管的开态电流，降低晶体管的关态电流，以及降低功耗，提高的稳定性。
需要说明的是，在第一栅线G1-n加载栅极开启信号时，可以控制第一晶体管T1导通。在第一栅线G1-n加载栅极关闭信号时，可以控制第一晶体管T1截止。其中，在第一晶体管T1为N型晶体管时，栅极开启信号可以为高 电平信号，栅极关闭信号可以为低电平信号。在第一晶体管T1为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
需要说明的是，在第二栅线G2-n加载栅极开启信号时，可以控制第二晶体管T2导通。在第二栅线G2-n加载栅极关闭信号时，可以控制第二晶体管T2截止。其中，在第二晶体管T2为N型晶体管时，栅极开启信号可以为高电平信号，栅极关闭信号可以为低电平信号。在第二晶体管T2为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
需要说明的是，在第三栅线G3-n加载栅极开启信号时，可以控制第三晶体管T3导通。在第三栅线G3-n加载栅极关闭信号时，可以控制第三晶体管T3截止。其中，在第三晶体管T3为N型晶体管时，栅极开启信号可以为高电平信号，栅极关闭信号可以为低电平信号。在第三晶体管T3为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
在具体实施时，在本公开实施例中，如图1所示，同一所述行组PZX-n中，沿所述列方向F2上相邻的两个子像素可以组成一个子像素组。例如，第一个行组PZX-1中，共用同一个第三晶体管T3的两个子像素可以作为一个子像素组。并且，该所述子像素组可以被配置为显示画面中的一个像素点的至少部分区域。例如，可以使该所述子像素组被配置为显示画面中的一个像素点。或者，也可以使该所述子像素组被配置为显示画面中的一个像素点的部分区域。当然，在实际应用中，子像素组的具体实施方式可以根据实际应用环境的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图1所示，显示面板可以包括多个像素单元PX。示例性地，像素单元PX可以包括多个子像素组，各子像素组阵列排布。例如，像素单元PX可以包括沿行方向F1依次排列的第一颜色子像素组spx-1、第二颜色子像素组spx-2以及第三颜色子像素组spx-3。示例性地，第一颜色、第二颜色、第三颜色可以从红色、绿色以及蓝色中任意选取。例如，可以使第一颜色设置为红色，使第二颜色设置为绿色，使第三颜色设置为蓝色，则第一颜色子像素组spx-1具有两个红色子像素，第二颜色子 像素组spx-2具有两个绿色子像素，第三颜色子像素组spx-3具有两个蓝色子像素，这样可以采用红绿蓝进行混色以形成显示画面中的一个像素点，从而使显示面板实现显示效果。这样可以使本公开实施例中的像素单元作为显示画面中的一个像素点，子像素组可以作为显示画面中的一个像素点的部分区域。当然，在实际应用中，可以根据实际应用环境来设计像素单元的具体实现方式，在此不作限定。下面以像素单元包括沿行方向F1依次排列的红色子像素组、绿色子像素组以及蓝色子像素组为例进行说明。
在具体实施时，在本公开实施例中，结合图4a所示，显示面板还可以包括：
第一平坦化层312，位于反射电极所在层与衬底基板100之间；
源导电层1300，位于第一平坦化层312与衬底基板100之间，且源导电层1300可以包括多条间隔设置的数据线DA；
栅绝缘层311，位于源导电层1300与衬底基板100之间；
栅导电层1200，位于栅绝缘层311与衬底基板100之间，且栅导电层1200可以包括间隔设置的多条第一栅线G1-n、多条第二栅线G2-n以及多条第三栅线G3-n。并且，一行第一子行组Z1-n中的子像素电连接一条第一栅线G1-n，一行第二子行组Z2-n中的子像素电连接一条第二栅线G2-n，一列子像素电连接一条数据线DA。
示例性地，如图4a所示，栅绝缘层311与源导电层1300之间还设置有半导体层。其中，半导体层可以包括形成每个晶体管的有源层。有源层具有沟道区。并且，栅导电层1200还可以包括形成每个晶体管的栅极。示例性地，结合图4a所示，以第一晶体管T1，第一极为第一源极部，第二极为第一漏极部为例，第一晶体管T1可以包括：栅极1321、与栅极1321绝缘设置的有源层1322、与栅极1321绝缘设置且与有源层1322电连接的第一源极部1323与第一漏极部1324，以及第一像素电极110-1和第二像素电极110-2。并且，栅极1321位于有源层1322与衬底基板100之间。第一源极部1323与第一漏极部1324所在层位于有源层1322背离衬底基板100一侧。在栅极1321和有源 层1322之间设置有栅绝缘层311。第一源极部1323与第一漏极部1324分别与有源层1322直接搭接。第一源极部1323与第一漏极部1324所在层与第一像素电极110-1和第二像素电极110-2所在层之间设置有第一平坦化层312。第一像素电极110-1通过贯穿第一平坦化层312的过孔3121与第一漏极部1324电连接。第二晶体管T2和第三晶体管T3的结构与第一晶体管T1的结构大致相同，并且，第二像素电极110-2通过贯穿第一平坦化层312的过孔3122与第二晶体管T2的第二极电连接，其余结构在此不做赘述。
在具体实施时，结合图3与图4a所示，第三晶体管T3的有源层包括第一源极区ts-S、第一漏极区ts-D1、第二漏极区ts-D2、第一沟道区ts-A1以及第二沟道区ts-A2；其中，第一沟道区ts-A1位于第一源极区ts-S和第一漏极区ts-D1之间，第二沟道区ts-A2位于第一源极区ts-S和第二漏极区ts-D2之间。并且，第一源极区ts-S与对应的数据线DA电连接，第一漏极区ts-D1与第一晶体管T1的第一极电连接，第二漏极区ts-D2与第二晶体管T2的第一极电连接。
示例性地，如图3与图4a所示，源导电层1300还可以包括：多个源连接部1523、多个第一源极部1323、多个第二源极部1423、多个第一漏极部1324、多个第二漏极部1424；其中，一个源连接部1523、一个第一源极部1323、一个第一漏极部1324、一个第二源极部以及一个第二漏极部1424位于一个子像素组中。一个第一源极部1323作为一个第一晶体管T1的第一极，一个第一漏极部1324作为一个第一晶体管T1的第二极。一个第二源极部1423作为一个第二晶体管T2的第一极，一个第二漏极部1424作为一个第二晶体管T2的第二极。并且，同一子像素组中，所述第一源极部1323与所述第一漏极区ts-D1电连接，所述第二源极部1423与所述第二漏极区ts-D2电连接，所述第一源极区ts-S与所述源连接部1523电连接，所述源连接部1523与一条所述数据线DA电连接。当然，本公开包括但不限于此。
示例性地，结合图3所示，源连接部1523可以包括：相互电连接的第一子源连接部15231和第二子源连接部15232；其中，第一子源连接部15231沿 行方向F1延伸，第二子源连接部15232沿列方向F2延伸；并且，第一子源连接部15231与数据线DA电连接，第二子源连接部15232与第一源极区ts-S电连接，即第二子源连接部15232与第三晶体管T3电连接。这样可以使源连接部1523设置为折线形。当然，本公开包括但不限于此。
示例性地，可以将像素电极设置为反射电极。并且，如图5至图6c所示，第一像素电极110-1设置有第一通孔111，第二像素电极110-2设置有第二通孔112，第一通孔111的面积与第二通孔112的面积不同。需要说明的是，通孔可以用于透射背光；反射电极可以用于反射入射到反射电极上的光。当然，通孔和反射电极还可以实现其他显示面板中的功能，在此不作限定。
本公开实施例提供的上述显示面板，通过在第一反射电极中设置贯穿的第一通孔，以及在第二反射电极中设置贯穿的第二通孔。在外部环境光较强时，显示面板可以处于反射模式，这样可以使外部环境光线通过反射电极的反射，为显示面板提供光源，以使显示面板显示图像，此时可以关闭背光源，降低功耗。而在外部无光或弱光的环境下，显示面板可以处于透视模式，通过使背光源工作，背光源的出射光线穿过第一通孔和第二通孔，为显示面板提供光源，以使显示面板显示图像。因此，本公开实施例提供的上述显示面板可以实现半透半反式显示面板。
示例性地，在具体实施时，在本公开实施例中，如图5至图6c所示，衬底基板可以具有第一分区Q-1和第二分区Q-2，其中，所述第一分区覆盖所述子像素组中的一个子像素，所述第二分区覆盖所述子像素组的另一个子像素。例如，一个第一像素电极110-1和一个第一晶体管T1在衬底基板100的正投影位于一个第一分区Q-1内。一个第二像素电极110-2和一个第二晶体管T2在衬底基板100的正投影位于一个第二分区Q-2内。并且，显示面板还可以包括：与衬底基板100相对设置的对向基板200，位于衬底基板100与对向基板200之间的色阻层。其中，色阻层可以包括：位于各子像素的子色阻层。其中，子色阻层可以具有第一子色阻区S-1和第二子色阻区S-2。在垂直于衬底基板100所在平面的方向上，第一分区Q-1覆盖第一子色阻区S-1，第二分 区Q-2覆盖第二子色阻区S-2。这样可以使同一子像素实现多灰阶显示，从而可以提高显示效果。
在具体实施时，在本公开实施例中，如图5至图6c所示，显示面板还可以包括封装于衬底基板100和对向基板200之间的液晶层300。对向基板200上设置有公共电极，衬底基板100还设置有位于各分区中的薄膜晶体管(Thin Film Transistor，TFT)。并且，显示面板中还可以包括多条栅线和多条数据线DA，一行子像素同一分区中的TFT的栅极可以与一条栅线电连接，一列子像素中的TFT的源极可以与一条数据线DA电连接，TFT的漏极可以与反射电极电连接。示例性地，栅极上传输的信号控制TFT打开时，可以将数据线DA上传输的数据信号输入到反射电极中，以使反射电极输入用于显示的数据信号的电压。并且，还对公共电极施加相应的电压，从而可以使反射电极与公共电极之间具有电场，以控制液晶分子偏转，并且结合光源，以实现显示效果。
在具体实施时，在本公开实施例中，如图5至图6c所示，第一像素电极110-1与位于第一子色阻区S-1的子色阻层可以具有第一正对面积，第二像素电极110-2与位于第二子色阻区S-2的子色阻层可以具有第二正对面积。其中，同一子像素组中，第一正对面积与第二正对面积不同。这样可以使同一子像素组中，第一正对面积所在区域的发光亮度和第二正对面积所在区域的发光亮度不同，从而可以使子像素组实现不同灰阶的亮度。需要说明的是，第一像素电极110-1在衬底基板100的正投影与位于第一子色阻区S-1的子色阻层在衬底基板100的正投影可以具有第一交叠区域，该第一交叠区域的面积可以作为第一正对面积。第二像素电极110-2在衬底基板100的正投影与位于第二子色阻区S-2的子色阻层在衬底基板100的正投影可以具有第二交叠区域，该第二交叠区域的面积可以作为第二正对面积。
示例性地，在具体实施时，在本公开实施例中，如图5至图6c所示，可以使同一子像素组中，第一像素电极110-1的面积和第二像素电极110-2的面积大致相同，且第一子色阻区S-1的面积小于第二子色阻区S-2的面积。这样 在显示面板处于反射模式时，由于第一子色阻区S-1的面积和第二子色阻区S-2的面积不同，可以使第一分区Q-1的亮度和第二分区Q-2的亮度不同，可以使同一颜色子像素组实现4个灰阶的亮度。在显示面板处于透视模式时，由于第一子色阻区S-1的面积和第二子色阻区S-2的面积不同，可以使第一分区Q-1的亮度和第二分区Q-2的亮度不同，可以使同一颜色子像素组实现4个灰阶的亮度。
示例性地，以红色子像素为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过反射外界环境光，以使显示面板进行显示。若一帧显示时间内，一个红色子像素组中，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，一个红色子像素组中，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，一个红色子像素组中，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，一个红色子像素组中，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
在具体实施时，在本公开实施例中，如图5至图6c以及图7所示，可以使位于第一分区Q-1内的子色阻层设置有第一过孔，第一过孔贯穿子色阻层，位于第二分区Q-2内的子色阻层未设置有第一过孔。并且，第一过孔在衬底基板100的正投影与第一通孔111在衬底基板100的正投影不交叠。示例性地，同一子像素中，可以使第一分区Q-1内的子色阻层的面积与第一过孔的面积之和与第二分区Q-2内的子色阻层的面积相同。这样通过设置第一过孔，从而可以使第一分区Q-1内的子色阻层所占用的面积小于第二分区Q-2内的子色阻层所占用的面积。
在具体实施时，在本公开实施例中，可以使同一子像素组中，第一通孔 的面积与第二通孔的面积不同。示例性地，如图5与图8所示，同一子像素组中，可以使第二通孔112的面积设置为第一通孔111的面积的N倍。其中，可以使1＜N≤5。示例性地，可以使2≤N≤3。例如，可以使N＝2，同一子像素组中，也可以使第二通孔112的面积设置为第一通孔111的面积的2倍，这样可以使第二分区Q-2的透射光的光强为第一分区Q-1的透射光的光强的2倍。也可以使N＝3，同一子像素组中，也可以使第二通孔112的面积设置为第一通孔111的面积的3倍，这样可以使第二分区Q-2的透射光的光强为第一分区Q-1的透射光的光强的3倍。示例性地，可以使每一子像素组中，第一通孔111的面积大致相同。以及使每一子像素组中，第二通孔112的面积大致相同。需要说明的是，在实际应用中，第二通孔112的面积与第一通孔111的面积以及N的取值可以根据实际应用环境来设计确定，在此不作限定。
示例性地，以N＝2为例，由于同一子像素组中，第二通孔112的面积设置为第一通孔111的面积的2倍。在实际制备中，子像素组所在区域可以根据沿行方向F1延伸的中轴线大致镜像对称，为了使同一子像素组中，第一像素电极110-1的面积与第二像素电极110-2的面积相同，可以使第一像素电极110-1沿行方向F1的宽度和第二像素电极110-2沿行方向F1的宽度大致相同，第二像素电极110-2沿列方向F2的宽度大于第一像素电极110-1沿列方向F2的宽度。以第一像素电极110-1和第一通孔111组成的区域的中心作为第一中心，以第二像素电极110-2和第二通孔112组成的区域的中心作为第二中心，第一中心距离上述中轴线相较于第二中心更近，从而可以使同一子像素组中，第一像素电极110-1的面积与第二像素电极110-2的面积相同。
在具体实施时，在本公开实施例中，如图9所示，同一子像素组中，也可以使第一通孔111的面积设置为第二通孔112的面积的X倍；其中，可以使1＜X≤5。示例性地，可以使2≤X≤3。例如，可以使X＝2，同一子像素组中，也可以使第一通孔111的面积设置为第二通孔112的面积的2倍，这样可以使第一分区Q-1的透射光的光强为第二分区Q-2的透射光的光强的2倍。或者，可以使X＝3，同一子像素组中，也可以使第一通孔111的面积设置为 第二通孔112的面积的3倍，这样可以使第一分区Q-1的透射光的光强为第二分区Q-2的透射光的光强的3倍。示例性地，可以使每一子像素组中，第一通孔111的面积大致相同。以及使每一子像素组中，第二通孔112的面积大致相同。需要说明的是，在实际应用中，第二通孔112的面积与第一通孔111的面积以及X的取值可以根据实际应用环境来设计确定，在此不作限定。
示例性地，以X＝2为例，由于同一子像素组中，第一通孔111的面积设置为第二通孔112的面积的2倍。在实际制备中，子像素组所在区域可以根据沿行方向F1延伸的中轴线大致镜像对称，为了使同一子像素组中，第一像素电极110-1的面积与第二像素电极110-2的面积相同，可以使第一像素电极110-1沿行方向F1的宽度和第二像素电极110-2沿行方向F1的宽度大致相同，第一像素电极110-1沿列方向F2的宽度大于第二像素电极110-2沿列方向F2的宽度。以第一像素电极110-1和第一通孔111组成的区域的中心作为第一中心，以第二像素电极110-2和第二通孔112组成的区域的中心作为第二中心，第二中心距离上述中轴线相较于第一中心更近，从而可以使同一子像素组中，第一像素电极110-1的面积与第二像素电极110-2的面积相同。
示例性地，以红色子像素为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，一个红色子像素组中，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，一个红色子像素组中，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，一个红色子像素组中，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，一个红色子像素组中，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
由于第一通孔区域未设置第一像素电极，在具体实施时，如图3和图4a所示，可以在反射电极背离衬底基板一侧设置透明导电层。该透明导电层可以包括间隔设置的多个第一子透明导电部310。其中，可以使一个第一子透明导电部310在衬底基板100的正投影位于一个第一分区内Q-1内，即一个第一分区Q-1设置一个第一子透明导电部310。一个第一通孔111对应一个第一子透明导电部310，且同一第一分区Q-1内，第一子透明导电部310在衬底基板100的正投影覆盖第一通孔111在衬底基板100的正投影。且，第一子透明导电部310在衬底基板100的正投影位于第一像素电极110-1在衬底基板100的正投影内。进一步地，第一子透明导电部310与第一像素电极110-1直接电连接。例如，直接将透明导电层制备在反射电极上。这样可以通过第一子透明导电部遮挡第一通孔，以及可以使第一通孔区域也存在电场，进而提高显示效果。
由于第二通孔区域未设置第二像素电极，在具体实施时，如图3和图4a所示，可以在反射电极背离衬底基板一侧设置透明导电层。该透明导电层包括间隔设置的多个第二子透明导电部320。其中，一个第二子透明导电部320在衬底基板100的正投影位于一个第二分区Q-2内。即一个第二分区Q-2设置一个第二子透明导电部320。一个第二通孔112对应一个第二子透明导电部320，且同一第二分区Q-2内，第二子透明导电部320在衬底基板100的正投影覆盖第二通孔112在衬底基板100的正投影。且，第二子透明导电部320在衬底基板100的正投影位于第二像素电极110-2在衬底基板100的正投影内。进一步地，第二子透明导电部320与第二像素电极110-2直接电连接。例如，直接将透明导电层制备在反射电极上。这样可以通过第二子透明导电部320遮挡第二通孔112，从而可以使第二通孔区域也存在电场，进而提高显示效果。
在具体实施时，为了增加第一像素电极和第二像素电极的电容值。如图4b所示，可以在反射电极所在层和第一平坦化层312之间设置辅助电极层400，以及在辅助电极层400与反射电极所在层之间设置第二平坦化层313。并且，第一像素电极110-1通过贯穿第一平坦化层312和第二平坦化层313的过孔 3121与第一漏极部1324电连接。第二像素电极110-2通过贯穿第一平坦化层312和第二平坦化层313的过孔3122与第二晶体管T2的第二极电连接，其余结构在此不做赘述。
示例性地，如图4b所示，辅助电极层400可以包括间隔设置的多个第一辅助电极410。其中，一个第一辅助电极410在衬底基板100的正投影位于一个第一分区Q-1内，即第一分区Q-1设置一个第一辅助电极410，一个第一像素电极110-1对应一个第一辅助电极410，且同一第一分区Q-1内，第一像素电极110-1在衬底基板100的正投影覆盖第一辅助电极410在衬底基板100的正投影。这样可以使第一像素电极110-1与第一辅助电极410之间具有正对面积，以形成电容结构C11。
示例性地，如图4b所示，辅助电极层400可以包括间隔设置的多个第二辅助电极420。其中，一个第二辅助电极420在衬底基板100的正投影位于一个第二分区Q-2内，即一个第二分区Q-2设置一个第二辅助电极420，一个第一像素电极110-1对应一个第一辅助电极410。且同一第二分区Q-2内，第二像素电极110-2在衬底基板100的正投影覆盖第二辅助电极420在衬底基板100的正投影。这样可以使第二像素电极110-2与第二辅助电极420之间具有正对面积，以形成电容结构C12。
进一步地，为了增加第一像素电极和第二像素电极的电容值。如图4b所示，栅导电层还可以包括：间隔设置的多个第一补偿电极510；即可以在栅极1321所在层中设置相互间隔的多个第一补偿电极510；其中，一个第一补偿电极510在衬底基板100的正投影位于一个第一分区Q-1内，即一个第一像素电极110-1对应一个第一补偿电极510。并且，同一第一分区Q-1内，第一像素电极110-1在衬底基板100的正投影覆盖第一补偿电极510在衬底基板100的正投影，以及第一补偿电极510在衬底基板100的正投影与第一晶体管T1的第一漏极部1324在衬底基板100的正投影具有交叠区域。这样可以使第一补偿电极510与第一晶体管T1的第一漏极部1324之间具有正对面积，以形成电容结构C21。
示例性地，如图4b所示，栅导电层1200还可以包括：间隔设置的多个第二补偿电极520。其中，一个第二补偿电极520在衬底基板100的正投影位于一个第二分区Q-2内。即，一个第二像素电极110-2对应一个第二辅助电极420。并且，同一第二分区Q-2内，第二像素电极110-2在衬底基板100的正投影覆盖第二补偿电极520在衬底基板100的正投影，以及第二补偿电极520在衬底基板100的正投影与第二晶体管T2的第二漏极部1424在衬底基板100的正投影具有交叠区域。这样可以使第二补偿电极520与第二晶体管T2的第二漏极部1424之间具有正对面积，以形成电容结构C22。
综上，可以使电容结构C11和C21形成并联关系，以提高第一像素电极的电容值。以及使电容结构C12和C22形成并联关系，以提高第二像素电极的电容值。并且，需要说明的是，可以使第一像素电极的电容值的总和与第二像素电极的电容值的总和大致相同。例如，可以使电容结构C11的电容值与电容结构C21的电容值大致相同，使电容结构C12的电容值与电容结构C22的电容值大致相同。当然，在实际应用中，可以根据实际应用环境来设计确定电容结构C11、C12、C21以及C22的具体结构形式，在此不作限定。
一般源导电层和栅导电层采用金属材料制备形成。而金属材料一般是不透光的，因此，为了避免源导电层和栅导电层遮挡第一通孔，在具体实施时，在本公开实施例中，结合图3至图4b所示，可以使第一通孔111在衬底基板100的正投影分别与源导电层和栅导电层在衬底基板的正投影不交叠。这样可以避免源导电层和栅导电层遮挡第一通孔的光。
在具体实施时，在本公开实施例中，结合图3至图4b所示，可以使第二通孔112在衬底基板100的正投影分别与源导电层和栅导电层在衬底基板的正投影不交叠。这样可以避免源导电层和栅导电层遮挡第二通孔的光。
在具体实施时，在本公开实施例中，结合图3所示，针对与第一晶体管T1电连接的第一栅线G1和第一像素电极110-1，第一栅线G1和第一晶体管T1在衬底基板100的正投影分别与第一像素电极110-1在衬底基板100的正投影具有交叠区域。例如，第一像素电极110-1在衬底基板100的正投影覆盖 第一晶体管T1在衬底基板100的正投影，第一像素电极110-1在衬底基板100的正投影与第一栅线G1在衬底基板100的正投影具有交叠区域。由于第一栅线G1和第一晶体管T1所在膜层位于第一像素电极110-1和衬底基板100之间，并且，第一栅线G1在衬底基板100的正投影与第一像素电极110-1和第一晶体管T1在衬底基板100的正投影具有交叠区域，这样可以采用第一像素电极110-1将第一栅线G1和第一晶体管T1进行遮挡，提高第一像素电极110-1在子像素中的占用面积，从而可以提高像素开口率。
在具体实施时，在本公开实施例中，结合图3所示，针对与第二晶体管T2电连接的第二栅线G2和第二像素电极110-2，第二栅线G2和第二晶体管T2在衬底基板100的正投影分别与第二像素电极110-2在衬底基板100的正投影具有交叠区域。例如，第二像素电极110-2在衬底基板100的正投影覆盖第二晶体管T2在衬底基板100的正投影，第二像素电极110-2在衬底基板100的正投影与第二栅线G2在衬底基板100的正投影具有交叠区域。由于第二栅线G2和第二晶体管T2所在膜层位于第二像素电极110-2和衬底基板100之间，并且，第二栅线G2在衬底基板100的正投影与第二像素电极110-2和第二晶体管T2在衬底基板100的正投影具有交叠区域，这样可以采用第二像素电极110-2将第二栅线G2和第二晶体管T2进行遮挡，提高第二像素电极110-2在子像素中的占用面积，从而可以提高像素开口率。
在具体实施时，在本公开实施例中，结合图3所示，第三栅线G3在衬底基板100的正投影与电连接的第三晶体管T3、第一像素电极110-1和第二像素电极110-2在衬底基板100的正投影具有交叠区域，且第一通孔111和第二通孔112在衬底基板100的正投影与源导电层和栅导电层在衬底基板100的正投影也不交叠。这样可以避免第三栅线G3和第三晶体管T3遮挡第一通孔111和第二通孔112，降低第三栅线G3和第三晶体管T3对显示效果的影响。
在具体实施时，在本公开实施例中，结合图3所示，第一像素电极110-1可以设置有一个第一通孔111。例如，第一通孔111的面积可以设置为208.377μm 2。示例性地，第一通孔111的形状可以设置为长方形，该长方形的 长边沿行方向F1延伸，该长方形的短边可以沿列方向F2延伸，并且，其长边的宽度可以为短边的宽度的2～3倍。在实际应用中，可以根据实际应用的需求来设置第一通孔111的长边和短边的长度，在此不作限定。
在具体实施时，在本公开实施例中，结合图3与图5所示，可以使源连接部1523设置为曲线或折线的形式。第二通孔112可以包括间隔设置的第一子通孔112-1和第二子通孔112-2，即第二像素电极110-2可以设置有一个第一子通孔112-1和一个第二子通孔112-2，这样可以将第二通孔一分为二，从而可以分散设置在第二像素电极110-2中。示例性地，第一子通孔112-1和第二子通孔112-2的面积可以大致相同。例如，第一子通孔112-1的面积可以设置为4.008μm 2。示例性地，第一子通孔112-1的形状可以为长方形，该长方形的长边沿列方向F2延伸，该长方形的短边可以沿行方向F1延伸，并且，其长边的宽度可以为短边的宽度的1.5～2倍。第二子通孔112-2的形状可以为长方形，该长方形的长边沿列方向F2延伸，该长方形的短边可以沿行方向F1延伸。当然，在实际应用中，可以根据实际应用环境的需求来设计第一子通孔112-1和第二子通孔112-2的长边与短边，在此不作限定。
示例性地，在第二通孔112包括第一子通孔112-1和第二子通孔112-2时，在具体实施时，在本公开实施例中，结合图3所示，针对同一行子像素电连接的第二栅线G2、第三栅线G3以及第一子通孔112-1和第二子通孔112-2，第一子通孔112-1和第二子通孔112-2在衬底基板100的正投影位于第二栅线G2和第三栅线G3在衬底基板100的正投影之间。
示例性地，在具体实施时，在本公开实施例中，结合图3所示，针对一个子像素组，第一子通孔112-1在衬底基板100的正投影相对第二子通孔112-2在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影。示例性地，可以使每一个子像素组中，第一子通孔112-1在衬底基板100的正投影相对第二子通孔112-2在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影。
示例性地，结合图3所示，针对一个子像素组，第二子通孔112-2在衬底 基板100的正投影相对第一子通孔112-1在衬底基板100的正投影远离子像素电连接的数据线DA在衬底基板100的正投影。
需要说明的是，针对一个子像素组，通过将第一子通孔112-1靠近该子像素电连接的数据线DA设置，并将第二子通孔112-2远离该子像素数据线DA设置，这样可以将第二分区Q-2中的第一子通孔112-1和第二子通孔112-2进行分散设置，从而可以根据第二分区Q-2内的空间对第一子通孔112-1和第二子通孔112-2进行灵活设置。
示例性地，结合图3所示，同一行子像素组中，第三栅线G3在衬底基板100的正投影位于第一栅线G1在衬底基板100的正投影和第二栅线G2在衬底基板100的正投影之间。
示例性地，结合图3所示，可以使第一子通孔112-1在衬底基板100的正投影位于第一子源连接部15231在衬底基板100的正投影与数据线DA在衬底基板100的正投影之间，且第一子通孔112-1在衬底基板100的正投影位于第二子源连接部15232在衬底基板100的正投影与第三栅线G3在衬底基板100的正投影之间。
进一步地，结合图3所示，同一子像素组中，第一子通孔112-1在衬底基板100的正投影位于源连接部1523在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影的一侧；第二源极部1423在衬底基板100的正投影位于源连接部1523在衬底基板100的正投影远离数据线DA在衬底基板100的正投影的一侧；第二子通孔112-2在衬底基板100的正投影位于第二源极部1423在衬底基板100的正投影远离源连接部1523在衬底基板100的正投影的一侧。
示例性地，结合图3所示，可以使第一子通孔112-1在衬底基板100的正投影位于第一子源连接部15231在衬底基板100的正投影与数据线DA在衬底基板100的正投影之间，且第一子通孔112-1在衬底基板100的正投影位于第二子源连接部15232在衬底基板100的正投影与第一栅线G1在衬底基板100的正投影之间。
示例性地，如图5、图6a以及图7所示，第一颜色子像素组spx-1(例如红色子像素组)中，位于第一分区Q-1内的子色阻层设置有第一过孔121，第一过孔121贯穿子色阻层120-1。如图5、图6b以及图7所示，第二颜色子像素组spx-2(例如绿色子像素组)中，位于第一分区Q-1内的子色阻层设置有第一过孔122，第一过孔122贯穿子色阻层120-2。如图5、图6c以及图7所示，第三颜色子像素组spx-3(例如蓝色子像素组)中，位于第一分区Q-1内的子色阻层设置有第一过孔123，第一过孔123贯穿子色阻层120-3。
一般人眼对不同颜色的光的敏感度不同，例如，人眼对绿色的敏感度最高，对红色的敏感度次之，对蓝色的敏感度最低。若将不同颜色子像素中的第一过孔的面积设置为相同，那么在观看显示面板显示的画面时，人眼会觉得画面偏绿。为了提高显示效果，可以根据人眼对红色、绿色以及蓝色的敏感度来设计不同颜色子像素中第一过孔的大小。在具体实施时，如图5所示，可以使第二颜色子像素组spx-2内的第一过孔122的面积大于第一颜色子像素组spx-1内的第一过孔121的面积，可以使第一颜色子像素组spx-1内的第一过孔121的面积大于第三颜色子像素组spx-3内的第一过孔123的面积。示例性地，可以使绿色子像素组内的第一过孔的面积大于红色子像素组内的第一过孔的面积，使红色子像素组内的第一过孔的面积大于蓝色子像素组内的第一过孔的面积。这样可以降低绿色子像素组的绿光出射，从而可以改善画面偏绿的问题。
在具体实施时，在本公开实施例中，如图5与图7所示，第一颜色子像素组spx-1可以具有相对的第一侧C1和第二侧C2；其中，第一侧C1和第二侧C2沿行方向F1排列。第一颜色子像素组spx-1内的第一过孔121可以包括第一子过孔121-1和第二子过孔121-2；第一子过孔121-1位于第一侧C1，第二子过孔121-2位于第二侧C2。这样可以将第一子过孔121-1和第二子过孔121-2分别设置于子色阻层的边缘。
在具体实施时，在本公开实施例中，如图5与图7所示，可以使第一子过孔121-1的面积与第二子过孔121-2的面积大致相同。这样可以统一制备第 一子过孔121-1和第二子过孔121-2，降低工艺制备难度。示例性地，可以使第一子过孔121-1在衬底基板100的正投影与第二子过孔121-2在衬底基板100的正投影的形状大致相同，以及使第一子过孔121-1在衬底基板100的正投影与第二子过孔121-2在衬底基板100的正投影的面积大致相同。例如，可以使第一子过孔121-1与第二子过孔121-2的形状设置为长方形，该长方形的长边沿列方向F2延伸，该长方形的短边沿行方向F1延伸。且，该长方形的面积可以设置为200μm 2。示例性地，可以使该长方形的长边为短边的2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第一子过孔121-1和第二子过孔121-2的面积，在此不作限定。
在具体实施时，在本公开实施例中，如图5与图7所示，第二颜色子像素组spx-2具有相对的第三侧C3和第四侧C4；其中，第三侧C3和第四侧C4沿行方向F1排列。并且，第二颜色子像素组spx-2内的第一过孔在衬底基板100的正投影从第三侧C3延伸至第四侧C4。示例性地，第二颜色子像素组spx-2中的第一过孔可以设置为长方形，该长方形的长边沿行方向F1延伸，该长方形的短边沿列方向F2延伸。且，该长方形的面积可以设置为812μm 2。示例性地，可以使该长方形的长边的宽度为短边的宽度2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第二颜色子像素组spx-2内的第一过孔，在此不作限定。
在具体实施时，在本公开实施例中，如图5与图7所示，第三颜色子像素组spx-3具有相对的第五侧C5和第六侧C6；其中，第五侧C5和第六侧C6沿行方向F1排列。并且，第三颜色子像素组spx-3内的第一过孔可以包括第三子过孔123-1和第四子过孔123-2；第三子过孔123-1位于第五侧C5，第四子过孔123-2位于第六侧C6。这样可以将第三子过孔123-1和第四子过孔123-2分别设置于子色阻层的边缘。
在具体实施时，在本公开实施例中，如图5与图7所示，可以使第三子过孔123-1的面积与第四子过孔123-2的面积大致相同。这样可以统一制备第 三子过孔123-1和第四子过孔123-2，降低工艺制备难度。示例性地，可以使第三子过孔123-1在衬底基板100的正投影与第四子过孔123-2在衬底基板100的正投影的形状大致相同，以及使第三子过孔123-1在衬底基板100的正投影与第四子过孔123-2在衬底基板100的正投影的面积大致相同。例如，可以使第三子过孔123-1与第四子过孔123-2的形状设置为长方形，该长方形的长边沿列方向F2延伸，该长方形的短边沿行方向F1延伸。且，该长方形的面积可以设置为157μm 2。示例性地，长边的长度可以设置为短边的长度的2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第三子过孔123-1和第四子过孔123-2，在此不作限定。
在具体实施时，在本公开实施例中，如图7所示，可以使第一颜色子像素组spx-1内的第一过孔的中心，第二颜色子像素组spx-2内的第一过孔的中心，以及第三颜色子像素组spx-3内的第一过孔的中心沿行方向F1排列于同一直线L0上。这样可以降低这些第一过孔的设计难度。在实际应用中，可以使每相邻两个子像素组中的子色阻层具有交叠区域或毗邻。如图10所示，在每相邻两个子像素组中的子色阻层毗邻时，在第一过孔为长方形时，第一颜色子像素组spx-1内的第一子过孔121-1的长边可以与第三颜色子像素组spx-3内的第四子过孔123-2的长边重合。第一颜色子像素组spx-1内的第二子过孔121-2的长边可以与第二颜色子像素组spx-2内的位于第三侧C3的第一过孔的短边重合。第一颜色子像素组spx-1内的位于第四侧C4的第二子过孔121-2的短边可以与第三颜色子像素组spx-3内的第三子过孔123-1的长边重合。
需要说明的是，行方向F1可以为子像素的行方向，列方向F2可以为子像素的列方向。或者，行方向F1也可以为子像素的列方向，列方向F2可以为子像素的行方向。在实际应用中，可以根据实际应用环境来设计确定，在此不作限定。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述各特征中的相同并不能完全相同，可能会有一些偏差，因此上述各特征之间 的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
本公开实施例还提供了一种上述显示面板的驱动方法，可以包括：在一帧时间的各数据输入阶段中驱动一个所述行组中的子像素。其中，在一个所述数据写入阶段中驱动一个所述行组中的子像素，如图11所示，可以包括如下步骤：
S11、对行组中的第一子行组的子像素电连接的第一栅线加载栅极开启信号，对第一子行组的子像素电连接的第二栅线加载栅极关闭信号，对第一子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使第一子行组的第一像素电极输入数据信号；
S12、对行组中的第二子行组的子像素电连接的第一栅线加载栅极关闭信号，对第二子行组的子像素电连接的第二栅线加载栅极开启信号，对第二子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使第二子行组的第二像素电极输入数据信号。
下面以图3所示的第一像素电极110-1和第二像素电极110-2的结构为例，结合图12所示的信号时序图，对本公开实施例提供的上述显示面板的工作过程进行说明。
一帧显示时间可以包括：n个数据输入阶段t0-n，其中第n个数据输入阶段t0-n包括：阶段t1-n和t2-n。其中，在阶段t1-n中，第n行子像素组电连接的第一栅线G1-n和第三栅线G3-n分别输入栅极开启信号。在阶段t2-n中，第n行子像素组电连接的第二栅线G2-n和第三栅线G3-n分别输入栅极开启信号。下面以第一个行组PXZ-1中的第一子行组(例如第一行子像素)和第二子行组(例如第二行子像素)以及第二个行组PXZ-2中的第一子行组(例如第三行子像素)和第二子行组(例如第四行子像素)为例进行说明。
其中，第1个数据输入阶段t0-1包括：阶段t1-1和t2-1。第2个数据输入阶段t0-2包括：阶段t1-2和t2-2。并且，g1-1为第1行子像素电连接的第一栅线G1-1输入的信号，g2-1为第2行子像素电连接的第二栅线G2-1输入 的信号。g3-1为第一个行组PXZ-1的第三栅线G3-1输入的信号。g1-2为第3行子像素电连接的第一栅线G1-2输入的信号，g2-2为第4行子像素电连接的第二栅线G2-2输入的信号。g3-2为第二个行组PXZ-2的第三栅线G3-2输入的信号。
在阶段t1-1中，第2行子像素电连接的第二栅线G2-1输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第3行子像素电连接的第一栅线G1-2输入低电平信号，以控制第3行子像素中的第一晶体管T1均截止。第4行子像素电连接的第二栅线G2-2输入低电平信号，以控制第4行子像素中的第二晶体管T2均截止。第二个行组PXZ-2的第三栅线G3-2输入低电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均截止。第1行子像素电连接的第一栅线G1-1输入高电平信号，以控制第1行子像素中的第一晶体管T1均导通。第一个行组PXZ-1的第三栅线G3输入高电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第1行子像素中的第一像素电极110-1输入数据信号。
在阶段t2-1中，第1行子像素电连接的第一栅线G1-1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2-1输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第3行子像素电连接的第一栅线G1-2输入低电平信号，以控制第3行子像素中的第一晶体管T1均截止。第二个行组PXZ-2的第三栅线G3输入低电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均截止。第2行子像素电连接的第二栅线G2-1输入高电平信号，以控制第2行子像素中的第二晶体管T2均导通。第一个行组PXZ-1的第三栅线G3输入高电平信号，以控制第一个行组PXZ-1中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第2行子像素中的第二像素电极110-2输入数据信号。
在阶段t1-2中，第1行子像素电连接的第一栅线G1-1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2-1输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。 第4行子像素电连接的第二栅线G2-2输入低电平信号，以控制第4行子像素中的第二晶体管T2均截止。第二个行组PXZ-2的第三栅线G3输入低电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均截止。第3行子像素电连接的第一栅线G1-2输入高电平信号，以控制第3行子像素中的第一晶体管T1均导通。第二个行组PXZ-2的第三栅线G3-2输入高电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第3行子像素中的第一像素电极110-1输入数据信号。
在阶段t2-2中，第1行子像素电连接的第一栅线G1-1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2-1输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第3行子像素电连接的第一栅线G1-2输入低电平信号，以控制第3行子像素中的第一晶体管T1均截止。第一个行组PXZ-1的第三栅线G3-1输入低电平信号，以控制第一个行组PXZ-1中的第三晶体管T3均截止。第4行子像素电连接的第二栅线G2-2输入高电平信号，以控制第4行子像素中的第二晶体管T2均导通。第二个行组PXZ-2的第三栅线G3-2输入高电平信号，以控制第二个行组PXZ-2中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第4行子像素中的第二像素电极110-2输入数据信号。
其余过程依次类推，在此不作赘述。
示例性地，以红色子像素组为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过反射外界环境光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2中的反射电极输入的数据信号不能控制液晶分子翻转，则第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制液晶分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号不能控制驱动分子翻转，则第一分区Q-1中的第一反射电极110-1可以将入射的光反射出去，从而使得仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，第一分区Q-1中的第一反射电极 110-1输入的数据信号不能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号能控制驱动分子翻转，则第二分区Q-2中的第二反射电极110-2可以将入射的光反射出去，从而使得仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号也能控制驱动分子翻转，则第一分区Q-1中的第一反射电极110-1可以将入射的光反射出去，并且，第二分区Q-2中的第二反射电极110-2也可以将入射的光反射出去，从而使得第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
示例性地，以红色子像素组为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2中的反射电极输入的数据信号不能控制液晶分子翻转，则第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号不能控制驱动分子翻转，则背光源的光可以穿过第一通孔111并通过第一分区Q-1发射出去，从而使得仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号不能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号能控制驱动分子翻转，则背光源的光可以穿过第二通孔112并通过第二分区Q-2发射出去，从而使得仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电 极110-2输入的数据信号也能控制驱动分子翻转，则背光源的光可以穿过第一通孔111并通过第一分区Q-1发射出去，以及背光源的光可以穿过第二通孔112并通过第二分区Q-2发射出去，从而使第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
本公开实施例又提供了一些显示面板，其结构示意图如图13所示，其针对上述实施例的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，同一子像素中，可以使第一像素电极110-1的面积小于第二像素电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。示例性地，如图13所示，各第一颜色子像素组spx-1中，第一像素电极110-1的面积小于第二像素电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。各第二颜色子像素组spx-2中，第一像素电极110-1的面积小于第二像素电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。各第三颜色子像素组spx-3中，第一像素电极110-1的面积小于第二像素电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。
需要说明的是，在显示面板处于反射模式时，由于第一像素电极110-1的面积小于第二像素电极110-2的面积，可以使第一分区Q-1的亮度小于第二分区Q-2的亮度，从而可以使显示面板实现64灰阶。示例性地，以红色子像素组为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过反射外界环境光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间 内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
在具体实施时，第二通孔112和第一通孔111的实施方式可以参照上述实施方式，在此不作赘述。
需要说明的是，在显示面板处于透射模式时，由于第一像素电极110-1的面积和第二像素电极110-2的面积不同，可以使第一反射区的亮度和第二反射区的亮度不同，从而可以使显示面板实现64灰阶。示例性地，以红色子像素组为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
需要说明的是，本实施例中的显示面板的工作过程可以参照上述实施例中显示面板的工作过程，具体在此不作赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相 似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置还可以包括背光源。该背光源可以位于衬底基板背离对向基板的一侧。其中，背光源可以为直下式背光源或侧入式背光源，其具体设置方式可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底基板；
    多个子像素，设置于所述衬底基板上，所述多个子像素中的至少一个包括像素电极；
    多个晶体管，所述多个晶体管包括多个第一晶体管、多个第二晶体管、多个第三晶体管；
    多条数据线，间隔设置于所述衬底基板上；
    多条栅线，间隔设置于所述衬底基板上；且所述多条栅线包括多条第一栅线、多条第二栅线以及多条第三栅线；
    其中，以相邻的两行子像素为一个行组，所述行组具有沿列方向排列的第一子行组和第二子行组；所述像素电极包括第一像素电极和第二像素电极；
    所述第一子行组中的一个子像素包括一个所述第一晶体管和一个所述第一像素电极；其中，所述第一子行组中的第一晶体管的栅极电连接一条所述第一栅线；并且，同一所述子像素中，所述第一晶体管的第二极电连接所述第一像素电极；
    所述第二子行组中的一个子像素包括一个所述第二晶体管和一个所述第二像素电极；其中，所述第二子行组中的第二晶体管的栅极电连接一条所述第二栅线；并且，同一所述子像素中，所述第二晶体管的第二极电连接所述第二像素电极；
    同一所述行组中，沿列方向上相邻的两个子像素共用一个所述第三晶体管；其中，所述行组中的第三晶体管的栅极电连接一条所述第三栅线；
    一列子像素中的第一晶体管和第二晶体管通过共用的第三晶体管与一条所述数据线电连接。
  2. 如权利要求1所述的显示面板，其中，同一所述行组中，沿所述列方向上相邻的两个子像素组成一个子像素组；
    所述子像素组被配置为显示画面中的一个像素点的至少部分区域。
  3. 如权利要求1或2所述的显示面板，其中，所述第三晶体管的有源层包括第一源极区、第一漏极区、第二漏极区、第一沟道区以及第二沟道区；其中，所述第一沟道区位于所述第一源极区和所述第一漏极区之间，所述第二沟道区位于所述第一源极区和所述第二漏极区之间；
    所述第一源极区与所述数据线电连接，所述第一漏极区与所述第一晶体管的第一极电连接，所述第二漏极区与所述第二晶体管的第一极电连接。
  4. 如权利要求3所述的显示面板，其中，所述显示面板还包括：
    源导电层，位于所述衬底基板上，且所述源导电层包括所述多条间隔设置的数据线、多个源连接部、多个第一源极部和多个第二源极部；其中，一个所述源连接部、一个所述第一源极部以及一个所述第二源极部位于一个所述子像素组中；
    所述第一源极部作为所述第一晶体管的第一极，所述第二源极部作为所述第二晶体管的第一极；
    同一所述子像素组中，所述第一源极部与所述第一漏极区电连接，所述第二源极部与所述第二漏极区电连接，所述第一源极区与所述源连接部电连接，所述源连接部与一条所述数据线电连接。
  5. 如权利要求4所述的显示面板，其中，所述源连接部包括：相互电连接的第一子源连接部和第二子源连接部；其中，所述第一子源连接部沿行方向延伸，所述第二子源连接部沿列方向延伸；并且，所述第一子源连接部与所述数据线电连接，所述第二子源连接部与所述第一源极区电连接。
  6. 如权利要求1-5任一项所述的显示面板，其中，所述像素电极设置为反射电极；所述第一像素电极设置有第一通孔，所述第二像素电极设置有第二通孔，所述第一通孔的面积与所述第二通孔的面积不同。
  7. 如权利要求6所述的显示面板，其中，所述衬底基板具有：第一分区和第二分区；其中，所述第一分区覆盖所述子像素组中的一个子像素，所述第二分区覆盖所述子像素组的另一个子像素；
    所述显示面板还包括：
    对向基板，与所述衬底基板相对设置；
    色阻层，位于所述衬底基板与所述对向基板之间，并且，所述色阻层包括：位于各所述子像素的子色阻层；
    其中，所述子色阻层具有第一子色阻区和第二子色阻区，在垂直于所述衬底基板所在平面的方向上，所述第一分区覆盖所述第一子色阻区，所述第二分区覆盖所述第二子色阻区。
  8. 如权利要求7所述的显示面板，其中，所述第一像素电极与位于所述第一子色阻区的子色阻层具有第一正对面积；
    所述第二像素电极与位于所述第二子色阻区的子色阻层具有第二正对面积；
    同一所述子像素组中，所述第一正对面积与所述第二正对面积不同。
  9. 如权利要求8所述的显示面板，其中，同一所述子像素组中，所述第一像素电极的面积和所述第二像素电极的面积大致相同，且所述第一子色阻区的面积小于所述第二子色阻区的面积。
  10. 如权利要求9所述的显示面板，其中，位于所述第一分区内的所述子色阻层设置有第一过孔，所述第一过孔贯穿所述子色阻层；
    所述第一过孔在所述衬底基板的正投影与所述第一通孔在所述衬底基板的正投影不交叠。
  11. 如权利要求8所述的显示面板，其中，同一所述子像素组中，所述第一像素电极的面积小于所述第二像素电极的面积，且所述第一子色阻区的面积小于或大致等于所述第二子色阻区的面积。
  12. 如权利要求6-11任一项所述的显示面板，其中，所述第一通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠；
    所述第二通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠。
  13. 如权利要求12所述的显示面板，其中，针对与所述第一晶体管电连接的第一栅线和第一像素电极，所述第一栅线和所述第一晶体管在所述衬底基板的正投影分别与所述第一像素电极在所述衬底基板的正投影具有交叠区域；和/或，
    针对与所述第二晶体管电连接的第二栅线和第二像素电极，所述第二栅线和所述第二晶体管在所述衬底基板的正投影分别与所述第二像素电极在所述衬底基板的正投影具有交叠区域；和/或，
    所述第三栅线在所述衬底基板的正投影与电连接的所述第三晶体管、所述第一像素电极和所述第二像素电极在所述衬底基板的正投影具有交叠区域。
  14. 如权利要求6-13任一项所述的显示面板，其中，所述第一像素电极设置有一个第一通孔，所述第二通孔包括间隔设置的第一子通孔和第二子通孔；
    针对一个所述子像素组，所述第一子通孔在所述衬底基板的正投影相对所述第二子通孔在所述衬底基板的正投影靠近所述子像素电连接的数据线在所述衬底基板的正投影；和/或，
    针对一个所述子像素组，所述第二子通孔在所述衬底基板的正投影相对所述第一子通孔在所述衬底基板的正投影远离所述子像素电连接的数据线在所述衬底基板的正投影。
  15. 如权利要求14所述的显示面板，其中，所述第一子通孔在所述衬底基板的正投影位于所述第一子源连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影之间，且所述第一子通孔在所述衬底基板的正投影位于所述第二子源连接部在所述衬底基板的正投影与所述第三栅线在所述衬底基板的正投影之间。
  16. 如权利要求6-15任一项所述的显示面板，其中，所述显示面板还包括：透明导电层，位于所述像素电极背离所述衬底基板一侧；
    所述透明导电层包括间隔设置的多个第一子透明导电部；其中，一个所述第一子透明导电部在所述衬底基板的正投影位于一个所述第一分区内；同 一所述第一分区内，所述第一子透明导电部在所述衬底基板的正投影覆盖所述第一通孔在所述衬底基板的正投影，且所述第一子透明导电部在所述衬底基板的正投影位于所述第一像素电极在所述衬底基板的正投影内；和/或，
    所述透明导电层包括间隔设置的多个第二子透明导电部；其中，一个所述第二子透明导电部在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二子透明导电部在所述衬底基板的正投影覆盖所述第二通孔在所述衬底基板的正投影，且所述第二子透明导电部在所述衬底基板的正投影位于所述第二像素电极在所述衬底基板的正投影内。
  17. 如权利要求6-16任一项所述的显示面板，其中，所述显示面板还包括：
    第一平坦化层，位于所述反射电极所在层与所述衬底基板之间；
    辅助电极层，位于所述第一平坦化层与所述反射电极所在层之间；
    第二平坦化层，位于所述辅助电极层与所述反射电极所在层之间；
    所述辅助电极层包括间隔设置的多个第一辅助电极；其中，一个所述第一辅助电极在所述衬底基板的正投影位于一个所述第一分区内；同一所述第一分区内，所述第一像素电极在所述衬底基板的正投影覆盖所述第一辅助电极在所述衬底基板的正投影；和/或，
    所述辅助电极层包括间隔设置的多个第二辅助电极；其中，一个所述第二辅助电极在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二像素电极在所述衬底基板的正投影覆盖所述第二辅助电极在所述衬底基板的正投影。
  18. 如权利要求3-17任一项所述的显示面板，其中，所述显示面板还包括：
    栅绝缘层，位于所述源导电层与所述衬底基板之间；
    栅导电层，位于所述栅绝缘层与所述衬底基板之间；且所述栅导电层包括多条第一栅线、多条第二栅线以及多条第三栅线；
    所述栅导电层还包括：间隔设置的多个第一补偿电极；其中，一个所述 第一补偿电极在所述衬底基板的正投影位于一个所述第一分区内；同一所述第一分区内，所述第一像素电极在所述衬底基板的正投影覆盖所述第一补偿电极在所述衬底基板的正投影，且所述第一补偿电极在所述衬底基板的正投影与所述第一晶体管的第一漏极部在所述衬底基板的正投影具有交叠区域；和/或，
    所述栅导电层还包括：间隔设置的多个第二补偿电极；其中，一个所述第二补偿电极在所述衬底基板的正投影位于一个所述第二分区内；同一所述第二分区内，所述第二像素电极在所述衬底基板的正投影覆盖所述第二补偿电极在所述衬底基板的正投影，且所述第二补偿电极在所述衬底基板的正投影与所述第二晶体管的第二漏极部在所述衬底基板的正投影具有交叠区域。
  19. 一种显示装置，其中，包括如权利要求1-18任一项所述的显示面板。
  20. 一种如权利要求1-18任一项所述的显示面板的驱动方法，其中，包括：
    在一帧时间的各数据输入阶段中驱动一个所述行组中的子像素；
    其中，在一个所述数据写入阶段中驱动一个所述行组中的子像素，包括：
    对所述行组中的第一子行组的子像素电连接的第一栅线加载栅极开启信号，对所述第一子行组的子像素电连接的第二栅线加载栅极关闭信号，对所述第一子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使所述第一子行组的第一像素电极输入数据信号；
    对所述行组中的第二子行组的子像素电连接的第一栅线加载栅极关闭信号，对所述第二子行组的子像素电连接的第二栅线加载栅极开启信号，对所述第二子行组的子像素电连接的第三栅线加载栅极开启信号，对各数据线加载数据信号，使所述第二子行组的第二像素电极输入数据信号。
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