WO2021163975A1 - 显示面板、其驱动方法及显示装置 - Google Patents

显示面板、其驱动方法及显示装置 Download PDF

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Publication number
WO2021163975A1
WO2021163975A1 PCT/CN2020/076077 CN2020076077W WO2021163975A1 WO 2021163975 A1 WO2021163975 A1 WO 2021163975A1 CN 2020076077 W CN2020076077 W CN 2020076077W WO 2021163975 A1 WO2021163975 A1 WO 2021163975A1
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WIPO (PCT)
Prior art keywords
sub
base substrate
pixels
area
reflective electrode
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Application number
PCT/CN2020/076077
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English (en)
French (fr)
Inventor
秦相磊
林坚
张勇
杨智超
张丽敏
孙泽鹏
唐亮珍
段智龙
金红贵
安亚帅
乜玲芳
王建
宋雪超
田丽
庞净
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/076077 priority Critical patent/WO2021163975A1/zh
Priority to CN202080000145.5A priority patent/CN113728271B/zh
Priority to US17/755,329 priority patent/US12038661B2/en
Publication of WO2021163975A1 publication Critical patent/WO2021163975A1/zh
Priority to US18/678,563 priority patent/US20240310686A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device.
  • transflective display panels have been widely used in display devices such as mobile phones and tablet computers due to their advantages of low power consumption and strong environmental adaptability.
  • the display panel provided by the embodiment of the present disclosure includes: a base substrate;
  • a plurality of sub-pixels are arranged on the base substrate, and at least one of the plurality of sub-pixels includes a reflective electrode;
  • the reflective electrode at least includes a first reflective electrode and a second reflective electrode that are insulated and spaced apart from each other, the first reflective electrode is provided with a first through hole, and the second reflective electrode is provided with a second through hole, so The area of the first through hole is different from the area of the second through hole.
  • the base substrate has a first partition and a second partition, the orthographic projection of the first reflective electrode on the base substrate is located in the first partition, and the The orthographic projection of the second reflective electrode on the base substrate is located in the second subarea;
  • the display panel also includes:
  • the opposite substrate is arranged opposite to the base substrate;
  • the color resist layer is located between the base substrate and the opposite substrate, and the color resist layer includes: a sub-color resist layer located in each of the sub-pixels;
  • the sub-color resist layer has a first sub-color resist area and a second sub-color resist area, and in a direction perpendicular to the plane of the base substrate, the first sub-area covers the first sub-color resist Area, the second sub-area covers the second sub-color resistance area.
  • the first reflective electrode and the sub-color resist layer located in the first sub-color resist region have a first facing area
  • the second reflective electrode and the sub-color-resist layer located in the second sub-color-resist region have a second facing area
  • the first facing area is different from the second facing area.
  • the area of the first reflective electrode and the area of the second reflective electrode are approximately the same, and the area of the first sub-color resist region is smaller than The area of the second sub-color resistance region.
  • the sub-color resist layer located in the first partition is provided with a first via hole, and the first via hole penetrates the sub-color resist layer;
  • the orthographic projection of the first via on the base substrate and the orthographic projection of the first through hole on the base substrate do not overlap.
  • the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel;
  • the area of the first via hole in the second color sub-pixel is greater than the area of the first via hole in the first color sub-pixel; and/or,
  • the area of the first via hole in the first color sub-pixel is larger than the area of the first via hole in the third color sub-pixel.
  • the first color sub-pixel has a first side and a second side opposite to each other; wherein, the first side and the second side are arranged along a first direction;
  • the first via in the first color sub-pixel includes a first sub-via and a second sub-via; the first sub-via is located on the first side, and the second sub-via is located on the second Side; and/or,
  • the second color sub-pixel has a third side and a fourth side opposite to each other; wherein the third side and the fourth side are arranged along a first direction; the first via hole in the second color sub-pixel
  • the orthographic projection on the base substrate extends from the third side to the fourth side; and/or,
  • the third color sub-pixel has a fifth side and a sixth side opposite to each other; wherein the fifth side and the sixth side are arranged along a first direction; the first via hole in the third color sub-pixel Comprising a third sub-via and a fourth sub-via; the third sub-via is located on the fifth side, and the fourth sub-via is located on the sixth side; and/or,
  • the area of the first sub-via is substantially the same as the area of the second sub-via; and/or,
  • the area of the third sub-via is approximately the same as the area of the fourth sub-via.
  • the center of the first via hole in the first color sub-pixel, the center of the first via hole in the second color sub-pixel, and the third color sub-pixel are arranged on the same straight line along the first direction.
  • the area of the first reflective electrode is smaller than the area of the second reflective electrode, and the area of the first sub-color resist region is smaller than or approximately It is equal to the area of the second sub-color resistance region.
  • the display panel further includes:
  • the first planarization layer is located between the layer where the reflective electrode is located and the base substrate;
  • the source conductive layer is located between the first planarization layer and the base substrate, and the source conductive layer includes a plurality of data lines arranged at intervals;
  • a gate insulating layer located between the source conductive layer and the base substrate;
  • the gate conductive layer is located between the gate insulating layer and the base substrate, and the gate conductive layer includes a plurality of first gate lines and a plurality of second gate lines arranged at intervals;
  • the display panel further includes: a plurality of first transistors and a plurality of second transistors arranged at intervals; wherein, the orthographic projection of one of the first transistors on the base substrate is located in one of the first sub-regions, and one of the first transistors is located in the first subarea.
  • the orthographic projection of the second transistor on the base substrate is located in one of the second sub-regions;
  • the gates of the first transistors in a row of sub-pixels are electrically connected to the same first gate line;
  • the gates of the second transistors in a row of sub-pixels are electrically connected to the same second gate line;
  • the first pole of the first transistor and the first pole of the second transistor in a column of sub-pixels are electrically connected to the same data line;
  • the second electrode of the first transistor is electrically connected to the first reflective electrode
  • the second electrode of the second transistor is electrically connected to the second reflective electrode.
  • the orthographic projection of the first through hole on the base substrate is not intersected with the orthographic projection of the source conductive layer and the gate conductive layer on the base substrate.
  • the orthographic projection of the second through hole on the base substrate does not overlap with the orthographic projection of the source conductive layer and the gate conductive layer on the base substrate, respectively.
  • the gate conductive layer further includes a plurality of third gate lines arranged at intervals;
  • the display panel further includes: a plurality of third transistors arranged at intervals; one of the first transistors The orthographic projection of the three transistors on the base substrate is located in one of the sub-pixels;
  • the gates of the third transistors in a row of sub-pixels are electrically connected to the same third gate line;
  • the first transistor and the second transistor are electrically connected to the source connection part through the third transistor.
  • the source conductive layer further includes: a plurality of source connection parts
  • the source connection portion includes: a first sub-source connection portion and a second sub-source connection portion that are electrically connected to each other; wherein the first sub-source connection portion extends along a first direction, and the second sub-source connection portion extends along Extending in the second direction; and, the first sub-source connecting portion is electrically connected to the data line, and the second sub-source connecting portion is electrically connected to the third transistor.
  • the orthographic projection of the first sub-via on the base substrate is located at the orthographic projection of the first sub-source connection portion on the base substrate and the data line Between the orthographic projections of the base substrate, and the orthographic projection of the first sub-via on the base substrate is located between the orthographic projection of the second sub-source connecting portion on the base substrate and the The third grid line is between the orthographic projections of the base substrate.
  • the display panel further includes: a transparent conductive layer located on a side of the reflective electrode away from the base substrate;
  • the transparent conductive layer includes a plurality of first sub-transparent conductive parts arranged at intervals; wherein, an orthographic projection of one of the first sub-transparent conductive parts on the base substrate is located in one of the first sub-regions;
  • the orthographic projection of the first sub-transparent conductive portion on the base substrate covers the orthographic projection of the first through hole on the base substrate, and the first sub-transparent conductive The orthographic projection of the portion on the base substrate is located within the orthographic projection of the first reflective electrode on the base substrate.
  • the transparent conductive layer includes a plurality of second transparent conductive sub-parts arranged at intervals; wherein, the orthographic projection of one second transparent conductive sub-part on the base substrate is located In one of the second partitions;
  • the orthographic projection of the second sub-transparent conductive portion on the base substrate covers the orthographic projection of the second through hole on the base substrate, and the second sub-transparent conductive The orthographic projection of the portion on the base substrate is located within the orthographic projection of the second reflective electrode on the base substrate.
  • the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • the embodiment of the present disclosure also provides a driving method of the display panel, including:
  • driving a row of sub-pixels in one of the data writing phases includes:
  • a gate-on signal is applied to the first gate line electrically connected to the row sub-pixels, a gate-off signal is applied to the second gate line electrically connected to the row sub-pixels, and a data signal is applied to each data line to make the row
  • the first reflective electrode in the sub-pixel inputs a data signal
  • a gate-off signal is applied to the first gate line electrically connected to the row sub-pixels, a gate-on signal is applied to the second gate line electrically connected to the row sub-pixels, and a data signal is applied to each data line to make the row
  • the second reflective electrode in the sub-pixel inputs a data signal.
  • the method when the first gate line electrically connected to the row of sub-pixels is loaded with a gate turn-on signal, the method further includes: a third gate electrically connected to the row of sub-pixels. Line load gate turn-on signal; and/or,
  • the method further includes: applying a gate turn-on signal to the third gate line that is electrically connected to the row of sub-pixels.
  • FIG. 1 is a schematic diagram of some top-view structures of a display panel provided by an embodiment of the disclosure
  • FIG. 2a is a schematic cross-sectional view of the display panel shown in FIG. 1 along the AA' direction;
  • FIG. 2b is a schematic cross-sectional view of the display panel shown in FIG. 1 along the BB' direction;
  • 2c is a schematic cross-sectional view of the display panel shown in FIG. 1 along the CC' direction;
  • FIG. 3 is a schematic diagram of some top-view structures of reflective electrodes in a display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of other top-view structures of reflective electrodes in a display panel provided by embodiments of the present disclosure.
  • Fig. 5a is an equivalent circuit diagram of a sub-pixel of a display panel provided by an embodiment of the disclosure.
  • FIG. 5b is a schematic diagram of a layout structure in sub-pixels of a display panel provided by an embodiment of the present disclosure
  • FIG. 5c is a schematic cross-sectional structure diagram of the display panel shown in FIG. 5b along the AA' direction;
  • FIG. 5d is a schematic cross-sectional structure view of the display panel shown in FIG. 5b along the BB' direction;
  • FIG. 5e is a schematic diagram of other cross-sectional structures of the display panel shown in FIG. 5b along the AA' direction;
  • 5f is a schematic diagram of another layout structure of the sub-pixels of the display panel provided by the embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of some top-view structures of sub-color resist layers in a display panel provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of further top views of the sub-color resist layer in the display panel provided by the embodiments of the present disclosure.
  • FIG. 8 is a flowchart of a driving method provided by an embodiment of the disclosure.
  • FIG. 9 is a signal timing diagram provided by an embodiment of the disclosure.
  • FIG. 10a is a diagram of some other equivalent circuits in the sub-pixels of the display panel provided by the embodiments of the disclosure.
  • FIG. 10b is a schematic diagram of still some layout structures in the sub-pixels of the display panel provided by the embodiments of the present disclosure.
  • FIG. 10c is a schematic cross-sectional structure view of the display panel shown in FIG. 10b along the AA' direction;
  • FIG. 11 is a flowchart of still other driving methods provided by the embodiments of the present disclosure.
  • FIG. 12 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 13 is a schematic diagram of still other top-view structures of the display panel provided by the embodiments of the present disclosure.
  • the display area of a transflective display panel can be divided into a reflective area and a transmissive area.
  • the external ambient light is strong, the external ambient light is reflected by the reflective area to provide a light source for the transflective display panel to make It displays the image.
  • the backlight in the transflective display panel works, and the light emitted from the backlight passes through the transmissive area to provide a light source for the transflective display panel to display image.
  • An embodiment of the present disclosure provides a display panel, as shown in FIGS. 1 to 2c, which may include a base substrate 100 and a plurality of sub-pixels provided on the base substrate 100. At least one of the plurality of sub-pixels may include a reflective electrode; wherein, the reflective electrode includes at least a first reflective electrode 110-1 and a second reflective electrode 110-2 that are insulated and spaced apart from each other, and the first reflective electrode 110-1 is provided with The first through hole 111 and the second reflective electrode 110-2 are provided with a second through hole 112, and the area of the first through hole 111 is different from the area of the second through hole 112.
  • the through hole can be used to transmit the backlight; the reflective electrode can be used to reflect the light incident on the reflective electrode.
  • the through holes and the reflective electrodes can also implement functions in other display panels, which are not limited here.
  • sub-pixels are provided with partitions, reflective electrodes are provided in the partitions, and through holes are provided in the reflective electrodes.
  • the display panel can be in the reflective mode, which can make the external ambient light reflect by the reflective electrode to provide a light source for the display panel so that the display panel can display images.
  • the backlight can be turned off to reduce power consumption.
  • the display panel can be in see-through mode.
  • the backlight source work, the light emitted from the backlight source passes through the through holes in the reflective electrode to provide a light source for the display panel so that the display panel can display image. Therefore, the above-mentioned display panel provided by the embodiments of the present disclosure can realize a transflective display panel.
  • the display panel may include a plurality of pixel units PX.
  • the pixel unit in the embodiment of the present disclosure may refer to a combination of sub-pixels that can independently display one pixel point.
  • the pixel unit PX may include a plurality of sub-pixels, each of which is arranged in an array.
  • the plurality of sub-pixels in the pixel unit PX may include the first color sub-pixel spx-1, the second color sub-pixel spx-2, and the third color sub-pixel spx-3 that are sequentially arranged along the first direction F1.
  • the first-color sub-pixel spx-1, the second-color sub-pixel spx-2, and the third-color sub-pixel spx-3 can be arbitrarily selected from the red sub-pixel, the green sub-pixel, and the blue sub-pixel.
  • the first color sub-pixel spx-1 can be set as a red sub-pixel
  • the second color sub-pixel spx-2 can be set as a green sub-pixel
  • the third color sub-pixel spx-3 can be set as a blue sub-pixel. Red, green and blue can be used for color mixing to enable the display panel to achieve a display effect.
  • the pixel unit includes red sub-pixels, green sub-pixels, and blue sub-pixels sequentially arranged along the first direction F1 as an example for description.
  • the specific implementation of K can be designed according to the actual application environment, which is not limited here.
  • the base substrate may have a first partition Q-1 and a second partition Q-2.
  • the orthographic projection of the electrode 110-1 on the base substrate 100 is located in a first zone Q-1, that is, the reflective electrode located in the first zone Q-1 can be used as the first reflective electrode 110-1.
  • the orthographic projection of a second reflective electrode 110-2 on the base substrate 100 is located in a second subarea Q-2, that is, the reflective electrode located in the second subarea Q-2 can be used as the second reflective electrode 110-2.
  • the first reflective electrode 110-1 is provided with a first through hole 111
  • the second reflective electrode 110-2 is provided with a second through hole 112.
  • the display panel may further include a counter substrate 200 disposed opposite to the base substrate 100, and a color resist layer located between the base substrate 100 and the counter substrate 200.
  • the color resist layer may include: a sub-color resist layer located in each sub-pixel.
  • the sub-color resistance layer may have a first sub-color resistance region S-1 and a second sub-color resistance region S-2. In the direction perpendicular to the plane where the base substrate 100 is located, the first sub-region Q-1 covers the first sub-color resistance region S-1, and the second sub-region Q-2 covers the second sub-color resistance region S-2. In this way, the same sub-pixel can realize multi-gray-scale display, thereby improving the display effect.
  • the display panel may further include a liquid crystal layer 300 packaged between the base substrate 100 and the counter substrate 200.
  • the counter substrate 200 is provided with a common electrode
  • the base substrate 100 is also provided with a thin film transistor (TFT) located in each subarea.
  • the display panel may also include multiple gate lines and multiple data lines DA.
  • the gates of the TFTs in the same sub-pixel of a row can be electrically connected to one gate line, and the source of the TFTs in a column of sub-pixels can be connected to one
  • the data line DA is electrically connected, and the drain of the TFT may be electrically connected to the reflective electrode.
  • the data signal transmitted on the data line DA can be input to the reflective electrode, so that the reflective electrode can input the voltage of the data signal for display.
  • a corresponding voltage is also applied to the common electrode, so that an electric field can be provided between the reflective electrode and the common electrode to control the deflection of liquid crystal molecules, and the light source is combined to achieve a display effect.
  • the first reflective electrode 110-1 and the sub-color resist layer located in the first sub-color resist region S-1 may have a first direct opposite Area
  • the second reflective electrode 110-2 and the sub-color-resist layer located in the second sub-color-resist region S-2 may have a second facing area.
  • the first facing area is different from the second facing area.
  • the light-emitting brightness of the area where the first facing area is located is different from the light-emitting brightness of the area where the second facing area is located, so that the same color sub-pixels can achieve different grayscale brightness.
  • the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 and the orthographic projection of the sub-color resist layer located in the first sub-color resist region S-1 on the base substrate 100 may have a first overlap. Area, the area of the first overlapping area may be used as the first facing area.
  • the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 and the orthographic projection of the sub-color resist layer located in the second sub-color resist region S-2 on the base substrate 100 may have a second overlapping area, The area of the overlapping area can be used as the second facing area.
  • the area of the first reflective electrode 110-1 and the area of the second reflective electrode 110-2 in the same sub-pixel can be The areas are approximately the same, and the area of the first sub-color resistance region S-1 is smaller than the area of the second sub-color resistance region S-2.
  • the display panel is in the reflective mode, since the area of the first sub-color-resist region S-1 and the area of the second sub-color-resist region S-2 are different, the brightness of the first sub-region Q-1 and the second sub-region Q can be changed.
  • the brightness of -2 is different, so that the same color sub-pixel can realize the brightness of 4 gray scales.
  • the display panel When the display panel is in the see-through mode, since the area of the first sub-color-resist region S-1 and the area of the second sub-color-resist region S-2 are different, the brightness of the first sub-region Q-1 and the second sub-region Q- can be changed.
  • the brightness of 2 is different, so that the same color sub-pixel can realize the brightness of 4 gray scales.
  • the red sub-pixel is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects the external ambient light to make the display panel display.
  • red is used as the first gray level H1.
  • red is used as the second gray level H2.
  • red is used as the third gray level H3.
  • red is used as the fourth gray level H4.
  • H1 may be the lowest gray level of red
  • H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the sub-color resist layer located in the first subarea Q-1 may be provided with a first via hole.
  • the sub-color resist layer located in the second partition Q-2 is not provided with the first via hole.
  • the orthographic projection of the first via hole on the base substrate 100 and the orthographic projection of the first through hole 111 on the base substrate 100 do not overlap.
  • the sum of the area of the sub-color resist layer in the first partition Q-1 and the area of the first via hole may be the same as the area of the sub-color resist layer in the second partition Q-2. . In this way, by providing the first via hole, the area occupied by the sub-color resist layer in the first partition Q-1 can be made smaller than the area occupied by the sub-color resist layer in the second partition Q-2.
  • the area of the first through hole and the area of the second through hole in the same sub-pixel may be different.
  • the area of the second through hole 112 may be set to Y times the area of the first through hole 111.
  • 1 ⁇ Y ⁇ 5 can be set.
  • 2 ⁇ Y ⁇ 3 can be set.
  • the area of the second through hole 112 can also be set to 3 times the area of the first through hole 111, so that the intensity of the transmitted light of the second sub-region Q-2 can be increased. It is 3 times the intensity of the transmitted light of the first zone Q-1.
  • the area of the first through hole 111 in each sub-pixel may be approximately the same.
  • the area of the second through hole 112 is approximately the same. It should be noted that in practical applications, the area of the second through hole 112 and the area of the first through hole 111 and the value of Y can be designed and determined according to the actual application environment, which is not limited here.
  • the area of the second through hole 112 is set to be twice the area of the first through hole 111.
  • the area where the sub-pixel is located may be approximately mirror-symmetrical according to the central axis extending along the first direction F1.
  • the width of the first reflective electrode 110-1 in the first direction F1 and the width of the second reflective electrode 110-2 in the first direction F1 can be substantially the same, and the width of the second reflective electrode 110-2 in the second direction F2 It is greater than the width of the first reflective electrode 110-1 in the second direction F2.
  • the center of the area composed of the first reflective electrode 110-1 and the first through hole 111 is taken as the first center, and the center of the area composed of the second reflective electrode 110-2 and the second through hole 112 is taken as the second center.
  • the center is closer to the aforementioned central axis than the second center, so that in the same sub-pixel, the area of the first reflective electrode 110-1 and the area of the second reflective electrode 110-2 can be the same.
  • the area of the first through hole 111 in the same sub-pixel, can also be set to X times the area of the second through hole 112; 1 ⁇ X ⁇ 5.
  • 2 ⁇ X ⁇ 3 can be set.
  • the area of the first through hole 111 in each sub-pixel may be approximately the same.
  • the area of the second through hole 112 is approximately the same. It should be noted that in practical applications, the area of the second through hole 112 and the area of the first through hole 111 and the value of X can be designed and determined according to the actual application environment, which is not limited here.
  • the area of the first through hole 111 is set to be twice the area of the second through hole 112.
  • the area where the sub-pixel is located may be approximately mirror-symmetrical according to the central axis extending along the first direction F1.
  • the width of the first reflective electrode 110-1 in the first direction F1 and the width of the second reflective electrode 110-2 in the first direction F1 can be approximately the same, and the width of the first reflective electrode 110-1 in the second direction F2 It is greater than the width of the second reflective electrode 110-2 in the second direction F2.
  • the center of the area composed of the first reflective electrode 110-1 and the first through hole 111 is taken as the first center, and the center of the area composed of the second reflective electrode 110-2 and the second through hole 112 is taken as the second center.
  • the center is closer to the aforementioned central axis than the first center, so that in the same sub-pixel, the area of the first reflective electrode 110-1 and the area of the second reflective electrode 110-2 can be the same.
  • the red sub-pixel is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If neither the first zone Q-1 nor the second zone Q-2 emit light within one frame of display time, then red is used as the first gray level H1. If only the first subarea Q-1 emits light within one frame of display time, then red is used as the second gray level H2. If only the second subarea Q-2 emits light within one frame of display time, then red is used as the third gray level H3. If the first zone Q-1 and the second zone Q-2 both emit light within one frame of display time, then red is used as the fourth gray level H4.
  • H1 may be the lowest gray level of red
  • H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • a transparent conductive layer may be provided on the side of the reflective electrode away from the base substrate.
  • the transparent conductive layer may include a plurality of first sub transparent conductive parts 310 arranged at intervals.
  • the orthographic projection of one first sub-transparent conductive part 310 on the base substrate 100 may be located in a first zone Q-1, that is, one first sub-transparent conductive part 310 is provided in one first zone Q-1.
  • One first through hole 111 corresponds to one first sub-transparent conductive portion 310, and in the same first zone Q-1, the orthographic projection of the first sub-transparent conductive portion 310 on the base substrate 100 covers the first through hole 111 on the substrate. Orthographic projection of the substrate 100. Moreover, the orthographic projection of the first sub-transparent conductive portion 310 on the base substrate 100 is located within the orthographic projection of the first reflective electrode 110-1 on the base substrate 100. Further, the first sub-transparent conductive part 310 is directly electrically connected to the first reflective electrode 110-1. For example, the transparent conductive layer is directly prepared on the reflective electrode. In this way, the first through hole can be blocked by the first sub-transparent conductive part, and an electric field can also exist in the first through hole area, thereby improving the display effect.
  • a transparent conductive layer may be provided on the side of the reflective electrode away from the base substrate.
  • the transparent conductive layer includes a plurality of second transparent conductive sub-parts 320 arranged at intervals.
  • the orthographic projection of a second sub-transparent conductive portion 320 on the base substrate 100 is located in a second subarea Q-2. That is, one second sub-transparent conductive part 320 is provided in one second partition Q-2.
  • One second through hole 112 corresponds to one second sub-transparent conductive portion 320, and in the same second partition Q-2, the orthographic projection of the second sub-transparent conductive portion 320 on the base substrate 100 covers the second through hole 112 in the substrate Orthographic projection of the substrate 100. Moreover, the orthographic projection of the second sub-transparent conductive portion 320 on the base substrate 100 is located within the orthographic projection of the second reflective electrode 110-2 on the base substrate 100. Further, the second sub-transparent conductive part 320 is directly electrically connected to the second reflective electrode 110-2. For example, the transparent conductive layer is directly prepared on the reflective electrode. In this way, the second through hole 112 can be blocked by the second sub-transparent conductive portion 320, so that an electric field can also exist in the second through hole area, thereby improving the display effect.
  • the display panel may further include:
  • the first planarization layer 312 is located between the layer where the reflective electrode is located and the base substrate 100;
  • the source conductive layer 1300 is located between the first planarization layer 312 and the base substrate 100, and the source conductive layer 1300 may include a plurality of data lines DA arranged at intervals;
  • the gate insulating layer 311 is located between the source conductive layer 1300 and the base substrate 100;
  • the gate conductive layer 1200 is located between the gate insulating layer 311 and the base substrate 100, and the gate conductive layer 1200 may include a plurality of first gate lines G1 and a plurality of second gate lines G2 arranged at intervals.
  • a row of sub-pixels is electrically connected to a first gate line G1 and a second gate line G2
  • a column of sub-pixels is electrically connected to a data line DA.
  • the display panel may further include: a plurality of first transistors T1 and a plurality of second transistors T2 arranged at intervals; wherein, one first transistor The orthographic projection of T1 on the base substrate 100 is located in a first zone Q-1, and the orthographic projection of a second transistor T2 on the base substrate 100 is located in a second zone Q-2.
  • the gates of the first transistors in a row of sub-pixels are electrically connected to the same first gate line
  • the gates of the second transistors in a row of sub-pixels are electrically connected to the same second gate line.
  • the first pole of the first transistor and the first pole of the second transistor in a column of sub-pixels are electrically connected to the same data line.
  • the second electrode of the first transistor is electrically connected to the first reflective electrode.
  • the second electrode of the second transistor is electrically connected to the second reflective electrode.
  • the gate of the first transistor T1 is electrically connected to a first gate line G1
  • the first electrode of the first transistor T1 is electrically connected to a data line DA
  • the second electrode of the first transistor T1 is electrically connected to the first reflective electrode 110- 1 Electrical connection.
  • the gate of the second transistor T2 is electrically connected to a second gate line G2, the first electrode of the second transistor T2 is electrically connected to a data line DA, and the second electrode of the second transistor T2 is electrically connected to the second reflective electrode 110-2. connect.
  • a semiconductor layer is further provided between the gate insulating layer 311 and the source conductive layer 1300.
  • the semiconductor layer may include an active layer forming each transistor.
  • the active layer has a channel region.
  • the gate conductive layer 1200 may further include a gate forming each transistor.
  • the source conductive layer 1300 may further include: a plurality of source connection portions 1523, a plurality of first source portions 1323, a plurality of second source portions 1423, a plurality of first drain portions 1324, and a plurality of second drain portions 1424 ; Among them, a source connection portion 1523, a first source portion 1323, a first drain portion 1324, a second source portion and a second drain portion 1424 are located in a sub-pixel.
  • a first source portion 1323 serves as a first electrode of a first transistor T1
  • a first drain portion 1324 serves as a second electrode of a first transistor T1.
  • a second source portion 1423 serves as a first electrode of a second transistor T2, and a second drain portion 1424 serves as a second electrode of a second transistor T2.
  • the first source portion 1323 and the second source portion 1423 are electrically connected to the same data line DA through the source connection portion 1523.
  • the present disclosure includes but is not limited to this.
  • the first transistor T1 may include: a gate 1321 and an active layer insulated from the gate 1321 1322.
  • the first source portion 1323 and the first drain portion 1324 which are insulated from the gate 1321 and electrically connected to the active layer 1322, and the first reflective electrode 110-1 and the second reflective electrode 110-2.
  • the gate 1321 is located between the active layer 1322 and the base substrate 100.
  • the layer where the first source portion 1323 and the first drain portion 1324 are located is on the side of the active layer 1322 away from the base substrate 100.
  • a gate insulating layer 311 is provided between the gate 1321 and the active layer 1322.
  • the first source portion 1323 and the first drain portion 1324 directly overlap the active layer 1322 respectively.
  • a first planarization layer 312 is provided between the layer where the first source portion 1323 and the first drain portion 1324 are located and the layer where the first reflective electrode 110-1 and the second reflective electrode 110-2 are located.
  • the first reflective electrode 110-1 is electrically connected to the first drain portion 1324 through a via 3121 penetrating the first planarization layer 312.
  • the structure of the second transistor T2 is substantially the same as the structure of the first transistor T1, and the second reflective electrode 110-2 is electrically connected to the second electrode of the second transistor T2 through the via 3122 penetrating the first planarization layer 312, and the rest The structure is not repeated here.
  • an auxiliary electrode layer 400 may be provided between the layer where the reflective electrode is located and the first planarization layer 312, and a second planarization layer 313 may be provided between the auxiliary electrode layer 400 and the layer where the reflective electrode is located.
  • the first reflective electrode 110-1 is electrically connected to the first drain portion 1324 through a via 3121 penetrating the first planarization layer 312 and the second planarization layer 313.
  • the second reflective electrode 110-2 is electrically connected to the second electrode of the second transistor T2 through the via hole 3122 penetrating the first planarization layer 312 and the second planarization layer 313, and the rest of the structure is not described here.
  • the auxiliary electrode layer 400 may include a plurality of first auxiliary electrodes 410 arranged at intervals.
  • the orthographic projection of a first auxiliary electrode 410 on the base substrate 100 is located in a first zone Q-1, that is, the first zone Q-1 is provided with a first auxiliary electrode 410, and one first reflective electrode 110-1 corresponds to One first auxiliary electrode 410, and in the same first zone Q-1, the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 covers the orthographic projection of the first auxiliary electrode 410 on the base substrate 100.
  • the first reflective electrode 110-1 and the first auxiliary electrode 410 can have a facing area to form the capacitor structure C11.
  • the auxiliary electrode layer 400 may include a plurality of second auxiliary electrodes 420 arranged at intervals.
  • the orthographic projection of a second auxiliary electrode 420 on the base substrate 100 is located in a second subarea Q-2, that is, a second subarea Q-2 is provided with a second auxiliary electrode 420 and a first reflective electrode 110-1 Corresponds to one first auxiliary electrode 410.
  • the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 covers the orthographic projection of the second auxiliary electrode 420 on the base substrate 100. In this way, a facing area between the second reflective electrode 110-2 and the second auxiliary electrode 420 can be provided to form the capacitor structure C12.
  • the gate conductive layer may further include: a plurality of first compensation electrodes 510 spaced apart; that is, a plurality of first compensation electrodes 510 spaced apart in the layer where the gate 1321 is located; wherein, The orthographic projection of one first compensation electrode 510 on the base substrate 100 is located in a first zone Q-1, that is, one first reflective electrode 110-1 corresponds to one first compensation electrode 510.
  • the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 covers the orthographic projection of the first compensation electrode 510 on the base substrate 100, and the orthographic projection of the first compensation electrode 510 on the substrate 100
  • the orthographic projection of the substrate 100 and the orthographic projection of the first drain portion 1324 of the first transistor T1 on the base substrate 100 have an overlapping area. In this way, a facing area between the first compensation electrode 510 and the first drain portion 1324 of the first transistor T1 can be provided to form a capacitor structure C21.
  • the gate conductive layer 1200 may further include a plurality of second compensation electrodes 520 arranged at intervals.
  • the orthographic projection of a second compensation electrode 520 on the base substrate 100 is located in a second zone Q-2. That is, one second reflective electrode 110-2 corresponds to one second auxiliary electrode 420.
  • the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 covers the orthographic projection of the second compensation electrode 520 on the base substrate 100, and the second compensation electrode 520 is on the substrate 100.
  • the orthographic projection of the substrate 100 and the orthographic projection of the second drain portion 1424 of the second transistor T2 on the base substrate 100 have an overlapping area. In this way, an area facing the second compensation electrode 520 and the second drain portion 1424 of the second transistor T2 can be provided to form a capacitor structure C22.
  • the capacitor structures C11 and C21 can be connected in parallel to increase the capacitance value of the first reflective electrode.
  • the capacitor structures C12 and C22 are connected in parallel to increase the capacitance value of the second reflective electrode.
  • the total capacitance of the first reflective electrode and the total capacitance of the second reflective electrode may be approximately the same.
  • the capacitance value of the capacitor structure C11 and the capacitance value of the capacitor structure C21 may be approximately the same, and the capacitance value of the capacitor structure C12 and the capacitance value of the capacitor structure C22 may be approximately the same.
  • the specific structural forms of the capacitor structures C11, C12, C21, and C22 can be designed and determined according to the actual application environment, which is not limited here.
  • the source conductive layer and the gate conductive layer are made of metal materials. Metal materials are generally opaque. Therefore, in order to prevent the source conductive layer and the gate conductive layer from blocking the first through hole, in a specific implementation, in the embodiment of the present disclosure, in conjunction with FIG. 5b, the first through hole can be made
  • the orthographic projection of the hole on the base substrate does not overlap with the orthographic projections of the source conductive layer and the gate conductive layer on the base substrate, respectively. This can prevent the source conductive layer and the gate conductive layer from blocking the light of the first through hole.
  • the orthographic projection of the second through hole on the base substrate can be made to not overlap with the orthographic projections of the source conductive layer and gate conductive layer on the base substrate, respectively. . This can prevent the source conductive layer and the gate conductive layer from blocking the light of the second through hole.
  • the first gate line G1 and the first reflective electrode 110-1 electrically connected to the first transistor T1 the first gate line G1 and the first transistor
  • the orthographic projection of T1 on the base substrate 100 and the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 respectively have overlapping areas.
  • the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 covers the orthographic projection of the first transistor T1 on the base substrate 100, and the orthographic projection of the first reflective electrode 110-1 on the base substrate 100 and the first grid
  • the orthographic projection of the line G1 on the base substrate 100 has an overlapping area.
  • the film layer where the first gate line G1 and the first transistor T1 are located is between the first reflective electrode 110-1 and the base substrate 100, and the orthographic projection of the first gate line G1 on the base substrate 100 and the first reflective electrode
  • the orthographic projection of 110-1 and the first transistor T1 on the base substrate 100 has an overlapping area, so that the first reflective electrode 110-1 can be used to shield the first gate line G1 and the first transistor T1 to increase the first reflective electrode.
  • the area occupied by 110-1 in the sub-pixel can increase the pixel aperture ratio.
  • the second gate line G2 and the second reflective electrode 110-2 electrically connected to the second transistor T2 the second gate line G2 and the second transistor
  • the orthographic projection of T2 on the base substrate 100 and the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 respectively have overlapping areas.
  • the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 covers the orthographic projection of the second transistor T2 on the base substrate 100, and the orthographic projection of the second reflective electrode 110-2 on the base substrate 100 and the second grid
  • the orthographic projection of the line G2 on the base substrate 100 has an overlapping area.
  • the film layer where the second gate line G2 and the second transistor T2 are located is between the second reflective electrode 110-2 and the base substrate 100, and the orthographic projection of the second gate line G2 on the base substrate 100 and the second reflective electrode
  • the orthographic projection of 110-2 and the second transistor T2 on the base substrate 100 has an overlapping area, so that the second reflective electrode 110-2 can be used to shield the second gate line G2 and the second transistor T2 to increase the second reflective electrode
  • the area occupied by 110-2 in the sub-pixel can increase the pixel aperture ratio.
  • the source connecting portion 1523 may be extended along the first direction F1.
  • the first reflective electrode 110-1 may be provided with a first through hole 111.
  • the second reflective electrode 110-2 may also be provided with a second through hole 112.
  • the orthographic projection of the source connection portion 1523 on the base substrate and the orthographic projection of the first reflective electrode 110-1 and the second reflective electrode 110-2 on the base substrate 100 may not overlap. In this way, the length of the source connection portion 1523 can be reduced, thereby reducing the signal delay.
  • the first reflective electrode 110-1 may be provided with a first through hole 111.
  • the area of the first through hole 111 may be set to 208.377 ⁇ m 2 .
  • the shape of the first through hole 111 may be a rectangle, the long side of the rectangle may extend in the first direction F1, the short side of the rectangle may extend in the second direction F2, and the width of the long side may be short. 2 to 3 times the width of the side.
  • the length of the long side and the short side of the first through hole 111 can be set according to the requirements of the actual application, which is not limited here.
  • the source connecting portion 1523 may be arranged in the form of a curve or a broken line.
  • the second through hole 112 may include a first sub-through hole 112-1 and a second sub-through hole 112-2 arranged at intervals, that is, the second reflective electrode 110-2 may be provided with one first sub-through hole 112-1 and one
  • the second through-hole 112-2 can divide the second through-hole into two so as to be dispersedly arranged in the second reflective electrode 110-2.
  • the areas of the first sub-through hole 112-1 and the second sub-through hole 112-2 may be substantially the same.
  • the area of the first sub-via 112-1 may be set to 4.008 ⁇ m 2 .
  • the shape of the first sub-through hole 112-1 may be a rectangle, the long side of the rectangle may extend in the second direction F2, the short side of the rectangle may extend in the first direction F1, and the width of the long side may be It is 1.5 to 2 times the width of the short side.
  • the shape of the second sub-through hole 112-2 may be a rectangle, the long side of the rectangle may extend along the second direction F2, and the short side of the rectangle may extend along the first direction F1.
  • the long sides and short sides of the first through-hole 112-1 and the short side of the second through-hole 112-2 can be designed according to the requirements of the actual application environment, which is not limited here.
  • the orthographic projection of the first sub-through hole 112-1 on the base substrate 100 is close to the orthographic projection of the second sub-through hole 112-2 on the base substrate 100.
  • the data line DA to which the pixels are electrically connected is orthographically projected on the base substrate 100.
  • the orthographic projection of the second sub-through hole 112-2 on the base substrate 100 is farther from the orthographic projection of the first sub-through hole 112-1 on the base substrate 100.
  • the data line DA to which the pixels are electrically connected is orthographically projected on the base substrate 100.
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 is located at the source connection portion 1523 on the base substrate 100 and the orthographic projection of the first sub-via 112-1 is close to the data line DA on the base substrate 100.
  • the orthographic projection of the second source portion 1423 on the base substrate 100 is located at one of the orthographic projection of the source connection portion 1523 on the base substrate 100 away from the orthographic projection of the data line DA on the base substrate 100 Side; the orthographic projection of the second sub-via 112-2 on the base substrate 100 is located on the side of the orthographic projection of the second source portion 1423 on the base substrate 100 away from the orthographic projection of the source connection portion 1523 on the base substrate 100.
  • the source connection portion 1523 may include: a first sub-source connection portion 15231 and a second sub-source connection portion 15232 that are electrically connected to each other; wherein, the first sub-source connection portion 15231 is along the first direction F1 extends, and the second sub-source connection portion 15232 extends along the second direction F2; and, the first sub-source connection portion 15231 is electrically connected to the data line DA, and the second sub-source connection portion 15232 is respectively connected to the first source portion 1323 and the second The two source portions 1423 are electrically connected.
  • the source connecting portion 1523 can be arranged in a broken line shape.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 can be positioned at the orthographic projection of the first sub-source connection portion 15231 on the base substrate 100 and the data line DA in the liner. Between the orthographic projections of the base substrate 100, and the orthographic projection of the first sub-via 112-1 on the base substrate 100 is located at the orthographic projection of the second sub-source connection portion 15232 on the base substrate 100 and the first grid line G1 is in line Between the orthographic projection of the base substrate 100.
  • the sub-color resist layer located in the first partition Q-1 is provided with a first pass The hole 121, the first via hole 121 penetrates the sub-color resist layer 120-1.
  • the sub-color resist layer located in the first partition Q-1 is provided with a first via 122, A via hole 122 penetrates the sub-color resist layer 120-2.
  • the sub-color resist layer located in the first partition Q-1 is provided with a first via 123,
  • the first via 123 penetrates the sub-color resist layer 120-3.
  • the human eye has different sensitivity to different colors of light. For example, the human eye has the highest sensitivity to green, followed by red sensitivity, and the lowest sensitivity to blue. If the areas of the first via holes in the sub-pixels of different colors are set to be the same, the human eyes will feel that the image is greenish when viewing the image displayed on the display panel.
  • the size of the first via holes in the sub-pixels of different colors can be designed according to the sensitivity of human eyes to red, green, and blue.
  • the area of the first via hole 122 in the second color sub-pixel spx-2 can be made larger than the area of the first via hole 121 in the first color sub-pixel spx-1.
  • the area of the first via hole 121 in the first color sub-pixel spx-1 is larger than the area of the first via hole 123 in the third color sub-pixel spx-3.
  • the area of the first via hole in the green sub-pixel can be made larger than the area of the first via hole in the red sub-pixel, and the area of the first via hole in the red sub-pixel can be made larger than the area of the first via hole in the blue sub-pixel.
  • the area of a via In this way, the green light emission of the green sub-pixels can be reduced, so that the problem of the greenish picture can be improved.
  • the first color sub-pixel spx-1 may have a first side C1 and a second side C2 opposite to each other; wherein, the first side C1 and The second side C2 is arranged along the first direction F1.
  • the first via 121 in the first color sub-pixel spx-1 may include a first sub-via 121-1 and a second sub-via 121-2; the first sub-via 121-1 is located on the first side C1, The second via hole 121-2 is located on the second side C2. In this way, the first sub-via 121-1 and the second sub-via 121-2 can be respectively arranged on the edge of the sub-color resist layer.
  • the area of the first sub-via 121-1 and the area of the second sub-via 121-2 can be substantially the same.
  • the first sub-via 121-1 and the second sub-via 121-2 can be uniformly prepared, which reduces the difficulty of process preparation.
  • the shape of the orthographic projection of the first sub-via 121-1 on the base substrate 100 and the shape of the orthographic projection of the second sub-via 121-2 on the base substrate 100 can be approximately the same, and the first sub-via The area of the orthographic projection of the hole 121-1 on the base substrate 100 and the area of the orthographic projection of the second sub-via 121-2 on the base substrate 100 are approximately the same.
  • the shape of the first sub-via 121-1 and the second sub-via 121-2 can be set to a rectangle, the long side of the rectangle extends in the second direction F2, and the short side of the rectangle extends in the first direction F1.
  • the area of the rectangle can be set to 200 ⁇ m 2 .
  • the long side of the rectangle may be 2 to 3 times the short side.
  • the areas of the first sub-via 121-1 and the second sub-via 121-2 can be designed according to the actual application environment, which is not limited herein.
  • the second color sub-pixel spx-2 has a third side C3 and a fourth side C4 opposite to each other; wherein, the third side C3 and the fourth side C3 are opposite to each other.
  • the four sides C4 are arranged along the first direction F1.
  • the orthographic projection of the first via hole in the second color sub-pixel spx-2 on the base substrate 100 extends from the third side C3 to the fourth side C4.
  • the first via hole in the second color sub-pixel spx-2 may be configured as a rectangle, the long side of the rectangle extends in the first direction F1, and the short side of the rectangle extends in the second direction F2.
  • the area of the rectangle can be set to 812 ⁇ m 2 .
  • the width of the long side of the rectangle may be 2 to 3 times the width of the short side.
  • the first via hole in the second color sub-pixel spx-2 can be designed according to the actual application environment, which is not limited here.
  • the third color sub-pixel spx-3 has a fifth side C5 and a sixth side C6 opposite to each other; among them, the fifth side C5 and the fourth side C5 and C6 are opposite to each other.
  • the six sides C6 are arranged along the first direction F1.
  • the first via in the third color sub-pixel spx-3 may include a third sub-via 123-1 and a fourth sub-via 123-2; the third sub-via 123-1 is located on the fifth side C5, The fourth sub-via 123-2 is located on the sixth side C6. In this way, the third sub-via 123-1 and the fourth sub-via 123-2 can be respectively arranged on the edge of the sub-color resist layer.
  • the area of the third sub-via 123-1 can be substantially the same as the area of the fourth sub-via 123-2.
  • the third sub-via 123-1 and the fourth sub-via 123-2 can be uniformly prepared, which reduces the difficulty of process preparation.
  • the shape of the orthographic projection of the third sub-via 123-1 on the base substrate 100 and the shape of the orthographic projection of the fourth sub-via 123-2 on the base substrate 100 may be approximately the same, and the third sub-via The area of the orthographic projection of the hole 123-1 on the base substrate 100 and the area of the orthographic projection of the fourth sub-via 123-2 on the base substrate 100 are approximately the same.
  • the shape of the third sub-via 123-1 and the fourth sub-via 123-2 can be set to a rectangle, the long side of the rectangle extends in the second direction F2, and the short side of the rectangle extends in the first direction F1.
  • the area of the rectangle can be set to 157 ⁇ m 2 .
  • the length of the long side can be set to 2 to 3 times the length of the short side.
  • the third sub-via 123-1 and the fourth sub-via 123-2 can be designed according to the actual application environment, which is not limited here.
  • the center of the first via hole in the first color sub-pixel spx-1 can be set to be the first via hole in the second color sub-pixel spx-2.
  • the center of the hole and the center of the first via hole in the third color sub-pixel spx-3 are arranged on the same straight line L0 along the first direction F1. This can reduce the design difficulty of these first vias.
  • the sub-color resist layers in every two adjacent sub-pixels may have overlapping regions or adjacent. As shown in FIG.
  • the first sub-via 121-1 in the first color sub-pixel spx-1 The long side may coincide with the long side of the fourth sub-via 123-2 in the third color sub-pixel spx-3.
  • the long side of the second sub-via 121-2 in the first color sub-pixel spx-1 may coincide with the short side of the first via on the third side C3 in the second color sub-pixel spx-2.
  • the short side of the second sub-via 121-2 located on the fourth side C4 in the first color sub-pixel spx-1 may be the same as the long side of the third sub-via 123-1 in the third color sub-pixel spx-3 coincide.
  • first direction F1 may be the row direction of the sub-pixels
  • second direction F2 may be the column direction of the sub-pixels
  • first direction F1 may also be the column direction of the sub-pixels
  • second direction F2 may be the row direction of the sub-pixels.
  • it can be designed and determined according to the actual application environment, which is not limited here.
  • the above-mentioned features are not completely the same, and there may be some deviations. Therefore, the same relationship between the above-mentioned features as long as the above-mentioned conditions are substantially satisfied. That is, all belong to the protection scope of the present disclosure.
  • the above-mentioned sameness may be the same as allowed within the allowable error range.
  • the embodiment of the present disclosure also provides a driving method of the above-mentioned display panel, which may include: driving a row of sub-pixels in each data input stage of one frame time. Among them, driving a row of sub-pixels in a data writing stage, as shown in FIG. 8, may include the following steps:
  • the first transistor T1 when the first gate line G1 is loaded with a gate-on signal, the first transistor T1 can be controlled to be turned on. When the gate-off signal is applied to the first gate line G1, the first transistor T1 can be controlled to be turned off.
  • the gate-on signal when the first transistor T1 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the gate-on signal when the first transistor T1 is a P-type transistor, the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • the second transistor T2 when the second gate line G2 is loaded with a gate-on signal, the second transistor T2 can be controlled to be turned on. When the second gate line G2 is loaded with a gate-off signal, the second transistor T2 can be controlled to be turned off.
  • the gate-on signal when the second transistor T2 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the second transistor T2 when the second transistor T2 is a P-type transistor, the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • One frame of display time may include: a data input stage t1-y (1 ⁇ y ⁇ Y, and Y is the total number of first gate lines G1 in the display panel, y and Y are both integers) and a data input stage t2-y.
  • the first gate line G1 electrically connected to the y-th row of sub-pixels inputs a gate-on signal.
  • the second gate line G2 electrically connected to the sub-pixels in the yth row inputs a gate turn-on signal.
  • the following takes the first row of sub-pixels and the second row of sub-pixels as an example for description.
  • g1-1 is a signal input from the first gate line G1 electrically connected to the sub-pixels in the first row
  • g2-1 is a signal input from the second gate line G2 electrically connected to the sub-pixels in the first row
  • g1-2 is a signal input from the first gate line G1 electrically connected to the second row of sub-pixels
  • g2-2 is a signal input from the second gate line G2 electrically connected to the second row of sub-pixels.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first reflective electrode 110-1 in the first row of sub-pixels.
  • the first gate line G1 electrically connected to the first row of sub-pixels inputs a low-level signal to control the first transistors T1 in the first row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the first row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the second reflective electrode 110-2 in the first row of sub-pixels.
  • the second gate line G2 electrically connected to the second row of sub-pixels inputs a low-level signal to control the second transistors T2 in the second row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first reflective electrode 110-1 in the second row of sub-pixels.
  • the first gate line G1 electrically connected to the second row of sub-pixels inputs a low-level signal to control the first transistors T1 in the second row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the second reflective electrode 110-2 in the second row of sub-pixels.
  • the red sub-pixel is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects the external ambient light to make the display panel display. If the data signals input by the reflective electrodes in the first subarea Q-1 and the second subarea Q-2 cannot control the inversion of the liquid crystal molecules within the display time of one frame, the first subarea Q-1 and the second subarea Q-2 are not Glow, then red is used as the first gray level H1.
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the inversion of the liquid crystal molecules, the data input by the second reflective electrode 110-2 in the second subarea Q-2 If the signal cannot control the driving molecule to flip, the first reflective electrode 110-1 in the first subarea Q-1 can reflect the incident light, so that only the first subarea Q-1 emits light, and then red is used as the second gray scale. H2.
  • the data signal input by the first reflective electrode 110-1 in the first zone Q-1 cannot control the flipping of the driving molecule
  • the data input by the second reflective electrode 110-2 in the second zone Q-2 The signal can control the driving molecule to flip, then the second reflective electrode 110-2 in the second subarea Q-2 can reflect the incident light, so that only the second subarea Q-2 emits light, then the red color is used as the third gray level H3 .
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2
  • the signal can also control the driving molecule to flip, so the first reflective electrode 110-1 in the first subarea Q-1 can reflect the incident light, and the second reflective electrode 110-2 in the second subarea Q-2 also The incident light can be reflected out, so that both the first subarea Q-1 and the second subarea Q-2 emit light, and the red color is used as the fourth gray level H4.
  • the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the red sub-pixel is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If the data signals input by the reflective electrodes in the first subarea Q-1 and the second subarea Q-2 cannot control the inversion of the liquid crystal molecules within the display time of one frame, the first subarea Q-1 and the second subarea Q-2 are not Glow, then red is used as the first gray level H1.
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2 If the signal cannot control the driving molecule to flip, the light of the backlight can pass through the first through hole 111 and be emitted through the first subarea Q-1, so that only the first subarea Q-1 emits light, and then red is used as the second gray scale. H2.
  • the data signal input by the first reflective electrode 110-1 in the first zone Q-1 cannot control the flipping of the driving molecule
  • the data input by the second reflective electrode 110-2 in the second zone Q-2 The signal can control the driving molecule to flip, then the light of the backlight source can pass through the second through hole 112 and be emitted through the second partition Q-2, so that only the second partition Q-2 emits light, then red is used as the third gray level H3 .
  • the data signal input by the first reflective electrode 110-1 in the first subarea Q-1 can control the flipping of the driving molecule, and the data input by the second reflective electrode 110-2 in the second subarea Q-2
  • the signal can also control the driving molecule to flip, so the light of the backlight can pass through the first through hole 111 and be emitted through the first partition Q-1, and the light of the backlight can pass through the second through hole 112 and pass through the second partition.
  • Q-2 is emitted, so that both the first subarea Q-1 and the second subarea Q-2 emit light, and the red color is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4.
  • H1 may be the lowest gray level of red
  • H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state. Similarly, in a pixel unit, the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the embodiments of the present disclosure also provide some display panels, the structural schematic diagrams of which are shown in Figs. 10a to 10c, which are modified with respect to the implementation of the above-mentioned embodiment.
  • Figs. 10a to 10c which are modified with respect to the implementation of the above-mentioned embodiment.
  • Figs. 10a to 10c which are modified with respect to the implementation of the above-mentioned embodiment.
  • the gate conductive layer further includes a plurality of third gate lines G3 arranged at intervals; the display panel may also include: a plurality of third gate lines G3 arranged at intervals.
  • Transistor T3 wherein the orthographic projection of a third transistor T3 on the base substrate 100 is located in a sub-pixel; wherein the gate of the third transistor T3 in a row of sub-pixels is electrically connected to the same third gate line G3.
  • the first source portion 1323 and the second source portion 1423 are electrically connected to the source connection portion 1523 through the third transistor T3.
  • one first section Q-1 may also be provided with a first transistor T1
  • one second section Q-2 may also be provided with a second transistor T2.
  • One sub-pixel also includes a third transistor T3. That is, one first subarea Q-1 and one second subarea Q-2 share one third transistor T3.
  • a row of sub-pixels is electrically connected to a first gate line G1, a second gate line G2, and a third gate line G3, and a column of sub-pixels is electrically connected to a data line DA.
  • each sub-pixel may include a first transistor T1, a second transistor T2, and a third transistor T3.
  • the gate of the first transistor T1 is electrically connected to the first gate line G1
  • the first electrode of the first transistor T1 is electrically connected to the second electrode of the third transistor T3
  • the second electrode of the first transistor T1 is electrically connected to the first reflector.
  • the electrode 110-1 is electrically connected.
  • the gate of the second transistor T2 is electrically connected to the second gate line G2, the first electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second reflective electrode 110 -2 Electrical connection.
  • the gate of the third transistor T3 is electrically connected to the third gate line G3, and the first electrode of the third transistor T3 is electrically connected to the data line DA.
  • the third transistor T3 when the third gate line G3 is loaded with a gate-on signal, the third transistor T3 can be controlled to be turned on. When the third gate line G3 loads the gate-off signal, the third transistor T3 can be controlled to be turned off.
  • the gate-on signal when the third transistor T3 is an N-type transistor, the gate-on signal may be a high-level signal, and the gate-off signal may be a low-level signal.
  • the gate-on signal may be a low-level signal, and the gate-off signal may be a high-level signal.
  • the first transistor T1 and the third transistor T3 are both turned on, the data signal transmitted on the data line can be provided to the first reflective electrode 110-1.
  • the first transistor T1 and the third transistor T3 can be combined into a double-gate TFT, so that the on-state current of the TFT can be increased, the off-state current of the TFT can be reduced, and the power consumption can be reduced.
  • the second transistor T2 and the third transistor T3 are both turned on, the data signal transmitted on the data line can be provided to the second reflective electrode 110-2.
  • the second transistor T2 and the third transistor T3 can be combined into a double-gate TFT, so that the on-state current of the TFT can be increased, the off-state current of the TFT can be reduced, and the power consumption can be reduced.
  • the structure of the third transistor T3 can refer to the structure of the first transistor T1 described above, and will not be repeated here.
  • the orthographic projection of the third gate line G3 on the base substrate 100 is electrically connected to the third transistor T3, the first reflective electrode 110-1 and the second
  • the orthographic projection of the reflective electrode 110-2 on the base substrate 100 has an overlapping area, and the orthographic projection of the first through hole 111 and the second through hole 112 on the base substrate 100 is the same as the source conductive layer and gate conductive layer on the base substrate.
  • the orthographic projections of 100 also do not overlap. This can prevent the third gate line G3 and the third transistor T3 from blocking the first through hole 111 and the second through hole 112, and reduce the influence of the third gate line G3 and the third transistor T3 on the display effect.
  • the orthographic projections do not overlap. This can prevent the first transistor T1 and the third transistor T3 from blocking the first through hole 111, and reduce the influence of the first transistor T1 and the third transistor T3 on the display effect.
  • the orthographic projections do not overlap. In this way, the second transistor T2 and the third transistor T3 can be prevented from blocking the second through hole 112, and the influence of the second transistor T2 and the third transistor T3 on the display effect can be reduced.
  • the second through hole 112 includes the first sub-through hole 112-1 and the second sub-through hole 112-2
  • the second gate line G2 the third gate line G3, the first sub-via 112-1 and the second sub-via 112-2, the first sub-via 112-1 and the second sub-via that are electrically connected to the row sub-pixels
  • the orthographic projection of 112-2 on the base substrate 100 is located between the orthographic projections of the second grid line G2 and the third grid line G3 on the base substrate 100.
  • the orthographic projection on the base substrate 100 is close to the orthographic projection of the data line DA on the base substrate 100.
  • the orthographic projection of the first sub-through hole 112-1 on the base substrate 100 is closer to the data line DA than the orthographic projection of the second sub-through hole 112-2 on the base substrate 100.
  • the orthographic projection of the base substrate 100 is closer to the data line DA than the orthographic projection of the second sub-through hole 112-2 on the base substrate 100.
  • FIG. -1 The orthographic projection on the base substrate 100 is far away from the orthographic projection of the data line DA on the base substrate 100.
  • the orthographic projection of the second sub-through hole 112-2 on the base substrate 100 is farther away from the data line DA than the orthographic projection of the first sub-through hole 112-1 on the base substrate 100.
  • the orthographic projection of the base substrate 100 is far away from the orthographic projection of the data line DA on the base substrate 100.
  • the first sub-through hole 112-1 is arranged close to the data line DA electrically connected to the sub-pixel, and the second sub-through hole 112-2 is arranged away from the sub-pixel data line DA.
  • the first sub-through holes 112-1 and the second sub-through holes 112-2 in the second partition Q-2 can be dispersedly arranged, so that the first sub-through holes can be communicated according to the space in the second partition Q-2.
  • the hole 112-1 and the second sub-through hole 112-2 are flexibly arranged.
  • the orthographic projection of the third grid line G3 on the base substrate 100 is located at the orthographic projection of the first grid line G1 on the base substrate 100 and the orthographic projection of the second grid line G2 on the base substrate 100. Between the orthographic projection of the base substrate 100.
  • the source connection portion 1523 may include: a first sub-source connection portion 15231 and a second sub-source connection portion 15232 that are electrically connected to each other; wherein, the first sub-source connection portion 15231 is along the first direction F1 extends, and the second sub-source connecting portion 15232 extends along the second direction F2; and, the first sub-source connecting portion 15231 is electrically connected to the data line DA, and the second sub-source connecting portion 15232 is electrically connected to the third transistor T3.
  • the source connecting portion 1523 can be arranged in a broken line shape.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the first sub-via 112-1 on the base substrate 100 can be located at the orthographic projection of the first sub-source connection portion 15231 on the base substrate 100 and the data line DA in the liner. Between the orthographic projections of the base substrate 100, and the orthographic projection of the first sub-via 112-1 on the base substrate 100 is located between the orthographic projection of the second sub-source connection portion 15232 on the base substrate 100 and the third grid line G3 on the base substrate 100. Between the orthographic projection of the base substrate 100.
  • the embodiment of the present disclosure also provides a method for driving the above-mentioned display panel. While the gate-on signal is applied to the first gate line G1 electrically connected to the row of sub-pixels, it may also include: The third gate line G3 loads a gate turn-on signal. While applying the gate-on signal to the second gate line G2 electrically connected to the row sub-pixels, it may also include: applying the gate-on signal to the third gate line G3 electrically connected to the row sub-pixels.
  • the driving method of the above-mentioned display panel may include the following steps:
  • One frame of display time may include: a data input stage t1-y (1 ⁇ y ⁇ Y, and Y is the total number of first gate lines G1 in the display panel, y and Y are both integers) and a data input stage t2-y.
  • the first gate line G1 and the third gate line G3 electrically connected to the sub-pixels in the yth row input gate turn-on signals, respectively.
  • the second gate line G2 and the third gate line G3 electrically connected to the y-th row of sub-pixels input gate turn-on signals, respectively.
  • the following takes the first row of sub-pixels and the second row of sub-pixels as an example for description.
  • g1-1 is a signal input from the first gate line G1 electrically connected to the sub-pixels in the first row
  • g2-1 is a signal input from the second gate line G2 electrically connected to the sub-pixels in the first row
  • g3-1 is a signal input from the third gate line G3 electrically connected to the sub-pixels in the first row
  • g1-2 is a signal input from the first gate line G1 electrically connected to the second row of sub-pixels
  • g2-2 is a signal input from the second gate line G2 electrically connected to the second row of sub-pixels
  • g3-2 is a signal input from the third gate line G3 electrically connected to the sub-pixels in the first row.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the third gate line G3 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the third transistors T3 in the sub-pixels in the second row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned on.
  • the third gate line G3 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the third transistors T3 in the sub-pixels in the first row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first reflective electrode 110-1 in the first row of sub-pixels.
  • the first gate line G1 electrically connected to the first row of sub-pixels inputs a low-level signal to control the first transistors T1 in the first row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a low-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned off.
  • the third gate line G3 electrically connected to the sub-pixels in the second row inputs a low-level signal to control all the third transistors T3 in the sub-pixels in the second row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the first row to be turned on.
  • the third gate line G3 electrically connected to the sub-pixels in the first row inputs a high-level signal to control the third transistors T3 in the sub-pixels in the first row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the second reflective electrode 110-2 in the first row of sub-pixels.
  • the second gate line G2 electrically connected to the second row of sub-pixels inputs a low-level signal to control the second transistors T2 in the second row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the third gate line G3 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the third transistors T3 in the sub-pixels in the first row to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the first transistors T1 in the sub-pixels in the second row to be turned on.
  • the third gate line G3 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the third transistors T3 in the sub-pixels in the second row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the first reflective electrode 110-1 in the second row of sub-pixels.
  • the first gate line G1 electrically connected to the second row of sub-pixels inputs a low-level signal to control the first transistors T1 in the second row of sub-pixels to be turned off.
  • the first gate line G1 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the first transistors T1 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the second transistors T2 in the sub-pixels in the first row to be turned off.
  • the third gate line G3 electrically connected to the sub-pixels in the first row inputs a low-level signal to control all the third transistors T3 in the sub-pixels in the first row to be turned off.
  • the second gate line G2 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the second transistors T2 in the sub-pixels in the second row to be turned on.
  • the third gate line G3 electrically connected to the sub-pixels in the second row inputs a high-level signal to control the third transistors T3 in the sub-pixels in the second row to be turned on.
  • a data signal is applied to each data line DA, and a data signal is input to the second reflective electrode 110-2 in the second row of sub-pixels.
  • the embodiments of the present disclosure further provide some display panels, the structural diagram of which is shown in FIG. 13, which is modified with respect to the implementation of the foregoing embodiment.
  • FIG. 13 is modified with respect to the implementation of the foregoing embodiment.
  • the area of the first reflective electrode 110-1 can be made smaller than the area of the second reflective electrode 110-2, and the area of the first sub-color resistance region S-1 The area is approximately equal to the area of the second sub-color resistance region S-2.
  • the area of the first reflective electrode 110-1 is smaller than the area of the second reflective electrode 110-2, and the first sub-color resist region S- The area of 1 is approximately equal to the area of the second sub-color resistance region S-2.
  • each second color sub-pixel spx-2 the area of the first reflective electrode 110-1 is smaller than the area of the second reflective electrode 110-2, and the area of the first sub-color resistance region S-1 is substantially equal to the second sub-color resistance The area of area S-2.
  • the area of the first reflective electrode 110-1 is smaller than the area of the second reflective electrode 110-2, and the area of the first sub-color resistance region S-1 is substantially equal to the second sub-color resistance The area of area S-2.
  • the display panel when the display panel is in the reflective mode, since the area of the first reflective electrode 110-1 is smaller than the area of the second reflective electrode 110-2, the brightness of the first zone Q-1 can be made smaller than that of the second zone Q- 2 brightness, which can make the display panel achieve 64 gray scales.
  • the red sub-pixel is taken as an example for description.
  • the backlight source is turned off, and the reflective electrode reflects external ambient light to make the display panel display. If neither the first subarea Q-1 nor the second subarea Q-2 emit light within one frame of display time, then red is used as the first gray level H1. If only the first subarea Q-1 emits light within one frame of display time, then red is used as the second gray level H2.
  • red is used as the third gray level H3. If only the second subarea Q-2 emits light within one frame of display time, then red is used as the third gray level H3. If the first zone Q-1 and the second zone Q-2 both emit light within one frame of display time, then red is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4. That is, H1 may be the lowest gray level of red, and H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state. Similarly, in a pixel unit, the green part can also have 4 gray levels from the dark state to the bright state, and the blue part can also have 4 gray levels from the dark state to the bright state. In this way, a pixel unit can display 64 gray levels of colors.
  • the area of the first through hole 111 can be approximately the same as the area of the second through hole 112, so that the light passing through the first through hole 111 and the second through hole 112 can be made strong. same.
  • the area of the second through hole 112 may be Y times the area of the first through hole 111. In this way, the light intensity passing through the first through hole 111 can be made smaller than the light intensity passing through the second through hole 112.
  • the area of the first through hole 111 may be Y times the area of the second through hole 112. In this way, the light transmitted through the first through hole 111 can be stronger than the light transmitted through the second through hole 112.
  • the display panel when the display panel is in the transmissive mode, since the area of the first reflective electrode 110-1 and the area of the second reflective electrode 110-2 are different, the brightness of the first reflective area and the brightness of the second reflective area can be changed. Different, so that the display panel can achieve 64 gray scales.
  • the red sub-pixel is taken as an example for description.
  • the backlight source works, and the through holes pass through the light emitted by the backlight source to enable the display panel to display. If neither the first subarea Q-1 nor the second subarea Q-2 emit light within one frame of display time, then red is used as the first gray level H1.
  • red is used as the second gray level H2. If only the second subarea Q-2 emits light within one frame of display time, then red is used as the third gray level H3. If both the first sub-area Q-1 and the second sub-area Q-2 emit light within one frame of display time, then red is used as the fourth gray level H4. Among them, H1 ⁇ H2 ⁇ H3 ⁇ H4. That is, H1 may be the lowest gray level of red, and H4 may be the highest gray level of red. Therefore, in a pixel unit, the red part can have 4 gray levels from the dark state to the bright state.
  • the green part can also have 4 gray levels from the dark state to the bright state
  • the blue part can also have 4 gray levels from the dark state to the bright state.
  • a pixel unit can display 64 gray levels of colors.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display panel provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive points will not be repeated here.
  • the display device may further include a backlight source.
  • the backlight source may be located on the side of the base substrate away from the opposite substrate.
  • the backlight source may be a direct-type backlight source or an edge-type backlight source, and the specific setting method may be designed and determined according to the actual application environment, which is not limited herein.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the sub-pixels are provided with partitions, the partitions are provided with reflective electrodes, and the reflective electrodes are provided with penetrating through holes.
  • the display panel can be in the reflective mode, which can make the external ambient light reflect by the reflective electrode to provide a light source for the display panel so that the display panel can display images.
  • the backlight can be turned off to reduce power consumption.
  • the display panel can be in see-through mode.
  • the backlight source By making the backlight source work, the light emitted from the backlight source passes through the through holes in the reflective electrode to provide a light source for the display panel so that the display panel can display image. Therefore, the above-mentioned display panel provided by the embodiments of the present disclosure can realize a transflective display panel.

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Abstract

显示面板、其驱动方法及显示装置，其中，显示面板包括：衬底基板（100）；多个子像素，设置于衬底基板（100）上，多个子像素中的至少一个包括反射电极；其中，反射电极至少包括彼此绝缘间隔设置的第一反射电极（110-1）和第二反射电极（110-2），第一反射电极（110-1）设置有第一通孔（111），第二反射电极（110-2）设置有第二通孔（112），第一通孔（111）的面积与第二通孔（112）的面积不同。

Description

显示面板、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板、其驱动方法及显示装置。
背景技术
随着显示技术的不断发展，半透半反式显示面板因其具有功耗低、环境适应性强等优点，在手机、平板电脑等显示装置中得到了广泛应用。
发明内容
本公开实施例提供的显示面板，包括：衬底基板；
多个子像素，设置于所述衬底基板上，所述多个子像素中的至少一个包括反射电极；
其中，所述反射电极至少包括彼此绝缘间隔设置的第一反射电极和第二反射电极，所述第一反射电极设置有第一通孔，所述第二反射电极设置有第二通孔，所述第一通孔的面积与所述第二通孔的面积不同。
可选地，在本公开实施例中，所述衬底基板具有第一分区和第二分区，所述第一反射电极在所述衬底基板的正投影位于所述第一分区内，所述第二反射电极在所述衬底基板的正投影位于所述第二分区内；
所述显示面板还包括：
对向基板，与所述衬底基板相对设置；
色阻层，位于所述衬底基板与所述对向基板之间，并且，所述色阻层包括：位于各所述子像素的子色阻层；
其中，所述子色阻层具有第一子色阻区和第二子色阻区，在垂直于所述衬底基板所在平面的方向上，所述第一分区覆盖所述第一子色阻区，所述第二分区覆盖所述第二子色阻区。
可选地，在本公开实施例中，所述第一反射电极与位于所述第一子色阻 区的子色阻层具有第一正对面积；
所述第二反射电极与位于所述第二子色阻区的子色阻层具有第二正对面积；
同一所述子像素中，所述第一正对面积与所述第二正对面积不同。
可选地，在本公开实施例中，同一所述子像素中，所述第一反射电极的面积和所述第二反射电极的面积大致相同，且所述第一子色阻区的面积小于所述第二子色阻区的面积。
可选地，在本公开实施例中，位于所述第一分区内的所述子色阻层设置有第一过孔，所述第一过孔贯穿所述子色阻层；
所述第一过孔在所述衬底基板的正投影与所述第一通孔在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述多个子像素包括第一颜色子像素，第二颜色子像素和第三颜色子像素；
所述第二颜色子像素内的第一过孔的面积大于所述第一颜色子像素内的第一过孔的面积；和/或，
所述第一颜色子像素内的第一过孔的面积大于所述第三颜色子像素内的第一过孔的面积。
可选地，在本公开实施例中，所述第一颜色子像素具有相对的第一侧和第二侧；其中，所述第一侧和所述第二侧沿第一方向排列；所述第一颜色子像素内的第一过孔包括第一子过孔和第二子过孔；所述第一子过孔位于所述第一侧，所述第二子过孔位于所述第二侧；和/或，
所述第二颜色子像素具有相对的第三侧和第四侧；其中，所述第三侧和所述第四侧沿第一方向排列；所述第二颜色子像素内的第一过孔在所述衬底基板的正投影从所述第三侧延伸至所述第四侧；和/或，
所述第三颜色子像素具有相对的第五侧和第六侧；其中，所述第五侧和所述第六侧沿第一方向排列；所述第三颜色子像素内的第一过孔包括第三子过孔和第四子过孔；所述第三子过孔位于所述第五侧，所述第四子过孔位于 所述第六侧；和/或，
可选地，在本公开实施例中，所述第一子过孔的面积与所述第二子过孔的面积大致相同；和/或，
第三子过孔的面积与所述第四子过孔的面积大致相同。
可选地，在本公开实施例中，所述第一颜色子像素内的第一过孔的中心，所述第二颜色子像素内的第一过孔的中心，以及所述第三颜色子像素内的第一过孔的中心沿第一方向排列于同一直线上。
可选地，在本公开实施例中，同一所述子像素中，所述第一反射电极的面积小于所述第二反射电极的面积，且所述第一子色阻区的面积小于或大致等于所述第二子色阻区的面积。
可选地，在本公开实施例中，所述显示面板还包括：
第一平坦化层，位于所述反射电极所在层与所述衬底基板之间；
源导电层，位于所述第一平坦化层与所述衬底基板之间，且所述源导电层包括多条间隔设置的数据线；
栅绝缘层，位于所述源导电层与所述衬底基板之间；
栅导电层，位于所述栅绝缘层与所述衬底基板之间，且所述栅导电层包括间隔设置的多条第一栅线和多条第二栅线；
所述显示面板还包括：间隔设置的多个第一晶体管和多个第二晶体管；其中，一个所述第一晶体管在所述衬底基板的正投影位于一个所述第一分区内，一个所述第二晶体管在所述衬底基板的正投影位于一个所述第二分区内；
一行子像素中的第一晶体管的栅极电连接同一条所述第一栅线；
一行子像素中的第二晶体管的栅极电连接同一条所述第二栅线；
一列子像素中的第一晶体管的第一极和第二晶体管的第一极电连接同一条所述数据线；
同一所述第一分区内，所述第一晶体管的第二极与所述第一反射电极电连接；
同一所述第二分区内，所述第二晶体管的第二极与所述第二反射电极电 连接。
可选地，在本公开实施例中，所述第一通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠；
所述第二通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠。
可选地，在本公开实施例中，所述栅导电层还包括间隔设置的多条第三栅线；所述显示面板还包括：间隔设置的多个第三晶体管；其中，一个所述第三晶体管在所述衬底基板的正投影位于一个所述子像素内；
一行子像素中的第三晶体管的栅极电连接同一条所述第三栅线；
同一所述子像素中，所述第一晶体管和所述第二晶体管通过所述第三晶体管与所述源连接部电连接。
可选地，在本公开实施例中，所述源导电层还包括：多个源连接部；
所述源连接部包括：相互电连接的第一子源连接部和第二子源连接部；其中，所述第一子源连接部沿第一方向延伸，所述第二子源连接部沿第二方向延伸；并且，所述第一子源连接部与所述数据线电连接，所述第二子源连接部与所述第三晶体管电连接。
可选地，在本公开实施例中，所述第一子通孔在所述衬底基板的正投影位于所述第一子源连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影之间，且所述第一子通孔在所述衬底基板的正投影位于所述第二子源连接部在所述衬底基板的正投影与所述第三栅线在所述衬底基板的正投影之间。
可选地，在本公开实施例中，所述显示面板还包括：透明导电层，位于所述反射电极背离所述衬底基板一侧；
所述透明导电层包括间隔设置的多个第一子透明导电部；其中，一个所述第一子透明导电部在所述衬底基板的正投影位于一个所述第一分区内；
同一所述第一分区内，所述第一子透明导电部在所述衬底基板的正投影覆盖所述第一通孔在所述衬底基板的正投影，且所述第一子透明导电部在所 述衬底基板的正投影位于所述第一反射电极在所述衬底基板的正投影内。
可选地，在本公开实施例中，所述透明导电层包括间隔设置的多个第二子透明导电部；其中，一个所述第二子透明导电部在所述衬底基板的正投影位于一个所述第二分区内；
同一所述第二分区内，所述第二子透明导电部在所述衬底基板的正投影覆盖所述第二通孔在所述衬底基板的正投影，且所述第二子透明导电部在所述衬底基板的正投影位于所述第二反射电极在所述衬底基板的正投影内。
本公开实施例还提供了显示装置，包括上述显示面板。
本公开实施例还提供了显示面板的驱动方法，包括：
在一帧时间的各数据输入阶段中驱动一行子像素；
其中，在一个所述数据写入阶段中驱动一行子像素，包括：
对所述行子像素电连接的第一栅线加载栅极开启信号，对所述行子像素电连接的第二栅线加载栅极关闭信号，对各数据线加载数据信号，使所述行子像素中的第一反射电极输入数据信号；
对所述行子像素电连接的第一栅线加载栅极关闭信号，对所述行子像素电连接的第二栅线加载栅极开启信号，对各数据线加载数据信号，使所述行子像素中的第二反射电极输入数据信号。
可选地，在本公开实施例中，在所述对所述行子像素电连接的第一栅线加载栅极开启信号的同时，还包括：对所述行子像素电连接的第三栅线加载栅极开启信号；和/或，
在所述对所述行子像素电连接的第二栅线加载栅极开启信号的同时，还包括：对所述行子像素电连接的第三栅线加载栅极开启信号。
附图说明
图1为本公开实施例提供的显示面板的一些俯视结构示意图；
图2a为图1所示的显示面板沿AA’方向上的剖视结构示意图；
图2b为图1所示的显示面板沿BB’方向上的剖视结构示意图；
图2c为图1所示的显示面板沿CC’方向上的剖视结构示意图；
图3为本公开实施例提供的显示面板中的反射电极的一些俯视结构示意图；
图4为本公开实施例提供的显示面板中的反射电极的另一些俯视结构示意图；
图5a为本公开实施例提供的显示面板的子像素中的等效电路图；
图5b为本公开实施例提供的显示面板的子像素中的布局结构示意图；
图5c为图5b所示的显示面板的沿AA’方向上的剖视结构示意图；
图5d为图5b所示的显示面板的沿BB’方向上的剖视结构示意图；
图5e为图5b所示的显示面板的沿AA’方向上的另一些剖视结构示意图；
图5f为本公开实施例提供的显示面板的子像素中的另一些布局结构示意图；
图6为本公开实施例提供的显示面板中的子色阻层的一些俯视结构示意图；
图7为本公开实施例提供的显示面板中的子色阻层的又一些俯视结构示意图；
图8为本公开实施例提供的驱动方法的流程图；
图9为本公开实施例提供的信号时序图；
图10a为本公开实施例提供的显示面板的子像素中的又一些等效电路图；
图10b为本公开实施例提供的显示面板的子像素中的又一些布局结构示意图；
图10c为图10b所示的显示面板的沿AA’方向上的剖视结构示意图；
图11为本公开实施例提供的又一些驱动方法的流程图；
图12为本公开实施例提供的又一些信号时序图；
图13为本公开实施例提供的显示面板的又一些俯视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
一般半透半反式显示面板的显示区域可划分为反射区域和透射区域，在外部环境光较强时，外部环境光线通过反射区域的反射，为半透半反式显示面板提供光源，以使其显示图像。而在外部无光或弱光的环境下，半透半反式显示面板中的背光源工作，背光源的出射光线穿过透射区域，为半透半反式显示面板提供光源，以使其显示图像。
本公开实施例提供一种显示面板，如图1至图2c所示，可以包括：衬底基板100，设置于衬底基板100上的多个子像素。多个子像素中的至少一个可以包括反射电极；其中，其中，反射电极至少包括彼此绝缘间隔设置的第一反射电极110-1和第二反射电极110-2，第一反射电极110-1设置有第一通孔111，第二反射电极110-2设置有第二通孔112，第一通孔111的面积与第二通 孔112的面积不同。需要说明的是，通孔可以用于透射背光；反射电极可以用于反射入射到反射电极上的光。当然，通孔和反射电极还可以实现其他显示面板中的功能，在此不作限定。
本公开实施例提供的上述显示面板，通过在子像素中设置分区，分区中设置反射电极，反射电极中设置贯穿的通孔。在外部环境光较强时，显示面板可以处于反射模式，这样可以使外部环境光线通过反射电极的反射，为显示面板提供光源，以使显示面板显示图像，此时可以关闭背光源，降低功耗。而在外部无光或弱光的环境下，显示面板可以处于透视模式，通过使背光源工作，背光源的出射光线穿过反射电极中的通孔，为显示面板提供光源，以使显示面板显示图像。因此，本公开实施例提供的上述显示面板可以实现半透半反式显示面板。
在具体实施时，在本公开实施例中，如图1所示，显示面板可以包括多个像素单元PX。示例性地，本公开实施例中的像素单元指的可以是能独立显示一个像素点的子像素组合。
示例性地，像素单元PX可以包括多个子像素，各子像素阵列排布。其中，像素单元PX中的多个子像素可以包括沿第一方向F1依次排列的第一颜色子像素spx-1、第二颜色子像素spx-2以及第三颜色子像素spx-3。示例性地，第一颜色子像素spx-1、第二颜色子像素spx-2、第三颜色子像素spx-3可以从红色子像素、绿色子像素以及蓝色子像素中任意选取。例如，可以使第一颜色子像素spx-1设置为红色子像素，使第二颜色子像素spx-2设置为绿色子像素，使第三颜色子像素spx-3设置为蓝色子像素，这样可以采用红绿蓝进行混色以使显示面板实现显示效果。
当然，在实际应用中，可以根据实际应用环境来设计像素单元中子像素的具体实现方式，在此不作限定。下面以像素单元包括沿第一方向F1依次排列的红色子像素、绿色子像素以及蓝色子像素为例进行说明。
在具体实施时，可以使K＝2或K＝3或K＝4等。当然，在实际应用中，可以根据实际应用环境来设计K的具体实现方式，在此不作限定。
示例性地，在具体实施时，在本公开实施例中，如图1至图2c所示，衬底基板可以具有第一分区Q-1和第二分区Q-2，其中，一个第一反射电极110-1在衬底基板100的正投影位于一个第一分区Q-1内，即位于第一分区Q-1的反射电极可以作为第一反射电极110-1。一个第二反射电极110-2在衬底基板100的正投影位于一个第二分区Q-2内，即位于第二分区Q-2的反射电极可以作为第二反射电极110-2。第一反射电极110-1设置有第一通孔111，第二反射电极110-2设置有第二通孔112。并且，显示面板还可以包括：与衬底基板100相对设置的对向基板200，位于衬底基板100与对向基板200之间的色阻层。其中，色阻层可以包括：位于各子像素的子色阻层。其中，子色阻层可以具有第一子色阻区S-1和第二子色阻区S-2。在垂直于衬底基板100所在平面的方向上，第一分区Q-1覆盖第一子色阻区S-1，第二分区Q-2覆盖第二子色阻区S-2。这样可以使同一子像素实现多灰阶显示，从而可以提高显示效果。
在具体实施时，在本公开实施例中，如图1至图2c所示，显示面板还可以包括封装于衬底基板100和对向基板200之间的液晶层300。对向基板200上设置有公共电极，衬底基板100还设置有位于各分区中的薄膜晶体管(Thin Film Transistor，TFT)。并且，显示面板中还可以包括多条栅线和多条数据线DA，一行子像素同一分区中的TFT的栅极可以与一条栅线电连接，一列子像素中的TFT的源极可以与一条数据线DA电连接，TFT的漏极可以与反射电极电连接。示例性地，栅极上传输的信号控制TFT打开时，可以将数据线DA上传输的数据信号输入到反射电极中，以使反射电极输入用于显示的数据信号的电压。并且，还对公共电极施加相应的电压，从而可以使反射电极与公共电极之间具有电场，以控制液晶分子偏转，并且结合光源，以实现显示效果。
在具体实施时，在本公开实施例中，如图1至图2c所示，第一反射电极110-1与位于第一子色阻区S-1的子色阻层可以具有第一正对面积，第二反射电极110-2与位于第二子色阻区S-2的子色阻层可以具有第二正对面积。其中，同一子像素中，第一正对面积与第二正对面积不同。这样可以使同一子像素 中，第一正对面积所在区域的发光亮度和第二正对面积所在区域的发光亮度不同，从而可以使同一颜色子像素实现不同灰阶的亮度。需要说明的是，第一反射电极110-1在衬底基板100的正投影与位于第一子色阻区S-1的子色阻层在衬底基板100的正投影可以具有第一交叠区域，该第一交叠区域的面积可以作为第一正对面积。第二反射电极110-2在衬底基板100的正投影与位于第二子色阻区S-2的子色阻层在衬底基板100的正投影可以具有第二交叠区域，该第二交叠区域的面积可以作为第二正对面积。
示例性地，在具体实施时，在本公开实施例中，如图1至图2c所示，可以使同一子像素中，第一反射电极110-1的面积和第二反射电极110-2的面积大致相同，且第一子色阻区S-1的面积小于第二子色阻区S-2的面积。这样在显示面板处于反射模式时，由于第一子色阻区S-1的面积和第二子色阻区S-2的面积不同，可以使第一分区Q-1的亮度和第二分区Q-2的亮度不同，可以使同一颜色子像素实现4个灰阶的亮度。在显示面板处于透视模式时，由于第一子色阻区S-1的面积和第二子色阻区S-2的面积不同，可以使第一分区Q-1的亮度和第二分区Q-2的亮度不同，可以使同一颜色子像素实现4个灰阶的亮度。
示例性地，以红色子像素为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过反射外界环境光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
在具体实施时，在本公开实施例中，如图1至图2c以及图6所示，可以使位于第一分区Q-1内的子色阻层设置有第一过孔，第一过孔贯穿子色阻层，位于第二分区Q-2内的子色阻层未设置有第一过孔。并且，第一过孔在衬底基板100的正投影与第一通孔111在衬底基板100的正投影不交叠。示例性地，同一子像素中，可以使第一分区Q-1内的子色阻层的面积与第一过孔的面积之和与第二分区Q-2内的子色阻层的面积相同。这样通过设置第一过孔，从而可以使第一分区Q-1内的子色阻层所占用的面积小于第二分区Q-2内的子色阻层所占用的面积。
在具体实施时，在本公开实施例中，可以使同一子像素中，第一通孔的面积与第二通孔的面积不同。示例性地，如图1与图3所示，同一子像素中，可以使第二通孔112的面积设置为第一通孔111的面积的Y倍。其中，可以使1＜Y≤5。示例性地，可以使2≤Y≤3。例如，可以使Y＝2，同一子像素中，也可以使第二通孔112的面积设置为第一通孔111的面积的2倍，这样可以使第二分区Q-2的透射光的光强为第一分区Q-1的透射光的光强的2倍。也可以使Y＝3，同一子像素中，也可以使第二通孔112的面积设置为第一通孔111的面积的3倍，这样可以使第二分区Q-2的透射光的光强为第一分区Q-1的透射光的光强的3倍。示例性地，可以使每一子像素中，第一通孔111的面积大致相同。以及使每一子像素中，第二通孔112的面积大致相同。需要说明的是，在实际应用中，第二通孔112的面积与第一通孔111的面积以及Y的取值可以根据实际应用环境来设计确定，在此不作限定。
示例性地，以Y＝2为例，由于同一子像素中，第二通孔112的面积设置为第一通孔111的面积的2倍。在实际制备中，子像素所在区域可以根据沿第一方向F1延伸的中轴线大致镜像对称，为了使同一子像素中，第一反射电极110-1的面积与第二反射电极110-2的面积相同，可以使第一反射电极110-1沿第一方向F1的宽度和第二反射电极110-2沿第一方向F1的宽度大致相同，第二反射电极110-2沿第二方向F2的宽度大于第一反射电极110-1沿第二方向F2的宽度。以第一反射电极110-1和第一通孔111组成的区域的中心作为 第一中心，以第二反射电极110-2和第二通孔112组成的区域的中心作为第二中心，第一中心距离上述中轴线相较于第二中心更近，从而可以使同一子像素中，第一反射电极110-1的面积与第二反射电极110-2的面积相同。
在具体实施时，在本公开实施例中，如图4所示，同一子像素中，也可以使第一通孔111的面积设置为第二通孔112的面积的X倍；其中，可以使1＜X≤5。示例性地，可以使2≤X≤3。例如，可以使X＝2，同一子像素中，也可以使第一通孔111的面积设置为第二通孔112的面积的2倍，这样可以使第一分区Q-1的透射光的光强为第二分区Q-2的透射光的光强的2倍。或者，可以使X＝3，同一子像素中，也可以使第一通孔111的面积设置为第二通孔112的面积的3倍，这样可以使第一分区Q-1的透射光的光强为第二分区Q-2的透射光的光强的3倍。示例性地，可以使每一子像素中，第一通孔111的面积大致相同。以及使每一子像素中，第二通孔112的面积大致相同。需要说明的是，在实际应用中，第二通孔112的面积与第一通孔111的面积以及X的取值可以根据实际应用环境来设计确定，在此不作限定。
示例性地，以X＝2为例，由于同一子像素中，第一通孔111的面积设置为第二通孔112的面积的2倍。在实际制备中，子像素所在区域可以根据沿第一方向F1延伸的中轴线大致镜像对称，为了使同一子像素中，第一反射电极110-1的面积与第二反射电极110-2的面积相同，可以使第一反射电极110-1沿第一方向F1的宽度和第二反射电极110-2沿第一方向F1的宽度大致相同，第一反射电极110-1沿第二方向F2的宽度大于第二反射电极110-2沿第二方向F2的宽度。以第一反射电极110-1和第一通孔111组成的区域的中心作为第一中心，以第二反射电极110-2和第二通孔112组成的区域的中心作为第二中心，第二中心距离上述中轴线相较于第一中心更近，从而可以使同一子像素中，第一反射电极110-1的面积与第二反射电极110-2的面积相同。
示例性地，以红色子像素为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一 个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
由于第一通孔区域未设置第一反射电极，在具体实施时，如图5b至图5e所示，可以在反射电极背离衬底基板一侧设置透明导电层。该透明导电层可以包括间隔设置的多个第一子透明导电部310。其中，可以使一个第一子透明导电部310在衬底基板100的正投影位于一个第一分区内Q-1内，即一个第一分区Q-1设置一个第一子透明导电部310。一个第一通孔111对应一个第一子透明导电部310，且同一第一分区Q-1内，第一子透明导电部310在衬底基板100的正投影覆盖第一通孔111在衬底基板100的正投影。且，第一子透明导电部310在衬底基板100的正投影位于第一反射电极110-1在衬底基板100的正投影内。进一步地，第一子透明导电部310与第一反射电极110-1直接电连接。例如，直接将透明导电层制备在反射电极上。这样可以通过第一子透明导电部遮挡第一通孔，以及可以使第一通孔区域也存在电场，进而提高显示效果。
由于第二通孔区域未设置第二反射电极，在具体实施时，如图5b至图5e所示，可以在反射电极背离衬底基板一侧设置透明导电层。该透明导电层包括间隔设置的多个第二子透明导电部320。其中，一个第二子透明导电部320在衬底基板100的正投影位于一个第二分区Q-2内。即一个第二分区Q-2设置一个第二子透明导电部320。一个第二通孔112对应一个第二子透明导电部320，且同一第二分区Q-2内，第二子透明导电部320在衬底基板100的正投影覆盖第二通孔112在衬底基板100的正投影。且，第二子透明导电部320 在衬底基板100的正投影位于第二反射电极110-2在衬底基板100的正投影内。进一步地，第二子透明导电部320与第二反射电极110-2直接电连接。例如，直接将透明导电层制备在反射电极上。这样可以通过第二子透明导电部320遮挡第二通孔112，从而可以使第二通孔区域也存在电场，进而提高显示效果。
在具体实施时，在本公开实施例中，结合图5a至图5c所示，显示面板还可以包括：
第一平坦化层312，位于反射电极所在层与衬底基板100之间；
源导电层1300，位于第一平坦化层312与衬底基板100之间，且源导电层1300可以包括多条间隔设置的数据线DA；
栅绝缘层311，位于源导电层1300与衬底基板100之间；
栅导电层1200，位于栅绝缘层311与衬底基板100之间，且栅导电层1200可以包括间隔设置的多条第一栅线G1和多条第二栅线G2。并且，一行子像素电连接一条第一栅线G1和一条第二栅线G2，一列子像素电连接一条数据线DA。
在具体实施时，在本公开实施例中，结合图5a至图5c所示，显示面板还可以包括：间隔设置的多个第一晶体管T1和多个第二晶体管T2；其中，一个第一晶体管T1在衬底基板100的正投影位于一个第一分区Q-1内，一个第二晶体管T2在衬底基板100的正投影位于一个第二分区Q-2内。其中，一行子像素中的第一晶体管的栅极电连接同一条第一栅线，一行子像素中的第二晶体管的栅极电连接同一条第二栅线。一列子像素中的第一晶体管的第一极和第二晶体管的第一极电连接同一条数据线。同一第一分区内，第一晶体管的第二极与第一反射电极电连接。并且，同一第二分区内，第二晶体管的第二极与第二反射电极电连接。例如，第一晶体管T1的栅极与一条第一栅线G1电连接，第一晶体管T1的第一极与一条数据线DA电连接，第一晶体管T1的第二极与第一反射电极110-1电连接。第二晶体管T2的栅极与一条第二栅线G2电连接，第二晶体管T2的第一极与一条数据线DA电连接，第二晶体管T2的第二极与第二反射电极110-2电连接。
示例性地，如图5b与图5c所示，栅绝缘层311与源导电层1300之间还设置有半导体层。其中，半导体层可以包括形成每个晶体管的有源层。有源层具有沟道区。并且，栅导电层1200还可以包括形成每个晶体管的栅极。源导电层1300还可以包括：多个源连接部1523、多个第一源极部1323、多个第二源极部1423、多个第一漏极部1324、多个第二漏极部1424；其中，一个源连接部1523、一个第一源极部1323、一个第一漏极部1324、一个第二源极部以及一个第二漏极部1424位于一个子像素中。一个第一源极部1323作为一个第一晶体管T1的第一极，一个第一漏极部1324作为一个第一晶体管T1的第二极。一个第二源极部1423作为一个第二晶体管T2的第一极，一个第二漏极部1424作为一个第二晶体管T2的第二极。并且，同一子像素中，第一源极部1323和第二源极部1423通过源连接部1523电连接同一条数据线DA。当然，本公开包括但不限于此。
示例性地，结合图5c所示，以第一晶体管T1，第一极为源极，第二极为漏极为例，第一晶体管T1可以包括：栅极1321、与栅极1321绝缘设置的有源层1322、与栅极1321绝缘设置且与有源层1322电连接的第一源极部1323与第一漏极部1324，以及第一反射电极110-1和第二反射电极110-2。并且，栅极1321位于有源层1322与衬底基板100之间。第一源极部1323与第一漏极部1324所在层位于有源层1322背离衬底基板100一侧。在栅极1321和有源层1322之间设置有栅绝缘层311。第一源极部1323与第一漏极部1324分别与有源层1322直接搭接。第一源极部1323与第一漏极部1324所在层与第一反射电极110-1和第二反射电极110-2所在层之间设置有第一平坦化层312。第一反射电极110-1通过贯穿第一平坦化层312的过孔3121与第一漏极部1324电连接。第二晶体管T2的结构与第一晶体管T1的结构大致相同，并且，第二反射电极110-2通过贯穿第一平坦化层312的过孔3122与第二晶体管T2的第二极电连接，其余结构在此不做赘述。
在具体实施时，为了增加第一反射电极和第二反射电极的电容值。如图5e所示，可以在反射电极所在层和第一平坦化层312之间设置辅助电极层400， 以及在辅助电极层400与反射电极所在层之间设置第二平坦化层313。并且，第一反射电极110-1通过贯穿第一平坦化层312和第二平坦化层313的过孔3121与第一漏极部1324电连接。第二反射电极110-2通过贯穿第一平坦化层312和第二平坦化层313的过孔3122与第二晶体管T2的第二极电连接，其余结构在此不做赘述。
示例性地，如图5e所示，辅助电极层400可以包括间隔设置的多个第一辅助电极410。其中，一个第一辅助电极410在衬底基板100的正投影位于一个第一分区Q-1内，即第一分区Q-1设置一个第一辅助电极410，一个第一反射电极110-1对应一个第一辅助电极410，且同一第一分区Q-1内，第一反射电极110-1在衬底基板100的正投影覆盖第一辅助电极410在衬底基板100的正投影。这样可以使第一反射电极110-1与第一辅助电极410之间具有正对面积，以形成电容结构C11。
示例性地，如图5e所示，辅助电极层400可以包括间隔设置的多个第二辅助电极420。其中，一个第二辅助电极420在衬底基板100的正投影位于一个第二分区Q-2内，即一个第二分区Q-2设置一个第二辅助电极420，一个第一反射电极110-1对应一个第一辅助电极410。且同一第二分区Q-2内，第二反射电极110-2在衬底基板100的正投影覆盖第二辅助电极420在衬底基板100的正投影。这样可以使第二反射电极110-2与第二辅助电极420之间具有正对面积，以形成电容结构C12。
进一步地，为了增加第一反射电极和第二反射电极的电容值。如图5b与图5e所示，栅导电层还可以包括：间隔设置的多个第一补偿电极510；即可以在栅极1321所在层中设置相互间隔的多个第一补偿电极510；其中，一个第一补偿电极510在衬底基板100的正投影位于一个第一分区Q-1内，即一个第一反射电极110-1对应一个第一补偿电极510。并且，同一第一分区Q-1内，第一反射电极110-1在衬底基板100的正投影覆盖第一补偿电极510在衬底基板100的正投影，以及第一补偿电极510在衬底基板100的正投影与第一晶体管T1的第一漏极部1324在衬底基板100的正投影具有交叠区域。这 样可以使第一补偿电极510与第一晶体管T1的第一漏极部1324之间具有正对面积，以形成电容结构C21。
示例性地，如图5b与图5e所示，栅导电层1200还可以包括：间隔设置的多个第二补偿电极520。其中，一个第二补偿电极520在衬底基板100的正投影位于一个第二分区Q-2内。即，一个第二反射电极110-2对应一个第二辅助电极420。并且，同一第二分区Q-2内，第二反射电极110-2在衬底基板100的正投影覆盖第二补偿电极520在衬底基板100的正投影，以及第二补偿电极520在衬底基板100的正投影与第二晶体管T2的第二漏极部1424在衬底基板100的正投影具有交叠区域。这样可以使第二补偿电极520与第二晶体管T2的第二漏极部1424之间具有正对面积，以形成电容结构C22。
综上，可以使电容结构C11和C21形成并联关系，以提高第一反射电极的电容值。以及使电容结构C12和C22形成并联关系，以提高第二反射电极的电容值。并且，需要说明的是，可以使第一反射电极的电容值的总和与第二反射电极的电容值的总和大致相同。例如，可以使电容结构C11的电容值与电容结构C21的电容值大致相同，使电容结构C12的电容值与电容结构C22的电容值大致相同。当然，在实际应用中，可以根据实际应用环境来设计确定电容结构C11、C12、C21以及C22的具体结构形式，在此不作限定。
一般源导电层和栅导电层采用金属材料制备形成。而金属材料一般是不透光的，因此，为了避免源导电层和栅导电层遮挡第一通孔，在具体实施时，在本公开实施例中，结合图5b所示，可以使第一通孔在衬底基板的正投影分别与源导电层和栅导电层在衬底基板的正投影不交叠。这样可以避免源导电层和栅导电层遮挡第一通孔的光。
在具体实施时，在本公开实施例中，结合图5b所示，可以使第二通孔在衬底基板的正投影分别与源导电层和栅导电层在衬底基板的正投影不交叠。这样可以避免源导电层和栅导电层遮挡第二通孔的光。
在具体实施时，在本公开实施例中，结合图5b所示，针对与第一晶体管T1电连接的第一栅线G1和第一反射电极110-1，第一栅线G1和第一晶体管 T1在衬底基板100的正投影分别与第一反射电极110-1在衬底基板100的正投影具有交叠区域。例如，第一反射电极110-1在衬底基板100的正投影覆盖第一晶体管T1在衬底基板100的正投影，第一反射电极110-1在衬底基板100的正投影与第一栅线G1在衬底基板100的正投影具有交叠区域。由于第一栅线G1和第一晶体管T1所在膜层位于第一反射电极110-1和衬底基板100之间，并且，第一栅线G1在衬底基板100的正投影与第一反射电极110-1和第一晶体管T1在衬底基板100的正投影具有交叠区域，这样可以采用第一反射电极110-1将第一栅线G1和第一晶体管T1进行遮挡，提高第一反射电极110-1在子像素中的占用面积，从而可以提高像素开口率。
在具体实施时，在本公开实施例中，结合图5b所示，针对与第二晶体管T2电连接的第二栅线G2和第二反射电极110-2，第二栅线G2和第二晶体管T2在衬底基板100的正投影分别与第二反射电极110-2在衬底基板100的正投影具有交叠区域。例如，第二反射电极110-2在衬底基板100的正投影覆盖第二晶体管T2在衬底基板100的正投影，第二反射电极110-2在衬底基板100的正投影与第二栅线G2在衬底基板100的正投影具有交叠区域。由于第二栅线G2和第二晶体管T2所在膜层位于第二反射电极110-2和衬底基板100之间，并且，第二栅线G2在衬底基板100的正投影与第二反射电极110-2和第二晶体管T2在衬底基板100的正投影具有交叠区域，这样可以采用第二反射电极110-2将第二栅线G2和第二晶体管T2进行遮挡，提高第二反射电极110-2在子像素中的占用面积，从而可以提高像素开口率。
在具体实施时，在本公开实施例中，结合图5f所示，可以使源连接部1523沿第一方向F1延伸。并且，第一反射电极110-1可以设置有一个第一通孔111。第二反射电极110-2也可以设置有一个第二通孔112。例如，可以使源连接部1523在衬底基板的正投影与第一反射电极110-1和第二反射电极110-2在衬底基板100的正投影不交叠。这样可以减低源连接部1523的长度，从而降低信号延迟。
在具体实施时，在本公开实施例中，结合图5b所示，第一反射电极110-1 可以设置有一个第一通孔111。例如，第一通孔111的面积可以设置为208.377μm 2。示例性地，第一通孔111的形状可以设置为长方形，该长方形的长边沿第一方向F1延伸，该长方形的短边可以沿第二方向F2延伸，并且，其长边的宽度可以为短边的宽度的2～3倍。在实际应用中，可以根据实际应用的需求来设置第一通孔111的长边和短边的长度，在此不作限定。
在具体实施时，在本公开实施例中，结合图5b所示，可以使源连接部1523设置为曲线或折线的形式。第二通孔112可以包括间隔设置的第一子通孔112-1和第二子通孔112-2，即第二反射电极110-2可以设置有一个第一子通孔112-1和一个第二子通孔112-2，这样可以将第二通孔一分为二，从而可以分散设置在第二反射电极110-2中。示例性地，第一子通孔112-1和第二子通孔112-2的面积可以大致相同。例如，第一子通孔112-1的面积可以设置为4.008μm 2。示例性地，第一子通孔112-1的形状可以为长方形，该长方形的长边沿第二方向F2延伸，该长方形的短边可以沿第一方向F1延伸，并且，其长边的宽度可以为短边的宽度的1.5～2倍。第二子通孔112-2的形状可以为长方形，该长方形的长边沿第二方向F2延伸，该长方形的短边可以沿第一方向F1延伸。当然，在实际应用中，可以根据实际应用环境的需求来设计第一子通孔112-1和第二子通孔112-2的长边与短边，在此不作限定。
示例性地，结合图5b所示，针对一个子像素，第一子通孔112-1在衬底基板100的正投影相对第二子通孔112-2在衬底基板100的正投影靠近子像素电连接的数据线DA在衬底基板100的正投影。
示例性地，结合图5b所示，针对一个子像素，第二子通孔112-2在衬底基板100的正投影相对第一子通孔112-1在衬底基板100的正投影远离子像素电连接的数据线DA在衬底基板100的正投影。
进一步地，结合图5b所示，同一子像素中，第一子通孔112-1在衬底基板100的正投影位于源连接部1523在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影的一侧；第二源极部1423在衬底基板100的正投影位于源连接部1523在衬底基板100的正投影远离数据线DA在衬底基板100 的正投影的一侧；第二子通孔112-2在衬底基板100的正投影位于第二源极部1423在衬底基板100的正投影远离源连接部1523在衬底基板100的正投影的一侧。
示例性地，结合图5b所示，源连接部1523可以包括：相互电连接的第一子源连接部15231和第二子源连接部15232；其中，第一子源连接部15231沿第一方向F1延伸，第二子源连接部15232沿第二方向F2延伸；并且，第一子源连接部15231与数据线DA电连接，第二子源连接部15232分别与第一源极部1323和第二源极部1423电连接。这样可以使源连接部1523设置为折线形。当然，本公开包括但不限于此。
示例性地，结合图5b所示，可以使第一子通孔112-1在衬底基板100的正投影位于第一子源连接部15231在衬底基板100的正投影与数据线DA在衬底基板100的正投影之间，且第一子通孔112-1在衬底基板100的正投影位于第二子源连接部15232在衬底基板100的正投影与第一栅线G1在衬底基板100的正投影之间。
示例性地，如图1、图2a以及图6所示，第一颜色子像素spx-1(例如红色子像素)中，位于第一分区Q-1内的子色阻层设置有第一过孔121，第一过孔121贯穿子色阻层120-1。如图1、图2b以及图6所示，第二颜色子像素spx-2(例如绿色子像素)中，位于第一分区Q-1内的子色阻层设置有第一过孔122，第一过孔122贯穿子色阻层120-2。如图1、图2c以及图6所示，第三颜色子像素spx-3(例如蓝色子像素)中，位于第一分区Q-1内的子色阻层设置有第一过孔123，第一过孔123贯穿子色阻层120-3。
一般人眼对不同颜色的光的敏感度不同，例如，人眼对绿色的敏感度最高，对红色的敏感度次之，对蓝色的敏感度最低。若将不同颜色子像素中的第一过孔的面积设置为相同，那么在观看显示面板显示的画面时，人眼会觉得画面偏绿。为了提高显示效果，可以根据人眼对红色、绿色以及蓝色的敏感度来设计不同颜色子像素中第一过孔的大小。在具体实施时，如图1所示，可以使第二颜色子像素spx-2内的第一过孔122的面积大于第一颜色子像素 spx-1内的第一过孔121的面积，可以使第一颜色子像素spx-1内的第一过孔121的面积大于第三颜色子像素spx-3内的第一过孔123的面积。示例性地，可以使绿色子像素内的第一过孔的面积大于红色子像素内的第一过孔的面积，使红色子像素内的第一过孔的面积大于蓝色子像素内的第一过孔的面积。这样可以降低绿色子像素的绿光出射，从而可以改善画面偏绿的问题。
在具体实施时，在本公开实施例中，如图1与图6所示，第一颜色子像素spx-1可以具有相对的第一侧C1和第二侧C2；其中，第一侧C1和第二侧C2沿第一方向F1排列。第一颜色子像素spx-1内的第一过孔121可以包括第一子过孔121-1和第二子过孔121-2；第一子过孔121-1位于第一侧C1，第二子过孔121-2位于第二侧C2。这样可以将第一子过孔121-1和第二子过孔121-2分别设置于子色阻层的边缘。
在具体实施时，在本公开实施例中，如图1与图6所示，可以使第一子过孔121-1的面积与第二子过孔121-2的面积大致相同。这样可以统一制备第一子过孔121-1和第二子过孔121-2，降低工艺制备难度。示例性地，可以使第一子过孔121-1在衬底基板100的正投影与第二子过孔121-2在衬底基板100的正投影的形状大致相同，以及使第一子过孔121-1在衬底基板100的正投影与第二子过孔121-2在衬底基板100的正投影的面积大致相同。例如，可以使第一子过孔121-1与第二子过孔121-2的形状设置为长方形，该长方形的长边沿第二方向F2延伸，该长方形的短边沿第一方向F1延伸。且，该长方形的面积可以设置为200μm 2。示例性地，可以使该长方形的长边为短边的2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第一子过孔121-1和第二子过孔121-2的面积，在此不作限定。
在具体实施时，在本公开实施例中，如图1与图6所示，第二颜色子像素spx-2具有相对的第三侧C3和第四侧C4；其中，第三侧C3和第四侧C4沿第一方向F1排列。并且，第二颜色子像素spx-2内的第一过孔在衬底基板100的正投影从第三侧C3延伸至第四侧C4。示例性地，第二颜色子像素spx-2 中的第一过孔可以设置为长方形，该长方形的长边沿第一方向F1延伸，该长方形的短边沿第二方向F2延伸。且，该长方形的面积可以设置为812μm 2。示例性地，可以使该长方形的长边的宽度为短边的宽度2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第二颜色子像素spx-2内的第一过孔，在此不作限定。
在具体实施时，在本公开实施例中，如图1与图6所示，第三颜色子像素spx-3具有相对的第五侧C5和第六侧C6；其中，第五侧C5和第六侧C6沿第一方向F1排列。并且，第三颜色子像素spx-3内的第一过孔可以包括第三子过孔123-1和第四子过孔123-2；第三子过孔123-1位于第五侧C5，第四子过孔123-2位于第六侧C6。这样可以将第三子过孔123-1和第四子过孔123-2分别设置于子色阻层的边缘。
在具体实施时，在本公开实施例中，如图1与图6所示，可以使第三子过孔123-1的面积与第四子过孔123-2的面积大致相同。这样可以统一制备第三子过孔123-1和第四子过孔123-2，降低工艺制备难度。示例性地，可以使第三子过孔123-1在衬底基板100的正投影与第四子过孔123-2在衬底基板100的正投影的形状大致相同，以及使第三子过孔123-1在衬底基板100的正投影与第四子过孔123-2在衬底基板100的正投影的面积大致相同。例如，可以使第三子过孔123-1与第四子过孔123-2的形状设置为长方形，该长方形的长边沿第二方向F2延伸，该长方形的短边沿第一方向F1延伸。且，该长方形的面积可以设置为157μm 2。示例性地，长边的长度可以设置为短边的长度的2～3倍。当然，在实际应用中，不同应用环境的显示面板的需求不同，因此可以根据实际应用环境来设计第三子过孔123-1和第四子过孔123-2，在此不作限定。
在具体实施时，在本公开实施例中，如图6所示，可以使第一颜色子像素spx-1内的第一过孔的中心，第二颜色子像素spx-2内的第一过孔的中心，以及第三颜色子像素spx-3内的第一过孔的中心沿第一方向F1排列于同一直线L0上。这样可以降低这些第一过孔的设计难度。在实际应用中，可以使每 相邻两个子像素中的子色阻层具有交叠区域或毗邻。如图7所示，在每相邻两个子像素中的子色阻层毗邻时，在第一过孔为长方形时，第一颜色子像素spx-1内的第一子过孔121-1的长边可以与第三颜色子像素spx-3内的第四子过孔123-2的长边重合。第一颜色子像素spx-1内的第二子过孔121-2的长边可以与第二颜色子像素spx-2内的位于第三侧C3的第一过孔的短边重合。第一颜色子像素spx-1内的位于第四侧C4的第二子过孔121-2的短边可以与第三颜色子像素spx-3内的第三子过孔123-1的长边重合。
需要说明的是，第一方向F1可以为子像素的行方向，第二方向F2可以为子像素的列方向。或者，第一方向F1也可以为子像素的列方向，第二方向F2可以为子像素的行方向。在实际应用中，可以根据实际应用环境来设计确定，在此不作限定。
需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述各特征中的相同并不能完全相同，可能会有一些偏差，因此上述各特征之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
本公开实施例还提供了一种上述显示面板的驱动方法，可以包括：在一帧时间的各数据输入阶段中驱动一行子像素。其中，在一个数据写入阶段中驱动一行子像素，如图8所示，可以包括如下步骤：
S11、对该行子像素电连接的第一栅线G1加载栅极开启信号，对该行子像素电连接的第二栅线G2加载栅极关闭信号，对各数据线DA加载数据信号，使该行子像素中的第一反射电极110-1输入数据信号；
S12、对该行子像素电连接的第一栅线G1加载栅极关闭信号，对该行子像素电连接的第二栅线G2加载栅极开启信号，对各数据线DA加载数据信号，使该行子像素中的第二反射电极110-2输入数据信号。
需要说明的是，在第一栅线G1加载栅极开启信号时，可以控制第一晶体管T1导通。在第一栅线G1加载栅极关闭信号时，可以控制第一晶体管T1截止。其中，在第一晶体管T1为N型晶体管时，栅极开启信号可以为高电平 信号，栅极关闭信号可以为低电平信号。在第一晶体管T1为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
需要说明的是，在第二栅线G2加载栅极开启信号时，可以控制第二晶体管T2导通。在第二栅线G2加载栅极关闭信号时，可以控制第二晶体管T2截止。其中，在第二晶体管T2为N型晶体管时，栅极开启信号可以为高电平信号，栅极关闭信号可以为低电平信号。在第二晶体管T2为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
下面以图5b所示的第一反射电极110-1和第二反射电极110-2的结构为例，结合图1和图9对本公开实施例提供的上述显示面板的工作过程进行说明。
一帧显示时间可以包括：数据输入阶段t1-y(1≤y≤Y，且Y为显示面板中第一栅线G1的总数，y和Y均为整数)和数据输入阶段t2-y。其中，在数据输入阶段t1-y中，第y行子像素电连接的第一栅线G1输入栅极开启信号。在数据输入阶段t2-y中，第y行子像素电连接的第二栅线G2输入栅极开启信号。下面以第一行子像素和第二行子像素为例进行说明。
g1-1为第1行子像素电连接的第一栅线G1输入的信号，g2-1为第1行子像素电连接的第二栅线G2输入的信号。g1-2为第2行子像素电连接的第一栅线G1输入的信号，g2-2为第2行子像素电连接的第二栅线G2输入的信号。
在数据输入阶段t1-1中，第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第2行子像素电连接的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第1行子像素电连接的第一栅线G1输入高电平信号，以控制第1行子像素中的第一晶体管T1均导通。并且，对各数据线DA加载数据信号，使第1行子像素中的第一反射电极110-1输入数据信号。
在数据输入阶段t2-1中，第1行子像素电连接的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第2行子像素电连接 的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第1行子像素电连接的第二栅线G2输入高电平信号，以控制第1行子像素中的第二晶体管T2均导通。并且，对各数据线DA加载数据信号，使第1行子像素中的第二反射电极110-2输入数据信号。
在数据输入阶段t1-2中，第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第1行子像素电连接的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第2行子像素电连接的第一栅线G1输入高电平信号，以控制第2行子像素中的第一晶体管T1均导通。并且，对各数据线DA加载数据信号，使第2行子像素中的第一反射电极110-1输入数据信号。
在数据输入阶段t2-2中，第2行子像素电连接的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第1行子像素电连接的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第2行子像素电连接的第二栅线G2输入高电平信号，以控制第2行子像素中的第二晶体管T2均导通。并且，对各数据线DA加载数据信号，使第2行子像素中的第二反射电极110-2输入数据信号。
其余过程依次类推，在此不作赘述。
示例性地，以红色子像素为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过反射外界环境光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2中的反射电极输入的数据信号不能控制液晶分子翻转，则第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制液晶分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号不能控制驱动分子翻转，则第一分区Q-1中的第一反射 电极110-1可以将入射的光反射出去，从而使得仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号不能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号能控制驱动分子翻转，则第二分区Q-2中的第二反射电极110-2可以将入射的光反射出去，从而使得仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号也能控制驱动分子翻转，则第一分区Q-1中的第一反射电极110-1可以将入射的光反射出去，并且，第二分区Q-2中的第二反射电极110-2也可以将入射的光反射出去，从而使得第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
示例性地，以红色子像素为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2中的反射电极输入的数据信号不能控制液晶分子翻转，则第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号不能控制驱动分子翻转，则背光源的光可以穿过第一通孔111并通过第一分区Q-1发射出去，从而使得仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号不能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号能控制驱动分子翻转，则背光源的光可以穿过第二通孔112并通过第二分区Q-2发射出去，从而使得仅第二分区Q-2发光，那 么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1中的第一反射电极110-1输入的数据信号能控制驱动分子翻转，第二分区Q-2中的第二反射电极110-2输入的数据信号也能控制驱动分子翻转，则背光源的光可以穿过第一通孔111并通过第一分区Q-1发射出去，以及背光源的光可以穿过第二通孔112并通过第二分区Q-2发射出去，从而使第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
本公开实施例还提供了一些显示面板，其结构示意图如图10a至图10c所示，其针对上述实施例的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，结合图10a与图10b所示，栅导电层还包括间隔设置的多条第三栅线G3；显示面板还可以包括：间隔设置的多个第三晶体管T3；其中，一个第三晶体管T3在衬底基板100的正投影位于一个子像素内；其中，一行子像素中的第三晶体管T3的栅极电连接同一条第三栅线G3。并且，同一子像素中，第一源极部1323和第二源极部1423通过第三晶体管T3与源连接部1523电连接。
示例性地，一个第一分区Q-1还可以设置第一晶体管T1，一个第二分区Q-2还可以设置第二晶体管T2。一个子像素还包括第三晶体管T3。即一个第一分区Q-1和一个第二分区Q-2共用一个第三晶体管T3。并且，一行子像素电连接一条第一栅线G1、一条第二栅线G2以及一条第三栅线G3，一列子像素电连接一条数据线DA。
具体地，结合图10a至图10c所示，同一子像素中，第一晶体管T1和第二晶体管T2通过第三晶体管T3与数据线DA电连接。例如，每一个子像素中可以包括第一晶体管T1、第二晶体管T2以及第三晶体管T3。
其中，第一晶体管T1的栅极与第一栅线G1电连接，第一晶体管T1的第一极与第三晶体管T3的第二极电连接，第一晶体管T1的第二极与第一反射电极110-1电连接。
第二晶体管T2的栅极与第二栅线G2电连接，第二晶体管T2的第一极与第三晶体管T3的第二极电连接，第二晶体管T2的第二极与第二反射电极110-2电连接。
第三晶体管T3的栅极与第三栅线G3电连接，第三晶体管T3的第一极与数据线DA电连接。
需要说明的是，在第三栅线G3加载栅极开启信号时，可以控制第三晶体管T3导通。在第三栅线G3加载栅极关闭信号时，可以控制第三晶体管T3截止。其中，在第三晶体管T3为N型晶体管时，栅极开启信号可以为高电平信号，栅极关闭信号可以为低电平信号。在第三晶体管T3为P型晶体管时，栅极开启信号可以为低电平信号，栅极关闭信号可以为高电平信号。
需要说明的是，在第一晶体管T1和第三晶体管T3均导通时，可以将数据线上传输的数据信号提供给第一反射电极110-1。这样可以使第一晶体管T1和第三晶体管T3组合为双栅TFT，从而可以增大TFT的开态电流，降低TFT的关态电流，以及降低功耗。
需要说明的是，在第二晶体管T2和第三晶体管T3均导通时，可以将数据线上传输的数据信号提供给第二反射电极110-2。这样可以使第二晶体管T2和第三晶体管T3组合为双栅TFT，从而可以增大TFT的开态电流，降低TFT的关态电流，以及降低功耗。
需要说明的是，第三晶体管T3的结构可以参照上述第一晶体管T1的结构，在此不作赘述。
在具体实施时，在本公开实施例中，结合图10b所示，第三栅线G3在衬底基板100的正投影与电连接的第三晶体管T3、第一反射电极110-1和第二反射电极110-2在衬底基板100的正投影具有交叠区域，且第一通孔111和第二通孔112在衬底基板100的正投影与源导电层和栅导电层在衬底基板100 的正投影也不交叠。这样可以避免第三栅线G3和第三晶体管T3遮挡第一通孔111和第二通孔112，降低第三栅线G3和第三晶体管T3对显示效果的影响。
进一步地，在具体实施时，在本公开实施例中，结合图10b所示，第一通孔111在衬底基板100的正投影与第一晶体管T1和第三晶体管T3在衬底基板100的正投影不交叠。这样可以避免第一晶体管T1和第三晶体管T3遮挡第一通孔111，降低第一晶体管T1和第三晶体管T3对显示效果的影响。
进一步地，在具体实施时，在本公开实施例中，结合图10b所示，第二通孔112在衬底基板100的正投影与第二晶体管T2和第三晶体管T3在衬底基板100的正投影不交叠。这样可以避免第二晶体管T2和第三晶体管T3遮挡第二通孔112，降低第二晶体管T2和第三晶体管T3对显示效果的影响。
示例性地，在第二通孔112包括第一子通孔112-1和第二子通孔112-2时，在具体实施时，在本公开实施例中，结合图10b所示，针对同一行子像素电连接的第二栅线G2、第三栅线G3以及第一子通孔112-1和第二子通孔112-2，第一子通孔112-1和第二子通孔112-2在衬底基板100的正投影位于第二栅线G2和第三栅线G3在衬底基板100的正投影之间。
示例性地，在具体实施时，在本公开实施例中，结合图10b所示，针对一个子像素，第一子通孔112-1在衬底基板100的正投影相对第二子通孔112-2在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影。示例性地，可以使每一个子像素中，第一子通孔112-1在衬底基板100的正投影相对第二子通孔112-2在衬底基板100的正投影靠近数据线DA在衬底基板100的正投影。
示例性地，在具体实施时，在本公开实施例中，结合图10b所示，针对一个子像素，第二子通孔112-2在衬底基板100的正投影相对第一子通孔112-1在衬底基板100的正投影远离数据线DA在衬底基板100的正投影。示例性地，可以使每一个子像素中，第二子通孔112-2在衬底基板100的正投影相对第一子通孔112-1在衬底基板100的正投影远离数据线DA在衬底基板100的 正投影。
需要说明的是，针对一个子像素，通过将第一子通孔112-1靠近该子像素电连接的数据线DA设置，并将第二子通孔112-2远离该子像素数据线DA设置，这样可以将第二分区Q-2中的第一子通孔112-1和第二子通孔112-2进行分散设置，从而可以根据第二分区Q-2内的空间对第一子通孔112-1和第二子通孔112-2进行灵活设置。
示例性地，结合图10b所示，同一行子像素中，第三栅线G3在衬底基板100的正投影位于第一栅线G1在衬底基板100的正投影和第二栅线G2在衬底基板100的正投影之间。
示例性地，结合图10b所示，源连接部1523可以包括：相互电连接的第一子源连接部15231和第二子源连接部15232；其中，第一子源连接部15231沿第一方向F1延伸，第二子源连接部15232沿第二方向F2延伸；并且，第一子源连接部15231与数据线DA电连接，第二子源连接部15232与第三晶体管T3电连接。这样可以使源连接部1523设置为折线形。当然，本公开包括但不限于此。
示例性地，结合图10b所示，可以使第一子通孔112-1在衬底基板100的正投影位于第一子源连接部15231在衬底基板100的正投影与数据线DA在衬底基板100的正投影之间，且第一子通孔112-1在衬底基板100的正投影位于第二子源连接部15232在衬底基板100的正投影与第三栅线G3在衬底基板100的正投影之间。
本公开实施例还提供了一种上述显示面板的驱动方法，在对该行子像素电连接的第一栅线G1加载栅极开启信号的同时，还可以包括：对该行子像素电连接的第三栅线G3加载栅极开启信号。在对行子像素电连接的第二栅线G2加载栅极开启信号的同时，还可以包括：对行子像素电连接的第三栅线G3加载栅极开启信号。
如图11所示，本公开实施例提供的上述显示面板的驱动方法，可以包括如下步骤：
S21、对该行子像素电连接的第一栅线G1加载栅极开启信号，对该行子像素电连接的第二栅线G2加载栅极关闭信号，对该行子像素电连接的第三栅线G3加载栅极开启信号，对各数据线DA加载数据信号，使该行子像素中的第一反射电极110-1输入数据信号；
S22、对该行子像素电连接的第一栅线G1加载栅极关闭信号，对该行子像素电连接的第二栅线G2加载栅极开启信号，对该行子像素电连接的第三栅线G3加载栅极开启信号，对各数据线DA加载数据信号，使该行子像素中的第二反射电极110-2输入数据信号。
下面以图5b所示的第一反射电极110-1和第二反射电极110-2的结构为例，结合图1和图12对本公开实施例提供的上述显示面板的工作过程进行说明。
一帧显示时间可以包括：数据输入阶段t1-y(1≤y≤Y，且Y为显示面板中第一栅线G1的总数，y和Y均为整数)和数据输入阶段t2-y。其中，在数据输入阶段t1-y中，第y行子像素电连接的第一栅线G1和第三栅线G3分别输入栅极开启信号。在数据输入阶段t2-y中，第y行子像素电连接的第二栅线G2和第三栅线G3分别输入栅极开启信号。下面以第一行子像素和第二行子像素为例进行说明。
g1-1为第1行子像素电连接的第一栅线G1输入的信号，g2-1为第1行子像素电连接的第二栅线G2输入的信号。g3-1为第1行子像素电连接的第三栅线G3输入的信号。g1-2为第2行子像素电连接的第一栅线G1输入的信号，g2-2为第2行子像素电连接的第二栅线G2输入的信号。g3-2为第1行子像素电连接的第三栅线G3输入的信号。
在数据输入阶段t1-1中，第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第2行子像素电连接的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第2行子像素电连接的第三栅线G3输入低 电平信号，以控制第2行子像素中的第三晶体管T3均截止。第1行子像素电连接的第一栅线G1输入高电平信号，以控制第1行子像素中的第一晶体管T1均导通。第1行子像素电连接的第三栅线G3输入高电平信号，以控制第1行子像素中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第1行子像素中的第一反射电极110-1输入数据信号。
在数据输入阶段t2-1中，第1行子像素电连接的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第2行子像素电连接的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第2行子像素电连接的第三栅线G3输入低电平信号，以控制第2行子像素中的第三晶体管T3均截止。第1行子像素电连接的第二栅线G2输入高电平信号，以控制第1行子像素中的第二晶体管T2均导通。第1行子像素电连接的第三栅线G3输入高电平信号，以控制第1行子像素中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第1行子像素中的第二反射电极110-2输入数据信号。
在数据输入阶段t1-2中，第2行子像素电连接的第二栅线G2输入低电平信号，以控制第2行子像素中的第二晶体管T2均截止。第1行子像素电连接的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第1行子像素电连接的第三栅线G3输入低电平信号，以控制第1行子像素中的第三晶体管T3均截止。第2行子像素电连接的第一栅线G1输入高电平信号，以控制第2行子像素中的第一晶体管T1均导通。第2行子像素电连接的第三栅线G3输入高电平信号，以控制第2行子像素中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第2行子像素中的第一反射电极110-1输入数据信号。
在数据输入阶段t2-2中，第2行子像素电连接的第一栅线G1输入低电平信号，以控制第2行子像素中的第一晶体管T1均截止。第1行子像素电连接 的第一栅线G1输入低电平信号，以控制第1行子像素中的第一晶体管T1均截止。第1行子像素电连接的第二栅线G2输入低电平信号，以控制第1行子像素中的第二晶体管T2均截止。第1行子像素电连接的第三栅线G3输入低电平信号，以控制第1行子像素中的第三晶体管T3均截止。第2行子像素电连接的第二栅线G2输入高电平信号，以控制第2行子像素中的第二晶体管T2均导通。第2行子像素电连接的第三栅线G3输入高电平信号，以控制第2行子像素中的第三晶体管T3均导通。并且，对各数据线DA加载数据信号，使第2行子像素中的第二反射电极110-2输入数据信号。
其余过程依次类推，在此不作赘述。
需要说明的是，本公开实施例提供的上述显示面板可以实现64灰阶的原理与上述实施例基本相同，在此不作赘述。
本公开实施例又提供了一些显示面板，其结构示意图如图13所示，其针对上述实施例的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，同一子像素中，可以使第一反射电极110-1的面积小于第二反射电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。示例性地，如图13所示，各第一颜色子像素spx-1中，第一反射电极110-1的面积小于第二反射电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。各第二颜色子像素spx-2中，第一反射电极110-1的面积小于第二反射电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。各第三颜色子像素spx-3中，第一反射电极110-1的面积小于第二反射电极110-2的面积，且第一子色阻区S-1的面积大致等于第二子色阻区S-2的面积。
需要说明的是，在显示面板处于反射模式时，由于第一反射电极110-1的面积小于第二反射电极110-2的面积，可以使第一分区Q-1的亮度小于第二分区Q-2的亮度，从而可以使显示面板实现64灰阶。示例性地，以红色子像素为例进行说明。在显示面板处于反射模式时，背光源关闭，反射电极通过 反射外界环境光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
在具体实施时，同一子像素中，可以使第一通孔111的面积与第二通孔112的面积大致相同，这样可以使透过第一通孔111和第二通孔112的光强大致相同。
在具体实施时，同一子像素中，也可以使第二通孔112的面积为第一通孔111的面积的Y倍。这样可以使透过第一通孔111的光强小于透过第二通孔112的光强。
在具体实施时，同一子像素中，也可以使第一通孔111的面积为第二通孔112的面积的Y倍。这样可以使透过第一通孔111的光强大于透过第二通孔112的光强。
需要说明的是，在显示面板处于透射模式时，由于第一反射电极110-1的面积和第二反射电极110-2的面积不同，可以使第一反射区的亮度和第二反射区的亮度不同，从而可以使显示面板实现64灰阶。示例性地，以红色子像素为例进行说明。在显示面板处于透射模式时，背光源工作，通孔通过透射背光源发出的光，以使显示面板进行显示。若一帧显示时间内，第一分区Q-1和第二分区Q-2均不发光，那么红色作为第一个灰阶H1。若一帧显示时间内，仅第一分区Q-1发光，那么红色作为第二个灰阶H2。若一帧显示时间内，仅第二分区Q-2发光，那么红色作为第三灰阶H3。若一帧显示时间内，第一分 区Q-1和第二分区Q-2均发光，那么红色作为第四灰阶H4。其中，H1<H2<H3<H4。即，H1可以为红色的最低灰阶，H4可以为红色的最高灰阶。因此，一个像素单元中，红色部分从暗态到亮态可以为4个灰阶。同理，一个像素单元中，绿色部分从暗态到亮态也可以为4个灰阶，蓝色部分从暗态到亮态也可以为4个灰阶。这样使得一个像素单元可以显示的颜色的64个灰阶。
需要说明的是，本实施例中的显示面板的工作过程可以参照上述实施例中显示面板的工作过程，具体在此不作赘述。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置还可以包括背光源。该背光源可以位于衬底基板背离对向基板的一侧。其中，背光源可以为直下式背光源或侧入式背光源，其具体设置方式可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的上述显示面板、其驱动方法及显示装置，通过在子像素中设置分区，分区中设置反射电极，反射电极中设置贯穿的通孔。在外部环境光较强时，显示面板可以处于反射模式，这样可以使外部环境光线通过反射电极的反射，为显示面板提供光源，以使显示面板显示图像，此时可以关闭背光源，降低功耗。而在外部无光或弱光的环境下，显示面板可以处于透视模式，通过使背光源工作，背光源的出射光线穿过反射电极中的通孔，为显示面板提供光源，以使显示面板显示图像。因此，本公开实施例提供的 上述显示面板可以实现半透半反式显示面板。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底基板；
    多个子像素，设置于所述衬底基板上，所述多个子像素中的至少一个包括反射电极；
    其中，所述反射电极至少包括彼此绝缘间隔设置的第一反射电极和第二反射电极，所述第一反射电极设置有第一通孔，所述第二反射电极设置有第二通孔，所述第一通孔的面积与所述第二通孔的面积不同。
  2. 如权利要求1所述的显示面板，其中，所述衬底基板具有第一分区和第二分区，所述第一反射电极在所述衬底基板的正投影位于所述第一分区内，所述第二反射电极在所述衬底基板的正投影位于所述第二分区内；
    所述显示面板还包括：
    对向基板，与所述衬底基板相对设置；
    色阻层，位于所述衬底基板与所述对向基板之间，并且，所述色阻层包括：位于各所述子像素的子色阻层；
    其中，所述子色阻层具有第一子色阻区和第二子色阻区，在垂直于所述衬底基板所在平面的方向上，所述第一分区覆盖所述第一子色阻区，所述第二分区覆盖所述第二子色阻区。
  3. 如权利要求2所述的显示面板，其中，所述第一反射电极与位于所述第一子色阻区的子色阻层具有第一正对面积；
    所述第二反射电极与位于所述第二子色阻区的子色阻层具有第二正对面积；
    同一所述子像素中，所述第一正对面积与所述第二正对面积不同。
  4. 如权利要求3所述的显示面板，其中，同一所述子像素中，所述第一反射电极的面积和所述第二反射电极的面积大致相同，且所述第一子色阻区的面积小于所述第二子色阻区的面积。
  5. 如权利要求4所述的显示面板，其中，位于所述第一分区内的所述子色阻层设置有第一过孔，所述第一过孔贯穿所述子色阻层；
    所述第一过孔在所述衬底基板的正投影与所述第一通孔在所述衬底基板的正投影不交叠。
  6. 如权利要求5所述的显示面板，其中，所述多个子像素包括第一颜色子像素，第二颜色子像素和第三颜色子像素；
    所述第二颜色子像素内的第一过孔的面积大于所述第一颜色子像素内的第一过孔的面积；和/或，
    所述第一颜色子像素内的第一过孔的面积大于所述第三颜色子像素内的第一过孔的面积。
  7. 如权利要求6所述的显示面板，其中，所述第一颜色子像素具有相对的第一侧和第二侧；其中，所述第一侧和所述第二侧沿第一方向排列；所述第一颜色子像素内的第一过孔包括第一子过孔和第二子过孔；所述第一子过孔位于所述第一侧，所述第二子过孔位于所述第二侧；和/或，
    所述第二颜色子像素具有相对的第三侧和第四侧；其中，所述第三侧和所述第四侧沿第一方向排列；所述第二颜色子像素内的第一过孔在所述衬底基板的正投影从所述第三侧延伸至所述第四侧；和/或，
    所述第三颜色子像素具有相对的第五侧和第六侧；其中，所述第五侧和所述第六侧沿第一方向排列；所述第三颜色子像素内的第一过孔包括第三子过孔和第四子过孔；所述第三子过孔位于所述第五侧，所述第四子过孔位于所述第六侧。
  8. 如权利要求7所述的显示面板，其中，所述第一子过孔的面积与所述第二子过孔的面积大致相同；和/或，
    第三子过孔的面积与所述第四子过孔的面积大致相同。
  9. 如权利要求7或8所述的显示面板，其中，所述第一颜色子像素内的第一过孔的中心，所述第二颜色子像素内的第一过孔的中心，以及所述第三颜色子像素内的第一过孔的中心沿第一方向排列于同一直线上。
  10. 如权利要求3所述的显示面板，其中，同一所述子像素中，所述第一反射电极的面积小于所述第二反射电极的面积，且所述第一子色阻区的面积小于或大致等于所述第二子色阻区的面积。
  11. 如权利要求2-10任一项所述的显示面板，其中，所述显示面板还包括：
    第一平坦化层，位于所述反射电极所在层与所述衬底基板之间；
    源导电层，位于所述第一平坦化层与所述衬底基板之间，且所述源导电层包括多条间隔设置的数据线；
    栅绝缘层，位于所述源导电层与所述衬底基板之间；
    栅导电层，位于所述栅绝缘层与所述衬底基板之间，且所述栅导电层包括间隔设置的多条第一栅线和多条第二栅线；
    所述显示面板还包括：间隔设置的多个第一晶体管和多个第二晶体管；其中，一个所述第一晶体管在所述衬底基板的正投影位于一个所述第一分区内，一个所述第二晶体管在所述衬底基板的正投影位于一个所述第二分区内，
    一行子像素中的第一晶体管的栅极电连接同一条所述第一栅线；
    一行子像素中的第二晶体管的栅极电连接同一条所述第二栅线；
    一列子像素中的第一晶体管的第一极和第二晶体管的第一极电连接同一条所述数据线；
    同一所述第一分区内，所述第一晶体管的第二极与所述第一反射电极电连接；
    同一所述第二分区内，所述第二晶体管的第二极与所述第二反射电极电连接。
  12. 如权利要求11所述的显示面板，其中，所述第一通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠；
    所述第二通孔在所述衬底基板的正投影分别与所述源导电层和所述栅导电层在所述衬底基板的正投影不交叠。
  13. 如权利要求11或12所述的显示面板，其中，所述栅导电层还包括间隔设置的多条第三栅线；所述显示面板还包括：间隔设置的多个第三晶体管；其中，一个所述第三晶体管在所述衬底基板的正投影位于一个所述子像素内；
    一行子像素中的第三晶体管的栅极电连接同一条所述第三栅线；
    同一所述子像素中，所述第一晶体管和所述第二晶体管通过所述第三晶体管与所述源连接部电连接。
  14. 如权利要求13所述的显示面板，其中，所述源导电层还包括：多个源连接部；
    所述源连接部包括：相互电连接的第一子源连接部和第二子源连接部；其中，所述第一子源连接部沿第一方向延伸，所述第二子源连接部沿第二方向延伸；并且，所述第一子源连接部与所述数据线电连接，所述第二子源连接部与所述第三晶体管电连接。
  15. 如权利要求14所述的显示面板，其中，所述第一子通孔在所述衬底基板的正投影位于所述第一子源连接部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影之间，且所述第一子通孔在所述衬底基板的正投影位于所述第二子源连接部在所述衬底基板的正投影与所述第三栅线在所述衬底基板的正投影之间。
  16. 如权利要求1-15任一项所述的显示面板，其中，所述显示面板还包括：透明导电层，位于所述反射电极背离所述衬底基板一侧；
    所述透明导电层包括间隔设置的多个第一子透明导电部；其中，一个所述第一子透明导电部在所述衬底基板的正投影位于一个所述第一分区内；
    同一所述第一分区内，所述第一子透明导电部在所述衬底基板的正投影覆盖所述第一通孔在所述衬底基板的正投影，且所述第一子透明导电部在所述衬底基板的正投影位于所述第一反射电极在所述衬底基板的正投影内。
  17. 如权利要求16所述的显示面板，其中，所述透明导电层包括间隔设置的多个第二子透明导电部；其中，一个所述第二子透明导电部在所述衬底 基板的正投影位于一个所述第二分区内；
    同一所述第二分区内，所述第二子透明导电部在所述衬底基板的正投影覆盖所述第二通孔在所述衬底基板的正投影，且所述第二子透明导电部在所述衬底基板的正投影位于所述第二反射电极在所述衬底基板的正投影内。
  18. 一种显示装置，其中，包括如权利要求1-17任一项所述的显示面板。
  19. 一种如权利要求1-17任一项所述的显示面板的驱动方法，其中，包括：
    在一帧时间的各数据输入阶段中驱动一行子像素；
    其中，在一个所述数据写入阶段中驱动一行子像素，包括：
    对所述行子像素电连接的第一栅线加载栅极开启信号，对所述行子像素电连接的第二栅线加载栅极关闭信号，对各数据线加载数据信号，使所述行子像素中的第一反射电极输入数据信号；
    对所述行子像素电连接的第一栅线加载栅极关闭信号，对所述行子像素电连接的第二栅线加载栅极开启信号，对各数据线加载数据信号，使所述行子像素中的第二反射电极输入数据信号。
  20. 如权利要求19所述的驱动方法，其中，在所述对所述行子像素电连接的第一栅线加载栅极开启信号的同时，还包括：对所述行子像素电连接的第三栅线加载栅极开启信号；和/或，
    在所述对所述行子像素电连接的第二栅线加载栅极开启信号的同时，还包括：对所述行子像素电连接的第三栅线加载栅极开启信号。
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