WO2021149414A1 - Dispositif d'imagerie - Google Patents

Dispositif d'imagerie Download PDF

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WO2021149414A1
WO2021149414A1 PCT/JP2020/047087 JP2020047087W WO2021149414A1 WO 2021149414 A1 WO2021149414 A1 WO 2021149414A1 JP 2020047087 W JP2020047087 W JP 2020047087W WO 2021149414 A1 WO2021149414 A1 WO 2021149414A1
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layer
photoelectric conversion
ito layer
ito
electrode
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PCT/JP2020/047087
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English (en)
Japanese (ja)
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貴裕 小柳
高木　誠司
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パナソニックＩｐマネジメント株式会社
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • This disclosure relates to an imaging device.
  • an imaging device such as a CMOS (Complementary Metal Oxide Sensor) image sensor
  • CMOS Complementary Metal Oxide Sensor
  • Patent Document 1 a structure using an organic photoelectric conversion layer for a photoelectric conversion unit has been proposed.
  • Patent Document 1 a plurality of pixel electrodes arranged in a matrix on a substrate, an organic layer including a photoelectric conversion layer commonly provided on the plurality of pixel electrodes and a photoelectric conversion layer commonly provided on the plurality of pixel electrodes, and an organic layer.
  • the configuration of an image pickup apparatus including a translucent counter electrode provided in common with a plurality of pixel electrodes is disclosed above. The image pickup apparatus absorbs the light incident from the translucent counter electrode by the photoelectric conversion layer and converts it into electrons and holes.
  • ITO Indium tin oxide
  • ITO which is widely used as a transparent conductive film
  • resistivity which is one of the electrical characteristics, is defined by the reciprocal of the product of carrier concentration and mobility. Therefore, the specific resistance can be lowered by increasing the carrier concentration.
  • Patent Document 3 in an amorphous oxide composed of a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen, the work function is controlled by the oxygen concentration during film formation. It is disclosed that it can be done. Further, Non-Patent Document 1 shows that localized oxygen defects form a donor level and carrier electrons emitted from the donor level provide conductivity.
  • the present disclosure provides an imaging device capable of achieving both a low resistance of the ITO electrode and an improvement in the controllability of the current-voltage characteristics of the photoelectric conversion unit.
  • the imaging device includes a pixel electrode, a counter electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode.
  • the counter electrode includes a first main surface and a first indium tin oxide (ITO) layer having a second main surface facing the first main surface and closer to the photoelectric conversion layer than the first main surface. It includes a second ITO layer provided on the first main surface of the first ITO layer. The crystallite size of the second ITO layer is larger than the crystallite size of the first ITO layer.
  • ITO indium tin oxide
  • an image pickup apparatus capable of both lowering the resistance of the ITO electrode and improving the controllability of the current-voltage characteristics of the photoelectric conversion unit.
  • FIG. 1 is a cross-sectional view of a sample device used for analyzing the crystallite size of the ITO layer according to the embodiment.
  • FIG. 2 is a graph showing the relationship between the sheet resistance of the ITO layer and the crystallite size according to the embodiment.
  • FIG. 3 is a graph showing the relationship between the oxygen concentration in the film-forming gas of the ITO layer and the crystallite size according to the embodiment.
  • FIG. 4 is a cross-sectional view of a sample element used for evaluating the sheet resistance of the laminated structure of ITO layers according to the embodiment.
  • FIG. 5 is a graph showing an example of sheet resistance for each laminated structure of ITO layers according to the embodiment.
  • FIG. 6 is a cross-sectional view showing an example of the photoelectric conversion unit according to the embodiment.
  • FIG. 7 is a graph showing an example of the current-voltage characteristics of the photoelectric conversion unit according to the embodiment.
  • FIG. 8 is a cross-sectional view showing another example of the photoelectric conversion unit according to the embodiment.
  • FIG. 9 is a circuit diagram showing a circuit configuration of the image pickup apparatus according to the embodiment.
  • FIG. 10 is a cross-sectional view of a unit pixel in the image pickup apparatus according to the embodiment.
  • FIG. 11 is a cross-sectional view showing a laminated structure of ITO layers according to another embodiment of the present disclosure.
  • the imaging device includes a pixel electrode, a counter electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode.
  • the counter electrode has a first ITO layer facing the first main surface and a second main surface facing the first main surface and having a second main surface closer to the photoelectric conversion layer than the first main surface, and the first ITO layer. It includes a second ITO layer provided on the first main surface. The crystallite size of the second ITO layer is larger than the crystallite size of the first ITO layer.
  • the image pickup apparatus may further include an electrode terminal electrically connected to the first ITO layer.
  • the main surface of the electrode terminal and the main surface of the pixel electrode may be located at the same height in the stacking direction.
  • a power supply circuit for supplying power to the counter electrode and a signal processing circuit for the signal charge collected by the pixel electrodes can be collectively formed on the substrate side.
  • the sheet resistance of the second ITO layer may be lower than the sheet resistance of the first ITO layer.
  • the counter electrode contains the second ITO layer having a low sheet resistance, so that the resistance of the counter electrode can be reduced.
  • the work function of the second ITO layer may be larger than the work function of the first ITO layer.
  • the work function of the first ITO layer on the photoelectric conversion layer side becomes small, so that a current easily flows in the photoelectric conversion layer when a voltage is applied to the counter electrode. Therefore, it is possible to improve the controllability of the current-voltage characteristics of the photoelectric conversion unit, such as driving the photoelectric conversion unit with a drive voltage having a small absolute value.
  • the film thickness of the second ITO layer may be larger than the film thickness of the first ITO layer.
  • the resistance of the counter electrode can be further reduced.
  • the imaging device may further include a first functional layer located between the photoelectric conversion layer and the first ITO layer.
  • the function of photoelectric conversion can be improved.
  • the imaging device may further include a second functional layer located between the photoelectric conversion layer and the pixel electrode.
  • each figure is a schematic view and is not necessarily exactly illustrated. Therefore, for example, the scales and the like do not always match in each figure. Further, in each figure, substantially the same configuration is designated by the same reference numerals, and duplicate description will be omitted or simplified.
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking configuration. It is used as a term defined by the relative positional relationship with. Also, the terms “upper” and “lower” are used not only when the two components are spaced apart from each other and another component exists between the two components, but also when the two components It also applies when the two components are placed in close contact with each other and touch each other.
  • FIG. 1 is a cross-sectional view of a sample element used for analysis of crystallite size of the ITO layer according to the embodiment.
  • the present inventors have prepared the sample element 100 shown in FIG. 1 in order to clarify the relationship between the sheet resistance of the ITO layer and the crystallite size.
  • the sample element 100 includes a silicon wafer 101 and an ITO layer 102.
  • the ITO layer 102 is directly laminated on the upper surface of the silicon wafer 101.
  • the method for manufacturing the sample element 100 is as follows.
  • an ITO layer 102 having a film thickness of 50 nm was formed on a silicon wafer 101 by a sputtering method. Then, the sample element 100 was produced by performing a heat treatment at 200 ° C. for 50 minutes in a nitrogen atmosphere.
  • a film forming gas in which argon and oxygen were mixed was introduced into the chamber, and the pressure in the chamber was adjusted to 0.3 Pa.
  • the oxygen concentration in the film-forming gas different, the sample elements 100 according to Comparative Examples 1 to 4 were produced. Specifically, the oxygen concentrations in the film-forming gas of each of the sample elements 100 according to Comparative Examples 1 to 4 are 0.2%, 0.4%, 0.7%, and 1.1%. ..
  • the present inventors analyzed the crystallite size of the ITO layer 102 for each of the sample elements 100 according to Comparative Examples 1 to 4. Specifically, the X-ray diffraction spectrum is measured using the X-ray diffraction (XRD) method, and the crystal of the ITO layer 102 is crystallized from the half width of the measured X-ray diffraction spectrum using Scheller's formula. The child size was calculated.
  • a crystallite is a collection of crystals that can be regarded as a single crystal. Further, a group of single or a plurality of crystal grains is defined as a crystal grain boundary, and the amount of crystal grain boundaries occupying a certain region is defined as a crystal grain boundary density.
  • the present inventors measured the sheet resistance of the ITO layer 102 using a 4-probe measuring device. The analysis results of the ITO layer 102 are shown in Tables 1, 2 and 3 below.
  • FIG. 2 is a graph showing the relationship between the sheet resistance of the ITO layer and the crystallite size according to the embodiment.
  • the horizontal axis represents the sheet resistance of the ITO layer 102
  • the vertical axis represents the crystallite size of the ITO layer 102.
  • FIG. 3 is a graph showing the relationship between the oxygen concentration in the film-forming gas of the ITO layer and the crystallite size according to the embodiment.
  • the horizontal axis represents the oxygen concentration in the film-forming gas of the ITO layer 102
  • the vertical axis represents the crystallite size of the ITO layer 102.
  • the sheet resistance of the ITO layer 102 can be adjusted by adjusting the size of the crystallite size.
  • the sheet resistance of the ITO layer 102 is reduced by increasing the crystallite size.
  • the sheet resistance of the ITO layer 102 can be reduced by increasing the crystallite size of the ITO layer 102.
  • the ITO layer 102 is used alone as the counter electrode of the photoelectric conversion unit of the imaging device, the controllability of the current-voltage characteristics of the photoelectric conversion unit deteriorates. Therefore, the present inventors have studied the use of a laminated structure of two ITO layers having different crystallite sizes as counter electrodes. The controllability of the current-voltage characteristics of the photoelectric conversion unit will be described later.
  • FIG. 4 is a cross-sectional view of a sample element used for evaluating the sheet resistance of the laminated structure of ITO layers according to the embodiment.
  • the sample element 110 includes a silicon wafer 101, a first ITO layer 111, and a second ITO layer 112.
  • the first ITO layer 111 is directly laminated on the upper surface of the silicon wafer 101.
  • the second ITO layer 112 is directly laminated on the upper surface of the first ITO layer 111.
  • the manufacturing method of the sample element 110 is the same as the manufacturing method of the sample element 100 shown in FIG. Specifically, first, the first ITO layer 111 and the second ITO layer 112 were formed in order on the silicon wafer 101 by using a sputtering method. Then, the sample element 110 was produced by performing a heat treatment at 200 ° C. for 50 minutes in a nitrogen atmosphere.
  • the film forming conditions of the first ITO layer 111 and the film forming conditions of the second ITO layer 112 are the same as each other except that the oxygen concentration and the film thickness in the film forming gas are different.
  • the oxygen concentration in the film-forming gas of the first ITO layer 111 is 20%
  • the oxygen concentration in the film-forming gas of the second ITO layer 112 is 3%.
  • the film thickness of the first ITO layer 111 and the film thickness of the second ITO layer 112 were adjusted so that the total film thickness of the first ITO layer 111 and the second ITO layer 112 was 50 nm.
  • the present inventors have produced five sample elements 110 having different film thicknesses as Examples 1 to 3, Comparative Example 5, and Comparative Example 6.
  • the film thickness of each sample element 110 is as shown in Table 2 below.
  • the sample element 110 according to Comparative Example 5 has the same structure as the sample element 100 including the first ITO layer 111 as the ITO layer 102.
  • the sample element 110 according to Comparative Example 6 has the same structure as the sample element 100 including the second ITO layer 112 as the ITO layer 102 because the film thickness of the first ITO layer 111 is 0 nm.
  • the present inventors measured the sheet resistance of the laminated structure of the first ITO layer 111 and the second ITO layer 112 for each of the five sample elements 110 produced by using a four-probe measuring device.
  • the sheet resistance of the first ITO layer 111 or the second ITO layer 112 was measured.
  • FIG. 5 is a graph showing an example of sheet resistance for each laminated structure of ITO layers according to the embodiment.
  • the horizontal axis represents Examples 1 to 3, Comparative Example 5 and Comparative Example 6, and the vertical axis represents sheet resistance.
  • Example 1 to Example 3, Comparative Example 5 and Comparative Example 6 are arranged in order of increasing the film thickness of the second ITO layer 112 toward the right side of the horizontal axis.
  • the sheet of the laminated structure is formed by adjusting the film thickness ratio of the first ITO layer 111 and the second ITO layer 112. It turns out that the resistance can be adjusted. Specifically, if the total film thickness of the laminated structure of the ITO layers is the same, the sheet resistance decreases as the film thickness of the second ITO layer 112 formed in the film-forming gas having a low oxygen concentration increases. You can see that. That is, the larger the film thickness of the second ITO layer 112, which has a lower sheet resistance than the first ITO layer 111, the lower the sheet resistance of the laminated structure of the ITO layers.
  • the sheet resistance of the sample element 110 according to Comparative Example 6 is lower than the sheet resistance of the sample element 100 according to Comparative Example 4 even though the oxygen concentration is high. ing.
  • the sample element 100 according to Comparative Examples 1 to 4 and the sample element 110 according to Comparative Examples 5 and 6 differ in the film forming apparatus used for forming the ITO layer. This is because there was a difference in the conditions.
  • other materials can be added to the ITO layer. Metal elements such as Al, Au, Ag, Cu, Hf, Ta, Sr, Zr, Cr, Fe, Ni, Co, Zn, Ga, Li, La, Y, Ti, etc. are added to the ITO layer. May be good.
  • FIG. 6 is a cross-sectional view showing an example of the photoelectric conversion unit according to the present embodiment.
  • the photoelectric conversion unit 120 includes a pixel electrode 122, a photoelectric conversion layer 126, and a counter electrode 127.
  • the photoelectric conversion unit 120 is provided on the insulating layer 121.
  • the insulating layer 121 is formed with a connection wiring 123, an electrode terminal 124, and a connection wiring 125.
  • the insulating layer 121 is an insulating layer formed above the substrate (not shown).
  • the substrate is formed with, for example, a transistor included in a signal processing circuit that processes the signal charge generated by the photoelectric conversion unit 120.
  • the insulating layer 121 has a single-layer structure or a laminated structure such as a silicon oxide film or a silicon nitride film, but is not particularly limited.
  • the pixel electrode 122 is an electrode for collecting the signal charge generated by the photoelectric conversion layer 126.
  • a conductive material such as a metal, a metal oxide, a metal nitride, or a conductive polysilicon is used.
  • the metal is, for example, aluminum, silver, copper, titanium or tungsten.
  • the metal nitride is, for example, titanium nitride or tantalum nitride.
  • Conductive polysilicon is polysilicon that has been imparted with conductivity by adding impurities.
  • connection wiring 123 is a part of the wiring that electrically connects the pixel electrode 122 and the signal processing circuit.
  • a conductive material such as a metal, a metal oxide, a metal nitride, or a conductive polysilicon is used.
  • the electrode terminal 124 is a power supply terminal for supplying power to the counter electrode 127.
  • the electrode terminal 124 is electrically connected to the counter electrode 127.
  • a conductive material such as a metal, a metal oxide, a metal nitride, or a conductive polysilicon is used.
  • the main surface of the electrode terminal 124 and the main surface of the pixel electrode 122 are located at the same height in the thickness direction. Specifically, the upper surface 124a of the electrode terminal 124 and the upper surface 122a of the pixel electrode 122 are located at the same height in the thickness direction. In the present embodiment, the upper surface 124a of the electrode terminal 124, the upper surface 122a of the pixel electrode 122, and the upper surface 121a of the insulating layer 121 are flush with each other.
  • connection wiring 125 is a part of the wiring that electrically connects the electrode terminal 124 and the power supply circuit (not shown) that supplies the voltage applied to the counter electrode 127.
  • a conductive material such as a metal, a metal oxide, a metal nitride, or a conductive polysilicon is used.
  • the photoelectric conversion layer 126 is located between the pixel electrode 122 and the counter electrode 127.
  • the photoelectric conversion layer 126 is irradiated with light to generate electron-hole pairs inside.
  • the electron-hole pair is separated into electrons and holes by the electric field applied to the photoelectric conversion layer 126, and each moves to the pixel electrode 122 side or the counter electrode 127 side.
  • the photoelectric conversion layer 126 is formed using a known photoelectric conversion material.
  • the photoelectric conversion material is, for example, an organic material, but may be an inorganic material.
  • As the inorganic photoelectric conversion material hydrogenated amorphous silicon, a compound semiconductor material, a metal oxide semiconductor material, or the like can be used.
  • the compound semiconductor material is, for example, CdSe.
  • the metal oxide semiconductor material is, for example, ZnO.
  • the photoelectric conversion material is an organic material
  • the molecular design of the photoelectric conversion material can be relatively freely performed so that the desired photoelectric conversion characteristics can be obtained.
  • the photoelectric conversion layer 126 having excellent flatness can be easily formed by a coating process using a solution containing the photoelectric conversion material.
  • the organic semiconductor material can be formed, for example, by a vacuum deposition method or a coating method.
  • the photoelectric conversion layer 126 may be composed of a laminated film of a donor material and an acceptor material, or may be composed of a mixed film of these materials.
  • the structure of the laminated film of the donor material and the acceptor material is called a heterojunction type.
  • the structure of the mixed membrane of the donor material and the acceptor material is called the bulk heterojunction type.
  • the p-type semiconductor of an organic compound is a donor organic semiconductor, and mainly refers to an organic compound having a property of easily donating electrons, typified by a hole transporting organic compound.
  • the p-type semiconductor of an organic compound refers to an organic compound having a smaller ionization potential when two organic materials are used in contact with each other. Therefore, as the donor organic semiconductor, any organic compound can be used as long as it is an electron-donating organic compound.
  • donor organic semiconductors include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, cyanine compounds, merocyanine compounds, and oxonor.
  • a metal complex having a compound, a polyamine compound, an indol compound, a pyrrole compound, a pyrazole compound, a polyarylene compound, a condensed aromatic carbocyclic compound or a nitrogen-containing heterocyclic compound as a ligand can be used.
  • the condensed aromatic carbocyclic compound is, for example, a naphthalene derivative, an anthracene derivative, phenanthrene derivative, tetracene derivative, pyrene derivative, perylene derivative or fluoranthene derivative.
  • a naphthalene derivative an anthracene derivative
  • phenanthrene derivative tetracene derivative
  • pyrene derivative perylene derivative or fluoranthene derivative.
  • any organic compound having a smaller ionization potential than the organic compound used as the accepting organic semiconductor can be used as the donor organic semiconductor.
  • the n-type semiconductor of an organic compound is an acceptor-type organic semiconductor, and refers to an organic compound having a property of easily accepting electrons, mainly represented by an electron-transporting organic compound.
  • the n-type semiconductor of an organic compound refers to an organic compound having a larger electron affinity when two organic compounds are used in contact with each other. Therefore, as the accepting organic compound, any organic compound can be used as long as it is an electron-accepting organic compound.
  • a fullerene, a fullerene derivative, a condensed aromatic carbocyclic compound, a polyarylene compound, a fluorene compound, a cyclopentadiene compound, a silyl compound, a metal complex having a nitrogen-containing heterocyclic compound as a ligand, or the like is used. be able to.
  • a metal complex having a 5- or 7-membered heterocyclic compound containing a nitrogen atom, an oxygen atom or a sulfur atom as a ligand can be used.
  • the 5- or 7-membered heterocyclic compound containing a nitrogen atom, an oxygen atom or a sulfur atom includes, for example, pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinolin, pteridine, aclysine, and the like.
  • any organic compound having a higher electron affinity than the organic compound used as the donor organic compound can be used as an acceptor organic semiconductor.
  • the counter electrode 127 collects a charge having the opposite polarity to the signal charge collected by the pixel electrode 122. A predetermined voltage is applied to the counter electrode 127. As a result, a potential difference is generated between the counter electrode 127 and the plurality of pixel electrodes 122, and an electric field is applied to the photoelectric conversion layer 126. The counter electrode 127 collects the electric charges that move to the counter electrode 127 side due to the electric field among the holes and electrons generated in the photoelectric conversion layer 126.
  • the counter electrode 127 has a laminated structure of ITO layers. Specifically, as shown in FIG. 6, the counter electrode 127 includes a first ITO layer 127a and a second ITO layer 127b.
  • the first ITO layer 127a is provided closer to the photoelectric conversion layer 126 than the second ITO layer 127b. Specifically, the first ITO layer 127a is directly laminated on the upper surface of the photoelectric conversion layer 126.
  • the second ITO layer 127b is laminated on the main surface of the first ITO layer 127a on the side opposite to the photoelectric conversion layer 126. Specifically, the second ITO layer 127b is directly laminated on the upper surface of the first ITO layer 127a.
  • the first ITO layer 127a and the second ITO layer 127b cover the end face of the photoelectric conversion layer 126 and the portion of the insulating layer 121 that is not covered by the photoelectric conversion layer 126. Specifically, the first ITO layer 127a is in contact with the end face of the photoelectric conversion layer 126 and the portion of the insulating layer 121 that is not covered by the photoelectric conversion layer 126. The first ITO layer 127a is in contact with the electrode terminal 124 and is electrically connected to the electrode terminal 124.
  • the crystallite size of the second ITO layer 127b is larger than the crystallite size of the first ITO layer 127a. As can be seen from the relationship between the crystallite size and the sheet resistance described above, the sheet resistance of the second ITO layer 127b is smaller than the sheet resistance of the first ITO layer 127a. Further, the work function of the second ITO layer 127b is larger than the work function of the first ITO layer 127a.
  • the film thickness of the second ITO layer 127b is larger than the film thickness of the first ITO layer 127a.
  • the film thickness of the second ITO layer 127b is 1.5 times or more the film thickness of the first ITO layer 127a, but it may be 2 times or more, or 4 times or more.
  • the present inventors manufactured the photoelectric conversion unit 120 shown in FIG. 6 as a sample element according to Example 4 in order to measure the current-voltage characteristics. Further, as the sample element according to Comparative Example 7 and Comparative Example 8, the present inventors have produced a sample element having the same configuration as that of Example 4 except that the counter electrode 127 has a single-layer structure of an ITO layer. ..
  • a titanium nitride (TiN) film having a film thickness of 50 nm was formed as the pixel electrode 122 and the electrode terminal 124 by a sputtering method.
  • the photoelectric conversion layer 126 an organic photoelectric conversion film which is a mixed film containing Sn (OSiHex 3 ) 2 Nc and fullerene (C 60 ) in a volume ratio of 1: 9 was formed by a vacuum deposition method.
  • the first ITO layer 127a is an ITO layer having a film thickness of 20 nm formed in a film-forming gas having an oxygen concentration of 1.1%.
  • the second ITO layer 127b is an ITO layer having a film thickness of 30 nm formed in a film-forming gas having an oxygen concentration of 0.4%.
  • the sample element according to Comparative Example 7 has a single-layer structure of an ITO layer having a film thickness of 50 nm formed in a film-forming gas having an oxygen concentration of 0.4% as a counter electrode 127.
  • the sample element according to Comparative Example 8 has a single-layer structure of an ITO layer having a film thickness of 50 nm formed in a film-forming gas having an oxygen concentration of 1.1% as a counter electrode 127.
  • the sheet resistance of the counter electrode 127 of the sample element according to Comparative Example 7 is lower than the sheet resistance of the counter electrode 127 of the sample element according to Comparative Example 8.
  • the sheet resistance of the counter electrode 127 according to Comparative Example 7 is the same as that of Comparative Example 2, and is 71 ⁇ / sq.
  • the sheet resistance of the counter electrode 127 according to Comparative Example 8 is the same as that of Comparative Example 4, and is 372 ⁇ / sq.
  • the present inventors measured the current-voltage characteristics of the sample elements according to each of Example 4, Comparative Example 7, and Comparative Example 8. Specifically, the applied voltage applied to the counter electrode 127 was swept from ⁇ 0.2 V to 0 V, and the current value of the current flowing between the counter electrode 127 and the pixel electrode 122 was measured.
  • a semiconductor parameter analyzer B1500A manufactured by Keysight was used for measuring the current-voltage characteristics. Further, during the measurement, a xenon light source MAX-303 manufactured by Asahi Spectroscopy Co., Ltd. was used to irradiate the photoelectric conversion layer 126 of the sample element with light.
  • FIG. 7 is a graph showing an example of the current-voltage characteristics of the photoelectric conversion unit according to the embodiment.
  • the horizontal axis represents the applied voltage applied to the counter electrode 127
  • the vertical axis represents the current flowing between the pixel electrode 122 and the counter electrode 127. Since the potential of the pixel electrode 122 is constant, the horizontal axis corresponds to the potential difference between the counter electrode 127 and the pixel electrode 122.
  • the applied voltage when the current starts to flow is 0.06 V larger on the negative side than the sample element according to Comparative Example 8 having a high sheet resistance.
  • the time when the current value reaches 1.0 ⁇ 10-11 A is regarded as the time when the current starts to flow.
  • the current starts to flow when the electron-hole pair generated in the photoelectric conversion layer 126 can be separated into electrons and holes and moved, and can be detected as a signal charge, that is, photoelectric conversion. This is when the unit 120 can be driven. Therefore, the applied voltage applied to the counter electrode 127 when the current starts to flow is the driving voltage of the photoelectric conversion unit 120.
  • the sample element according to Comparative Example 7 having a low sheet resistance requires a drive voltage having a larger absolute value than the sample element according to Comparative Example 8 having a high sheet resistance. That is, when a single-layer ITO layer having a low sheet resistance is used as the counter electrode 127, a drive voltage having a large absolute value is required, so that it can be said that the controllability of the current-voltage characteristics of the photoelectric conversion unit 120 is poor.
  • the photoelectric conversion unit 120 can be driven with a drive voltage equivalent to that of the sample element according to the comparative example 8 having a high sheet resistance. I understand. Therefore, the controllability of the current-voltage characteristics can be improved by using the laminated structure of the ITO layer.
  • the change in drive voltage due to such a shift in current-voltage characteristics is affected by the difference in the work function of the ITO layer in contact with the photoelectric conversion layer 126.
  • the difference in work function between the ITO layer of the sample element according to Comparative Example 7 and the ITO layer of the sample element according to Comparative Example 8 is the difference in drive voltage shown in FIG. 7, which is about ⁇ 0.06 V. That is, the work function of the ITO layer having a small crystallite size according to Comparative Example 8 is smaller than the work function of the ITO layer having a large crystallite size according to Comparative Example 7.
  • the first ITO layer 127a on the photoelectric conversion layer 126 side is the same as the ITO layer of the sample element according to the comparative example 8, and is an ITO layer having a high sheet resistance and a small work function. Since the current-voltage characteristics of the sample element according to the fourth embodiment are the same as those of the comparative example 8, the controllability of the current-voltage characteristics is not the work of the counter electrode 127 as a whole, but the work of the first ITO layer 127a on the photoelectric conversion layer 126 side. You can see that it can be adjusted by a function.
  • the crystallite size of the second ITO layer 127b is larger than the crystallite size of the first ITO layer 127a, so that the sheet resistance of the second ITO layer 127b becomes the first ITO layer. It is lower than the sheet resistance of 127a. As a result, the sheet resistance of the entire counter electrode 127 can be reduced.
  • the crystallite size of the first ITO layer 127a on the photoelectric conversion layer 126 side is smaller than the crystallite size of the second ITO layer 127b, the work function of the first ITO layer 127a becomes smaller than the work function of the second ITO layer 127b. This makes it possible to improve the controllability of the current-voltage characteristics of the photoelectric conversion unit 120.
  • the film formation conditions of the ITO layer are not limited to the above-mentioned conditions as long as the crystallite size of the ITO layer can be adjusted.
  • the film formation of the ITO layer may be performed by using a wet method.
  • the heating temperature after the film formation may be any temperature as long as the crystallization of the ITO layer proceeds, and may be, for example, 150 ° C.
  • the atmosphere at the time of heating may be a vacuum depressurized atmosphere, a rare gas atmosphere such as argon, or an oxygen atmosphere.
  • the film-forming gas may contain a gas such as hydrogen or nitrogen.
  • the film thickness of each layer is not limited to the above-mentioned example.
  • FIG. 8 is a cross-sectional view showing another example of the photoelectric conversion unit according to the embodiment.
  • the photoelectric conversion unit 130 shown in FIG. 8 is different from the photoelectric conversion unit 120 shown in FIG. 6 in that it newly includes an electron block layer 128 and a hole block layer 129.
  • an electron block layer 128 and a hole block layer 129.
  • the electronic block layer 128 is an example of a second functional layer located between the photoelectric conversion layer 126 and the pixel electrode 122.
  • the electron block layer 128 has a function of suppressing the movement of electrons generated in the photoelectric conversion layer 126 by photoelectric conversion into the pixel electrode 122.
  • the electron block layer 128 suppresses the passage of electrons and enables the passage of holes.
  • a p-type semiconductor or a hole-transporting organic compound can be used as a material for forming the electron block layer 128, a p-type semiconductor or a hole-transporting organic compound can be used.
  • examples of such materials are TPD (N, N'-bis (3-methylphenyl)-(1,1'-biphenyl) -4,4'-diamine), ⁇ -NPD (4,4'-bis).
  • Aromatic diamine compounds such as [N- (naphthyl) -N-phenyl-amino] biphenyl), oxazole, oxadiazole, triazole, imidazole, imidazolone, stillben derivatives, pyrazoline derivatives, tetrahydroimidazoles, polyarylalkanes, butadiene, m -MTDATA (4,4', 4 "-tris (N- (3-methylphenyl) N-phenylamino) triphenylamine), perylene, and porfin, tetraphenylporphin copper, phthalocyanine, copper phthalocyanine and titanium phthalocyanine.
  • Polyphyllin compounds such as oxides, triazole derivatives, oxazazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, annealing amine derivatives, amino-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone Derivatives, silazane derivatives, etc.
  • a material for forming the electron blocking layer 1208 a polymer such as phenylene vinylene, fluorene, carbazole, indol, pyrene, pyrrole, picolin, thiophene, acetylene, diacetylene, or These derivatives can be used.
  • the material for forming the electron block layer 128 can be selected from the above materials in consideration of the electron affinity of the material constituting the photoelectric conversion layer 126.
  • the electron block layer 128 can be selected from the above materials. It may be formed using not only an organic material but also an inorganic material.
  • the film thickness of the electronic block layer 128 is not particularly limited.
  • the film thickness of the electron block layer 128 may be 5 nm or more from the viewpoint of sufficiently reducing the electron tunnel probability.
  • the upper limit of the film thickness of the electron block layer 128 is, for example, 100 nm.
  • the hole block layer 129 is an example of a first functional layer located between the photoelectric conversion layer 126 and the first ITO layer 127a.
  • the hole block layer 129 has a function of suppressing the movement of holes from the counter electrode 127 to the photoelectric conversion layer 126.
  • the hole block layer 129 suppresses the passage of holes and allows the passage of electrons.
  • an n-type semiconductor or an electron-transporting organic compound can be used as a material for forming the hole block layer 129.
  • n-type semiconductor or an electron-transporting organic compound examples include fullerenes such as C 60 and C 70 , fullerene derivatives such as inden-C 60 bis adducts (ICBA), carbon nanotubes and their derivatives, OXD-7 (1,3-bis (4-3)).
  • Oxadiazole derivatives such as tert-butylphenyl-1,3,4-oxadiazolyl) phenylene), anthracinodimethane derivatives, diphenylquinone derivatives, vasocproin (BCP), vasofenantroline and its derivatives, distyrylarylene derivatives, triazole compounds , Sirol compound, tris (8-hydroxyquinolinate) aluminum complex, bis (4-methyl-8-quinolinate) aluminum complex, acetylacetonate complex, copper phthalocyanine, 3,4,9,10-perylenetetracarboxylic acid di It is an organic substance such as anhydride (PTCDA) or Alq or an organic-metal compound, or an inorganic substance such as MgAg or MgO.
  • the material for forming the hole block layer 129 can be selected from the above materials in consideration of the ionization potential of the material constituting the photoelectric conversion layer 126.
  • the photoelectric conversion unit 130 can enhance the photoelectric conversion function by including the electron block layer 128 and the hole block layer 129.
  • the pixel electrode 122 may collect electrons as a signal charge.
  • the hole block layer 129 is located between the pixel electrode 122 and the photoelectric conversion layer 126
  • the electron block layer 128 is located between the photoelectric conversion layer 126 and the counter electrode 127.
  • the photoelectric conversion unit 130 may or may not include only one of the electron block layer 128 and the hole block layer 129. Further, the photoelectric conversion unit 130 may include a functional layer for enhancing the photoelectric conversion function such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, in addition to the layer having a charge blocking function. ..
  • FIG. 9 is a circuit diagram showing a circuit configuration of the image pickup apparatus 200 according to the present embodiment.
  • FIG. 10 is a cross-sectional view of a unit pixel 210 in the image pickup apparatus 200 according to the present embodiment.
  • the image pickup apparatus 200 includes a plurality of unit pixels 210 and peripheral circuits.
  • the plurality of unit pixels 210 include a charge detection circuit 25, a photoelectric conversion unit 120, and a charge storage node 24 electrically connected to the charge detection circuit 25 and the photoelectric conversion unit 120.
  • the image pickup device 200 is, for example, an organic image sensor realized by an integrated circuit of one chip, and has a pixel array including a plurality of unit pixels 210 arranged two-dimensionally.
  • the plurality of unit pixels 210 are arranged two-dimensionally, that is, in the row direction and the column direction to form a photosensitive region which is a pixel region.
  • FIG. 9 shows an example in which the unit pixels 210 are arranged in a matrix of 2 rows and 2 columns.
  • the image pickup apparatus 200 may be a line sensor. In that case, the plurality of unit pixels 210 may be arranged one-dimensionally.
  • the row direction and the column direction mean the directions in which the rows and columns extend, respectively. That is, the vertical direction is the column direction and the horizontal direction is the row direction.
  • Each unit pixel 210 includes a charge storage node 24 electrically connected to the photoelectric conversion unit 120 and the charge detection circuit 25.
  • the charge detection circuit 25 includes an amplification transistor 11, a reset transistor 12, and an address transistor 13.
  • the photoelectric conversion unit 120 includes a pixel electrode 122, a photoelectric conversion layer 126, and a counter electrode 127. A predetermined voltage is applied to the counter electrode 127 from the voltage control circuit 30 via the counter electrode signal line 16.
  • the pixel electrode 122 is connected to the gate electrode 39B (see FIG. 10) of the amplification transistor 11.
  • the signal charge collected by the pixel electrode 122 is stored in the charge storage node 24 located between the pixel electrode 122 and the gate electrode 39B of the amplification transistor 11.
  • the signal charge is a hole, but the signal charge may be an electron.
  • the signal charge accumulated in the charge storage node 24 is applied to the gate electrode 39B of the amplification transistor 11 as a voltage corresponding to the amount of the signal charge.
  • the amplification transistor 11 amplifies this voltage.
  • the amplified voltage is selectively read out by the address transistor 13 as a signal voltage.
  • One of the source electrode and the drain electrode of the reset transistor 12 is connected to the pixel electrode 122, and resets the signal charge accumulated in the charge storage node 24. In other words, the reset transistor 12 resets the potentials of the gate electrode 39B and the pixel electrode 122 of the amplification transistor 11.
  • the image pickup apparatus 200 uses the power supply wiring 21, the vertical signal line 17, the address signal line 26, and the reset signal line, as shown in FIG. It has 27 and. These lines are connected to each unit pixel 210.
  • the power supply wiring 21 is connected to one of the source electrode and the drain electrode of the amplification transistor 11.
  • the vertical signal line 17 is connected to one of the source electrode and the drain electrode of the address transistor 13.
  • the address signal line 26 is connected to the gate electrode 39C (see FIG. 10) of the address transistor 13.
  • the reset signal line 27 is connected to the gate electrode 39A (see FIG. 10) of the reset transistor 12.
  • the peripheral circuit includes a vertical scanning circuit 15, a horizontal signal reading circuit 20, a plurality of column signal processing circuits 19, a plurality of load circuits 18, a plurality of differential amplifiers 22, and a voltage control circuit 30.
  • the vertical scanning circuit 15 is also referred to as a row scanning circuit.
  • the horizontal signal reading circuit 20 is also referred to as a column scanning circuit.
  • the column signal processing circuit 19 is also referred to as a row signal storage circuit.
  • the differential amplifier 22 is also referred to as a feedback amplifier.
  • the vertical scanning circuit 15 is connected to the address signal line 26 and the reset signal line 27.
  • the vertical scanning circuit 15 selects a plurality of unit pixels 210 arranged in each row in units of rows, reads out the signal voltage, and resets the potential of the pixel electrodes 122.
  • the power supply wiring 21 which is a source follower power supply supplies a predetermined power supply voltage to each unit pixel 210.
  • the horizontal signal reading circuit 20 is electrically connected to a plurality of column signal processing circuits 19.
  • the column signal processing circuit 19 is electrically connected to the unit pixels 210 arranged in each row via the vertical signal lines 17 corresponding to each row.
  • the load circuit 18 is electrically connected to each vertical signal line 17.
  • the load circuit 18 and the amplification transistor 11 form a source follower circuit.
  • a plurality of differential amplifiers 22 are provided corresponding to each row.
  • the negative input terminal of the differential amplifier 22 is connected to the corresponding vertical signal line 17.
  • the output terminal of the differential amplifier 22 is connected to the unit pixel 210 via a feedback line 23 corresponding to each row.
  • the vertical scanning circuit 15 applies a row selection signal for controlling the on / off of the address transistor 13 to the gate electrode 39C of the address transistor 13 by the address signal line 26. As a result, the line to be read is scanned and selected. A signal voltage is read from the unit pixel 210 of the selected line to the vertical signal line 17.
  • the vertical scanning circuit 15 applies a reset signal for controlling the on / off of the reset transistor 12 to the gate electrode 39A of the reset transistor 12 via the reset signal line 27. As a result, the row of the unit pixel 210 that is the target of the reset operation is selected.
  • the vertical signal line 17 transmits the signal voltage read from the unit pixel 210 selected by the vertical scanning circuit 15 to the column signal processing circuit 19.
  • the column signal processing circuit 19 performs noise suppression signal processing represented by correlated double sampling, analog-to-digital conversion (AD conversion), and the like.
  • the horizontal signal reading circuit 20 sequentially reads signals from the plurality of column signal processing circuits 19 to the horizontal common signal line 28.
  • the differential amplifier 22 is connected to the other of the source electrode and the drain electrode of the reset transistor 12 via the feedback line 23, whichever is not connected to the pixel electrode 122. Therefore, the differential amplifier 22 receives the output value of the address transistor 13 at the negative input terminal when the address transistor 13 and the reset transistor 12 are in a conductive state.
  • the differential amplifier 22 performs a feedback operation so that the gate potential of the amplification transistor 11 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 22 is 0V or a positive voltage in the vicinity of 0V.
  • the feedback voltage means the output voltage of the differential amplifier 22.
  • the voltage control circuit 30 may generate a constant control voltage, or may generate a plurality of control voltages having different values. For example, the voltage control circuit 30 may generate a control voltage having two or more different values, or may generate a control voltage that continuously changes within a predetermined range.
  • the voltage control circuit 30 determines the value of the control voltage to be generated based on the command of the operator who operates the image pickup device 200 or the command of another control unit included in the image pickup device 200, and the control voltage of the determined value. To generate.
  • the voltage control circuit 30 is provided outside the photosensitive region as a part of the peripheral circuit.
  • the photosensitive area is substantially the same as the pixel area.
  • the voltage control circuit 30 generates two or more different control voltages, and by applying the control voltage to the counter electrode 127, the spectral sensitivity characteristic of the photoelectric conversion layer 126 changes. Further, the change in the spectral sensitivity characteristic includes the spectral sensitivity characteristic in which the sensitivity of the photoelectric conversion layer 126 to the light to be detected becomes zero.
  • a control voltage at which the sensitivity of the photoelectric conversion layer 126 becomes zero is applied from the voltage control circuit 30 to the counter electrode 127 while the unit pixel 210 reads out the detection signal row by row. Therefore, the influence of the incident light when reading the detection signal can be substantially eliminated. Therefore, the global shutter operation can be realized even if the detection signal is read out substantially line by line.
  • the voltage control circuit 30 applies a control voltage to the counter electrode 127 of the unit pixels 210 arranged in the row direction via the counter electrode signal line 16. As a result, the voltage between the pixel electrode 122 and the counter electrode 127 is changed, and the spectral sensitivity characteristic in the photoelectric conversion unit 120 is switched.
  • the voltage control circuit 30 realizes the electronic shutter operation by applying a control voltage so as to obtain a spectral sensitivity characteristic in which the sensitivity to light becomes zero at a predetermined timing during imaging.
  • the voltage control circuit 30 may apply a control voltage to the pixel electrodes 122.
  • the pixel electrode 122 In order to irradiate the photoelectric conversion unit 120 with light and collect electrons as signal charges on the pixel electrode 122, the pixel electrode 122 is set to a higher potential than the counter electrode 127. As a result, the electrons move toward the pixel electrode 122. At this time, since the moving direction of the electrons is opposite to the direction in which the current flows, the current flows from the pixel electrode 122 toward the counter electrode 127. Further, in order to irradiate the photoelectric conversion unit 120 with light and collect holes as signal charges on the pixel electrode 122, the pixel electrode 122 is set to a potential lower than that of the counter electrode 127. At this time, a current flows from the counter electrode 127 toward the pixel electrode 122.
  • the unit pixel 210 includes a semiconductor substrate 31, a charge detection circuit 25, a photoelectric conversion unit 120, and a charge storage node 24.
  • the plurality of unit pixels 210 are formed on the semiconductor substrate 31.
  • the photoelectric conversion unit 120 is provided above the semiconductor substrate 31.
  • the charge detection circuit 25 is provided inside and above the semiconductor substrate 31.
  • the semiconductor substrate 31 is an insulating substrate or the like in which a semiconductor layer is provided on the surface on the side where the photosensitive region is formed, and is, for example, a p-type silicon substrate.
  • the semiconductor substrate 31 has impurity regions 41A, 41B, 41C, 41D and 41E, and an element separation region 42 for electrical separation between unit pixels 210.
  • the element separation region 42 is also provided between the impurity region 41B and the impurity region 41C. As a result, leakage of the signal charge accumulated in the charge storage node 24 is suppressed.
  • the device separation region 42 is formed, for example, by implanting acceptor ions under predetermined implantation conditions.
  • the impurity regions 41A, 41B, 41C, 41D and 41E are, for example, diffusion layers formed in the semiconductor substrate 31.
  • the impurity regions 41A, 41B, 41C, 41D and 41E are n-type impurity regions.
  • the amplification transistor 11 includes an impurity region 41C, an impurity region 41D, a gate insulating film 38B, and a gate electrode 39B.
  • the impurity region 41C and the impurity region 41D function as a source region and a drain region of the amplification transistor 11, respectively.
  • a channel region of the amplification transistor 11 is formed between the impurity region 41C and the impurity region 41D.
  • the address transistor 13 includes an impurity region 41D, an impurity region 41E, a gate insulating film 38C, and a gate electrode 39C.
  • the amplification transistor 11 and the address transistor 13 are electrically connected to each other by sharing the impurity region 41D.
  • the impurity region 41D and the impurity region 41E function as a source region and a drain region of the address transistor 13, respectively.
  • the impurity region 41E is connected to the vertical signal line 17 shown in FIG.
  • the reset transistor 12 includes an impurity region 41A, an impurity region 41B, a gate insulating film 38A, and a gate electrode 39A.
  • the impurity region 41A and the impurity region 41B function as a source region and a drain region of the reset transistor 12, respectively.
  • the impurity region 41A is connected to the reset signal line 27 shown in FIG.
  • the gate insulating film 38A, the gate insulating film 38B, and the gate insulating film 38C are each insulating films formed by using an insulating material.
  • the insulating film has a single-layer structure or a laminated structure such as a silicon oxide film or a silicon nitride film.
  • the gate electrode 39A, the gate electrode 39B, and the gate electrode 39C are each formed by using a conductive material.
  • the conductive material is, for example, conductive polysilicon.
  • An interlayer insulating layer 43 is laminated on the semiconductor substrate 31 so as to cover the amplification transistor 11, the address transistor 13, and the reset transistor 12.
  • a wiring layer (not shown) may be arranged in the interlayer insulating layer 43.
  • the wiring layer is formed of, for example, a metal such as copper, and may include, for example, wiring such as the above-mentioned vertical signal line 17 as a part thereof.
  • the number of layers of the insulating layer in the interlayer insulating layer 43 and the number of layers included in the wiring layer arranged in the interlayer insulating layer 43 can be arbitrarily set.
  • a contact plug 45A connected to the impurity region 41B of the reset transistor 12 In the interlayer insulating layer 43, a contact plug 45A connected to the impurity region 41B of the reset transistor 12, a contact plug 45B connected to the gate electrode 39B of the amplification transistor 11, a contact plug 47 connected to the pixel electrode 122, and , A wiring 46 connecting the contact plug 47, the contact plug 45A, and the contact plug 45B is arranged.
  • the impurity region 41B of the reset transistor 12 is electrically connected to the gate electrode 39B of the amplification transistor 11.
  • a photoelectric conversion unit 120 is arranged on the interlayer insulating layer 43.
  • the specific configuration of the photoelectric conversion unit 120 is the same as that in FIG.
  • the interlayer insulating layer 43 and the contact plug 47 correspond to the insulating layer 121 and the connecting wiring 123 shown in FIG. 6, respectively.
  • the electrode terminals 124 and the connection wiring 125 shown in FIG. 6 are provided not in the unit pixel 210, for example, but in the peripheral portion of the photosensitive region.
  • the photoelectric conversion unit 120 may include at least one of a plurality of functional layers including the electron block layer 128 and the hole block layer 129, as in the photoelectric conversion unit 130 shown in FIG.
  • the imaging device 200 may include a photoelectric conversion unit 130 instead of the photoelectric conversion unit 120.
  • a color filter 60 is provided above the photoelectric conversion unit 120.
  • a microlens 61 is provided above the color filter 60.
  • the color filter 60 is formed as an on-chip color filter by patterning, for example, and a photosensitive resin in which a dye or a pigment is dispersed is used.
  • the microlens 61 is provided as an on-chip microlens, for example, and an ultraviolet photosensitive material or the like is used.
  • the image pickup apparatus 200 can be manufactured by using a general semiconductor manufacturing process.
  • a silicon substrate is used as the semiconductor substrate 31, it can be manufactured by using various silicon semiconductor processes.
  • the counter electrode 127 of the photoelectric conversion unit 120 included in the image pickup apparatus 200 has a laminated structure of the first ITO layer 127a and the second ITO layer 127b. Therefore, as described above, the image pickup apparatus 200 can achieve both a reduction in the resistance of the counter electrode 127 and an improvement in the controllability of the current-voltage characteristics of the photoelectric conversion unit 120.
  • a translucent and insulating protective film may be provided between the photoelectric conversion unit 130 and the color filter 60.
  • the ITO layer of the present disclosure for both lowering the resistance of the ITO electrode and improving the controllability of the current-voltage characteristics of the photoelectric conversion unit is formed by gradually reducing the flow rate of oxygen gas to form oxygen in the film-forming gas. It can also be obtained by forming a film while gradually lowering the concentration.
  • FIG. 11 is a cross-sectional view showing a laminated structure of the ITO layer according to the fifth embodiment of the present disclosure.
  • the laminated structure of the ITO layer shown in FIG. 11 includes a first ITO layer 127a and a second ITO layer 127b.
  • the oxygen concentration in the film-forming gas is reduced from 1.1% to 0.3% at a rate of 0.09% / 5 nm on the photoelectric conversion layer 126.
  • it can be obtained by forming an ITO layer having a thickness of 50 nm.
  • the crystallite size of the second ITO layer 127b laminated at the position farthest from the photoelectric conversion layer 126 becomes larger than the crystallite size of the first ITO layer 127a closest to the photoelectric conversion portion.
  • Example 1 after the first ITO layer is formed, the film formation is temporarily stopped, the oxygen concentration in the film forming gas is changed to an oxygen concentration suitable for forming the second ITO layer, and the inside of the chamber is formed. After the oxygen concentration of the above is stabilized, the second ITO layer is formed.
  • Example 5 since the ITO layer is continuously formed by gradually changing the flow rate of oxygen gas without stopping the film formation, the formation step of the ITO layer can be performed in a short time.
  • the counter electrode 127 may include three or more ITO layers.
  • the ITO layer closest to the photoelectric conversion layer 126 is the first ITO layer 127a.
  • the second ITO layer 127b is one of two or more ITO layers excluding the first ITO layer 127a.
  • the second ITO layer 127b may be the ITO layer farthest from the photoelectric conversion layer 126. That is, another ITO layer may be included between the first ITO layer 127a and the second ITO layer 127b.
  • an ITO layer that is farther from the photoelectric conversion layer 126 than the second ITO layer 127b may be provided.
  • the lower surfaces of the electrode terminal 124 and the pixel electrode 122 may be located at the same height in the thickness direction.
  • the electrode terminals 124 and the pixel electrodes 122 may be provided on the uppermost surface of the insulating layer 121 whose uppermost surface is flat.
  • the film thickness of the first ITO layer 127a and the film thickness of the second ITO layer 127b may be equal to each other.
  • the film thickness of the first ITO layer 127a may be larger than the film thickness of the second ITO layer 127b.
  • This disclosure can be used for, for example, a camera or a distance measuring device.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Selon un aspect, la présente invention concerne un dispositif d'imagerie pourvu d'électrodes de pixel, de contre-électrodes et d'une couche de conversion photoélectrique située entre les électrodes de pixel et les contre-électrodes. Les contre-électrodes comprennent : une première couche d'oxyde d'indium-étain présentant une première surface principale et une seconde surface principale qui est sur le côté opposé à la première surface principale et qui est plus proche de la couche de conversion photoélectrique que ne l'est la première surface principale ; et une seconde couche d'oxyde d'indium-étain disposée sur la première surface principale de la première couche d'oxyde d'indium-étain. La taille des cristallites de la seconde couche d'oxyde d'indium-étain est supérieure à la taille des cristallites de la première couche d'oxyde d'indium-étain.
PCT/JP2020/047087 2020-01-23 2020-12-17 Dispositif d'imagerie WO2021149414A1 (fr)

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WO2024018717A1 (fr) * 2022-07-20 2024-01-25 パナソニックＩｐマネジメント株式会社 Procédé d'inspection et procédé de fabrication d'élément d'imagerie

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JPS56129384A (en) * 1980-03-14 1981-10-09 Fuji Xerox Co Ltd Light receipt element of thin film type and manufacture
JPS62122282A (ja) * 1985-11-22 1987-06-03 Hitachi Ltd 受光素子
JPS63170974A (ja) * 1987-01-08 1988-07-14 Fujitsu Ltd イメ−ジセンサ及びその製造方法
JPH02213090A (ja) * 1989-02-13 1990-08-24 Sharp Corp 薄膜ｅｌパネルおよびその製造方法
JP2011187937A (ja) * 2010-02-09 2011-09-22 Fujifilm Corp 光電変換素子及び撮像素子並びにそれらの駆動方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129384A (en) * 1980-03-14 1981-10-09 Fuji Xerox Co Ltd Light receipt element of thin film type and manufacture
JPS62122282A (ja) * 1985-11-22 1987-06-03 Hitachi Ltd 受光素子
JPS63170974A (ja) * 1987-01-08 1988-07-14 Fujitsu Ltd イメ−ジセンサ及びその製造方法
JPH02213090A (ja) * 1989-02-13 1990-08-24 Sharp Corp 薄膜ｅｌパネルおよびその製造方法
JP2011187937A (ja) * 2010-02-09 2011-09-22 Fujifilm Corp 光電変換素子及び撮像素子並びにそれらの駆動方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024018717A1 (fr) * 2022-07-20 2024-01-25 パナソニックＩｐマネジメント株式会社 Procédé d'inspection et procédé de fabrication d'élément d'imagerie

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