WO2021147170A1 - 一种多行扫led灰度切换显示方法及系统 - Google Patents

一种多行扫led灰度切换显示方法及系统 Download PDF

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WO2021147170A1
WO2021147170A1 PCT/CN2020/082229 CN2020082229W WO2021147170A1 WO 2021147170 A1 WO2021147170 A1 WO 2021147170A1 CN 2020082229 W CN2020082229 W CN 2020082229W WO 2021147170 A1 WO2021147170 A1 WO 2021147170A1
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data
gray
display
low
grayscale
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PCT/CN2020/082229
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English (en)
French (fr)
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张若平
宋霄
蒋召宇
何书专
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南京浣轩半导体有限公司
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Priority to US17/252,194 priority Critical patent/US11295657B2/en
Publication of WO2021147170A1 publication Critical patent/WO2021147170A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Definitions

  • the present invention relates to the field of LED display technology, and more specifically, to a method and system for multi-line scanning LED gray scale switching display.
  • LED As a new type of lighting material, LED has the advantages of long life, low power consumption, small size, safety and reliability. At present, it has been widely used in lighting, display screens and other equipment. With the development of small dot pitch LED technology and gray-scale modulation technology, LED displays are now able to display more delicate and lifelike images and pictures. A small pitch LED display will place more light-emitting diodes on a relatively small light board. In order to improve the efficiency of the chip and save the cost of building the screen, a constant current source chip with multi-line scanning is generally used to control each A light-emitting diode. Therefore, the display algorithm of the driver chip plays a key role in whether the LED display screen can produce high-quality images.
  • the gray scale of the LED display screen There are two ways to control the gray scale of the LED display screen: one is to change the current that flows. Generally, the LED tube allows a continuous working current of about 20 mA. Except for the saturation of the red LED, the gray scale of other LEDs is basically the same as the current flow. The passing current is proportional; the other method is to use the visual inertia of the human eye, and use the pulse width modulation method to achieve gray-scale control, that is, to periodically change the light pulse width, as long as the repeated lighting period is short enough, the human eye It is not that the light-emitting pixels are shaking.
  • the present invention provides a multi-line scanning LED gray-scale switching display method And the system, it can still guarantee a higher refresh rate and gray level in the case of a large number of line scans, and at the same time, in the case of low gray scale display, it can solve the problem of low gray pitting, low gray dark and relatively low gray. Problems such as poor low gray linearity greatly improve the display effect.
  • Step 1 Obtain the gray level and gray data of the LED, the gray data K is the binary value corresponding to the gray level;
  • Step 2 Set the compensation level. According to the compensation level, add a compensation value to the gray data K to obtain the gray data K′, K′ is the gray data after the compensation process, and the compensation value is compared with the actual circuit response time The brightness loss caused by it is offset;
  • Step 3 According to the refresh rate of the LED, divide the compensated gray data K′ into high effective data and low effective data.
  • the bit width N of the low effective data is used to divide the complete display clock cycle into 2 N groups for display ,
  • the bit width M of the high-order valid data means that there are 2 M clock cycles in each group of sub-cycles after division;
  • Step 4 Set the merging level Q, determine whether the merging level Q is 0 or 2 Q is not greater than the high effective data K MSB , if it is, the gray data K′ after the compensation processing is broken up and displayed, otherwise the compensation The processed gray data K′ is combined and displayed to realize the switching display of the compensated gray data K′;
  • Step 5 According to the number of rows R and the number of channels C displayed by the LED constant current drive chip, repeat steps 1 to 4 R*C times to form a complete display output.
  • step 2 if the gray data K′ after the compensation process exceeds the maximum gray data at the corresponding gray level, the gray data K′ after the compensation process is limited to the maximum gray data at the corresponding gray level. Degree data to avoid data overflow.
  • step 3 Furthermore, the division of the compensated gray data K′ in step 3 includes the following steps:
  • step 4 performing the scatter display of the compensated gray data K′ includes the following steps:
  • the remaining low-order valid data K LSB is divided into 2 N groups for display according to the dichotomy, and the remaining low-order valid data is evenly distributed to the divided groups.
  • step 4 the combined display of the compensated gray data K′ includes the following steps:
  • the integer part is divided into 2 N groups and displayed according to the dichotomy, and the number of groups represented by the integer part is the part displayed in the 2 N groups;
  • the remainder is allocated to the sub-periods of the first group for display, that is, the extra lighting time is allocated to the first group for display.
  • assigning the remaining low-order valid data K LSB to 2 N groups according to the dichotomy method for display includes the following steps:
  • assigning the integer part to 2 N groups according to the dichotomy method includes the following steps:
  • generating an N-bit counter CNT to record the number of divided groups includes the following steps:
  • the counter CNT records the number of divided groups
  • the high and low bits of the counter CNT are exchanged to generate a new dichotomy group number, which is used to compare the low valid data K LSB and the integral part of the compensated gray data K′.
  • a multi-line scanning LED gray-scale switching display system is used to implement the above method and complete the display of all gray-scale data.
  • a multi-line scanning LED gray scale switching display system includes:
  • Shift register receive the gray data input from the outside, and store the gray data in SRAM;
  • SRAM receiving and storing grayscale data, and sending the grayscale data to the data processing module
  • Data processing module receiving gray data, processing the data, and sending the processed data to the comparator
  • Counter record the number of clocks of packet data, and send the number of clocks to the comparator
  • the comparator receives the data from the data processing module and the counter, compares the data, and outputs PWM pulses.
  • the present invention provides a SC-PWM algorithm.
  • This method breaks up the display period when displaying higher gray levels, improves the overall display refresh rate, and uses the principle of dichotomy to make the lighting period as possible Evenly distributed to each frame of the picture, so that the displayed image is more delicate and clear; and when the lower gray level is displayed, the gray level is merged to solve the problems of low gray pitting, dark and poor linearity, so that Under the condition of a large number of line scans, a higher gray level can still be guaranteed.
  • the present invention provides a low gray compensation method to compensate for the gray loss caused by the response time of the analog circuit, so that the actual display gray value can be closer to the theoretical value, and it can be used in conjunction with the SC-PWM algorithm. Makes the low gray scale display effect greatly improved.
  • Figure 1 is a schematic diagram of the process of the method of the present invention.
  • Fig. 2 is a schematic diagram of low gray scale compensation of the present invention
  • Fig. 3 is a schematic diagram of the dispersing principle of the present invention.
  • Fig. 4 is a schematic diagram of the dispersing principle of the present invention.
  • FIG. 5 is a schematic diagram of the comparison between the merged PWM and the dispersed PWM of the present invention.
  • Fig. 6 is a schematic diagram of the principle of the dichotomous distribution of the present invention.
  • Figure 7 is a schematic diagram of the dichotomy of the present invention for allocating low effective data
  • Fig. 8 is a schematic diagram showing the low-gray-level non-merging display of the traditional scatter algorithm
  • FIG. 9 is a schematic diagram of the low gray scale combined display of the present invention.
  • Figure 10 is a schematic diagram of the multi-line scanning display of the present invention.
  • Fig. 11 is a schematic diagram of the constant current LED display module of the present invention.
  • the chip can support as many line scans as possible to achieve the effect of power saving, but once the line scans increase, the unit lighting on time will be less than 10ns Or shorter, because the analog circuit needs response time, it is likely that the actual turn-on time is much shorter than the theoretical time, causing various display problems such as dark, pitting, and poor linearity at low gray levels.
  • the unit lighting on-time must be longer, so that only 12 or 13-bit gray levels can be available, and The refresh rate cannot be very high. In the end, the types and gradients of the colors displayed will be very limited, and the picture quality will be relatively poor, which will affect the display effect.
  • the present invention provides a multi-line scan LED grayscale switching display method and system, which can be applied to HX80XX series chips.
  • the present invention can be based on the acquired LED grayscale data, grayscale level, merge level, refresh rate and compensation level. , Perform PWM break-up and merging, in the case of a large number of line scans, still ensure a higher refresh rate and gray level, and at the same time in the case of low gray display, it can solve low gray pitting and low gray shift Problems such as darkness and poor low gray linearity greatly improve the display effect.
  • the present invention mainly includes the following steps:
  • Step 1 Obtain the gray level and gray level data of the LED.
  • the number of gray levels have L bits
  • the corresponding gray level data value is K.
  • the gray level L refers to the LED screen from the darkest to the brightest
  • the gray level data K is the binary value corresponding to the gray level L, which is any specific value included in the range of the gray level L, representing a certain brightness , The larger the value, the higher the brightness.
  • the gray data K is a specific value in the 2 L range
  • the L bit gray data ⁇ D L-1 ,D L-2 ...D 1 ,D 0 ⁇ is sent to the chip by the LED sending card
  • ⁇ D L-1 ,D L-2 ...D 1 ,D 0 ⁇ is the gray value Binary representation, from left to right, from the highest bit to the lowest bit of the data
  • the binary representation is 111000.
  • Step 2 Set the compensation level S, perform compensation processing on the gray data K according to the compensation level S, convert the gray data K into gray data K′, K′ is the gray data after the compensation process, and the compensation process It is to add a compensation value to the gray data K to obtain the compensated gray data K′ whose bit width is still L. K′ is still a binary number, and the compensation value of the compensation process is determined by the compensation level.
  • the compensation level in the compensation process is an adjustable parameter.
  • the value of the compensation level is set by the display time of a single gray scale, and the display time period is determined by the control panel of the LED screen. Therefore, the loss under various periods can be simulated according to the software. Time, combined with the actual selected display time period to pre-set appropriate values, for example, set to 0, 1, 2, ..., S, which greatly improves the flexibility and operability of the system.
  • the maximum gray value is the maximum gray level data under a certain gray level, for example, the gray level data corresponding to the 14-bit gray level varies from 0 to 16383, then the maximum gray value is 16383, the gray level It is manually set. If the gray level is set too high, but the display algorithm is not set well, that is, the display gray data adopts a single solution, such as the global use of the break up algorithm or the merge algorithm, which will cause some problems. The display effect is not good under the conditions, for example, the single dispersing algorithm has poor display effect due to insufficient brightness under low gray scale conditions, and the low refresh rate of the merged algorithm under medium and high gray conditions results in insufficient picture fineness.
  • the display time under low gray levels will be very short.
  • the grayscale data is 1, if the grayscale display time is 10ns under ideal conditions, but the actual analog circuit switch requires a certain response time, so the actual lighting time is likely to be much less than the theoretical value, which will cause low grayscale Dots, low gray and dark, and poor low gray linearity. Therefore, after obtaining the gray scale and gray scale data of the LED, it is necessary to perform compensation processing on the gray scale data K.
  • the compensation processing on the gray scale value is essentially to compensate the PWM pulse brightness that is lost within the response time of the analog circuit.
  • the gray data K is 1, and the gray data K is compensated with a gray value of 1, and the gray data K is converted into the compensated gray data K′ with a value of 2, then the actual circuit response time will bring The brightness loss will be offset with the increased compensation value, so that the theoretical gray value can be displayed truly, so the display effect at low gray levels will be greatly improved.
  • Step 3 According to the LED refresh rate P, divide the compensated gray data K′ into M-bit high-order effective data and N-bit low-order effective data.
  • the bit width N of the low-order effective data is used to display the complete clock
  • the period is divided into 2 N groups for display.
  • the bit width M of the high-order valid data means that there are 2 M clock periods in each group of sub-periods after division.
  • the display clock period of gray data K′ is 2 L , then 2 L display clocks
  • the display clock period is the unit display time, that is, the display time of a gray scale.
  • the display clock period corresponds to the gray scale data.
  • the refresh rate means the refresh rate that can be further improved on the basis of the basic refresh rate.
  • the target refresh rate refers to the LED display refresh rate to be obtained.
  • the unit of refresh rate is Hertz (Hz), which is defined as the number of screen changes per second, such as
  • the refresh rate is 1920Hz, which means the screen changes 1920 times per second.
  • the refresh rate refers to the multiple based on the minimum refresh rate.
  • the minimum refresh rate is the basic refresh rate in multiples, such as the minimum refresh rate that a designed chip can display. 960Hz, then the refresh rate of 960Hz is called refresh rate 1, then the refresh rate of 1920Hz is called refresh rate 2, and the refresh rate of 3840Hz is called refresh rate 4.
  • the refresh rate of 1920Hz and 3840Hz can be our goal Refresh rate, the target refresh rate is determined by the refresh rate and the basic refresh rate.
  • the number of bits of the above-mentioned low-order valid data and high-order valid data refers to the bit width. No matter what the value of the low-order valid data and the high-order valid data is, they are broken up into the number of groups corresponding to the bit width of the low-order valid data.
  • the value of the lower valid data means that there will be several groups that can get an extra unit of time to light up. In the merge mode, the lower valid data is not looked at, but is allocated according to the integer and the remainder.
  • Dividing high-order effective data and low-order effective data is used to improve the refresh rate of LED.
  • the more digits of low-order effective data the more groups of display clock cycle, and the higher the refresh rate of LED.
  • the LED screen has 60 frames per second.
  • the refresh rate defined here is P, the refresh 2 0, 2 1 ... 2 P ⁇ magnification may be set based on the refresh rate, since the gradation data are binary data, and refresh rate, so that the refresh rate is a multiple of 2.
  • M JP, P ⁇ J, the number of display clock cycles of each group of sub-periods is 2 JP ,
  • the number of sub-period groups is 2 N groups.
  • the size of the high effective data bit width M and the low effective data bit width N are adjusted by adjusting the value of the refresh magnification P, so as to realize the change of the refresh rate.
  • the bit width of the displayed gray data is 15 bits, and the value of the gray data is 16400.
  • the 15-bit grayscale data is first divided into high-order effective data and low-order effective data, such as 10-bit high-order effective data and 5-bit low-order effective data.
  • the bit width of the low-order effective data determines this
  • the number of scattered sub-period groups, the 5-bit low-order effective data breaks the gray-scale data into 25 groups of sub-periods. Since the high-order data plays a leading role in the display, the data in the high-order bits will be repeated in each group of sub-periods.
  • Display in 25 groups of sub-periods, there are 2 10 displayable clock cycles in each group of sub-periods. If the high-bit data with a bit width of 10 is 10'b10_0000_0000, it represents 512 units of lighting time, which will be in the sub-period. It is displayed first, because the maximum value of the 10-bit high-bit data is 1023, the binary is 10'b11_1111_1111, and the displayable clock cycle of each group is 1024, so the low-bit data will be allocated to these 32 groups of sub-cycles to determine the last one Brightness and darkness per unit time.
  • the low-bit data K LSB is 16, and the binary is 5'b1_0000, it will be allocated to the 32 sub-periods according to the principle of dichotomy, that is, the 16 low-bit data will be allocated to the first 1, 17, 9, 25, ..., 31 groups in sequence , The assigned sub-period will show an extra lighting time.
  • the extra lighting time means that there will be one more clock lighting time in this cycle.
  • the gray scale data is 67 and broken into 32 groups, then according to the principle of break up distribution, there will be 29 groups showing 2 gray levels, and there will be The 3 groups display 3 gray levels. These three groups are the so-called 1 extra light-up time, and the light-up time is the display clock cycle.
  • the division of gray scale data by the SC-PWM algorithm can be changed according to specific needs.
  • the set refresh rate and the basic refresh rate are obtained, and the target refresh rate is obtained by multiplying them, and an appropriate number of breakup groups is selected according to the target refresh rate.
  • Determine the low effective data bit width and then subtract the low effective data bit width from the total bit width to obtain the high effective data bit width.
  • the display refresh rate needs to be set to 3840Hz, and the frame rate is required to be 60Hz.
  • the degree data is divided into 9-bit high-order data and 6-bit low-order effective data.
  • Step 4 Set the merge level Q, determine whether the merge level Q is 0 or 2 Q is not greater than the high-order effective data K MSB , if it is, display the high-order effective data K MSB separately, and display the high-order effective data K MSB in 2 N groups respectively , That is, displayed in each divided group of sub-periods, and the remaining low-order effective data K LSB is divided into 2 N groups for display according to the dichotomy; otherwise, combined display is performed, and the high-order effective data K MSB is not displayed in 2 N groups.
  • K′[N+Q-1:Q] is divided into 2 N groups for display according to the dichotomy, and K′[Q-1 :0] is assigned to the first group of sub-period display
  • K′[N+Q-1:Q] represents the integer part of gray data K′ divided by 2 N
  • K′[Q-1:0] represents gray
  • the remainder part of the degree data K′ divided by 2 N the integer part is the number of groups displayed in the 2 N group, each display clock cycle is 2 Q , and the remainder part is the number of additional clock cycles displayed in the first group, even if The grayscale data is merged and displayed, but it is grouped according to the method of dispersing display.
  • the merged display here is to disperse and group the compensated grayscale data K′ according to the merged display rule, by reducing the sub-period display group
  • the number realizes the combination of display clock cycles in each group of sub-periods, thereby increasing the number of display clock cycles in each group of sub-periods, ensuring that the display clock cycles in each group of sub-periods can meet the display requirements of the combined level, such as 15-bit
  • the gray data is divided into the form of 10-bit high-level effective data + 5-bit low-level effective data.
  • the integer part we calculated is 19, but the data is still divided into 32 groups, but only 19 of these 32 groups will have data display , The remaining 13 groups are not displayed.
  • the dichotomy distributes the number of groups divided by an N-bit counter CNT.
  • CNT[0:N-1] is less than K LSB , the group needs to display an extra clock cycle of the PWM pulse. Otherwise, the group does not need to display an extra clock cycle of the PWM pulse, CNT[0:N-1] represents the number of dichotomy groups, used to achieve dichotomy distribution.
  • CNT[0:N-1] is less than K′[N+Q-1:Q]
  • the group will display 2 Q unit time PWM pulses, otherwise the group does not need to display PWM pulses
  • the first group of sub-periods will display additional K'[Q:0] clock cycles of PWM pulses.
  • the merging level Q represents the minimum clock cycle of each group of display after the total gray data is broken up, and can be set to 2 0 , 2 1 , ..., 2 Q display clock cycles.
  • the setting rule of the merge level is related to the displayed gray level. In this embodiment, when the gray level is 13 bits or less, the merge level is set to 0; when the gray level is 14 bits, the merge level is set to 1; When the gray level is 15 bits, the merge level is set to 2; when the gray level is 16 bits, the merge level is set to 3.
  • the sub-grayscale data displayed in each group is less than the set value or the combined level is 0, then the sub-grayscale data will be combined and displayed, and the high-level effective data K MSB will not be displayed; otherwise, the scattered display will be performed, that is, the high-level effective data.
  • K MSB is displayed in each group of sub-periods, and K MSB unit time PWM pulses are displayed in each group of sub-periods.
  • the sub-gray scale data refers to the high effective data K MSB in each clock cycle. When the sub-gray scale data is lower than the set value, it means that the screen brightness is not enough, which may cause the picture to be unclear.
  • the brightness can be increased by combining the display;
  • the gray scale data is higher than the set value, it indicates that the screen brightness is sufficient, so by breaking up the display, increase the display refresh rate of the screen, thereby improving the smoothness of the picture.
  • aggregation level Q is set to 1, when the data is not less than 2 active high is performed when a broken display, active high when the data is less than 21:00 will be merged display.
  • the gray data with a bit width of 15 is grouped according to the 10+5 grouping mechanism
  • the high effective data will be less than 2, which is considered to be a low gray value at this time, so it will be used
  • the high-level effective data will be greater than 2, which is considered to be a high gray value at this time, so the method of split display will be used.
  • the combined PWM display is to display all 40 clock periods together, followed by the extinguishing time of 40 clock periods.
  • the break up PWM display divides a total of 40 clock cycles into 4 groups of displays. After every 10 clock cycles, the display turns off for 10 clock cycles, so that the original one cycle display becomes 4 smaller cycles. Display, so the refresh rate is increased by 4 times, so the broken PWM method can increase the refresh rate of the LED display without affecting the grayscale.
  • the program divides the gray data into 16 groups, which can be counted by a 4-bit counter.
  • the counting range is 4'b0000 to 4'b1111, that is, 0 to 15 in decimal, using CNT[3: 0], and CNT[0:3] swaps the high and low bits of CNT[3:0] to generate a new group called the dichotomy group number.
  • the dichotomy group number is less than K LSB , the group A number will be allocated to realize the dichotomy of 3 and 5 for the low-order valid data K LSB.
  • this dichotomy distribution method makes the LED screen lighting cycle as even as possible, which is very friendly to the visual effect of the human eye.
  • the display refresh rate can be changed by changing the refresh rate to change the number of scattered sub-cycles.
  • the 10-bit high-order effective data is 10'b00_0000_0010, which is 2
  • the 5-bit low-order effective data is 5'b0_0001, which is the decimal 1.
  • the high-order effective data K MSB value is 2, which is less than the merge level 2 2 , so it needs to be combined display.
  • the maximum display clock period of each group of sub-periods is set to 2 Q , that is, each group of display has 4 display clock cycles.
  • K′[6:2] K′[6:2]
  • 2'b01 which is 1 in decimal.
  • the gray data is broken up into 4 groups, and each group is allocated 4 gray data.
  • the traditional PWM algorithm distributes the gray data evenly in sequence. In each group, this dispersing mechanism has a short display clock cycle of each sub-cycle when the gray value is small. Because the analog circuit cannot quickly respond to the change of the digital signal, plus the inter-channel of each chip Or there may be differences between different chips, so there will be pitting or dark conditions on the LED display.
  • the low gray level merging mechanism of the present invention can enhance the display under low gray level.
  • the minimum gray value of each group of scattered sub-periods is set to 2 Q. When the gray value is less than 2 Q * the number of scattered groups, the combined display is adopted. Method, otherwise use the method of breaking up the display.
  • each gray value change if combined with the low gray compensation function mentioned before, can further improve the display effect to adapt to different line scans, gray levels and so on.
  • the display clock cycle itself in each group of sub-cycles is already relatively long, and a higher refresh rate can be provided by generating more groups by breaking up.
  • Step 5 According to the number of rows R and the number of channels C displayed by a single LED constant current drive chip, repeat the above steps 1-4 R*C times to form a complete display output, where R and C are positive integers.
  • the number of channels refers to the number of pixels driven by a chip. For example, an LED driver chip has 16 channels, and each row changes, there will be 16 pixels in each row.
  • the line chip For multi-line scanning and multi-channel LED constant current driver chips, after the sub-period data of each line is displayed, the line chip will perform a line-feed display operation. The channels will not interfere with each other and display at the same time until all the data is displayed. data.
  • each broken-up sub-period the sub-period display of each line is sequentially performed from 1 to 64 lines, and then the line scanning of the next sub-period is performed. Display, when the last line of data of the last sub-period is displayed, one frame of data is fully displayed.
  • each output data is 16 bits wide
  • These 16 groups of data are processed by the SC-PWM algorithm of the data processing module, and the current displayed clock cycle is recorded by a 16bit counter.
  • Count compare the data value processed by the data processing module with the data in the counter through 16 16-bit comparators, and output the PWM pulse of each channel.
  • the counter records the number of clock cycles currently displayed.
  • the value of the gray data represents the time of how many clock cycles need to be lit, so the number of clocks of the counter and the gray data should be compared.
  • the value of the counter is smaller than the gray data, it means that the display has not been completed, and the display continues.
  • the value of the counter is larger than the gray scale data, it means that it has been displayed, and it will no longer be displayed. The channels will not interfere with each other and display at the same time until all the data is displayed.

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Abstract

一种多行扫LED灰度切换显示方法及系统，该方法在显示较高灰度时，将显示周期打散，使得点亮的周期尽可能平均地分配到每一帧画面里，在显示较低灰度时进行灰度的合并，并通过灰度补偿方法，弥补模拟电路响应时间带来的灰度损失，可以在行扫数较多的情况下，仍然保证较高的刷新率和灰度等级，同时在低灰度显示的情况下，解决低灰麻点、低灰偏暗和较差的低灰线性度等问题，实现显示画面效果的提升。

Description

一种多行扫LED灰度切换显示方法及系统 技术领域
本发明涉及LED显示技术领域，更具体地说，涉及一种多行扫LED灰度切换显示方法及系统。
背景技术
LED作为一种新型的照明材料，具有寿命长，功耗低，体积小，安全可靠等优点。目前在照明，显示屏等设备中已经广泛使用。随着小点距LED技术和灰度调制技术的发展，LED显示屏目前已经能够显示出更加细腻逼真的图像与画面。小点距的LED显示屏会在一个比较小的灯板上放置较多的发光二极管，为了提高芯片的使用效率和节省构建屏幕的成本，一般会使用多行扫的恒流源芯片来控制每个发光二极管。因此，驱动芯片的显示算法对于LED显示屏是否能够产生高质量的图像起到了关键作用。
控制LED显示屏灰度的方法有两种：一种是改变流过的电流，一般LED管允许连续工作电流在20毫安左右，除了红色LED有饱和现象外，其他LED灰度基本上与流过的电流成比例；另一种方法是利用人眼的视觉惰性，用脉宽调制方法来实现灰度控制，也就是周期性改变光脉冲宽度，只要这个重复点亮的周期足够短，人眼是感觉不到发光象素在抖动。
在灰度调制算法中，常用到两种算法。一种是常见的内置PWM算法，即集中显示LED的亮/暗时间，来体现不同灰阶的显示效果。但该方法存在一个主要的缺陷，就是显示刷新率会很低，因为相邻两个发光周期的时间间隔会比较长，如果帧频比较低的话，可能会有人眼容易感觉到的闪烁现象。另一种方法是SPWM(scrambled-PWM)算法，即将一组数据的导通时间打散成许多个时间段，以增加LED显示屏的整体刷新率。这种方法虽然改善了内置PWM算法刷新率低的缺点，但是低灰度下本来点亮的导通时间就非常短，如果再将这些灰度打散，每一组时钟周期内的单个灰度值很可能显示不完整，从而出现低灰麻点、低灰偏暗和较差的低灰线性度。当灰度显示时钟频率较高时，这一现象尤为明显。
发明内容
1.要解决的技术问题
针对现有技术中存在的对于多行扫恒流源芯片的刷新率不足、灰度等级不高、低灰度显示效果差等问题，本发明提供了一种多行扫LED灰度切换显示方法及系统，它可以在行扫数较多的情况下，仍然保证较高的刷新率和灰度等级，同时在低灰度显示的情况下，能够解决低灰麻点、低灰偏暗和较差的低灰线性度等问题，使得显示画面的效果大大提升。
2.技术方案
本发明的目的通过以下技术方案实现。
一种多行扫LED灰度切换显示方法，其特征在于，包括以下步骤：
步骤1：获取LED的灰度等级和灰度数据，灰度数据K为灰度等级所对应的二进制数值；
步骤2：设定补偿等级，根据补偿等级，将灰度数据K加上一个补偿数值，得到灰度数据K′，K′即为补偿处理后的灰度数据，将补偿值与实际电路响应时间所带来的亮度损失相抵消；
步骤3：根据LED的刷新倍率，将补偿处理后的灰度数据K′划分为高位有效数据和低位有效数据，低位有效数据的位宽N用于将完整的显示时钟周期划分成2 N组显示，高位有效数据的位宽M表示划分后每组子周期有2 M个时钟周期；
步骤4：设定合并等级Q，判断合并等级Q是否为0或者2 Q是否不大于高位有效数据K MSB，如果是，则对补偿处理后的灰度数据K′进行打散显示，否则对补偿处理后的灰度数据K′进行合并显示，实现对补偿处理后的灰度数据K′的切换显示；
步骤5：根据LED恒流驱动芯片显示的行数R和通道数C，重复R*C次步骤1至步骤4，形成完整的显示输出。
进一步的，在步骤2中，如果补偿处理后的灰度数据K′超过对应灰度等级下的最大灰度数据，则补偿处理后的灰度数据K′限定为对应灰度等级下的最大灰度数据，避免数据溢出。
更进一步的，步骤3中对补偿处理后的灰度数据K′的划分包括以下步骤：
获取LED的刷新倍率和帧频；
将刷新倍率乘以基础刷新率，得到目标刷新率；
将目标刷新率除以帧频得出低位有效数据位宽N；
将灰度等级减去低位有效数据位宽N，得出高位有效数据位宽M。
更进一步的，步骤4中对补偿处理后的灰度数据K′进行打散显示包括以下步骤：
将高位有效数据K MSB分别在2 N组中显示，将高位有效数据进行打散显示；
将剩余的低位有效数据K LSB按照二分法分配到2 N组中显示，将剩余的低位有效数据均匀分配到划分的分组中。
更进一步的，步骤4中对补偿处理后的灰度数据K′进行合并显示包括以下步骤：
将补偿处理后的灰度数据K′除以2 N得出整数部分与余数部分；
将整数部分按照二分法分配到2 N组中显示，整数部分所代表的组数是2 N组中显示的部分；
将余数部分分配到第一组的子周期中显示，即将额外的点亮时间分配到第一组中显示。
更进一步的，将剩余的低位有效数据K LSB按照二分法分配到2 N组中显示包括以下步骤：
生成一个N位的计数器CNT，用于记录划分的组数；
判断CNT[0:N-1]是否小于低位有效数据K LSB，若小于，则在该组显示一个额外时钟周期的PWM脉冲，否则该组不显示一个额外时钟周期的PWM脉冲。
更进一步的，将整数部分按照二分法分配到2 N组中显示包括以下步骤：
生成一个N位的计数器CNT，用于记录划分的组数；
判断CNT[0:N-1]是否小于补偿处理后的灰度数据K′的整数部分数值，如果小于，则在该组显示2 Q个时钟周期的PWM脉冲，否则该组不需要显示PWM脉冲。
更进一步的，生成一个N位的计数器CNT记录划分的组数包括以下步骤：
计数器CNT记录划分的组数；
将计数器CNT的高低位互换，生成新的二分法组数，新的二分法组数用于对低位有效数据K LSB以及补偿处理后的灰度数据K′的整数部分数值进行比较。
一种多行扫LED灰度切换显示系统，用于执行上述方法，完成对所有灰度数据的显示。
进一步的，一种多行扫LED灰度切换显示系统包括：
移位寄存器，接收外部输入的灰度数据，将灰度数据存储到SRAM中；
SRAM，接收并存储灰度数据，将灰度数据发送到数据处理模块；
数据处理模块，接收灰度数据，对数据进行处理，将处理后的数据发送到比较器中；
计数器，记录分组数据的时钟个数，将时钟个数发送到比较器中；
比较器，接收数据处理模块与计数器中的数据，对数据进行比较，输出PWM脉冲。
3.有益效果
相比于现有技术，本发明的优点在于：
本发明提供了一种SC-PWM算法，该方法在显示较高灰度时，将显示周期打散，提高了整体的显示刷新率，并通过二分法分配的原理，使得点亮的周期尽可能平均地分配到每一帧画面里，使显示出的图像更加细腻清晰；而在显示较低灰度时进行灰度的合并，解决了低灰麻点、偏暗和线性度差等问题，使得在行扫数较多的条件下，仍然可以保证较高的灰度等级。同时本发明给出了一种低灰补偿方法，用于弥补因为模拟电路响应时间带来的灰度损失，使得实际的显示灰度值与理论值可以更加接近，可配合SC-PWM算法使用，使得低灰度显示效果大大提高。
附图说明
图1为本发明的方法流程示意图；
图2为本发明的低灰度补偿示意图；
图3为本发明的打散原理示意图；
图4为本发明的打散原理示意图；
图5为本发明的合并PWM和打散PWM的对比示意图；
图6为本发明的二分法分配原理示意图；
图7为本发明的二分法分配低位有效数据示意图；
图8为传统打散算法低灰度不合并显示示意图；
图9为本发明的低灰度合并显示示意图；
图10为本发明的多行扫显示示意图；
图11为本发明的恒流LED显示模块示意图。
具体实施方式
对于LED常用的多行扫的恒流源芯片来说，该芯片能够支持尽量多的行扫数，从而实现节电的效果，但是一旦行扫数增加，单位点亮导通时间会低于10ns或更短，由于模拟电路需要响应时间，很有可能造成实际的点亮导通时间比理论时间小很多，造成低灰度下偏暗、麻点、线性度差等各种显示问题。目前市面上的产品，如果行扫数达到64扫，想要保证较好的低灰效果，单位点亮导通时间就必须较大，这样的话只能有12或13位的灰度等级，并且刷新率不能很高。最终显示出的颜色的种类和渐变度就会很有限，画面质量就会比较差，影响显示效果。
本发明提供了一种多行扫LED灰度切换显示方法及系统，可以应用于HX80XX系列芯片中，本发明可根据获取到的LED灰度数据、灰度等级、合并等级、刷新倍率以及补偿等级，进行PWM的打散和合并，在行扫数较多的情况下，仍然保证较高的刷新率和灰度等级，同时在低灰显示的情况下，能够解决低灰麻点、低灰偏暗和较差的低灰线性度等问题，使得显示画面的效果大大提升。
下面结合说明书附图和具体的实施例，对本发明作详细描述。
如图1所示，本发明主要包括以下步骤：
步骤1：获取LED的灰度等级和灰度数据，这里令灰度等级位数有L位，对应的灰度数据的值为K，灰度等级L指的是LED屏幕从最暗到最亮所具有的变化数量，代表灰度数据的位宽，而灰度数据K为灰度等级L所对应的二进制数值，是包含在灰度等级L范围里的任意一个具体数值，代表一个确定的亮度，数值越大代表亮度越高，如灰度等级有L位，那么该LED屏幕具有2 L种颜色的变化，灰度数据K就是2 L范围内的一个具体数值，L位的灰度数据{D L-1,D L-2...D 1,D 0}由LED发送卡送给芯片，{D L-1,D L-2...D 1,D 0}为灰度值的二进制表示方式，从左到右依次为数据的最高位至最低位，所显示的灰度范围为0至2 L-1，如当L＝6时，灰度范围是0-63，0-63中的任意数值都可以用{D 5,D 4,D 3,D 2,D 1,D 0}，如果十进制的灰度数据56， 那么二进制的表示就是111000，此时D 5＝1，D 4＝1，D 3＝1，D 2＝0，D 1＝0，D 0＝0，由于{D L-1,D L-2...D 1,D 0}是二进制表示方式，所以每一位的数据范围只能是0或1。
步骤2：设定补偿等级S，根据补偿等级S，对灰度数据K进行补偿处理，将灰度数据K转化成灰度数据K′，K′即为补偿处理后的灰度数据，补偿处理是将灰度数据K加上一个补偿数值，得到位宽依然为L的补偿处理后的灰度数据K′，K′依然为二进制数，补偿处理的补偿数值由补偿等级决定。
补偿处理中的补偿等级为可调参数，补偿等级的数值由单个灰度的显示时间来设置，而显示时间的周期由LED屏幕的控制面板决定，因此可以根据软件仿真出各种周期下损失的时间，结合实际选择的显示时间周期来预先设定合适的数值，例如设定为0、1、2、……、S，这使得系统的灵活性和可操作性大大提高。当外部输入的灰度数据K较大时，若加上补偿的灰度值已经超过最大灰度值，则补偿处理后的灰度数据K′保持在最大灰度值处不变，避免数据溢出，最大灰度值就是在某一灰度等级下的最大灰度数据，例如14位的灰度等级所对应的灰度数据变化范围为0至16383，那么最大灰度值就是16383，灰度等级由人为设定，如果灰度等级设定过高，但显示的算法设定的不好，即显示灰度数据全采取单一的解决方法，例如全局采用打散算法或合并算法，就会在一些条件下出现显示效果不佳的现象，例如单一的打散算法在低灰度条件下由于亮度不足导致显示效果不良，合并算法在中高灰条件下的刷新率不高导致的画面细腻感不足。
如图2所示，当行扫数较多，且灰度等级较高时，低灰度下的显示时间就会非常的短。在灰度数据为1时，假如理想情况下灰度的显示时间为10ns，但是实际模拟电路开关需要一定的响应时间，所以实际点亮的时间很可能远远小于理论值，会造成低灰麻点、低灰偏暗和较差的低灰线性度等问题。因此获取到LED的灰度等级和灰度数据后，需要对灰度数据K进行补偿处理，对灰度数值进行补偿处理实质上是对模拟电路响应时间内丢失的PWM脉冲亮度进行补偿。例如灰度数据K为1，对其进行灰度值为1的补偿处理，将灰度数据K转化成值为2的补偿处理后的灰度数据K′，那么实际电路响应时间所带来的亮度损失就会和增加的补偿数值相抵消，使得能够真实的显示出理论的灰度数值，因此低灰度下的显示效果会大大提高。
步骤3：根据LED的刷新倍率P，将补偿处理后的灰度数据K′划分为M位的高位有效数据和N位的低位有效数据，低位有效数据的位宽N用于将完整的显示时钟周期划分成2 N组显示，高位有效数据的位宽M表示划分后每组子周期有2 M个时钟周期，例如灰度数据K′的显示时钟周期为2 L，则将2 L个显示时钟周期分成2 N组显示，每组2 M个时钟周期，其中M+N＝L，M和N均为正整数。显示时钟周期为单位显示时间，即一个灰度的显示时间，显示时钟周期 与灰度数据对应，如灰度等级是14位，那么可显示的总周期就是固定的16384个时钟周期，灰度数据是80，就会点亮80个时钟周期，熄灭16304个时钟周期；灰度数据是8000，就会点亮8000个时钟周期，熄灭8384个时钟周期。刷新倍率表示在基础刷新率的基础上可以进一步提升的刷新倍数，目标刷新率指所要得到的LED显示刷新率，刷新率的单位是赫兹(Hz)，定义为每秒钟画面变化的次数，比如刷新率为1920Hz，代表画面1秒变化了1920次，刷新倍率指建立在最小刷新率基础上的倍数，最小刷新率即为基础刷新率，单位是倍，比如设计的芯片可显示的最小刷新率为960Hz，那么这个960Hz的刷新率就称为刷新倍率1，那么1920Hz的刷新率就称为刷新倍率2，3840Hz的刷新率就称为刷新倍率4，1920Hz和3840Hz的刷新率可以是我们的目标刷新率，目标刷新率由刷新倍率和基础刷新率决定。上述的低位有效数据和高位有效数据的位数指的是位宽，无论低位有效数据和高位有效数据的数据本身值为多少，都被打散成低位有效数据的位宽所对应的组数，而低位有效数据的值代表将有几组能获得额外的一个单位时间的点亮，在合并模式下不看低位有效数据，而是根据整数和余数来分配。
划分高位有效数据和低位有效数据用于提高LED的刷新率，低位有效数据的位数越多，显示时钟周期分的组数越多，LED的刷新率也就越高。例如LED的画面一秒钟有60帧，15位的灰度数据如果不分组显示，那么显示刷新率就是60*1＝60赫兹，如果划分成10位高位有效数据，5位低位有效数据，即将15位的灰度数据分成了2 5组显示，那么显示刷新率就是60*32＝1920赫兹，显示刷新率大大提高，LED显示的图像质量也越高。所以根据LED屏幕所要求的显示刷新率来划分M+N的形式，以达到提高刷新率的要求。
这里将刷新倍率定义为P，刷新倍率可设定为基础刷新率的2 0，2 1...2 P倍，由于灰度数据和刷新率均为二进制数，因此刷新倍率为2的倍数。令上述划分的每组子周期的最大个数为2 J，这里的个数指显示时钟周期的个数，则M＝J-P，P<J，每组子周期的显示时钟周期个数为2 J-P，子周期的组数为2 N组。通过调节刷新倍率P的值来调整高位有效数据位宽M和低位有效数据位宽N的大小，从而实现刷新率的变化。
如图3和图4所示，显示的灰度数据的位宽为15位，灰度数据的值为16400。根据SC-PWM算法，首先会将15位的灰度数据分为高位有效数据和低位有效数据，比如10位的高位有效数据和5位的低位有效数据，其中低位有效数据的位宽决定这打散的子周期组数，5位低位有效数据将灰度数据打散成2 5组子周期，由于高位的数据对于显示起着主导作用，因此高位中的数据将会在每组子周期中重复显示，在2 5组子周期中，每组子周期中都有2 10个可显示时钟周期，如果位宽为10的高位数据为10’b10_0000_0000，代表512个单位点亮时间，会在子周期中先显示出来，由于10位高位数据最大值为1023，二进制为10’b11_1111_1111，而每 一组的可显示时钟周期为1024，所以低位数据会被分配到这32组子周期中来决定最后一个单位时间的亮暗。如果低位数据K LSB为16，二进制为5’b1_0000，则按照二分法的原则分配到32个子周期中，即16个低位数据会依次分配到第1、17、9、25、……、31组中，被分配到的子周期会显示一个额外的点亮时间。
额外点亮时间指该周期会多出一个时钟的点亮时间，如灰度数据是67，打散成32组，那么根据打散分配的原则，会有29组显示2个灰度，会有3组显示3个灰度，这三组就是所谓的1个额外的点亮时间，点亮时间即显示时钟周期。
本发明中SC-PWM算法对灰度数据的划分可根据具体的需求改变，首先获取设定的刷新倍率和基础刷新率，相乘得到目标刷新率，根据目标刷新率选取适当的打散组数，确定低位有效数据位宽，然后将总位宽减去低位有效数据位宽得出高位有效数据位宽，如显示刷新率需要设定为3840Hz，帧频要求为60Hz，计算公式为刷新率＝帧频*打散组数，则需要打散成3840/60＝64组，则低位有效数据位宽为6位，高位有效数据为15位灰度数据减去6位低位有效数据，15位灰度数据被划分为9位高位数据和6位低位有效数据，通过对灰度数据划分的灵活调整，提高了算法的鲁棒性。
步骤4：设定合并等级Q，判断合并等级Q是否为0或者2 Q是否不大于高位有效数据K MSB，如果是，则进行打散显示，将高位有效数据K MSB分别在2 N组中显示，即在划分出的每组子周期里显示，将剩余的低位有效数据K LSB按照二分法分配到2 N组中显示；否则进行合并显示，高位有效数据K MSB在2 N组中都不显示，即在划分出的每组子周期里全都不显示，而是将二进制数据K′[N+Q-1:Q]按照二分法分配到2 N组中显示，并将K′[Q-1:0]分配到第一组子周期显示，K′[N+Q-1:Q]代表灰度数据K′除以2 N得出的整数部分，K′[Q-1:0]代表灰度数据K′除以2 N得出的余数部分，整数部分为2 N组中有显示的组数，每组显示时钟周期为2 Q，余数部分为第一组额外显示的时钟周期数，即使对灰度数据进行合并显示，却还是按照打散显示的方法进行分组，这里的合并显示是将补偿处理后的灰度数据K′按照合并显示规则进行打散分组，通过减少子周期的显示组数实现每组子周期中的显示时钟周期的合并，从而增加每组子周期中的显示时钟周期数，保证每组子周期中的显示时钟周期都能满足合并等级的显示要求，比如15位的灰度数据分成10位高位有效数据+5位低位有效数据的形式，我们计算出的整数部分是19，但仍然把数据分成了32组，只不过是这32组中只有19组会有数据显示，其余的13组没有显示。
二分法分配通过一个N位的计数器CNT计数划分的组数，当进行打散显示时，如果CNT[0:N-1]小于K LSB时，则该组需要显示一个额外时钟周期的PWM脉冲，否则该组不需要显示一个额外时钟周期的PWM脉冲，CNT[0:N-1]代表二分法组数，用于实现二分法分配。 当进行合并显示时，如果CNT[0:N-1]小于K′[N+Q-1:Q]，则该组会显示2 Q个单位时间的PWM脉冲，否则该组不需要显示PWM脉冲，另外第一组的子周期会显示额外的K′[Q:0]个时钟周期的PWM脉冲。
合并等级Q表示总灰度数据被打散后每一组显示的最小时钟周期，可设定为2 0、2 1、……、2 Q个显示时钟周期。合并等级的设定规则与显示的灰度等级有关，在本实施例中，当灰度等级为13位以下时，合并等级设定为0；灰度等级为14位时，合并等级设定为1；灰度等级为15位时，合并等级设定为2；灰度等级为16位时，合并等级设定为3。如果每个分组中显示的子灰度数据小于设定值或合并等级为0，则进行对子灰度数据进行合并显示，不显示高位有效数据K MSB；否则进行打散显示，即高位有效数据K MSB分别在每组子周期内显示，每组子周期里都会显示K MSB个单位时间的PWM脉冲。子灰度数据指每组时钟周期内的高位有效数据K MSB，当子灰度数据低于设定值时，说明屏幕亮度不够，可能会造成画面不清晰，因此通过合并显示增加亮度；当子灰度数据高于设定值时，说明屏幕亮度足够，因此通过打散显示，提高屏幕的显示刷新率，从而提高画面流畅度。例如合并等级Q设定为1，当高位有效数据不小于2 1时会进行打散显示，当高位有效数据小于2 1时会进行合并显示。假设位宽为15的灰度数据，根据10+5的分组机制分组，当这个15位数据本身比较小的时候，高位有效数据就会小于2，认为此时属于低灰度值，因此会采用合并显示的方法，当15位数据本身比较大的时候，高位有效数据就会大于2，认为此时属于高灰度值，因此会采用打散显示的方法。
如图5所示，以显示总时钟周期为80个单位时间，显示灰度数据为40为例，合并PWM显示就是将40个时钟周期全部集中到一起显示，之后是40个时钟周期的熄灭时间。而打散PWM显示则是将总共40个时钟周期平均分成了4组显示，每显示10个时钟周期后熄灭10个时钟周期，这样将原来的一个周期的显示变成的4个更小周期的显示，所以刷新率提高了4倍，因此打散的PWM方法可以在不影响灰度的情况下提高LED显示屏的刷新率。
如图6所示，该方案将灰度数据分为16组，可以用一个4位的计数器来计数，计数范围为4’b0000到4’b1111，即十进制的0到15，用CNT[3:0]来表示，而CNT[0:3]就是将CNT[3:0]的高低位互换，生成一个新的小组叫做二分法组数，当二分法组数序号小于K LSB时，该组会分配到一个数，以此实现低位有效数据K LSB为3和5的二分法分配。
如图7所示，这种二分法分配方式使得LED屏幕点亮的周期尽可能平均，对人眼的视觉效果非常友好。这样总的显示时间仍然为1024t*32＝32768t，在点亮的总时间不变的前提下，刷新率提高了32倍。显示刷新率的改变可通过改变刷新倍率来改变打散的子周期数实现。
以位宽为15位的灰度数据为例，合并等级Q设定为2，K′＝15’b000_0000_0100_0001， 即十进制65。按照M＝10，N＝5的分组规则划分，则10位高位有效数据为10’b00_0000_0010，即十进制的2，5位低位有效数据为5’b0_0001，即十进制的1。根据判断机制，高位有效数据K MSB值为2，小于合并等级2 2，所以要合并显示，合并显示时，每组子周期的最大显示时钟周期设置为2 Q，即显示的每一组都有4个显示时钟周期。因为65/4＝16，余数为1，整数部分为K′[N+Q-1:Q]就是K′[5+2-1:2]＝K′[6:2]，此为数字电路中位宽的标准定义，K′[0]代表15位数据K′的第1位，K′[6:2]代表K′的第7位到第3位，为5’b10000，即十进制的16，而余数部分为K′[Q-1:0]就是K′[2-1:0]＝K′[1:0]，为2’b01，即十进制的1。因此，将整数部分16按照二分法分到32组当中，每组显示4个单位灰度，余数1分到第一组的子周期显示，即第一子周期会显示4+1＝5个单位灰度，总灰度为4*16+1＝65不变。
如图8的传统PWM算法所示，以4位灰度数据为例，将灰度数据打散成4组，每组分配4个灰度数据，传统PWM算法按顺序将灰度数据均匀分配到每组中，这种打散的机制在灰度值较小的情况下每组子周期的显示时钟周期很短，由于模拟电路不能快速反应数字信号的变化，再加上每颗芯片的通道间或者不同芯片之间可能会有差异性，所以会在LED显示屏上出现麻点或者偏暗的状况。本发明的低灰度合并机制可以增强低灰度下的显示，设置每组打散子周期最小的灰度值为2 Q，当灰度值小于2 Q*打散组数时采用合并显示的方法，否则采用打散显示的方法。
如图9所示，设置合并等级Q为1，即每组打散的子周期中的显示时钟周期必须不小于2 1，灰度数据为1除外，打散组数为4。所以当灰度值小于2*4时，采用合并显示的方法，这样通过集中显示增加通道的打开时间，有效缓解脉宽过短带来的低灰麻点或者亮度偏暗等问题，能够清楚的看出每一个灰度值的变化，若配合之前所提到的低灰度补偿功能，可以进一步提高显示效果，以适应不同的行扫数，灰度等级等等。而当随着灰度值的增加，每组子周期中的显示时钟周期本身已经比较长，可通过打散生成较多的组数来提供较高的刷新率。
步骤5：根据单个LED恒流驱动芯片显示的行数R和通道数C，重复R*C次上述步骤1-4，形成完整的显示输出，其中R、C为正整数。通道数是指一颗芯片所驱动的像素点的个数，如一个LED驱动芯片有16个通道，那么每次换行时，每行就会有16个像素点跟着一起变化。对于多行扫多通道的LED恒流驱动芯片，在每一行的子周期数据显示完毕后，会由行芯片进行换行显示操作，各个通道互相之间不会干扰并且同时显示，直至显示完所有的数据。
如图10所示，以64行扫，32打散为例，在每一个打散的子周期中，从1至64行依次进行每行的子周期显示，然后进行下一个子周期的行扫显示，当最后一个子周期的最后一行数据显示完毕后，一帧数据便进行了完整的显示。
如图11所示，假设每个输出的数据为16位的位宽，首先通过移位寄存器将外部串行输 入的64行扫16通道所有灰度显示数据存储到SRAM中，然后每一次从SRAM里拿出某行行扫时16个通道所需要的所有数据，总计16x16bit，这16组数据经过数据处理模块的SC-PWM算法的相关数据处理，通过一个16bit的计数器记录当前显示的时钟周期个数，将数据处理模块处理后的数据值与计数器中的数据通过16路的16bit比较器进行比较，输出每个通道的PWM脉冲，计数器记录的是当前显示的时钟周期个数。灰度数据的值代表需要点亮多少个时钟周期的时间，所以要比较计数器的时钟个数和灰度数据，当计数器的值比灰度数据小的时候就表示没显示完，继续显示，当计数器的值比灰度数据大的时候就表示已经显示完了，便不再显示。各个通道互相之间不会干扰并且同时显示，直至显示完所有的数据。
以上示意性地对本发明创造及其实施方式进行了描述，该描述没有限制性，在不背离本发明的精神或者基本特征的情况下，能够以其他的具体形式实现本发明。附图中所示的也只是本发明创造的实施方式之一，实际的结构并不局限于此，权利要求中的任何附图标记不应限制所涉及的权利要求。所以，如果本领域的普通技术人员受其启示，在不脱离本创造宗旨的情况下，不经创造性的设计出与该技术方案相似的结构方式及实施例，均应属于本专利的保护范围。此外，“包括”一词不排除其他元件或步骤，在元件前的“一个”一词不排除包括“多个”该元件。产品权利要求中陈述的多个元件也可以由一个元件通过软件或者硬件来实现。第一，第二等词语用来表示名称，而并不表示任何特定的顺序。

Claims (10)

  1. 一种多行扫LED灰度切换显示方法，其特征在于，包括以下步骤：
    步骤1：获取LED的灰度等级L和灰度数据K；
    步骤2：设定补偿等级，根据补偿等级，将灰度数据K加上一个补偿数值，得到灰度数据K′，K′即为补偿处理后的灰度数据；
    步骤3：根据LED的刷新倍率，将补偿处理后的灰度数据K′划分为高位有效数据和低位有效数据；
    步骤4：设定合并等级Q，判断合并等级Q是否为0或者2 Q是否不大于高位有效数据K MSB，如果是，则对补偿处理后的灰度数据K′进行打散显示，否则对补偿处理后的灰度数据K′进行合并显示；
    步骤5：根据LED恒流驱动芯片显示的行数R和通道数C，重复R*C次步骤1至步骤4，形成完整的显示输出。
  2. 根据权利要求1所述的一种多行扫LED灰度切换显示方法，其特征在于：在步骤2中，如果补偿处理后的灰度数据K′超过对应灰度等级下的最大灰度数据，则将补偿处理后的灰度数据K′限定为对应灰度等级下的最大灰度数据。
  3. 根据权利要求1所述的一种多行扫LED灰度切换显示方法，其特征在于：步骤3中对补偿处理后的灰度数据K′的划分包括以下步骤：
    获取LED的刷新倍率和帧频；
    将刷新倍率乘以基础刷新率，得到目标刷新率；
    将目标刷新率除以帧频得出低位有效数据位宽N；
    将灰度等级减去低位有效数据位宽N，得出高位有效数据位宽M。
  4. 根据权利要求1或3所述的一种多行扫LED灰度切换显示方法，其特征在于，步骤4中对补偿处理后的灰度数据K′进行打散显示包括以下步骤：
    将高位有效数据K MSB分别在2 N组中显示；
    将剩余的低位有效数据K LSB按照二分法分配到2 N组中显示。
  5. 根据权利要求4所述的一种多行扫LED灰度切换显示方法，其特征在于，步骤4中对补偿处理后的灰度数据K′进行合并显示包括以下步骤：
    将补偿处理后的灰度数据K′除以2 N得出整数部分与余数部分；
    将整数部分按照二分法分配到2 N组中显示；
    将余数部分分配到第一组的子周期中显示。
  6. 根据权利要求5所述的一种多行扫LED灰度切换显示方法，其特征在于，将剩余的低位有效数据K LSB按照二分法分配到2 N组中显示包括以下步骤：
    生成一个N位的计数器CNT，记录划分的组数；
    判断CNT[0:N-1]是否小于低位有效数据K LSB，若小于，则在该组显示一个额外时钟周期的PWM脉冲，否则该组不显示一个额外时钟周期的PWM脉冲。
  7. 根据权利要求6所述的一种多行扫LED灰度切换显示方法，其特征在于，将整数部分按照二分法分配到2 N组中显示包括以下步骤：
    生成一个N位的计数器CNT，记录划分的组数；
    判断CNT[0:N-1]是否小于补偿处理后的灰度数据K′的整数部分数值，如果小于，则在该组显示2 Q个时钟周期的PWM脉冲，否则该组不需要显示PWM脉冲。
  8. 根据权利要求7所述的一种多行扫LED灰度切换显示方法，其特征在于，生成一个N位的计数器CNT记录划分的组数包括以下步骤：
    计数器CNT记录划分的组数；
    将计数器CNT的高低位互换，生成新的二分法组数。
  9. 一种多行扫LED灰度切换显示系统，其特征在于：用于执行权利要求1-8中任一项所述的方法步骤。
  10. 根据权利要求9所述的一种多行扫LED灰度切换显示系统，其特征在于，包括：
    移位寄存器，接收外部输入的灰度数据，将灰度数据存储到SRAM中；
    SRAM，接收并存储灰度数据，将灰度数据发送到数据处理模块；
    数据处理模块，接收灰度数据，对灰度数据进行处理，将处理后的数据值发送到比较器中；
    计数器，记录当前显示的时钟周期个数，将时钟周期个数发送到比较器中；
    比较器，接收数据处理模块的数据值与计数器中的时钟周期个数，对两者进行比较，输出PWM脉冲。
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