WO2021139676A1 - 电致发光显示面板及其驱动方法和显示装置 - Google Patents

电致发光显示面板及其驱动方法和显示装置 Download PDF

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Publication number
WO2021139676A1
WO2021139676A1 PCT/CN2021/070448 CN2021070448W WO2021139676A1 WO 2021139676 A1 WO2021139676 A1 WO 2021139676A1 CN 2021070448 W CN2021070448 W CN 2021070448W WO 2021139676 A1 WO2021139676 A1 WO 2021139676A1
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Prior art keywords
gate line
display panel
display area
electrically connected
compensation circuit
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PCT/CN2021/070448
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English (en)
French (fr)
Inventor
王苗
郭永林
张锴
肖云升
魏昕宇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/630,236 priority Critical patent/US20220284852A1/en
Publication of WO2021139676A1 publication Critical patent/WO2021139676A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to an electroluminescent display panel, a driving method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • Organic electroluminescent diode Organic electroluminescent diode
  • Traditional OLED mobile phone screens can no longer meet people's visual needs, so full screens have emerged.
  • the full screen increases the screen-to-body ratio, reduces the marginal space, and brings great enjoyment to people's vision.
  • external devices such as cameras and earpieces can no longer be placed on the edge of the screen, which gives birth to special-shaped screens such as Liu Haiping, which solves the problem of external device placement.
  • Alien area shows abnormal problems. Because the number of pixel units in the irregular display area and the normal display area are different, the grid line load of the irregular display area and the normal display area is different, resulting in uneven display brightness in the irregular display area and the normal display area of the screen.
  • an electroluminescent display panel including at least one regular display area and at least one special-shaped display area, and the display panel further includes an electroluminescent display panel located in the at least one regular display area and the at least one special-shaped display area.
  • Each of the at least one load compensation circuit further includes at least one first load compensation circuit, the at least one first load compensation circuit is electrically connected to one of the at least one gate line, and the at least one first load compensation circuit is relatively electrically connected to the at least one first load compensation circuit.
  • the pixel units connected to the same gate line are electrically connected to the side of the same gate line that is closer to the signal input end of the at least one gate line.
  • the display panel further includes at least one second load compensation circuit and at least one gate line signal output electrically connected to the at least one gate line in each of the at least one special-shaped display area. Terminal, wherein the at least one second load compensation circuit is electrically connected to one of the at least one gate line, and the at least one second load compensation circuit is opposite to the pixel that is electrically connected to the same gate line.
  • the unit is electrically connected to a side of the same gate line that is closer to the signal output end of the at least one gate line.
  • the at least one first load compensation circuit includes at least one first capacitor
  • the at least one second load compensation circuit includes at least one second capacitor
  • the at least one first capacitor includes a plurality of first capacitors, and the plurality of first capacitors are closer to the at least one gate line signal of the pixel unit electrically connected to the same gate line. One side of the input terminal is connected in parallel.
  • the at least one second capacitor includes a plurality of second capacitors that are closer to the gate line signal output terminal of the pixel unit electrically connected to the same gate line. Parallel on one side.
  • the electroluminescent display panel further includes a voltage stabilizing signal terminal, wherein the first capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate is electrically connected to the at least one One of the gate lines, the second electrode plate is electrically connected to the voltage stabilizing signal terminal.
  • the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate is electrically connected to one of the at least one gate line, and the fourth electrode plate is electrically connected to The voltage stabilizing signal terminal.
  • the first electrode plate and the at least one gate line are arranged in the same layer and made of the same material.
  • the third electrode plate and the at least one gate line are arranged in the same layer and made of the same material.
  • the electroluminescent display panel further includes a voltage stabilizing signal terminal, wherein the first capacitor includes a first electrode plate and a second electrode plate, and one of the at least one gate line is multiplexed The first electrode plate is used as the first capacitor, and the second electrode plate is electrically connected to the voltage stabilizing signal terminal.
  • the second capacitor includes a third plate and a fourth plate, one of the at least one gate line is multiplexed as the third plate of the second capacitor, so The fourth electrode plate is electrically connected to the voltage stabilizing signal terminal.
  • the pixel unit includes at least one transistor located on a substrate, each of the at least one transistor includes a gate, an active layer, a source and a drain, and the second plate and the The fourth electrode plate and the source and drain of the at least one transistor are arranged in the same layer and made of the same material.
  • the pixel unit includes at least one transistor on a substrate, each of the at least one transistor includes a gate, an active layer, a source, and a drain, and the electroluminescent display panel further It includes: a flat layer, which is located on the side of the at least one transistor away from the substrate; and a light-emitting element, which includes a first electrode, an organic light-emitting layer, and a light-emitting element which are sequentially arranged on the flat layer in a direction away from the substrate.
  • the second electrode wherein the second electrode plate and the fourth electrode plate and one of the active layer of the at least one transistor, the first electrode and the second electrode of the light-emitting element are arranged in the same layer and adopt Made of the same material.
  • the pixel units in the at least one irregular display area and the at least one regular display area are arranged in multiple rows, and the pixels in each row of the multiple rows of pixel units in the at least one regular display area
  • the number of units is greater than or equal to the number of pixel units in each row of the multiple rows of pixel units in the at least one irregular display area
  • the at least one first load compensation circuit is electrically connected to the pixel unit of the same gate line Located in the same row, the at least one second load compensation circuit and the pixel unit electrically connected to the same gate line are located in the same row.
  • each of the at least one gate line includes a first end and a second end opposite to the first end, wherein the first end is electrically connected to a gate line signal input end, so The second terminal is electrically connected to a gate line signal output terminal.
  • each of the at least one gate line includes a first end and a second end opposite to the first end, wherein the first end and the second end are electrically connected to two A gate line signal input terminal, and the gate line signal output terminal is electrically connected to a part of the gate line except the first terminal and the second terminal.
  • the capacitance values of the first capacitor and the second capacitor are equal.
  • the capacitance values of the first capacitor and the second capacitor are equal to the equivalent capacitance value of one pixel unit.
  • the total number of capacitors in the at least one first load compensation circuit and/or the at least one second compensation circuit is calculated by the following formula:
  • N represents the number of capacitors
  • C1 represents the equivalent capacitance value of a row of pixel units in the regular display area
  • C2 represents the equivalent capacitance value of a row of pixel units in the irregular display area
  • C represents the capacitance value of a capacitor.
  • a display device including the electroluminescent display panel described above and a driving circuit for driving the electroluminescent display panel.
  • FIG. 1 is a top view of a partial structure of an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a part of the structure of the electroluminescent display panel in FIG. 1 along the C-C' section line;
  • FIG. 3 is a simulation waveform diagram of the gate line signal at positions A and B in FIG. 1 of the display panel adopting the related special-shaped display area gate line load compensation scheme;
  • FIG. 4 is a simulation waveform diagram of gate line signals at positions A and B in FIG. 1 of a display panel adopting a gate line load compensation scheme in a special-shaped display area according to an embodiment of the present disclosure
  • FIG. 5 is a schematic top view of a special-shaped display area of an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 6 is an enlarged view of a partial area of a special-shaped display area of an electroluminescent display panel according to an embodiment of the present disclosure
  • FIG. 7 is a top view of a partial structure of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a partial top view of the structure in which the gate lines of the irregular display area in the electroluminescent display panel according to the embodiment of the present disclosure are double-ended input signals;
  • FIG. 9 is a top view of a partial structure of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic cross-sectional view of a part of the structure of the electroluminescent display panel in FIG. 9 along the D-D' section line;
  • FIG. 11 is a simulation waveform diagram of gate line signals at positions A and B in FIG. 9 of a display panel adopting a gate line load compensation scheme in an irregular display area according to an embodiment of the present disclosure.
  • FIG. 12 is a top view of a partial structure of an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 1 is a top view of a partial structure of a single shaped display area in an electroluminescent display panel according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional view of a part of the structure of the electroluminescent display panel in FIG. 1 along the C-C' section line.
  • the electroluminescent display panel includes at least one regular display area 2 and at least one irregular display area 3.
  • the electroluminescent display panel also includes at least one gate line 5 and at least one pixel unit 1 in each of at least one regular display area 2 and at least one irregular display area 3, and at least one gate line 5 respectively (directly (Or indirectly) at least one gate line signal input terminal electrically connected (wherein the direction marked by arrow 10 shows the direction of the gate line signal input terminal).
  • the number of pixel units 1 in at least one regular display area 2 is greater than the number of pixel units 1 in at least one irregular display area 3 (that is, the distribution density of pixel units 1 in at least one regular display area 2 is greater than at least one irregular display area The distribution density of pixel unit 1 in 3).
  • the electroluminescent display panel further includes at least one first load compensation circuit 4 in each of the at least one special-shaped display area 3.
  • the first load compensation circuit 4 is electrically connected to one of the at least one gate line 5, and is electrically connected to the gate line signal input terminal 10 of the same gate line, relative to the pixel unit electrically connected to the same gate line.
  • the special-shaped display area 3 is the area where the external configuration devices of the display panel such as the camera and the earpiece are integrated on the display panel. Since the external configuration device occupies a part of the display area of the display panel, the distribution of pixel units 1 in this part of the display area is irregular compared to the distribution of pixel units 1 in the regular display area 2, so this part of the display area is called an irregular display Zone 3. As shown in FIG. 1, in the regular display area 2, the pixel units 1 are arranged in a regular matrix, and the number of pixel units 1 in each row is the same, that is, the number of pixel units 1 electrically connected to each gate line 5 is the same.
  • the pixel units 1 are arranged irregularly, and the number of pixel units 1 in each row is not all the same, that is, the number of pixel units 1 electrically connected to each gate line 5 is not all the same.
  • the number of pixel units 1 electrically connected to any gate line 5 in the irregular display area 3 is less than the number of pixel units 1 electrically connected to any gate line 5 in the regular display area 2, resulting in the irregular display area 3.
  • the load of each gate line 5 in the regular display area 2 is usually less than the load of any gate line 5 in the regular display area 2, which will cause the unevenness of the luminous brightness of the pixel unit 1 in the irregular display area 3 and the pixel unit 1 in the regular display area 2 , Affect the display effect.
  • a certain gate line in the irregular display area and a gate line in the regular display area are in the same vertical direction (that is, the same column of pixel units).
  • the pixel units on) (the pixel units at position A and position B in Fig. 1) have different light-emitting brightness.
  • FIG. 3 is a simulation waveform diagram of the gate line signal at positions A and B in FIG. 1 of the display panel adopting the related special-shaped display area gate line load compensation scheme.
  • the waveforms of the signals on the grid lines monitored at positions A and B are different.
  • the waveform difference is specifically reflected in the fact that the signals on the grid lines at positions A and B change from high-level signals to The duration of low-level signals varies greatly.
  • FIG. 4 is a simulation waveform diagram of gate line signals at positions A and B in FIG. 1 of a display panel adopting a gate line load compensation scheme in an irregular display area according to an embodiment of the present disclosure.
  • the first load compensation circuit 4 in this embodiment can load the gate lines 5 in the special-shaped display area 3 in advance. Compensation, so that the signal waveforms on the gate lines at positions A and B are closer, as shown in Figure 4.
  • the gate line load compensation scheme of the present disclosure is adopted to reduce the difference in the light-emitting brightness of the pixel unit 1 at positions A and B.
  • Tf represents the signal from high level The time it takes for the signal to become a low-level signal
  • Tf1, Tf2, and Tf3 in the position A in the special-shaped display area refer to the signals on the grid lines collected three times at the position A; the average Tf of the position A in the special-shaped display area refers to the three collected at the position A
  • the ultimate goal of load compensation for the grid lines in the irregular display area is to make the signal waveforms on the grid lines at positions A and B more consistent, that is, position A is relative to position B, and the tf of the signal on the grid line
  • the load compensation scheme of the gate line of the irregular display area in this embodiment enables the waveform of the signal on the gate line at the position A of the irregular display area to be relative to the waveform of the signal on the gate line at the position B of the regular display area The change is smaller, so as to achieve a better load compensation effect for the grid lines in the irregular display area.
  • the electroluminescent display panel of the present disclosure by providing the special-shaped display area 3, the problem of the placement of the external configuration devices is solved when the edge space of the display panel is small, and the pixels are opposed to each other in the special-shaped display area 3.
  • the unit 1 is provided with at least one first load compensation circuit 4 on the side closer to the gate line signal input terminal 10.
  • the first load compensation circuit of the present disclosure is The load compensation circuit 4 can perform load compensation on the gate line 5 in the irregular display area 3 in advance, so that the load of the gate line 5 in the irregular display area 3 is more consistent with the load of the gate line 5 in the regular display area 2, thereby making the irregular display area 2 more consistent.
  • the light-emitting brightness of the pixel unit 1 in the display area 3 and the regular display area 2 tends to be uniform, which improves the uniformity of the display brightness of the display panel and improves the display effect of the display panel.
  • the first load compensation circuit 4 may include a first capacitor, that is, the first load compensation circuit 4 may be a capacitor, and the capacitance value of the capacitor of each of the at least one first load compensation circuit 4 is equal.
  • the load compensation of the gate line 5 in the special-shaped display area 3 is carried out by a capacitor.
  • the preparation process is simple, and on the other hand, the capacitance value of the capacitor is easy to adjust during the preparation process, so that the gate line 5 can be more accurately compensated for load.
  • the first load compensation circuit 4 includes one capacitor as an example for description, but the present disclosure is not limited to this, and the first load compensation circuit 4 may include multiple first capacitors.
  • the number of the first load compensation circuit 4 (ie, the first capacitor) electrically connected to each gate line 5 is based on the load of each gate line 5 in the irregular display area 3 and the regular display area 2, and each The capacitance value of the first capacitor is set.
  • the load of each grid line 5 in the regular display area 3 can be calculated first, and the load of each grid line 5 in the irregular display area 3 before load compensation is calculated, and then the irregular display area 3 and the regular display area can be calculated. 2
  • the load difference of the gate line 5, the number of capacitors is calculated according to the load difference and the capacitance value of each capacitor, and finally the load of each gate line 5 in the irregular display area 3 is the same as the gate line 5 in the regular display area 2.
  • the load is basically the same.
  • the first capacitor includes a first electrode plate and a second electrode plate, and the second electrode plate can be electrically connected to a voltage stabilizing signal terminal (for example, to provide a driving voltage for an OLED in a pixel unit).
  • a part of the gate line 5 can be reused as the first plate of the first capacitor.
  • the pixel unit 1 includes at least one transistor on a substrate, and each of the at least one transistor includes a gate, an active layer, a source, and a drain.
  • the second plate of the first capacitor and the source and drain of the at least one transistor are arranged in the same layer and made of the same material.
  • the electroluminescent display panel of the present disclosure further includes: a flat layer (not shown), which is located on a side of the at least one transistor away from the substrate; and a light-emitting element, which includes a flat layer on the flat layer in a direction away from the substrate.
  • the first pole, the organic light-emitting layer and the second pole are provided.
  • the second electrode plate may be provided in the same layer as one of the active layer of the at least one transistor and the first electrode and the second electrode of the light-emitting element and made of the same material.
  • the second plate of the first capacitor can also be arranged on the same layer as any of the active layer of the transistor, the first electrode (anode) of the light-emitting element, and the second electrode (cathode) of the light-emitting element, and the same material is used. production.
  • the second electrode plate uses these film materials and the same layer as these film layers, its load adjustment effect is significantly smaller than that of the second electrode plate and the source and drain electrodes of the transistor in the same layer and use the same material.
  • the second electrode plates of different first capacitors can be made of the same layer with different film layers and made of the same material, so as to perform more accurate load compensation on the gate line.
  • the materials for making the gate lines, the active layer, the source and drain electrodes, and the first electrode and the second electrode of the light-emitting element can be materials required for making corresponding structures in the related art.
  • the load of the gate line 5 mainly refers to the load caused by the pixel unit electrically connected to the gate line 5.
  • the load caused by the pixel unit mainly includes the gate line 5 and each transistor in the pixel drive circuit.
  • the load between the source and drain film layer 7 (including the source and drain) of the transistor, the active layer film layer 8 (including the active layer), and the gate line 5 and the anode film layer 9 first The load formed between the electrodes).
  • the two plates of the first capacitor can also be prepared separately, and the first plate of the first capacitor is electrically connected to the gate line 5, and the second plate is electrically connected to the voltage-stabilizing signal terminal.
  • the first plate of the first capacitor and the gate line are arranged in the same layer and are made of the same material.
  • the second plate of the first capacitor is arranged in the same layer with any one of the source and drain of the transistor, the anode of the light-emitting element, and the cathode of the light-emitting element, and the same material is used.
  • the pixel units 1 in at least one irregular display area 3 and at least one regular display area 2 are arranged in multiple rows, and the pixel units in each row of the multiple rows of pixel units in at least one regular display area 2
  • the number is greater than or equal to the number of pixel units in each row of the multiple rows of pixel units in at least one irregular display area 3, that is, the number of pixel units in at least one regular display area 2 is less than that in at least one irregular display area 3.
  • at least one first load compensation circuit 4 and the pixel unit electrically connected to the same gate line 5 are located in the same row.
  • At least one irregularly-shaped display area 3 may include an area surrounded by a shape of a ridge 31 having pixel units, and a recessed area between the ridges 31.
  • the recessed area may be a hole or hole structure.
  • FIG. 6 is an enlarged view of a ridge 31 in FIG. 5.
  • a row of pixel units 1 is electrically connected to a gate line 5 correspondingly.
  • the first load compensation circuit 4 includes a plurality of first load compensation circuits 4, and each of the first load compensation circuits 4 is correspondingly disposed at the gate line signal input terminal 10 close to the different-shaped display area 3.
  • a plurality of first load compensation circuits 4 are located on the side of the gate line 5 electrically connected to the pixel unit 1 close to the gate line signal input terminal 10.
  • the first load compensation circuit 4 can also be arranged along the edge of the irregular display area 3, for example, at the boundary between the irregular display area 3 and the regular display area 2. In this way, the screen-to-body ratio of the display area in the special-shaped display area 3 can be further increased, thereby further satisfying people's visual needs.
  • the first load compensation circuit 4 can also be located in any area in the irregular display area 3 where no pixel unit is provided.
  • the specific location of the first load compensation circuit 4 is not limited, as long as it is ensured that the first load compensation circuit 4 is located on the side closer to the gate line signal input terminal 10 relative to the pixel unit 1, that is, the gate
  • the signal input on the line 5 first passes through the first load compensation circuit 4, and then passes through the pixel unit 1, so that the first load compensation circuit 4 performs load compensation on the gate line 5 in advance, and can ensure that the gate line 5 in the special-shaped display area 3
  • the load of is basically the same as the load of the gate line 5 in the regular display area 2.
  • one of the electrically at least one gate line includes a first end 51 and a second end 52.
  • the first terminal 51 is electrically connected to a gate line signal input terminal 10
  • the second terminal 52 is electrically connected to a gate line signal output terminal (as indicated by the arrow 20)
  • the first terminal 51 and the second terminal 52 are electrically connected to two
  • a gate line signal input terminal 10 and a gate line signal output terminal 20 are electrically connected to the gate line except for the first terminal and the second terminal. That is, in the irregular display area 3 and the regular display area 2, a row of pixel units can be driven by a single-side drive or a bilateral drive (as shown in FIG. 8).
  • the light emitting element in the pixel unit 1 may be an organic electroluminescent diode (OLED), a light emitting diode (LED), a micro light emitting diode (Micro LED), or a mini light emitting diode (Mini LED).
  • OLED organic electroluminescent diode
  • LED light emitting diode
  • Micro LED micro light emitting diode
  • Mini LED mini light emitting diode
  • this embodiment also provides a driving method of the electroluminescent display panel.
  • the driving method includes: sequentially supplying a driving signal to at least one gate line in the regular display area 2 and the abnormal display area 3 through a plurality of gate line signal input terminals.
  • a driving signal provides a driving signal to a row of pixel units via one of at least one gate line.
  • the driving signal reaches the pixel unit row after passing through at least one first load compensation circuit through one of the at least one gate line.
  • the drive signal input via the gate line first passes through the first load compensation circuit, and then passes through the pixel unit, so that the gate line in the irregular display area can be compensated for load, so that the The load of the gate line in the display area is more consistent with the load of the gate line in the regular display area.
  • This embodiment also provides an electroluminescent display panel. As shown in FIGS. 9 and 10, on the basis of the display panel in the foregoing embodiment, in this embodiment, at least One second load compensation circuit 6, and at least one second load compensation circuit 6 is electrically connected to one of the at least one gate line 5. Compared to the pixel unit 1, the at least one second load compensation circuit 6 is located closer to the gate line signal output One side of end 20.
  • At least one second load compensation circuit 6 is provided on the basis of providing at least one first load compensation circuit 4 in the foregoing embodiment.
  • the driving signal provided by the gate line signal input terminal 10 passes through the gate line 5 through the at least one first load compensation circuit 4 and the pixel unit 1 in sequence, and then reaches the at least one second load compensation circuit 6.
  • the at least one second load compensation circuit 6 performs further load compensation on the gate lines 5 in the irregular display area 3 on the basis of the at least one first load compensation circuit 4 performing load compensation on the gate lines 5 in the irregular display area 3 in advance.
  • the first load compensation circuit 4 and the second load compensation circuit 6 it is possible to perform further load compensation on the gate line 5 in the special-shaped display area 3 on the basis of the load compensation for the gate line 5 in the special-shaped display area 3 in advance, thereby
  • the load of the gate line 5 in the irregular display area 3 is more consistent with the load of the gate line 5 in the regular display area 2, so that the light-emitting brightness of the pixel unit 1 in the irregular display area 3 and the regular display area 2 tends to be uniform, improving The uniformity of the display brightness of the display panel is improved, and the display effect of the display panel is improved.
  • FIG. 11 shows the simulated signal waveforms on the gate lines at the position A in the irregular display area 3 and the position B in the regular display area 2 after using the grid line load compensation scheme in the irregular display area in this embodiment.
  • the position of the grid line A of the abnormal display area 3 adopts the current load compensation scheme, the load compensation scheme using only the first load compensation circuit, and the load compensation scheme of the first load compensation circuit and the second load compensation circuit.
  • Tf represents the time it takes for the signal to change from a high-level signal to a low-level signal).
  • the load compensation scheme of the gate line of the irregular display area in this embodiment can make the waveform of the gate line signal at the irregular display area A relative to the waveform change of the gate signal at the regular display area B relative to the current scheme and only The scheme of adopting the first load compensation circuit is reduced, thereby achieving a better load compensation effect for the gate lines in the irregular display area.
  • the second load compensation circuit 6 may include one or more second capacitors.
  • the load compensation of the gate line 5 in the special-shaped display area 3 is carried out by a capacitor.
  • the preparation process is simple, and on the other hand, the capacitance value of the capacitor is easy to adjust during the preparation process, so that the gate line 5 can be more accurately compensated for load.
  • the second load compensation circuit 6 includes a second capacitor as an example for description, but the present disclosure is not limited to this, and the second load compensation circuit 6 may include a plurality of second capacitors. The capacitance values of the second capacitor and the first capacitor may be set to be equal.
  • the second capacitor in the second load compensation circuit 6 includes a third electrode plate and a fourth electrode plate.
  • the structure, electrical connection relationship, and material of the third electrode plate may be the same as the structure, electrical connection relationship, and material of the first electrode plate of the first capacitor in the first load compensation circuit 4.
  • the structure, electrical connection relationship, and material of the fourth electrode plate may be the same as the structure, electrical connection relationship, and material of the second electrode plate of the first capacitor in the first load compensation circuit 4.
  • the number of first capacitors in the first load compensation circuit 4 and the number of second capacitors in the second load compensation circuit 6 that are electrically connected to each gate line 5 in the special-shaped display area 3 depends on the size of the load on each gate line 5.
  • An example of setting the capacitance value of each capacitor is as follows. Assume that the load of one pixel unit 1 is 25, the load of one first load compensation circuit 4 is 20, and the load of one second load compensation circuit 6 is 20. In FIG. 9, the pixel unit 1 is ranked 100th along the extension direction of the gate line 5 at position A, and the pixel unit 1 is ranked 150th along the extension direction of the gate line 5 at position B. It is necessary to set the A load compensation circuit 4 and a second load compensation circuit 6 compensate the load at the A position.
  • the capacitor should be placed on the left side of the pixel unit 1. If the left side compensation space is limited, the compensation can be The capacitor is adjusted according to the actual situation and is arranged on the right side of the pixel unit 1 (that is, the gate line signal output side).
  • the capacitance values of the first capacitor and the second capacitor are equal.
  • the capacitance value of the first capacitor and the second capacitor is equal to the equivalent capacitance value of a pixel unit.
  • the total number of capacitors in at least one first load compensation circuit and/or at least one second compensation circuit is calculated by the following formula:
  • N (C1-C2)/C (1)
  • N represents the number of capacitors
  • C1 represents the equivalent capacitance value of a row of pixel units (including a complete number of pixel units) in the regular display area
  • C2 represents the equivalent capacitance value of a row of pixel units in the irregular display area
  • C represents The capacitance value of a capacitor.
  • the above formula (1) can be used to calculate the total number of capacitors that need to be compensated in a row of pixel units in the irregular display area.
  • the number of capacitors on the left and right sides is determined according to the number of missing pixel units on the left and right sides of a row of pixel units in the irregular display area.
  • At least one second load compensation circuit 6 includes multiple, and each second load compensation circuit 6 is correspondingly disposed at the gate line signal output terminal 20 of each special-shaped display area 3, and is located along the input direction of the gate line signal. The signal output terminal on the side away from the signal input terminal 10.
  • the first load compensation circuit 4 and the second load compensation circuit 6 are arranged as shown in FIG. 12.
  • a hole or hole structure is usually provided to provide external configuration devices such as a camera, as shown in FIG. 5 and FIG. 6, an extension of one of the at least one gate line (using The part outside the electrically connected pixel unit) can extend along the edge of the hole or hole structure, or be arranged along the edge of the irregular display area. In this way, the screen-to-body ratio of the actual display area in the special-shaped display area 3 can be further increased, thereby further satisfying people's visual needs.
  • the extension portion of one of the at least one gate line may be located in an area where no pixel unit is provided in the irregular display area, and the extension portion and other film layers of the display panel form a first capacitor and/or a second capacitor.
  • the pixel unit may be located in the area surrounded by the ridge 31, the area between the ridges 31 is a hole or hole structure, and the first capacitor and/or the second capacitor may be disposed in the area where the pixel unit is located.
  • each arrow schematically shows the placement position of the capacitor, and the placement position includes a side close to the gate line signal input terminal and a side close to the gate line signal output terminal.
  • the arrows between the ridges 31 correspond to the capacitors corresponding to the gate line signal output end along the edge of the hole or hole structure, and the other arrows correspond to the capacitors at the gate line signal input end.
  • At least one first load compensation circuit 4 and/or at least one second load compensation circuit 6 is arranged on a side of at least one irregular display area 3 away from the regular display area 2, and at least one The first load compensation circuit 4 and/or the at least one second load compensation circuit 5 are sequentially arranged at a uniform interval on the side of the at least one irregular display area 3 away from the regular display area 2.
  • the arrangement sequence of the at least one first load compensation circuit 4 and/or the at least one second load compensation circuit 5 and the electrical connection sequence of the gate lines in the area surrounded by the ridge 31 may be random, as long as it is ensured that at least one The plurality of first capacitors in the first load compensation circuit 4 and/or the second capacitor in the at least one second load compensation circuit 5 is close to the gate line signal input terminal or the gate line signal output terminal with respect to the gate line electrically connected thereto. Arrange them at even intervals on one side one by one.
  • the specific location of the second load compensation circuit 6 is not limited, as long as it is ensured that the signal input via the gate line 5 sequentially passes through the first load compensation circuit 4, passes through the pixel unit 1, and then passes through the second load compensation circuit 4.
  • the load compensation circuit 6 can realize the load compensation of the gate line 5 by the first load compensation circuit 4 and the second load compensation circuit 6 and can ensure the load of the gate line 5 in the irregular display area 3 and the gate line in the regular display area 2
  • the load of 5 is basically the same.
  • at least one second load compensation circuit 6 is electrically connected in parallel on a side closer to the gate line signal output terminal 20 relative to the pixel unit electrically connected to the same gate line.
  • the plurality of capacitors of the at least one first load compensation circuit 4 are closer to the gate line signal than the pixel unit 1 electrically connected to the same gate line.
  • One side of the input terminal 10 is sequentially arranged at a uniform interval, and the multiple capacitors of the at least one second load compensation circuit 6 are closer to the side of the gate line signal output terminal 20 than the pixel unit 1 electrically connected to the same gate line. They are arranged sequentially at even intervals, which is beneficial to the load balance of the display panel.
  • the distance between the adjacent first capacitors of the two adjacent first load compensation circuits of the same gate line and the plurality of first capacitors in the at least one first load compensation circuit are electrically connected.
  • the distance between the capacitors is equal, and the distance between the adjacent second capacitors of the two adjacent second load compensation circuits that are electrically connected to the same gate line is the same as the distance between the second capacitors in the at least one second load compensation circuit.
  • the spacing between the two capacitors is equal.
  • the other structures of the electroluminescent display panel in this embodiment are the same as the other structures of the electroluminescent display panel only provided with at least one first load compensation circuit, and will not be repeated here.
  • At least one first load compensation circuit and at least one second load compensation circuit are provided on the basis of the driving method of the electroluminescence display panel only provided with at least one first load compensation circuit
  • the driving signal passes through the pixel unit row, it reaches the at least one second load compensation circuit via at least one gate line, thereby realizing further load compensation for the at least one gate line.
  • the drive signal input via the gate line sequentially passes through the first load compensation circuit, the pixel unit and the second load compensation circuit, so that the gate line in the irregular display area can be processed.
  • Load compensation makes the load of the gate line in the irregular display area more consistent with the load of the gate line in the regular display area.
  • the electroluminescent display panel provided by the present disclosure, by setting the special-shaped display area, when the edge space of the display panel is small, the problem of the placement of the external configuration device is solved, and the pixel unit is opposed to the pixel unit in the special-shaped display area.
  • the first load compensation circuit is arranged on the side closer to the gate line signal input end. Compared with the current load compensation scheme in which the compensation capacitors are arranged on the side of the gate line signal output end, the first load compensation circuit can compensate the gate line in the irregular display area.
  • the load compensation is carried out in advance, so that the load of the gate line in the irregular display area is more consistent with the load of the gate line in the regular display area, and the luminous brightness of the pixel units in the irregular display area and the regular display area tends to be uniform, improving The uniformity of the display brightness of the display panel is improved, and the display effect of the display panel is improved.
  • a display device including the electroluminescence display panel described above and a driving circuit for driving the electroluminescence display panel.
  • the display device can not only realize a full-screen display with a higher screen-to-body ratio, but also can improve the uniformity of the display brightness of the display device, thereby enhancing its display effect.
  • the display device provided by the present disclosure may be any product or component with display function, such as an OLED panel, an OLED TV, a Micro LED panel, a Micro LED TV, a Mini LED panel, a Mini LED TV, a display, a mobile phone, and a navigator.

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Abstract

一种电致发光显示面板和显示装置，电致发光显示面板包括至少一个规则显示区（2）和至少一个异形显示区（3），显示面板在至少一个异形显示区（3）内还包括至少一个第一负载补偿电路（4），至少一个第一负载补偿电路（4）电连接至少一条栅线（5）中的一条栅线（5），至少一个第一负载补偿电路（4）相对于与其电连接同一条栅线（5）的像素单元（1）电连接在同一条栅线（5）的更接近至少一个栅线信号输入端（10）的一侧。

Description

电致发光显示面板及其驱动方法和显示装置
相关申请的交叉引用
本申请要求于2020年1月6日在中国知识产权局提交的No.202010008769.3的中国专利申请的优先权，该中国专利申请的全部内容通过引用合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种电致发光显示面板及其驱动方法和显示装置。
背景技术
近年来，智能有机发光二极管(Organic Light-Emitting Diode，OLED)手机(或者，有机电致发光二极管(Organic electroluminescent diode))手机的发展为人们的生活带来了巨大的变化，市场对智能OLED手机的要求也日益增长。传统的OLED手机屏已不能满足人们的视觉需求，故全面屏应运而生。全面屏提高了屏占比，缩小了边缘空间，为人们的视觉带来了极大的享受。但是，在全面屏中，由于边缘空间的缩小，摄像头和听筒等外部器件就不能再放置于屏幕边缘，由此就诞生了刘海屏等异形屏，这在解决外部器件放置的同时也带来了异形区显示异常的问题。因为异形显示区和正常显示区内像素单元的设置数量不同，使得异形显示区和正常显示区的栅线负载存在差异，导致屏幕异形显示区和正常显示区显示亮度不均匀。
发明内容
根据一个方面，提供了一种电致发光显示面板，包括至少一个规则显示区 和至少一个异形显示区，所述显示面板还包括位于所述至少一个规则显示区和所述至少一个异形显示区中的每一个中的至少一条栅线和至少一个像素单元、以及与所述至少一条栅线分别电连接的至少一个栅线信号输入端，其中，所述显示面板在所述至少一个异形显示区中的每一个中还包括至少一个第一负载补偿电路，所述至少一个第一负载补偿电路电连接所述至少一条栅线中的一条栅线，所述至少一个第一负载补偿电路相对于与其电连接同一条栅线的所述像素单元电连接在所述同一条栅线的更接近所述至少一个栅线信号输入端的一侧。
在一些实施例中，所述显示面板在所述至少一个异形显示区中的每一个中还包括至少一个第二负载补偿电路和与所述至少一条栅线分别电连接的至少一个栅线信号输出端，其中，所述至少一个第二负载补偿电路电连接所述至少一条栅线中的一条栅线，并且所述至少一个第二负载补偿电路相对于与其电连接同一条栅线的所述像素单元电连接在所述同一条栅线的更接近所述至少一个栅线信号输出端的一侧。
在一些实施例中，所述至少一个第一负载补偿电路包括至少一个第一电容器，以及所述至少一个第二负载补偿电路包括至少一个第二电容器。
在一些实施例中，所述至少一个第一电容器包括多个第一电容器，所述多个第一电容器在与其电连接同一条栅线的所述像素单元的更接近所述至少一个栅线信号输入端的一侧并联。
在一些实施例中，所述至少一个第二电容器包括多个第二电容器，所述多个第二电容器在与其电连接同一条栅线的所述像素单元的更接近所述栅线信号输出端的一侧并联。
在一些实施例中，所述电致发光显示面板还包括稳压信号端，其中，所述第一电容器包括第一极板和第二极板，所述第一极板电连接所述至少一条栅线中的一条栅线，所述第二极板电连接所述稳压信号端。
在一些实施例中，所述第二电容器包括第三极板和第四极板，所述第三极板电连接所述至少一条栅线中的一条栅线，所述第四极板电连接所述稳压信号端。
在一些实施例中，所述第一极板与所述至少一条栅线同层设置且采用相同材料制成。
在一些实施例中，所述第三极板与所述至少一条栅线同层设置且采用相同材料制成。
在一些实施例中，所述电致发光显示面板还包括稳压信号端，其中，所述第一电容器包括第一极板和第二极板，所述至少一条栅线中的一条栅线复用作所述第一电容器的所述第一极板，所述第二极板电连接所述稳压信号端。
在一些实施例中，所述第二电容器包括第三极板和第四极板，所述至少一条栅线中的一条栅线复用作所述第二电容器的所述第三极板，所述第四极板电连接所述稳压信号端。
在一些实施例中，所述像素单元包括位于基底上的至少一个晶体管，所述至少一个晶体管中的每一个包括栅极、有源层、源极和漏极，所述第二极板和所述第四极板与所述至少一个晶体管的源极和漏极同层设置且采用相同材料制成。
在一些实施例中，所述像素单元包括位于基底上的至少一个晶体管，所述至少一个晶体管中的每一个包括栅极、有源层、源极和漏极，所述电致发光显示面板还包括：平坦层，其位于所述至少一个晶体管的远离所述基底的一侧；以及发光元件，其包括在所述平坦层上沿远离所述基底方向依次设置的第一电极、有机发光层和第二电极，其中，所述第二极板和所述第四极板与所述至少一个晶体管的有源层、所述发光元件的第一电极和第二电极中的一个同层设置且采用相同材料制成。
在一些实施例中，所述至少一个异形显示区和所述至少一个规则显示区中的像素单元呈多行排列，并且，所述至少一个规则显示区内的多行像素单元中每一行的像素单元的数量大于或等于所述至少一个异形显示区内的多行像素单元中每一行的像素单元的数量，所述至少一个第一负载补偿电路和与其电连接同一条栅线的所述像素单元位于同一行中，所述至少一个第二负载补偿电路和与其电连接同一条栅线的所述像素单元位于同一行中。
在一些实施例中，所述至少一条栅线的每一条包括第一端和与所述第一端相对的第二端，其中，所述第一端电连接至一个栅线信号输入端，所述第二端电连接至一个栅线信号输出端。
在一些实施例中，所述至少一条栅线的每一条包括第一端和与所述第一端相对的第二端，其中，所述第一端和所述第二端分别电连接至两个栅线信号输入端，所述栅线信号输出端电连接至该栅线上除了第一端和第二端以外的部分。
在一些实施例中，所述第一电容器和第二电容器的电容值相等。
在一些实施例中，所述第一电容器和所述第二电容器的电容值等于一个像素单元的等效电容值。
在一些实施例中，所述至少一个第一负载补偿电路和/或所述至少一个第二补偿电路中的电容器的总体数量通过下式计算：
N＝(C1-C2)/C
其中，N表示电容器的数量，C1表示规则显示区中的一行像素单元的等效电容值，C2表示异形显示区中的一行像素单元的等效电容值，C表示一个电容器的电容值。
根据另一方面，提供了一种显示装置，包括以上所述的电致发光显示面板以及用于驱动所述电致发光显示面板的驱动电路。
附图说明
图1为根据本公开实施例的电致发光显示面板的局部结构俯视图；
图2为图1中电致发光显示面板沿C-C’剖切线的部分结构剖视示意图；
图3为采用相关异形显示区栅线负载补偿方案的显示面板在图1中A、B位置的栅线信号仿真波形图；
图4为采用根据本公开实施例的异形显示区栅线负载补偿方案的显示面板在图1中A、B位置的栅线信号仿真波形图；
图5为根据本公开实施例的电致发光显示面板的异形显示区的俯视示意图；
图6为根据本公开实施例的电致发光显示面板的异形显示区的部分区域的放大视图；
图7为根据本公开实施例的电致发光显示面板的局部结构俯视图；
图8为根据本公开实施例的电致发光显示面板中异形显示区栅线为双端输入信号的局部结构俯视图；
图9为根据本公开实施例的电致发光显示面板的局部结构俯视图；
图10为图9中电致发光显示面板沿D-D’剖切线的部分结构剖视示意图；
图11为采用根据本公开实施例的异形显示区栅线负载补偿方案的显示面板在图9中A、B位置的栅线信号仿真波形图；以及
图12为根据本公开实施例的电致发光显示面板的局部结构俯视图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开的一种电致发光显示面板及其驱动方法和显示装置进行详细描述。
根据本公开的一个方面，提供了一种电致发光显示面板。图1为根据本公开实施例的电致发光显示面板中异形显示区为一个的局部结构俯视图。图2为图1中电致发光显示面板沿C-C’剖切线的部分结构剖视示意图。如图1和图2所示，该电致发光显示面板包括至少一个规则显示区2和至少一个异形显示区3。该电致发光显示面板还包括位于至少一个规则显示区2和至少一个异形显示区3中的每一个中的至少一条栅线5和至少一个像素单元1、以及与至少一条栅线5分别(直接或间接)电连接的至少一个栅线信号输入端(其中箭头10标注方向示出栅线信号输入端所在方向)。至少一个规则显示区2中的像素单元1的数量大于至少一个异形显示区3中的像素单元1的数量(即，至少一个规则显示区2中的像素单元1的分布密度大于至少一个异形显示区3中的像素单元1的分布密度)。该电致发光显示面板在至少一个异形显示区3中的每一个中还包括至少 一个第一负载补偿电路4。该第一负载补偿电路4电连接至少一条栅线5中的一条栅线，并且相对于与其电连接同一条栅线的像素单元电连接在该同一条栅线的更接近栅线信号输入端10的一侧。
异形显示区3是将摄像头和听筒等显示面板的外部配置器件集成到显示面板上时所处的区域。由于外部配置器件占用了显示面板的部分显示区，像素单元1在该部分显示区内的分布相对于像素单元1在规则显示区2的分布呈现不规则，所以将该部分显示区称为异形显示区3。如图1所示，在规则显示区2内，像素单元1呈规则的矩阵排布，各行像素单元1的数量相同，即每条栅线5电连接的像素单元1的数量相同。在异形显示区3内，像素单元1呈不规则排布，各行像素单元1的数量不是全部相同，即每条栅线5电连接的像素单元1的数量不是全部相同。一般情况下，异形显示区3内任一条栅线5电连接的像素单元1的数量都小于规则显示区2内任一条栅线5电连接的像素单元1的数量，由此导致异形显示区3内每条栅线5的负载通常都小于规则显示区2内任一栅线5的负载，这会导致异形显示区3内像素单元1与规则显示区2内像素单元1的发光亮度的不均匀，影响显示效果。
由于异形显示区内栅线的负载与规则显示区内栅线的负载存在差异，导致异形显示区内某一条栅线与规则显示区内某一条栅线在同一竖直方向(即同一列像素单元)上的像素单元(如图1中的A位置与B位置处的像素单元)的发光亮度有差异。对于上述发光亮度差异问题，目前解决方案为：在异形显示区设置补偿电容器，且补偿电容器均设置于栅线信号输出端(即相对于像素单元，补偿电容器更接近栅线信号输出端的一侧，通过栅线传输的信号先经过像素单元，再经过补偿电容器)。目前方案虽然在数值上补偿了栅线的负载差异量，但是对于栅线上的信号来说，当信号传输到A、B两位置时，这两条栅线上的信号所经历的负载差异仍然存在。图3为采用相关异形显示区栅线负载补偿方案的显示面板在图1中A、B位置的栅线信号仿真波形图。如图3所示，分别在A位置和B位置监测的栅线上信号的波形差异较大，该波形差异具体体现为：A位置和B位置的栅线上的信号从高电平信号变为低电平信号所用的时长差异较大。
本公开对异形显示区3内的栅线5的进行负载补偿的原理为：在异形显示区3内相对像素单元1更接近栅线信号输入端10的一侧设置至少一个第一负载补偿电路4，使栅线5上的信号到达A位置时所经历的负载与信号到达B位置时所经历的负载接近。图4为采用根据本公开实施例的异形显示区栅线负载补偿方案的显示面板在图1中A、B位置的栅线信号仿真波形图。相对于目前的将补偿电容器均设置于更接近栅线信号输出端20一侧的负载补偿方案，本实施例中的第一负载补偿电路4能对异形显示区3内的栅线5提前进行负载补偿，这样A、B位置的栅线上的信号波形就更接近，如图4所示。相对于目前栅线负载补偿方案，采用本公开的栅线负载补偿方案，A、B位置的像素单元1的发光亮度的差异减小。如以下表1中所示为异形显示区2中的A位置在采用目前方案的栅线负载补偿之后与采用本公开方案的栅线负载补偿之后的信号仿真波形参数(Tf表示信号从高电平信号变为低电平信号所用的时长)对比。
表1
Figure PCTCN2021070448-appb-000001
上述表1中，异形显示区内A位置的Tf1、Tf2、Tf3指在A位置采集三次分别得到的栅线上的信号；异形显示区内A位置的平均Tf指对在A位置采集的三个栅线上的信号求取的平均值；规则显示区内B位置的Tf1、Tf2、Tf3指在B 位置采集三次分别得到的栅线上的信号；规则显示区内B位置的平均Tf指对在B位置采集的三个栅线上的信号的求取的平均值；Δtf＝(B位置的平均Tf-A位置的平均Tf)/B位置的平均Tf。对异形显示区内的栅线进行负载补偿的最终目的是为了使得例如A、B两位置处的栅线上的信号波形更加趋于一致，即A位置相对于B位置，栅线上信号的tf参数的变化越小越好。从表1中可以看出，本实施例中异形显示区栅线的负载补偿方案能使异形显示区A位置栅线上的信号的波形相对于规则显示区B位置的栅线上的信号的波形变化更小，从而实现对异形显示区栅线更好的负载补偿效果。
在本公开的电致发光显示面板中，通过设置异形显示区3，使得在显示面板边缘空间较小的情况下，解决了其外部配置器件的安置问题，并且通过在异形显示区3内相对像素单元1更接近栅线信号输入端10的一侧设置至少一个第一负载补偿电路4，相对于目前将补偿电容器均设置于栅线信号输出端10一侧的负载补偿方案，本公开的第一负载补偿电路4能对异形显示区3内栅线5提前进行负载补偿，从而使异形显示区3内栅线5的负载与规则显示区2内栅线5的负载更加趋于一致，进而使异形显示区3与规则显示区2内像素单元1的发光亮度趋于均匀，改善了显示面板显示亮度的均匀性，提升了显示面板的显示效果。
本实施例中，第一负载补偿电路4可包括第一电容器，即第一负载补偿电路4可为电容器，并且至少一个第一负载补偿电路4中的每一个的电容器的电容值相等。通过电容器对异形显示区3中的栅线5进行负载补偿，一方面制备工艺简单，另一方面电容器的电容值容易在制备过程中进行调整，从而能对栅线5的进行比较准确的负载补偿。本实施例中，以第一负载补偿电路4包括一个电容器为例进行说明，但本公开不限于此，第一负载补偿电路4可包括多个第一电容器。
异形显示区3内，每条栅线5电连接的第一负载补偿电路4(即第一电容器)的数量根据异形显示区3和规则显示区2中的每条栅线5的负载、以及每个第一电容器的电容值进行设置。例如，可以先计算规则显示区3内每条栅线5的 负载，并计算出异形显示区3内每条栅线5在未进行负载补偿前的负载，然后计算异形显示区3与规则显示区2栅线5的负载差异，根据该负载差异和每个电容器的电容值计算出电容器的设置数量，最终使异形显示区3内每条栅线5的负载与规则显示区2内各栅线5的负载基本一致。
异形显示区3内各条栅线5电连接的第一负载补偿电路4的电容器的数量根据每条栅线5上负载的大小和每个电容器的电容值进行设置的例子如下。假设一个像素单元1的负载(即等效电容值)为25，一个第一负载补偿电路4的负载(电容值)为20。图1中像素单元1沿栅线5延伸方向(例如以栅线信号输入端为起始的方向)在A位置所处的排序为第100个，像素单元1沿栅线5延伸方向在B位置所处的排序为第150个，则需要通过设置第一负载补偿电路4对A位置处的栅线上的信号进行负载补偿。可以计算，栅线5上A位置左侧缺失50个像素单元1，则左侧第一负载补偿电路4的设置个数为(50*25)/20＝62.5个。
可选的，本实施例中，第一电容器包括第一极板和第二极板，第二极板可电连接稳压信号端(例如为像素单元中的OLED提供驱动电压)。栅线5的一部分可复用作第一电容器的第一极板。
可选的，像素单元1包括位于基底上的至少一个晶体管，至少一个晶体管中的每一个包括栅极、有源层、源极和漏极。第一电容器的第二极板与至少一个晶体管的源漏极同层设置且采用相同材料制成。如此设置，第一电容器的第一极板与第二极板之间的间距以及两极板的材料对栅线负载补偿的作用最大。另外，这样可使得不额外增加显示面板的制备工艺来制备电容器，并且制备工艺简单。
可选的，本公开的电致发光显示面板还包括：平坦层(未示出)，其位于至少一个晶体管的远离基底的一侧；以及发光元件，其包括在平坦层上沿远离基底方向依次设置的第一极、有机发光层和第二极。第二极板可与至少一个晶体管的有源层、发光元件的第一电极和第二电极中的一个同层设置且采用相同材料制成。也就是说，第一电容器的第二极板也可以与晶体管的有源层、发光元 件的第一电极(阳极)、发光元件的第二电极(阴极)中的任一同层设置且采用相同材料制成。但第二极板采用这些膜层材料且与这些膜层同层时，其对负载的调节作用明显小于第二极板与晶体管的源漏极同层且采用相同材料的情况。但为了通过电容器精确地调节栅线5的负载，可以通过使不同第一电容器的第二极板分别与不同膜层同层且采用相同材料，以对栅线进行更加精确地负载补偿。制作栅线、有源层、源漏极以及发光元件的第一电极和第二电极的材料可为相关技术中制作相应结构所需的材料。
需要说明的是，如图2所示，栅线5的负载主要是指与栅线5电连接的像素单元导致的负载，像素单元导致的负载主要包括栅线5与像素驱动电路中各晶体管及晶体管的源漏极膜层7(包括源极和漏极)、有源层膜层8(包括有源层)之间的负载，还包括栅线5与发光元件的阳极膜层9(第一电极)之间形成的负载。通过在异形显示区3内设置由栅线5与其它电极膜层构成的补偿电容器，并通过设置不同数量的补偿电容器，能够对异形显示区3内的栅线5进行负载补偿，以使其负载与规则显示区2内栅线5的负载保持基本一致，从而提高显示面板的显示亮度均匀性。通过上述设置，可知至少一个第一电容器在与其电连接同一条栅线的像素单元的更接近栅线信号输入端的一侧并联电连接。
需要说明的是，本实施例中，也可以单独制备第一电容器的两个极板，且使第一电容器的第一极板电连接栅线5，第二极板电连接稳压信号端。其中，第一电容器的第一极板与栅线同层设置且采用相同材料。第一电容器的第二极板与晶体管的源漏极、发光元件的阳极、发光元件的阴极中的任一同层设置且采用相同材料。如此设置，这样可使得不额外增加显示面板的制备工艺来制备电容器，并且制备工艺简单。
如图1所示，至少一个异形显示区3和至少一个规则显示区2内的像素单元1呈多行排列，并且，至少一个规则显示区2内的多行像素单元中每一行的像素单元的数量大于或等于至少一个异形显示区3内的多行像素单元中每一行的像素单元的数量，也就是说，至少一个规则显示区2内的像素单元的数量小于至少一个异形显示区3内的像素单元的数量。如图1所示，至少一个第一负 载补偿电路4和与其电连接同一条栅线5的像素单元位于同一行中。
本公开中，如图5所示，至少一个异形显示区3可以包括具有像素单元的例如山脊31形状所包围的区域以及山脊31之间的凹陷区域，该凹陷区域可为孔或洞结构等用于放置摄像头等外部配置器件。图6为图5中一个山脊31的放大视图。如图6所示，各个异形显示区3内，一行像素单元1对应电连接一条栅线5。
本实施例中，以异形显示区3为一个为例。如图1所示，第一负载补偿电路4包括多个，各个第一负载补偿电路4对应设置于靠近各异形显示区3的栅线信号输入端10。沿栅线信号的输入方向，多个第一负载补偿电路4位于像素单元1电连接的栅线5的靠近栅线信号输入端10的一侧。异形显示区3为两个以上时，第一负载补偿电路4的设置如图7所示。
需要说明的是，第一负载补偿电路4也可以沿异形显示区3的边缘设置，例如位于异形显示区3与规则显示区2的边界处。如此能进一步提高异形显示区3内的显示区域的屏占比，从而进一步满足人们的视觉需求。第一负载补偿电路4还可以位于异形显示区3内未设置像素单元的任何区域中。
进一步需要说明的是，对第一负载补偿电路4的具体设置位置不做限定，只要确保相对于像素单元1，第一负载补偿电路4位于更接近栅线信号输入端10的一侧，即栅线5上输入的信号先经过第一负载补偿电路4，再经过像素单元1，即可实现第一负载补偿电路4对栅线5提前进行负载补偿，并能确保异形显示区3内栅线5的负载与规则显示区2内栅线5的负载基本一致。
另外，本实施例中，在至少一个异形显示区3和/或至少一个规则显示区2内，电至少一条栅线中的一条栅线包括第一端51和第二端52。第一端51电连接至一个栅线信号输入端10，第二端52电连接至一个栅线信号输出端(如箭头20标识)，或者第一端51和第二端52分别电连接至两个栅线信号输入端10，栅线信号输出端20电连接至该栅线上除了第一端和第二端以外的部分。即异形显示区3和规则显示区2内，可以通过单边驱动或者双边驱动方式(如图8所示)来驱动一行像素单元。
另外需要说明的是，像素单元1中的发光元件可以是有机电致发光二极管(OLED)、发光二极管(LED)、微型发光二极管(Micro LED)或者迷你发光二极管(Mini LED)。
基于电致发光显示面板的上述结构，本实施例还提供一种该电致发光显示面板的驱动方法。该驱动方法包括：通过多个栅线信号输入端分别依次向规则显示区2和异常显示区3中的至少一条栅线提供驱动信号。在规则显示区2中，驱动信号经由至少一条栅线中的一条栅线向像素单元行提供驱动信号。在异形显示区3中，驱动信号经由至少一条栅线中的一条栅线通过至少一个第一负载补偿电路后，到达像素单元行。即该电致发光显示面板驱动时，对于异形显示区，经由栅线输入的驱动信号先经过第一负载补偿电路，再经过像素单元，从而能够对异形显示区内栅线进行负载补偿，使得异形显示区内栅线的负载与规则显示区内栅线的负载更加趋于一致。
本实施例还提供了一种电致发光显示面板，如图9和图10所示，在前述实施例中的显示面板的基础上，本实施例中，异形显示区3内，还设置有至少一个第二负载补偿电路6，至少一个第二负载补偿电路6电连接至少一条栅线5中的一条栅线，相对于像素单元1，至少一个第二负载补偿电路6位于更接近栅线信号输出端20的一侧。
本实施例中，在上述实施例设置至少一个第一负载补偿电路4的基础上，设置至少一个第二负载补偿电路6。通过栅线信号输入端10提供的驱动信号经由栅线5依次经过至少一个第一负载补偿电路4和像素单元1后，到达至少一个第二负载补偿电路6。至少一个第二负载补偿电路6在至少一个第一负载补偿电路4对异形显示区3内的栅线5提前进行负载补偿的基础上，对异形显示区3内的栅线5进行进一步负载补偿。
通过设置第一负载补偿电路4和第二负载补偿电路6，能在对异形显示区3内栅线5提前进行负载补偿的基础上，对异形显示区3内栅线5进行进一步负载补偿，从而使异形显示区3内栅线5的负载与规则显示区2内栅线5的负载更加趋于一致，进而使异形显示区3与规则显示区2内像素单元1的发光亮度 趋于均匀，改善了显示面板显示亮度的均匀性，提升了显示面板的显示效果。
如图11所示为采用本实施例中的异形显示区栅线负载补偿方案后，图9中异形显示区3内A位置和规则显示区2内B位置的栅线上的信号仿真波形。如以下表2中所示为异形显示区3栅线A位置采用负载目前补偿方案、仅采用第一负载补偿电路的负载补偿方案、以及第一负载补偿电路和第二负载补偿电路的负载补偿方案补偿后的信号仿真波形参数(Tf表示信号从高电平信号变为低电平信号所用的时长)对比。
表2
Figure PCTCN2021070448-appb-000002
从表2中可以看出，本实施例中异形显示区栅线的负载补偿方案能使异形显示区A位置栅线信号的波形相对规则显示区B位置栅线信号的波形变化相对目前方案和仅采用第一负载补偿电路的方案减小，从而实现对异形显示区栅线较好的负载补偿效果。
第二负载补偿电路6可包括一个或多个第二电容器。通过电容器对异形显示区3中的栅线5进行负载补偿，一方面制备工艺简单，另一方面电容器的电 容值容易在制备过程中进行调整，从而能对栅线5的进行比较准确的负载补偿。本实施例中，以第二负载补偿电路6包括一个第二电容器为例进行说明，但本公开不限于此，第二负载补偿电路6可包括多个第二电容器。第二电容器和第一电容器的电容值可设置为相等。
本实施例中，第二负载补偿电路6中的第二电容器包括第三极板和第四极板。第三极板的结构、电连接关系及材料可以与第一负载补偿电路4中的第一电容器的第一极板的结构、电连接关系及材料相同。第四极板的结构、电连接关系及材料可以与第一负载补偿电路4中的第一电容器的第二极板的结构、电连接关系及材料相同。
异形显示区3内各条栅线5电连接的第一负载补偿电路4中第一电容器的数量以及第二负载补偿电路6中第二电容器的数量根据每条栅线5上负载的大小和每个电容器的电容值进行设置的例子如下。假设一个像素单元1的负载为25，一个第一负载补偿电路4的负载为20，一个第二负载补偿电路6的负载为20。图9中像素单元1沿栅线5延伸方向在A位置所处的排序为第100个，像素单元1沿栅线5延伸方向在B位置所处的排序为第150个，则需要通过设置第一负载补偿电路4和第二负载补偿电路6对A位置处的负载进行补偿。可以计算，沿栅线5延伸方向，A位置左侧和右侧分别缺失的像素单元1的数量，若左侧缺失像素单元1的个数为30个，右侧缺失像素单元1的个数为20个，则左侧第一负载补偿电路4的设置个数为(30*25)/20＝37.5个，右侧第二负载补偿电路6的设置个数为(20*25)/20＝25个。在实际情况中，对于A位置，因为补偿左侧(即栅线信号输入侧)电容器更加重要，所以优先考虑将电容器设置于像素单元1的左侧，若左侧补偿空间受限，可将补偿电容器根据实际情况进行调整，设置在像素单元1的右侧(即栅线信号输出侧)。
可选地，所述第一电容器和第二电容器的电容值相等。第一电容器和第二电容器的电容值等于一个像素单元的等效电容值。
可选地，至少一个第一负载补偿电路和/或至少一个第二补偿电路中的电容器的总体数量通过下式计算：
N＝(C1-C2)/C         (1)
其中，N表示电容器的数量，C1表示规则显示区中的一行像素单元(包括完整数量的像素单元)的等效电容值，C2表示异形显示区中的一行像素单元的等效电容值，C表示一个电容器的电容值。
通过上式(1)可计算出异形显示区中某一行像素单元中需要补偿的总体电容器的数量。根据异形显示区中某一行像素单元左右两侧分别缺失的像素单元数量来确定左右两侧的电容器的数量。
本实施例中，至少一个第二负载补偿电路6包括多个，各个第二负载补偿电路6对应设置于各异形显示区3的栅线信号输出端20，且沿栅线信号的输入方向，位于远离信号输入端10一侧的信号输出端。异形显示区3为两个以上时，第一负载补偿电路4和第二负载补偿电路6的设置如图12所示。
需要说明的是，在至少一个异形显示区中通常设置有例如孔或洞结构来设置摄像头等外部配置器件，如图5和图6所示，该至少一条栅线中的一条的延长部分(用于电连接像素单元的之外的部分)可沿孔或洞结构的边缘延伸，或者沿异形显示区的边缘设置。如此能进一步提高异形显示区3内实际显示区域的屏占比，从而进一步满足人们的视觉需求。或者，该至少一条栅线中的一条的延长部分可位于异形显示区中未设置像素单元的区域中，该延长部分与显示面板的其他膜层形成第一电容器和/或第二电容器。如图5和图6所示，像素单元可位于山脊31所包围的区域中，山脊31之间的区域为孔或洞结构，第一电容器和/或第二电容器可设置于像素单元所在区域之外的山脊31之上或孔或洞结构的边缘区域。栅线5的一端电连接山脊31所包围的区域中的像素单元，栅线5另一端延伸出山脊31所包围的区域而与显示面板的其他膜层形成第一电容器和/或第二电容器。如图5所示，各箭头示意示出电容器的设置位置，该设置位置包括靠近栅线信号输入端的一侧，以及靠近栅线信号输出端的一侧。对于双向驱动，山脊31之间的箭头对应沿孔或洞结构的边缘设置对应栅线信号输出端的电容器，其他箭头对应栅线信号输入端的电容器。如图5和图6所示，至少一个第一负载补偿电路4和/或至少一个第二负载补偿电路6设置在至少一个 异形显示区3的远离规则显示区2的一侧，并且，至少一个第一负载补偿电路4和/或至少一个第二负载补偿电路5依次以均匀间距排布设置在至少一个异形显示区3的远离规则显示区2的一侧。并且，可选地，至少一个第一负载补偿电路4和/或至少一个第二负载补偿电路5排列顺序与山脊31所包围区域内的栅线的电连接顺序可为随机的，只要保证至少一个第一负载补偿电路4中的多个第一电容器和/或至少一个第二负载补偿电路5中的第二电容器相对于与其电连接的栅线的接近栅线信号输入端或栅线信号输出端的一侧依次以均匀间距排布即可。
进一步需要说明的是，对第二负载补偿电路6的具体设置位置不做限定，只要确保经由栅线5上输入的信号依次经过第一负载补偿电路4、经过像素单元1后，再经过第二负载补偿电路6，即可实现第一负载补偿电路4和第二负载补偿电路6对栅线5的负载补偿，并能确保异形显示区3内栅线5的负载与规则显示区2内栅线5的负载基本一致。如图5和图6所示，至少一个第二负载补偿电路6在相对于与其电连接同一条栅线的像素单元的更接近栅线信号输出端20的一侧并联电连接。
可选地，如图1、图7至图9以及图12所示，至少一个第一负载补偿电路4的多个电容器在相对于与其电连接同一条栅线的像素单元1更接近栅线信号输入端10的一侧依次以均匀间距排布，至少一个第二负载补偿电路6的多个电容器在相对于与其电连接同一条栅线的像素单元1更接近栅线信号输出端20的一侧依次以均匀间距排布，如此有利于显示面板的负载均衡性。并且，为了进一步均衡负载，电连接同一条栅线的彼此相邻的两个第一负载补偿电路的相邻的第一电容器之间的间距与至少一个第一负载补偿电路中的多个第一电容器之间的间距相等，以及电连接同一条栅线的彼此相邻的两个第二负载补偿电路的相邻的第二电容器之间的间距与至少一个第二负载补偿电路中的多个第二电容器之间的间距相等。
本实施例中电致发光显示面板的其他结构与仅设置至少一个第一负载补偿电路的电致发光显示面板的其他结构相同，此处不再赘述。
基于电致发光显示面板的上述结构，在仅设置至少一个第一负载补偿电路的电致发光显示面板的驱动方法的基础上，设置有至少一个第一负载补偿电路和至少一个第二负载补偿电路，在异形显示区内，驱动信号在经过像素单元行之后，经由至少一条栅线到达至少一个第二负载补偿电路，进而实现对至少一条栅线的进一步负载补偿。
在驱动该电致发光显示面板时，对于异形显示区，经由栅线输入的驱动信号依次经过第一负载补偿电路、像素单元和第二负载补偿电路，从而能够对异形显示区内的栅线进行负载补偿，使异形显示区内栅线的负载与规则显示区内栅线的负载更加趋于一致。
在本公开所提供的电致发光显示面板中，通过设置异形显示区，在显示面板边缘空间较小的情况下，解决了其外部配置器件的安置问题，并且通过在异形显示区内相对像素单元更接近栅线信号输入端的一侧设置第一负载补偿电路，相对于目前将补偿电容器均设置于栅线信号输出端一侧的负载补偿方案，第一负载补偿电路能对异形显示区内栅线的进行提前负载补偿，从而使异形显示区内栅线的负载与规则显示区内栅线的负载更加趋于一致，进而使异形显示区与规则显示区内像素单元的发光亮度趋于均匀，改善了显示面板显示亮度的均匀性，提升了显示面板的显示效果。
根据本公开的另一方面，还提供了一种显示装置，该显示装置包括以上所述的电致发光显示面板以及用于驱动电致发光显示面板的驱动电路。
通过采用上述实施例中的电致发光显示面板，不仅使该显示装置能实现更高屏占比的全面屏显示，而且还能提升该显示装置显示亮度的均匀性，从而提升其显示效果。
本公开所提供的显示装置可以为OLED面板、OLED电视、Micro LED面板、Micro LED电视、Mini LED面板、Mini LED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言， 在不脱离本发明所附权利要求限定的范围的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种电致发光显示面板，包括至少一个规则显示区和至少一个异形显示区，所述显示面板还包括位于所述至少一个规则显示区和所述至少一个异形显示区中的每一个中的至少一条栅线和至少一个像素单元、以及与所述至少一条栅线分别电连接的至少一个栅线信号输入端，
    其中，所述显示面板在所述至少一个异形显示区中的每一个中还包括至少一个第一负载补偿电路，所述至少一个第一负载补偿电路电连接所述至少一条栅线中的一条栅线，所述至少一个第一负载补偿电路相对于与其电连接同一条栅线的所述像素单元电连接在所述同一条栅线的更接近所述至少一个栅线信号输入端的一侧。
  2. 根据权利要求1所述的电致发光显示面板，其中，所述显示面板在所述至少一个异形显示区中的每一个中还包括至少一个第二负载补偿电路和与所述至少一条栅线分别电连接的至少一个栅线信号输出端，其中，所述至少一个第二负载补偿电路电连接所述至少一条栅线中的一条栅线，并且所述至少一个第二负载补偿电路相对于与其电连接同一条栅线的所述像素单元电连接在所述同一条栅线的更接近所述至少一个栅线信号输出端的一侧。
  3. 根据权利要求2所述的电致发光显示面板，其中，所述至少一个第一负载补偿电路包括至少一个第一电容器，以及所述至少一个第二负载补偿电路包括至少一个第二电容器。
  4. 根据权利要求3所述的电致发光显示面板，其中，所述至少一个第一电容器包括多个第一电容器，所述多个第一电容器在与其电连接同一条栅线的所述像素单元的更接近所述至少一个栅线信号输入端的一侧并联。
  5. 根据权利要求4所述的电致发光显示面板，其中，所述至少一个第二电容器包括多个第二电容器，所述多个第二电容器在与其电连接同一条栅线的所述像素单元的更接近所述栅线信号输出端的一侧并联。
  6. 根据权利要求3至5任一所述的电致发光显示面板，还包括稳压信号端，其中，
    所述第一电容器包括第一极板和第二极板，所述第一极板电连接所述至少一条栅线中的一条栅线，所述第二极板电连接所述稳压信号端。
  7. 根据权利要求6所述的电致发光显示面板，其中，
    所述第二电容器包括第三极板和第四极板，所述第三极板电连接所述至少一条栅线中的一条栅线，所述第四极板电连接所述稳压信号端。
  8. 根据权利要求7所述的电致发光显示面板，其中，所述第一极板与所述至少一条栅线同层设置且采用相同材料制成。
  9. 根据权利要求8所述的电致发光显示面板，其中，所述第三极板与所述至少一条栅线同层设置且采用相同材料制成。
  10. 根据权利要求3至5任一所述的电致发光显示面板，还包括稳压信号端，其中，
    所述第一电容器包括第一极板和第二极板，所述至少一条栅线中的一条栅线复用作所述第一电容器的所述第一极板，所述第二极板电连接所述稳压信号端。
  11. 根据权利要求10所述的电致发光显示面板，其中，
    所述第二电容器包括第三极板和第四极板，所述至少一条栅线中的一条栅线复用作所述第二电容器的所述第三极板，所述第四极板电连接所述稳压信号端。
  12. 根据权利要求9或11所述的电致发光显示面板，其中，所述像素单元包括位于基底上的至少一个晶体管，所述至少一个晶体管中的每一个包括栅极、有源层、源极和漏极，
    所述第二极板和所述第四极板与所述至少一个晶体管的源极和漏极同层设置且采用相同材料制成。
  13. 根据权利要求9或11所述的电致发光显示面板，其中，所述像素单元包括位于基底上的至少一个晶体管，所述至少一个晶体管中的每一个包括栅极、有源层、源极和漏极，
    所述电致发光显示面板还包括：
    平坦层，其位于所述至少一个晶体管的远离所述基底的一侧；以及
    发光元件，其包括在所述平坦层上沿远离所述基底方向依次设置的第一电极、有机发光层和第二电极，
    其中，所述第二极板和所述第四极板与所述至少一个晶体管的有源层、所述发光元件的第一电极和第二电极中的一个同层设置且采用相同材料制成。
  14. 根据权利要求3至13中任一项所述的电致发光显示面板，其中，所述至少一个异形显示区和所述至少一个规则显示区中的像素单元呈多行排列，并且，所述至少一个规则显示区内的多行像素单元中每一行的像素单元的数量大于或等于所述至少一个异形显示区内的多行像素单元中每一行的像素单元的数量，所述至少一个第一负载补偿电路和与其电连接同一条栅线的所述像素单元位于同一行中，所述至少一个第二负载补偿电路和与其电连接同一条栅线的所述像素单元位于同一行中。
  15. 根据权利要求14所述的电致发光显示面板，其中，
    所述至少一条栅线的每一条包括第一端和与所述第一端相对的第二端，其中，
    所述第一端电连接至一个栅线信号输入端，所述第二端电连接至一个栅线信号输出端。
  16. 根据权利要求14所述的电致发光显示面板，其中，
    所述至少一条栅线的每一条包括第一端和与所述第一端相对的第二端，其中，
    所述第一端和所述第二端分别电连接至两个栅线信号输入端，所述栅线信号输出端电连接至该栅线上除了第一端和第二端以外的部分。
  17. 根据权利要求15或16所述的电致发光显示面板，其中，所述第一电容器和第二电容器的电容值相等。
  18. 根据权利要求17所述的电致发光显示面板，其中，所述第一电容器和所述第二电容器的电容值等于一个像素单元的等效电容值。
  19. 根据权利要求18所述的电致发光显示面板，其中，所述至少一个第一负载补偿电路和/或所述至少一个第二补偿电路中的电容器的总体数量通过下式计算：
    N＝(C1-C2)/C
    其中，N表示电容器的数量，C1表示规则显示区中的一行像素单元的等效电容值，C2表示异形显示区中的一行像素单元的等效电容值，C表示一个电容器的电容值。
  20. 一种显示装置，包括权利要求1-19任意一项所述的电致发光显示面板以及用于驱动所述电致发光显示面板的驱动电路。
PCT/CN2021/070448 2020-01-06 2021-01-06 电致发光显示面板及其驱动方法和显示装置 WO2021139676A1 (zh)

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