WO2021139008A1 - 像素电路和具有该像素电路的显示装置 - Google Patents

像素电路和具有该像素电路的显示装置 Download PDF

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Publication number
WO2021139008A1
WO2021139008A1 PCT/CN2020/081768 CN2020081768W WO2021139008A1 WO 2021139008 A1 WO2021139008 A1 WO 2021139008A1 CN 2020081768 W CN2020081768 W CN 2020081768W WO 2021139008 A1 WO2021139008 A1 WO 2021139008A1
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Prior art keywords
transistor
line
pixel unit
pixel
electrode
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PCT/CN2020/081768
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English (en)
French (fr)
Inventor
刘建欣
韩佰祥
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/756,193 priority Critical patent/US20210407395A1/en
Publication of WO2021139008A1 publication Critical patent/WO2021139008A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of circuits and pixel driving, and in particular to a pixel circuit and a display device having the pixel circuit.
  • bottom-emission active matrix organic light-emitting diode (AMOLED) panels adopt a single scan line pixel structure in order to increase the aperture ratio, but the single scan line pixel structure loses the flexibility of voltage compensation and reduces the detection accuracy. There are certain flaws.
  • the prior art has the problem that it is difficult to balance the high aperture ratio of the pixel unit and the compensation accuracy of the pixel circuit.
  • the present invention provides a pixel circuit.
  • the pixel circuit includes a pixel unit circuit arranged in a matrix.
  • the pixel unit circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor, a light emitting device, a data line, and a scan line. , Detection signal line;
  • the drain of the first transistor of the pixel unit circuit in the nth row is connected to the first power line to receive the first voltage; the control electrode of the second transistor is connected to the scan line, and the first transistor of the second transistor is connected to the scan line.
  • the second electrode of the second transistor is connected to the control electrode of the first transistor and one electrode of the storage capacitor respectively; the control electrode of the third transistor is connected to the n+1th electrode.
  • the scan line of the pixel unit circuit of the row is connected, the first electrode of the third transistor is connected to the detection signal line, the second electrode of the third transistor is connected to the source of the first transistor, the storage capacitor
  • the other electrode is connected to one end of the light-emitting device respectively; the other end of the light-emitting device is connected to the second power line to receive the second voltage; the scan lines of the pixel unit circuits in the adjacent rows have at least half the same pulse.
  • the present invention provides a display device.
  • the pixel circuit of the display device includes pixel unit circuits distributed in a matrix.
  • the pixel unit circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor, a light emitting device, and a data line. , Scanning line, detection signal line;
  • the drain of the first transistor of the pixel unit circuit in the nth row is connected to the first power line to receive the first voltage; the control electrode of the second transistor is connected to the scan line, and the first transistor of the second transistor is connected to the scan line.
  • the second electrode of the second transistor is connected to the control electrode of the first transistor and one electrode of the storage capacitor respectively; the control electrode of the third transistor is connected to the n+1th electrode.
  • the scan line of the pixel unit circuit of the row is connected, the first electrode of the third transistor is connected to the detection signal line, the second electrode of the third transistor is connected to the source of the first transistor, the storage capacitor
  • the other electrode is connected to one end of the light-emitting device respectively; the other end of the light-emitting device is connected to the second power line to receive the second voltage; the scan lines of the pixel unit circuits in the adjacent rows have at least half the same pulse.
  • the present invention connects the control electrode of the third transistor of the pixel unit circuit in the nth row to the scan line of the pixel unit circuit in the n+1th row to control the pulse relationship of the scan lines of the pixel unit circuit in the adjacent row. Therefore, the detection accuracy of the threshold voltage is improved, and the compensation accuracy of the pixel circuit is improved. At the same time, the pixel structure of a single scan line is adopted to ensure the high aperture ratio of the pixel unit and achieve a better display effect.
  • FIG. 1 is an equivalent schematic diagram of a pixel circuit provided by an embodiment of the present invention
  • FIG. 2 is a timing diagram of a pixel circuit provided by an embodiment of the present invention.
  • FIG. 3 is a timing diagram of a pixel circuit provided by another embodiment of the present invention.
  • FIG. 4 is an equivalent schematic diagram of a pixel unit circuit provided by another embodiment of the present invention.
  • FIG. 5 is a timing diagram of a pixel unit circuit provided by another embodiment of the present invention.
  • an embodiment of the present invention provides a pixel circuit.
  • the pixel circuit includes a pixel unit circuit arranged in a matrix.
  • the pixel unit circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor.
  • C The light emitting device D, the data line V DATA , the scan line WR, and the detection signal line S, wherein the first transistor T1, the second transistor T2, and the third transistor T3 may be thin film transistors, and the light emitting device D may be AMOLED or other light-emitting devices.
  • the drain of the first transistor T1 of the pixel unit circuit 10 in the nth row is connected to the first power line to receive the first voltage V DD .
  • the control electrode of the second transistor T2 is connected to the scan line WR-n of the pixel unit circuit 10, the first electrode of the second transistor T2 is connected to the data line V DATA of the pixel unit circuit 10, and the second electrode of the second transistor T2 It is connected to the control electrode of the first transistor T1 of the pixel unit circuit 10 and one of the electrodes of the storage capacitor C respectively; wherein the first electrode of the second transistor T2 can be the source or the drain, and the corresponding second stage , This office does not make restrictions.
  • the first electrode of the third transistor T3 is connected to the detection signal line S of the pixel unit circuit 10, and the second electrode of the third transistor T3 is connected to the source of the first transistor T1 of the pixel unit circuit 10 and the other of the storage capacitor C.
  • One electrode is connected to one end of the light emitting device D, and the control electrode of the third transistor T3 of the pixel unit circuit 10 in the nth row is connected to the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row;
  • the first electrode of the third transistor T3 may be the source or the drain, and the corresponding second stage, which is not limited here.
  • the other end of the light emitting device D is connected to the second power line to receive the second voltage V SS , the second power line may be grounded, and the second voltage V SS may be 0V.
  • the pulses of the scan line signals of the pixel unit circuits of adjacent rows are the same.
  • at least half of the pulses of the scan lines of the pixel unit circuits in the adjacent rows are the same, which may be: in the pixel circuit, there are at least half pulses of the pulse signals of the scan lines of the upstream and downstream pixel unit circuits at the same time.
  • Level signal so that the second transistor T2 and the third transistor T3 respectively controlled by the uplink and downlink scan line signals are turned on at the same time.
  • the pulse signal diagram of the scan line of the pixel unit circuit of the adjacent row can be seen in FIG. 2.
  • the second transistor T2 and the third transistor T3 in the pixel unit circuit 10 of the nth row are turned on at the same time, and the data line V DATA is subsequently raised to a high level state to turn on the second transistor T2 in the pixel unit circuit 10
  • a transistor T1 starts to charge the storage capacitor C and drives the light emitting device D to start emitting light.
  • the scanning line WR-n+1 of the pixel unit circuit 11 in the n+1th row is raised to the high state for 1H
  • the scanning line WR-n of the pixel unit circuit 10 in the nth row is lowered to the low level.
  • the second transistor T2 is turned off, and the first transistor T1 is still turned on because the storage capacitor C begins to discharge, the voltage at the gate point Vs of the first transistor T1 is raised, and the voltage at the source point Vg of the first transistor T1 is The voltage drifts, so it is coupled up by the capacitor C.
  • the detection signal line S detects and obtains the more accurate gate-source voltage Vgs of the first transistor T1
  • the data is transmitted to the processing chip to start calculating the compensation voltage, and the data line V DATA in the next frame is adjusted according to the compensation voltage. Voltage to achieve voltage compensation for the pixel circuit.
  • the pulses of the scanning lines of the pixel unit circuit are at least half of the pulses the same, so that the gate-source voltage detected by the detection signal line S is more accurate, thereby improving the detection accuracy of the image circuit, and thus the compensation accuracy of the pixel circuit;
  • the pixel circuit structure of a single scan line is still adopted, a high aperture ratio of the pixel structure can be ensured, and a better display effect can be achieved.
  • the pixel circuit includes a pixel unit circuit arranged in a matrix.
  • the pixel unit circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor C, and a light emitting diode.
  • the device D, the data line V DATA , the scan line WR, and the detection signal line S, wherein the first transistor T1, the second transistor T2, and the third transistor T3 may be thin film transistors, and the light emitting device D may be AMOLED or other One of the light-emitting devices.
  • the drain of the first transistor T1 of the pixel unit circuit 10 in the nth row is connected to the first power line to receive the first voltage V DD .
  • the control electrode of the second transistor T2 is connected to the scan line WR-n of the pixel unit circuit 10, the first electrode of the second transistor T2 is connected to the data line V DATA of the pixel unit circuit 10, and the second electrode of the second transistor T2 It is connected to the control electrode of the first transistor T1 of the pixel unit circuit 10 and one of the electrodes of the storage capacitor C respectively; wherein the first electrode of the second transistor T2 can be the source or the drain, and the corresponding second stage , This office does not make restrictions.
  • the first electrode of the third transistor T3 is connected to the detection signal line S of the pixel unit circuit 10, and the second electrode of the third transistor T3 is connected to the source of the first transistor T1 of the pixel unit circuit 10 and the other of the storage capacitor C.
  • One electrode is connected to one end of the light emitting device D, and the control electrode of the third transistor T3 of the pixel unit circuit 10 in the nth row is connected to the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row;
  • the first electrode of the third transistor T3 may be the source or the drain, and the corresponding second stage, which is not limited here.
  • the other end of the light emitting device D is connected to the second power line to receive the second voltage, the second power line may be grounded, and the second voltage may be 0V.
  • the pulses of the scan line signals of the pixel unit circuits of adjacent rows are the same.
  • at least half of the pulses of the scan lines of the pixel unit circuits in the adjacent rows are the same. It may be that, in the pixel circuit, there are at least half pulses of the pulse signals of the scan lines of the upstream and downstream pixel unit circuits at the same time. Level signal, so that the second transistor T2 and the third transistor T3 respectively controlled by the uplink and downlink scan line signals are turned on at the same time.
  • the pulse signal diagram of the scanning lines of the pixel unit circuit in the adjacent row can be seen in FIG. 2.
  • the detection signal line S provides a reference voltage for the pixel unit circuit 10, and the drain of the first transistor T1 Connect the working voltage of 24V, and the other end of the light emitting device D is grounded.
  • the scan line WR-n of the pixel unit circuit 10 in the nth row is in the high state and the second transistor T21H of the pixel unit circuit 10 in the row is turned on for a time, the scan line of the pixel unit circuit 11 in the n+1th row WR-n+1 is also raised to a high level.
  • the second transistor T2 and the third transistor T3 in the pixel unit circuit 10 of the nth row are turned on at the same time, and the data line V DATA is subsequently raised to a high level.
  • the first transistor T1 in the pixel unit circuit 10 is turned on, the storage capacitor C is started to be charged, and the light-emitting device D is driven to start emitting light.
  • the scanning line WR-n+1 of the pixel unit circuit 11 in the n+1th row is raised to the high state for 1H
  • the scanning line WR-n of the pixel unit circuit 10 in the nth row is lowered to the low level.
  • the second transistor T2 is turned off, and the first transistor T1 is still turned on because the storage capacitor C begins to discharge, the voltage at the gate point Vs of the first transistor T1 is raised, and the voltage at the source point Vg of the first transistor T1 is The voltage drifts, so it is coupled by the storage capacitor C.
  • the pixel circuit may further include a last-row scan line, and the last-row scan line is connected to the control electrode of the third transistor T3 of the last-row pixel unit circuit, so as to realize the connection to the third transistor of the last-row pixel unit circuit. T3 control.
  • the scan line of the last row can be arranged under the pixel unit circuit of the last row to ensure a high aperture ratio of the pixel circuit and achieve more accurate voltage compensation.
  • the pixel unit circuit 10 may also include a reference voltage line and a data acquisition chip, the reference voltage line is connected to the detection signal line S through the reference voltage switch S1, and the data The collection chip is connected to the detection signal line S through the data collection switch S2.
  • the pixel circuit may further include an external control unit, which is connected to the scan line and the last scan line of each pixel power circuit in the pixel circuit to control all of the pixel circuit.
  • At least half of the pulses of the scan lines of adjacent rows in the pixel circuit are the same, wherein at least half of the pulses of the scan lines of the pixel unit circuits of the adjacent rows are the same, which can be:
  • In the pixel circuit there are at least half pulses of the pulse signals of the uplink and downlink scan lines (including the last scan line) at a high level signal at the same time, so that the second transistor T2 and the third transistor T3 controlled by the uplink and downlink scan line signals respectively There is a time for simultaneous conduction.
  • the pulse signal diagram of the scan line can be seen in FIGS. 3 and 5, and in conjunction with the structure diagram of the pixel unit circuit 10 in FIG. 4, the detection process of the pixel circuit can be divided into an initial stage and a detection stage. And the data reading stage.
  • the scan line WR-n of the pixel unit circuit 10 in the nth row is in a high level state to turn on the second transistor T2 of the pixel unit circuit 10 in the row.
  • the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row is in a high level state to turn on the third transistor T3.
  • the reference voltage switch S1 is turned on, and the reference voltage is provided to the pixel unit circuit 10 through the detection signal line S.
  • the data line V DATA is in a low level state, and the light emitting device D does not emit light, which is the black insertion stage V1.
  • the data line V DATA is raised to a high level state to turn on the first transistor T1 to start charging the storage capacitor C, and the light-emitting device D starts to emit light, which is the light-emitting phase V2.
  • the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row is raised to the high state for 1H, the scan line WR-n+1 of the pixel unit circuit 10 in the nth row is reduced to low.
  • the second transistor T2 is turned off, and the first transistor T1 remains open because the storage capacitor C begins to discharge, the voltage at the source point Vs of the first transistor T1 is raised, and the voltage at the gate point Vg of the first transistor T1 Due to the voltage drift, it is coupled up by the storage capacitor C.
  • the reference voltage switch S1 is turned off and stops supplying the reference voltage through the detection signal line S; the scan line WR-n of the pixel unit circuit 10 in the nth row maintains a low level state, and the second transistor T2 Keep off, the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row keeps the high level state, the third transistor T3 keeps on, the storage capacitor C keeps the discharged state, and the first transistor T1 The voltage at the source point Vs and the voltage at the gate point Vg of the first transistor T1 remain unchanged.
  • the reference voltage switch S1 remains closed and still stops providing the reference voltage; the scan line WR-n of the pixel unit circuit 10 in the nth row remains in a low level state, the second transistor T2 remains closed, and the n+th The scan line WR-n+1 of the pixel unit circuit 11 in the first row remains high, and the third transistor T3 of the pixel unit circuit 10 in the nth row remains on.
  • the data read switch Sam is opened, and the data read Take the chip to read the gate-source voltage Vgs of the first transistor T1T1 through the detection signal line S.
  • the gate-source voltage Vgs is equal to the difference between the gate voltage Vg and the source voltage Vs of the first transistor T1.
  • V DATA is used to realize voltage compensation for the pixel circuit.
  • the control electrode of the third transistor T3 of the pixel unit circuit 10 in the nth row of the pixel circuit is connected to the scan line WR-n+1 of the pixel unit circuit 11 in the n+1th row, and the At least half of the pulses of the scanning lines of the pixel unit circuits in adjacent rows are the same, and the addition of the last row of scanning lines, reference voltage lines, and data reading chips, etc., can make the detection data read through the detection signal line S
  • the gate-source voltage of the first transistor T1 taken is more accurate, thereby improving the detection accuracy of the image circuit and thus the compensation accuracy of the pixel circuit; in addition, since the pixel circuit architecture of a single scan line is still adopted, only the last scan line is added. The high aperture ratio of the pixel structure can still be ensured, and a better display effect can be achieved.
  • the present invention also provides a display device, which includes a pixel circuit, and the pixel circuit has the same or similar structure or function as the pixel circuit in the foregoing embodiment, so that the display device has a better display function.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

一种像素电路（10，11）和显示装置，像素电路（10，11）包括三个晶体管（T1、T2、T3）、存储电容（C）、发光器件（D）、数据线（V DATA）、扫描线（WR-n，WR-n+1， WR-n+2）、侦测信号线（S）；其中，第n行第三晶体管（T3）的控制极与第n+1行扫描线（WR-n+1）连接，相邻行的扫描线（WR-n与WR-n+1， WR-n+1与WR-n+2）至少有半个脉冲相同。通过对第二晶体管（T2）和第三晶体管（T3）的分别控制，提高对阈值电压的侦测精度，提高像素电路（10，11）的补偿精度。

Description

像素电路和具有该像素电路的显示装置 技术领域
本发明涉及电路以及像素驱动领域，具体而言，涉及一种像素电路和具有该像素电路的显示装置。
 背景技术
目前底发射型有源矩阵有机发光二极体（AMOLED）面板为了提高开口率，采用单扫描线的像素结构，但是单扫描线的像素结构失去了电压补偿的灵活性，降低了侦测精度，存在一定缺陷。
 技术问题
现有技术存在像素单元的高开口率和像素电路的补偿精度很难兼顾的问题。
 技术解决方案
本发明提供一种像素电路，所述像素电路包括呈矩阵分布的像素单元电路，所述像素单元电路包括第一晶体管、第二晶体管、第三晶体管、存储电容、发光器件、数据线、扫描线、侦测信号线；
所述第n行像素单元电路的第一晶体管的漏极与第一电源线连接以接收第一电压；所述第二晶体管的控制极与所述扫描线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述第一晶体管的控制极和所述存储电容的一电极分别连接；所述第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，所述第三晶体管的第一极与所述侦测信号线连接，所述第三晶体管的第二极与所述第一晶体管的源极、存储电容的另一电极和发光器件的一端分别连接；所述发光器件的另一端与第二电源线连接以接收第二电压；所述相邻行的像素单元电路的扫描线至少有半个脉冲相同。
本发明提供一种显示装置，所述显示装置的像素电路包括呈矩阵分布的像素单元电路，所述像素单元电路包括第一晶体管、第二晶体管、第三晶体管、存储电容、发光器件、数据线、扫描线、侦测信号线；
所述第n行像素单元电路的第一晶体管的漏极与第一电源线连接以接收第一电压；所述第二晶体管的控制极与所述扫描线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述第一晶体管的控制极和所述存储电容的一电极分别连接；所述第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，所述第三晶体管的第一极与所述侦测信号线连接，所述第三晶体管的第二极与所述第一晶体管的源极、存储电容的另一电极和发光器件的一端分别连接；所述发光器件的另一端与第二电源线连接以接收第二电压；所述相邻行的像素单元电路的扫描线至少有半个脉冲相同。
 有益效果
本发明通过将上述第n行的像素单元电路的第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，控制所述相邻行的像素单元电路的扫描线的脉冲关系，从而提高阈值电压的侦测精度，进而提高像素电路的补偿精度，同时采用单扫描线的像素结构，保证像素单元的高开口率，达到更好的显示效果。
 附图说明
图1为本发明一实施例所提供的像素电路等效示意图；
图2为本发明一实施例所提供的像素电路时序图；
图3为本发明另一实施例所提供的像素电路时序图；
图4为本发明另一实施例所提供的像素单元电路等效示意图；
图5为本发明另一实施例所提供的像素单元电路时序图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。在不冲突的情况下，下述各个实施例及其技术特征可以相互组合。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
如图1所示，本发明实施例提供一种像素电路，该像素电路包括呈矩阵分布的像素单元电路，该像素单元电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、存储电容C、发光器件D、数据线V DATA、扫描线WR、侦测信号线S，其中所述第一晶体管T1、第二晶体管T2和第三晶体管T3可以是薄膜晶体管，所述发光器件D可以是AMOLED或者其他发光器件。
第n行像素单元电路10的第一晶体管T1的漏极与第一电源线连接以接收第一电压V DD。第二晶体管T2的控制极与该像素单元电路10的扫描线WR-n连接，第二晶体管T2的第一极与该像素单元电路10的数据线V DATA连接，第二晶体管T2的第二极则与该像素单元电路10的第一晶体管T1的控制极和存储电容C的其中一个电极分别连接；其中该第二晶体管T2的第一极可以是源极或者漏极，以及相应的第二级，本处不做限定。第三晶体管T3的第一极与该像素单元电路10的侦测信号线S连接，第三晶体管T3的第二极与该像素单元电路10的第一晶体管T1的源极、存储电容C的另一个电极和发光器件D的一端分别连接，而该第n行像素单元电路10的第三晶体管T3的控制极则与第n+1行的像素单元电路11的扫描线WR-n+1连接；其中，该第三晶体管T3的第一极可以是源极或者漏极，以及相应的第二级，本处不做限定。此外，该像素单元电路10中，发光器件D的另一端与第二电源线连接以接收第二电压V SS，所述第二电源线可以接地，所述第二电压V SS可以为0V。
此外，在本发明所提供的像素电路中，相邻行像素单元电路的扫描线信号至少有半个脉冲相同。其中，所述相邻行的像素单元电路的扫描线至少有半个脉冲相同，可以是：在该像素电路中，上下行像素单元电路的扫描线的脉冲信号存在至少半个脉冲同时处于高电平信号，以使得上下行扫描线信号所分别控制的第二晶体管T2和第三晶体管T3同时导通。作为一种可实施的方式，所述相邻行像素单元电路的扫描线的脉冲信号图可以参见图2，当第n行的像素单元电路10的扫描线WR-n为高电平状态，导通该行像素单元电路10的第二晶体管T2 持续1H时间之后，其中，1H等于在一秒内特定频率下每行像素扫描的最大时间，第n+1行的像素单元电路的扫描线WR-n+1也被升至高电平状态。此时，第n行像素单元电路10中的第二晶体管T2和第三晶体管T3同时被导通，数据线V DATA随后也被升至高电平状态，以导通该像素单元电路10中的第一晶体管T1，并开始对存储电容C充电，并驱动发光器件D开始发光。该第n+1行的像素单元电路11的扫描线WR-n+1被升至高电平状态1H时间之后，所述第n行的像素单元电路10的扫描线WR-n降为低电平状态，所述第二晶体管T2被关闭，而第一晶体管T1由于存储电容C开始对外放电仍然被打开，第一晶体管T1栅极点Vs的电压被抬升，而第一晶体管T1源极点Vg的电压由于电压漂移，所以被电容C耦合上来，此时，侦测信号线S侦测得到的第一晶体管T1的栅源电压Vgs几乎不变，其中Vgs=Vg-Vs。
在侦测信号线S侦测获得第一晶体管T1更为精确的栅源电压Vgs之后，将该数据传输给处理芯片开始计算补偿电压，并且根据该补偿电压调整下一帧中数据线V DATA的电压，以实现对该像素电路的电压补偿。
通过将像素电路中的第n行的像素单元电路10的第三晶体管T3的控制极与第n+1行的像素单元电路11的扫描线WR-n+1连接，并且控制所述相邻行的像素单元电路的扫描线的脉冲至少有半个脉冲相同，从而使得侦测信号线S侦测的栅源电压更为精准，从而提高像电路的侦测精度，进而提高像素电路的补偿精度；此外由于仍然采用单扫描线的像素电路架构，可以保证像素结构的高开口率，达到更好的显示效果。
本发明的另一实施例还提供一种像素电路，该像素电路包括呈矩阵分布的像素单元电路，像素单元电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、存储电容C、发光器件D、数据线V DATA、扫描线WR、侦测信号线S，其中所述第一晶体管T1、第二晶体管T2和第三晶体管T3可以是薄膜晶体管，所述发光器件D可以是AMOLED或者其他发光器件当中的一种。
如图1所示，第n行像素单元电路10的第一晶体管T1的漏极与第一电源线连接以接收第一电压V DD。第二晶体管T2的控制极与该像素单元电路10的扫描线WR-n连接，第二晶体管T2的第一极与该像素单元电路10的数据线V DATA连接，第二晶体管T2的第二极则与该像素单元电路10的第一晶体管T1的控制极和存储电容C的其中一个电极分别连接；其中该第二晶体管T2的第一极可以是源极或者漏极，以及相应的第二级，本处不做限定。第三晶体管T3的第一极与该像素单元电路10的侦测信号线S连接，第三晶体管T3的第二极与该像素单元电路10的第一晶体管T1的源极、存储电容C的另一个电极和发光器件D的一端分别连接，而该第n行像素单元电路10的第三晶体管T3的控制极则与第n+1行的像素单元电路11的扫描线WR-n+1连接；其中，该第三晶体管T3的第一极可以是源极或者漏极，以及相应的第二级，本处不做限定。此外，该像素单元电路10中，发光器件D的另一端与第二电源线连接以接收第二电压，所述第二电源线可以接地，所述第二电压可以为0V。
此外，在本发明所提供的像素电路中，相邻行像素单元电路的扫描线信号至少有半个脉冲相同。其中，所述相邻行的像素单元电路的扫描线至少有半个脉冲相同，可以是，在该像素电路中，上下行像素单元电路的扫描线的脉冲信号存在至少半个脉冲同时处于高电平信号，以使得上下行扫描线信号所分别控制的第二晶体管T2和第三晶体管T3同时导通。作为一种可选择的实施方式，所述相邻行像素单元电路的扫描线的脉冲信号图可以参见图2，侦测信号线S为像素单元电路10提供参考电压，第一晶体管T1的漏极接入24V的工作电压，发光器件D的另一端接地。当第n行的像素单元电路10的扫描线WR-n为高电平状态，导通该行像素单元电路10的第二晶体管T21H时间之后，第n+1行的像素单元电路11的扫描线WR-n+1也被升至高电平状态，此时，第n行像素单元电路10中的第二晶体管T2和第三晶体管T3同时被导通，数据线V DATA随后也被升至高电平状态，以导通该像素单元电路10中的第一晶体管T1，开始对存储电容C充电，并驱动发光器件D开始发光。该第n+1行的像素单元电路11的扫描线WR-n+1被升至高电平状态1H时间之后，所述第n行的像素单元电路10的扫描线WR-n降为低电平状态，所述第二晶体管T2被关闭，而第一晶体管T1由于存储电容C开始对外放电仍然被打开，第一晶体管T1栅极点Vs的电压被抬升，而第一晶体管T1源极点Vg的电压由于电压漂移，所以被存储电容C耦合上来，此时，侦测信号线S侦测得到的第一晶体管T1的栅源电压Vgs几乎不变，其中Vgs=Vg-Vs。
在本实施例中，该像素电路还可以包括末行扫描线，该末行扫描线与末行像素单元电路的第三晶体管T3的控制极连接，以实现对末行像素单元电路的第三晶体管T3的控制。该末行扫描线可以设置于最后一行的像素单元电路的下方，保证像素电路的高开口率和实现更为精准的电压补偿。
在本实施例中，参见图4，所述像素单元电路10还可以包括参考电压线和数据采集芯片，所述参考电压线通过所述参考电压开关S1和侦测信号线S连接，所述数据采集芯片通过所述数据采集开关S2和侦测信号线S连接。
在本实施例中，所述像素电路还可以包括外部控制单元，所述外部控制单元与像素电路中的各像素电源电路的扫描线以及末行扫描线相连接，以控制所述像素电路的所有的扫描线的脉冲，使得所述像素电路中相邻行的扫描线至少有半个脉冲相同，其中所述相邻行的像素单元电路的扫描线至少有半个脉冲相同，可以是：在该像素电路中，上下行扫描线（包括末行扫描线）的脉冲信号存在至少半个脉冲同时处于高电平信号，以使得上下行扫描线信号所分别控制的第二晶体管T2和第三晶体管T3存在同时导通的时间。作为一种可实施的方式，所述扫描线的脉冲信号图可以参见图3、图5，结合像素单元电路10结构图图4，该像素电路的侦测过程可以分为初始阶段、侦测阶段和数据读取阶段。
其中，在初始阶段S1，第n行的像素单元电路10的扫描线WR-n为高电平状态，以导通该行像素单元电路10的第二晶体管T2。第n+1行的像素单元电路11的扫描线WR-n+1为高电平状态，以导通第三晶体管T3。并且此时参考电压开关S1被打开，通过侦测信号线S向像素单元电路10提供参考电压，所述数据线V DATA为低电平状态，发光器件D不发光，为插黑阶段V1。之后数据线V DATA被升至高电平状态，以导通第一晶体管T1，开始为存储电容C充电，发光器件D开始发光，为发光阶段V2。该第n+1行的像素单元电路11的扫描线WR-n+1被升至高电平状态1H时间之后，所述第n行的像素单元电路10的扫描线WR-n+1降为低电平状态，所述第二晶体管T2被关闭，而第一晶体管T1由于存储电容C开始对外放电仍然保持打开，第一晶体管T1的源极点Vs电压被抬升，第一晶体管T1的栅极点Vg电压由于电压漂移，被存储电容C耦合上来。
在侦测阶段S2，参考电压开关S1被关闭，停止通过侦测信号线S提供参考电压；第n行的像素单元电路10的扫描线WR-n保持低电平状态，所述第二晶体管T2保持关闭，第n+1行的像素单元电路11的扫描线WR-n+1保持高电平状态，所述第三晶体管T3保持打开，所述存储电容C保持放电状态，第一晶体管T1的源极点Vs电压和第一晶体管T1的栅极点Vg电压均保持不变。
在数据读取阶段S3，参考电压开关S1保持关闭，仍然停止提供参考电压；第n行的像素单元电路10的扫描线WR-n保持低电平状态，第二晶体管T2保持关闭，第n+1行的像素单元电路11的扫描线WR-n+1保持高电平状态，第n行的像素单元电路10的第三晶体管T3保持打开，此时，数据读取开关Sam被打开，数据读取芯片通过侦测信号线S读取第一晶体管T1T1的栅源电压Vgs，所述栅源电压Vgs等于第一晶体管T1的栅极电压Vg和源极电压Vs之差。
在数据读取芯片通过侦测信号线S侦测获得第一晶体管T1更为精确的栅源电压之后，将该数据进行处理并且开始计算补偿电压，并且根据该补偿电压调整下一帧中数据线V DATA的电压，以实现对该像素电路的电压补偿。
本实施例通过将像素电路中的第n行的像素单元电路10的第三晶体管T3的控制极与第n+1行的像素单元电路11的扫描线WR-n+1连接，并且控制所述相邻行的像素单元电路的扫描线的脉冲至少有半个脉冲相同，并且增加末行扫描线、参考电压线和数据读取芯片等结构，可以使得通过侦测信号线S的侦测数据读取的第一晶体管T1的栅源电压更为精准，从而提高像电路的侦测精度，进而提高像素电路的补偿精度；此外由于仍然采用单扫描线的像素电路架构，仅增加末行扫描线，仍然可以保证像素结构的高开口率，达到更好的显示效果。
本发明还提供一种显示装置，所述显示装置包括像素电路，所述像素电路与上述实施例当中的像素电路存在相同或者相似的结构或者功能，以使得该显示装置具备更好的显示功能。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。进一步地，应当理解的是，在本文中提及的“多个”是指两个或两个以上。对于本文中提及的步骤，其通过数字后缀仅仅是为了清晰表述实施例，便于理解，并不完全代表步骤执行的先后顺序，应当以逻辑关系的先后设定为思考
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种像素电路，其中，所述像素电路包括呈行排列的像素单元电路，所述像素单元电路包括第一晶体管、第二晶体管、第三晶体管、存储电容、发光器件、数据线、扫描线、侦测信号线；
    所述第n行像素单元电路的第一晶体管的漏极与第一电源线连接以接收第一电压；所述第二晶体管的控制极与所述扫描线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述第一晶体管的控制极和所述存储电容的一电极分别连接；所述第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，所述第三晶体管的第一极与所述侦测信号线连接，所述第三晶体管的第二极与所述第一晶体管的源极、存储电容的另一电极和发光器件的一端分别连接；所述发光器件的另一端与第二电源线连接以接收第二电压；所述相邻行的像素单元电路的扫描线至少有半个脉冲相同，其中，末行像素单元电路的第三晶体管的控制极与末行扫描线连接，所述侦测信号线为所述像素单元电路提供参考电压。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括外部控制单元，所述外部控制单元与所述像素单元电路的扫描线和末行扫描线连接，控制所述像素电路的扫描线的脉冲。
  3. 根据权利要求2所述的像素电路，其中，所述像素电路相邻行的扫描线至少有半个脉冲相同。
  4. 根据权利要求3所述的像素电路，其中，所述像素单元电路还包括参考电压线和数据采集芯片，所述参考电压线通过参考电压开关与侦测信号线连接，所述数据采集芯片通过所述数据采集开关与侦测信号线连接。
  5. 一种像素电路，其中，所述像素电路包括呈行排列的像素单元电路，所述像素单元电路包括第一晶体管、第二晶体管、第三晶体管、存储电容、发光器件、数据线、扫描线、侦测信号线；
    所述第n行像素单元电路的第一晶体管的漏极与第一电源线连接以接收第一电压；所述第二晶体管的控制极与所述扫描线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述第一晶体管的控制极和所述存储电容的一电极分别连接；所述第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，所述第三晶体管的第一极与所述侦测信号线连接，所述第三晶体管的第二极与所述第一晶体管的源极、存储电容的另一电极和发光器件的一端分别连接；所述发光器件的另一端与第二电源线连接以接收第二电压；所述相邻行的像素单元电路的扫描线至少有半个脉冲相同。
  6. 根据权利要求5所述的像素电路，其中，所述像素电路还包括末行扫描线，所述末行扫描线与末行像素单元电路的第三晶体管的控制极连接。
  7. 根据权利要求6所述的像素电路，其中，所述像素电路还包括外部控制单元，所述外部控制单元与所述像素单元电路的扫描线和末行扫描线连接，控制所述像素电路的扫描线的脉冲。
  8. 根据权利要求7所述的像素电路，其中，所述像素电路相邻行的扫描线至少有半个脉冲相同。
  9. 根据权利要求8所述的像素电路，其中，所述像素单元电路还包括参考电压线和数据采集芯片，所述参考电压线通过参考电压开关与侦测信号线连接，所述数据采集芯片通过所述数据采集开关与侦测信号线连接。
  10. 根据权利要求9所述的像素电路，其中，所述第二电源线接地，所述第二电压为0V。
  11. 根据权利要求10所述的像素电路，其中，所述发光器件为AMOLED。
  12. 根据权利要求11所述的像素电路，其中，所述第一晶体管、第二晶体管和第三晶体管均为薄膜晶体管。
  13. 一种显示装置，其中，所述显示装置包括像素电路，所述像素电路包括呈行排列的像素单元电路，所述像素单元电路包括第一晶体管、第二晶体管、第三晶体管、存储电容、发光器件、数据线、扫描线、侦测信号线；
    所述第n行像素单元电路的第一晶体管的漏极与第一电源线连接以接收第一电压；所述第二晶体管的控制极与所述扫描线连接，所述第二晶体管的第一极与所述数据线连接，所述第二晶体管的第二极与所述第一晶体管的控制极和所述存储电容的一电极分别连接；所述第三晶体管的控制极与第n+1行的像素单元电路的扫描线连接，所述第三晶体管的第一极与所述侦测信号线连接，所述第三晶体管的第二极与所述第一晶体管的源极、存储电容的另一电极和发光器件的一端分别连接；所述发光器件的另一端与第二电源线连接以接收第二电压；所述相邻行的像素单元电路的扫描线至少有半个脉冲相同。
  14. 根据权利要求13所述的显示装置，其中，所述像素电路还包括末行扫描线，所述末行扫描线与末行像素单元电路的第三晶体管的控制极连接。
  15. 根据权利要求14所述的显示装置，其中，所述像素电路还包括外部控制单元，所述外部控制单元与所述像素单元电路的扫描线和末行扫描线连接，控制所述像素电路的扫描线的脉冲。
  16. 根据权利要求15所述的显示装置，其中，所述像素电路相邻行的扫描线至少有半个脉冲相同。
  17. 根据权利要求16所述的显示装置，其中，所述像素单元电路还包括参考电压线和数据采集芯片，所述参考电压线通过参考电压开关与侦测信号线连接，所述数据采集芯片通过所述数据采集开关与侦测信号线连接。
  18. 根据权利要求17所述的显示装置，其中，所述第二电源线接地，所述第二电压为0V。
  19. 根据权利要求18所述的显示装置，其中，所述发光器件为AMOLED。
  20. 根据权利要求19所述的显示装置，其中，所述第一晶体管、第二晶体管和第三晶体管均为薄膜晶体管。
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