WO2021134762A1 - 一种控制方法及装置 - Google Patents

一种控制方法及装置 Download PDF

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Publication number
WO2021134762A1
WO2021134762A1 PCT/CN2020/070145 CN2020070145W WO2021134762A1 WO 2021134762 A1 WO2021134762 A1 WO 2021134762A1 CN 2020070145 W CN2020070145 W CN 2020070145W WO 2021134762 A1 WO2021134762 A1 WO 2021134762A1
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WIPO (PCT)
Prior art keywords
slave
address
peripheral
host
master control
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PCT/CN2020/070145
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English (en)
French (fr)
Inventor
李超
鲍鹏鑫
张兴新
王学寰
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20909555.3A priority Critical patent/EP4075736A4/en
Priority to CN202080002468.8A priority patent/CN113396565B/zh
Priority to PCT/CN2020/070145 priority patent/WO2021134762A1/zh
Priority to CN202310571717.0A priority patent/CN116708193A/zh
Publication of WO2021134762A1 publication Critical patent/WO2021134762A1/zh
Priority to US17/856,169 priority patent/US20220335002A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/12—Discovery or management of network topologies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling

Definitions

  • This application relates to the field of electronic communication technology, and in particular to a control method and device.
  • the inter integrated circuit (I 2 C) bus is a bidirectional serial bus used to connect the microcontroller and its peripheral devices.
  • the I 2 C bus has two signal lines, one is a serial data line ( serial data line, SDA), a serial clock line (serial clock line, SCL), all devices on the bus to an I 2 C data line is connected to the I 2 C bus SDA, all to I
  • the clock lines of the devices on the 2 C bus are all connected to the SCL in the I 2 C bus.
  • the I 2 C bus can be applied to a variety of possible scenarios, such as in-car audio systems.
  • the in-car audio system can include: audio processing (digital signal process, DSP) equipment, a transmission system, and peripheral equipment connected to the transmission system.
  • the transmission system can include multiple transmission devices; the host can communicate with one transmission device through the I 2 C bus. connection.
  • DSP digital signal process
  • the daisy chain topology can reduce the length of connecting cables, reduce the difficulty of wiring, reduce the number of DSP devices, and improve the flexibility of device deployment, multiple transmission devices in the transmission system are generally Adopt daisy chain topology.
  • the present application provides a control method and device to realize rapid control of slave devices and/or peripheral devices.
  • the embodiments of the present application provide a control method, which can be applied to a host, and the host is connected to the master control device through an I 2 C bus; in this control method, the host determines the target device that needs to be controlled, and the target device At least one of the P slave devices and/or at least one of the N peripheral devices is included; the N peripheral devices are connected to at least one of the P slave devices and the master device; the host sends to the master device Start signal; the host sends instruction information, a control command, and the address of the register of the target device to the master control device, the instruction information is used to indicate the target device, and the control command is a read command or a write command; and the host sends a stop signal to the master control device; Wherein, P and N are integers greater than or equal to 1.
  • the host since the host sends the instruction information, control command and register address of the target device to the host device after sending the start signal and before sending the stop signal, it can effectively improve the transmission efficiency and realize the target device (such as slave Fast control of equipment and/or peripheral equipment). It should be noted that, in the embodiment of the present application, the order in which the host sends the instruction information, the control command, and the address of the register of the target device is not limited.
  • the target device is the first peripheral device among the N peripheral devices;
  • the indication information includes the identification of the device connected to the first peripheral device, and also includes the index of the address of the first peripheral device or the first peripheral device. The address of the device.
  • the target device is the first slave device among the P slave devices; the indication information includes the identification of the first slave device.
  • the indication information also includes a preset index or a preset address.
  • the host sends instruction information to the master control device, including: the host obtains mapping relationship information; the mapping relationship information includes identification information, the mapping relationship between index information and address information, or the mapping relationship information includes identification The mapping relationship between information and address information; where the identification information includes the identification of P slave devices, the index information includes the index of the addresses of N peripheral devices, and the address information includes the addresses of N peripheral devices; the host, according to the mapping relationship information, Send instructions to the master device.
  • the host can determine the content included in the indication information used to indicate the target device according to the mapping relationship information, thereby effectively ensuring that the information target device is accurately indicated.
  • the manner in which the indication information indicates the target device may be predefined or agreed in advance by the host, master device, and slave device.
  • mapping relationship information includes the mapping relationship between identification information, index information, and address information
  • the identification of each slave device in the P slave devices and the peripheral device connected to each slave device
  • the mapping relationship information includes the mapping relationship between the identification information and the address information
  • the identification of each slave device in the P slave devices is associated with each Corresponds to the address of the peripheral device connected to the slave device.
  • the index information further includes a preset index
  • the address information further includes a preset address
  • control command is a read command
  • the host before the host sends a stop signal to the master control device, it also includes: the host receives the first data sent by the master control device; where the first data is from the target device Data; or, if the control command is a write command, before the host sends a stop signal to the main control device, it also includes: the host sends the second data to the main control device.
  • the embodiments of the present application provide a control method, which can be applied to a master control device, which is connected to the host via an I 2 C bus; in this control method, the master control device receives instructions from the host Information, control commands and the address of the register of the target device; the indication information is used to indicate the target device, the control command is a read command or a write command; the target device includes at least one of the P slave devices and/or N peripheral devices At least one peripheral device of the P; N peripheral devices are connected to at least one of the P slave devices; the master device sends a first message to the slave device connected to the master device, the first message includes indication information, control commands and target equipment The address of the register; where P and N are integers greater than or equal to 1.
  • the master device can send the instruction information, the control command and the address of the register of the target device to the slave device through a message, and then the slave device determines whether the target device is itself or a peripheral device connected to itself based on the instruction information.
  • the slave device determines whether the target device is itself or a peripheral device connected to itself based on the instruction information.
  • the target device is the first peripheral device among the N peripheral devices;
  • the indication information includes the identification of the device connected to the first peripheral device, and also includes the index of the address of the first peripheral device or the first peripheral device. The address of the device.
  • the method further includes: the master control device writes the identification of the device connected to the first peripheral device and the control command into the same register; or, the master control device writes the index or the first peripheral device address of the first peripheral device to the same register. The address of a peripheral device is written into the same register as the control command.
  • the identification and control command of the device connected to the first peripheral device occupy one register, or the index of the address of the first peripheral device or the address and control command of the first peripheral device occupy one register, thereby effectively saving register resources , And can also reduce the number of bits transmitted by the host to the main control device, and improve the transmission efficiency.
  • the target device is the first slave device among the P slave devices; the indication information includes the identification of the first slave device.
  • the indication information also includes a preset index or a preset address.
  • the method further includes: the master control device writes the identification of the first slave device and the control command into the same register; or, the master control device writes the preset index or the preset address and the control command into the same register. register.
  • the master control device receives the instruction information from the host, the control command and the address of the register of the target device, including: the master control device receives the start signal from the host; the master control device receives the instruction information from the host, Control command and the address of the register of the target device; the master control device receives the stop signal from the host.
  • the host since the host sends the instruction information, control command and register address of the target device to the host device after sending the start signal and before sending the stop signal, it can effectively improve the transmission efficiency and realize the target device (such as slave Fast control of equipment and/or peripheral equipment).
  • the method further includes: the master control device receives the first data from the target device and sends the first data to the host; or, if the control command is a write command , The method further includes: the master control device receives the second data from the host, and the first message further includes the second data.
  • an embodiment of the present application provides a control method, which may be applicable to a first slave device.
  • the first slave device receives a first message from the master device, and the first message includes an instruction Information, control commands and the address of the register of the target device; the indication information is used to indicate the target device, the control command is a read command or a write command; the target device includes at least one of the P slave devices and/or N peripheral devices At least one peripheral device of P; N peripheral devices are connected to at least one of P slave devices; the first slave device is any one of the P slave devices; if the first slave device determines that the target device is the first slave device , The first operation is executed according to the control command; where P and N are integers greater than or equal to 1.
  • the slave device After the slave device receives the first message from the autonomous control device, it can determine whether the target device is itself or a peripheral device connected to it based on the instruction information. When the instruction information indicates that the target device includes itself, it can be based on the control command Perform the first operation, so as to achieve rapid control of the host to the slave device, and has strong adaptability, for example, it can be applied to various complex topological structures.
  • the first slave device determines that the target device is the first slave device, including: if the first slave device determines that the indication information includes the identifier of the first slave device and the preset index or the preset address, then determining the target The device is the first slave device.
  • the method further includes: if the first slave device determines that the target device is the first peripheral device connected to the first slave device, controlling the first peripheral device to perform the first operation.
  • the peripheral device can be controlled according to the control command to perform the first operation, thereby realizing the host to the peripheral device Fast control.
  • the first slave device determines that the target device is the first peripheral device, including: if the first slave device determines that the indication information includes the identifier of the first slave device and the index of the address of the first peripheral device or the first peripheral device The address of the peripheral device determines that the target device is the first peripheral device.
  • the first message also includes the second data.
  • the first operation is at least one of a write operation, a memory clearing operation, or a read operation.
  • connection between the master control device and the P slave devices constitutes a daisy chain topology, or a ring topology, or a tree topology.
  • the present application provides a device that has the function of realizing any one of the possible designs of the first to third aspects.
  • the device includes performing any one of the first to third aspects.
  • the modules or units or means corresponding to the steps involved in this possible design can be realized by software, or by hardware, or by hardware executing corresponding software.
  • the device includes a processing unit and a communication unit.
  • the communication unit can be used to send and receive signals to achieve communication between the device and other devices; the processing unit can be used to execute some internal components of the device. operating.
  • the functions performed by the processing unit and the communication unit may correspond to the steps involved in any possible design from the first aspect to the third aspect.
  • the device includes a processor, and may also include a transceiver.
  • the transceiver is used to send and receive signals, and the processor executes program instructions to complete any possible design or implementation of the first aspect to the third aspect.
  • the device may also include one or more memories or be coupled with one or more memories.
  • One or more memories may be integrated with the processor, or may be provided separately from the processor, which is not limited in this application.
  • the memory may store necessary computer programs or instructions to realize the functions related to the first to third aspects.
  • the processor can execute the computer program or instruction stored in the memory, and when the computer program or instruction is executed, the device realizes the method in any possible design or implementation manner of the first aspect to the third aspect.
  • the device includes a processor and a memory, and the memory can store necessary computer programs or instructions for realizing the functions involved in the first to third aspects.
  • the processor can execute the computer program or instruction stored in the memory, and when the computer program or instruction is executed, the device realizes the method in any possible design or implementation manner of the first aspect to the third aspect.
  • the device includes at least one processor and an interface circuit, where at least one processor is used to communicate with other devices through the interface circuit, and execute any possible design from the first aspect to the third aspect. Or the method in the implementation mode.
  • the embodiments of the present application also provide a communication system, which includes a host, a master control device, and one or more slave devices, and the host and the master control device can be connected via an I 2 C bus; examples sexually, the master device and one or more slave devices can be connected to one or more peripheral devices.
  • the host can be used to execute the method described in any possible design of the first aspect
  • the master control device can be used to execute the method described in any possible design of the second aspect
  • the slave device can use To implement the method described in any one of the possible designs of the above-mentioned third aspect.
  • an embodiment of the present application also provides a computer storage medium, the storage medium stores a software program, and when the software program is read and executed by one or more processors, the first aspect to the third aspect may be implemented Any of the possible designs provided.
  • the embodiments of the present application also provide a computer program, which when the computer program runs on a computer, causes the computer to execute the method provided by any one of the possible designs of the first aspect to the third aspect. .
  • an embodiment of the present application also provides a chip, which is used to read a computer program stored in a memory and execute the method provided by any one of the possible designs from the first aspect to the third aspect.
  • an embodiment of the present application provides a chip system, and the chip system includes a processor for supporting the control device to implement the functions involved in the foregoing aspects.
  • the chip system further includes a memory, and the memory is used to store the necessary program instructions and data of the management device.
  • the chip system can be composed of chips, or include chips and other discrete devices.
  • FIG. 1 is a schematic diagram of a possible system architecture to which an embodiment of this application is applicable;
  • FIG. 2a is a schematic diagram of a daisy chain topology structure provided by an embodiment of the application.
  • FIG. 2b is a schematic diagram of a ring topology structure provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of another possible system architecture to which the embodiments of this application are applicable.
  • FIG. 4 is a schematic diagram of another possible system architecture to which the embodiments of this application are applicable.
  • FIG. 5 is a schematic diagram of a flow corresponding to the control method provided in Embodiment 1 of this application;
  • FIG. 6 is a schematic flow diagram corresponding to the control method provided in the second embodiment of the application.
  • FIG. 7 is a schematic flow chart corresponding to the control method provided in the third embodiment of this application.
  • FIG. 8 is a possible exemplary block diagram of a device involved in an embodiment of this application.
  • FIG. 9 is a schematic diagram of a control device provided by an embodiment of the application.
  • FIG. 1 is a system architecture diagram to which the embodiments of the application are applicable.
  • the system architecture includes a host, a transmission system connected to the host, and one or more peripheral devices connected to the transmission system.
  • the transmission system may include one or more transmission devices, one or more transmission devices include a master control device, and transmission devices other than the master control device may be called slave devices.
  • the transmission device may also be called a transmission node or node
  • the master control device may also be called a master device or a master node (Master)
  • the slave device may be called a slave node (Slave).
  • Peripheral devices can also be referred to as peripheral devices, external devices or peripherals.
  • connection relationship and connection mode between different devices in the system architecture shown in FIG. 1 will be described below.
  • the host can be connected to the master control device through an I2C (also can be written as I2C) bus.
  • I2C also can be written as I2C
  • the master device can be connected with the slave device, and different slave devices can be connected step by step.
  • the master device and the slave device and between the slave device and the slave device may be connected by a twisted pair (TP), or may also be connected in other ways, such as a coaxial, etc., which is not specifically limited.
  • TP twisted pair
  • a transmission device (such as a master device or a slave device) can be connected to a peripheral device through one or more I2C buses.
  • the transmission device 1 can be connected to one peripheral device through an I2C bus, or, Connect to multiple peripheral devices through one I2C bus, or connect to multiple peripheral devices through multiple I2C buses.
  • the master device can be connected to the peripheral device, or may not be connected to the peripheral device, and the slave device can be connected to the peripheral device, or It is also not necessary to connect peripheral devices.
  • one or more transmission devices are connected to peripheral devices as an example for description.
  • the host can control the transmission equipment in the transmission system, as well as the peripheral equipment. For example, the host can perform read and write control on the transmission equipment in the transmission system. For another example, the host can perform read and write control on peripheral devices connected to the transmission system. In addition, the host can also implement other functions, which are not listed here.
  • the host may include a processor, and the processor may be a general-purpose central processing unit (central processing unit, CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more An integrated circuit used to control the execution of the program of this application.
  • CPU central processing unit
  • ASIC application-specific integrated circuit
  • the master control device can receive the data sent by the host, encapsulate the data sent by the host, and transmit it to each slave device. It can also receive the data sent by each slave device and decapsulate the data sent by each slave device. Then sent to the host. If the main control device is connected to a peripheral device, it can also transmit data with the peripheral device, such as obtaining data collected by the peripheral device and sending data to the peripheral device. The master control device can also encapsulate the data collected by the peripheral device connected to the master control device and send it to the host, and can also decapsulate the data sent by the host and send it to the connected peripheral device. In addition, the main control device can also implement other functions, which are not listed here.
  • the slave device can obtain the data collected by the peripheral device and send it to the main control device, and can also send the data sent by the main control device to the connected peripheral device. If the slave device is an intermediate node in the daisy chain, the slave device can also forward the data sent by the subordinate slave device to the master control device, or forward the data sent by the master control device to the subordinate slave device. In addition, the slave device can also implement other functions, which are not listed here.
  • Peripheral equipment may include at least one of the following: microphone, millimeter wave radar, lidar, ultrasonic radar, camera, positioning system, inertial sensor, speed sensor, acceleration sensor, humidity sensor, light intensity sensor, and may also include playback equipment, such as Display screen, external power amplifier, speaker, etc.
  • the peripheral device may also include other possible devices, which are not listed here.
  • the network elements such as the host, master control device, and slave device involved in the embodiments of the present application may be logical concepts or physical concepts.
  • the form of the network elements such as the host, the master control device, and the slave device may be a physical device; further, multiple network elements may be multiple physical devices respectively, or multiple network elements may be aggregated into one physical device, for example, Slave 1 and Slave 2 may be on the same circuit board.
  • the form of network elements such as a host, a master control device, and a slave device may also be a function implemented by a circuit board or a chip or a chip area on the circuit board.
  • the system architecture described in Figure 1 can be applied to a variety of possible scenarios, for example, it can be applied to an in-car audio system.
  • the host may be a DSP device
  • the peripheral device may include a microphone array (MIC array), a speaker (SPK), etc.
  • P and N are both integers greater than or equal to 1, and P may be greater than N or less than N or also May be equal to N.
  • P slave devices can be slave device 0, slave device 1, slave device 2, ..., slave device P-1; among them, 0, 1, 2, ..., P-1 can be understood as slave device allocation Numbering.
  • a number may also be assigned to the master control device, for example, the number assigned to the master control device is P.
  • the master control device and slave device numbers can be respectively peripheral device 0, peripheral device 1, peripheral device 2,..., slave device N-1, where 0, 1, 2,..., N-1 can be understood as the allocation of peripheral devices Number.
  • the connections between multiple transmission devices can form a variety of possible topological structures, such as a daisy chain topology, as shown in Figure 2a; another example is a ring The topological structure is shown in Figure 2b; another example is a tree topological structure.
  • the system architecture can be applied to an in-car audio system.
  • the host and the main control device are connected through the I2C bus.
  • the host and the main control device can also be connected through an integrated audio interface (integrated interchip sound, I2S)/time-division multiplexing (time-division multiplexing).
  • I2S integrated interchip sound
  • time-division multiplexing time-division multiplexing
  • TDM pulsese code modulation
  • PDM pulse density modulation
  • GPIO general-purpose input/output
  • the master device and slave device 0 are connected by twisted pair, the slave device 0 and slave device 1 are connected by twisted pair, and the slave device 1 and slave device 2 are connected by twisted pair.
  • Slave device 0 is connected to peripheral device 1 (such as a MIC array) through the I2C bus
  • slave device 1 is connected to peripheral device 2 (such as SPK) through the I2C bus
  • slave device 2 is connected to peripheral device 3 (such as SPK) and peripherals through the I2C bus.
  • Device 4 (for example, a MIC array).
  • the transmission equipment and peripheral equipment can also be connected through the I2S/TDM/PCM/PDM/GPIO interface.
  • slave device 0 can be understood as the upper-level transmission device of slave device 1
  • slave device 1 can be understood as the lower-level transmission device of slave device 0
  • slave device 1 can be understood as the upper-level transmission device of slave device 2
  • Slave device 2 can be understood as a subordinate transmission device of slave device 1.
  • the master control device can also be connected to a power source, the power source can supply power to the master control device, the master control device can supply power to the slave devices, and each transmission device can also supply power to its connected peripherals.
  • the main control device can be connected to the power supply through the AP/AN interface, or can also be connected to the power supply through other interfaces.
  • the upper-level transmission equipment can be connected to the AP/AN interface of the lower-level transmission equipment through the BP/BN interface, so as to realize the electrical transmission and signal transmission between the upper-level transmission equipment and the lower-level transmission equipment.
  • the host can be used to process data transmitted by peripheral devices such as a microphone, such as filtering and noise reduction on voice data collected by the microphone.
  • the master control device can be used to encapsulate the data processed by the processor and send it to each slave device, and can also receive the data sent by each slave device and decapsulate it before sending it to the host.
  • the slave device can be used to send the data collected by the peripheral device to the main control device, and can also receive data from the main control device.
  • downstream data streams such as audio can be sent by the host to the master device, and then sent by the master device to each slave device, and then transmitted from the slave device to the peripheral device.
  • the transmission path can be described as Slave2->Slave1-> Slave0->Master->DSP.
  • Upstream data streams such as audio are collected and transmitted by the microphone to the slave device, sent from the slave device to the master device, and then transferred from the master device to the DSP.
  • the transmission path can be described as Slave2->Slave1->Slave0->Master->DSP .
  • the host also needs to control the master device, slave devices, and peripheral devices. For example, the host can control the main control device through the I2C interface. However, how the host can quickly control the slave and peripheral devices still needs further research at present.
  • the embodiments of the present application provide a control method for realizing rapid control of slave devices and/or peripheral devices.
  • multiple devices can share the bus on the hardware.
  • one I2C master device and one or more I2C slave devices can share the same I2C bus, that is, one I2C master device and one or more I2C slave devices Both are connected to the I2C bus through SCL and SDA.
  • Different I2C slave devices can be distinguished by addresses, that is, each I2C slave device can have a unique address, and the address can include 7 bits or 10 bits. In the embodiment of this application, 7 bits are used. Take an example for illustration. Since the I2C master device shares the same I2C bus with one or more I2C slave devices, the I2C master device needs to select the slave device that needs to communicate through addressing when communicating.
  • the I2C master device and the I2C slave device include three types of signals in the communication process, which are a start signal, a stop signal, and a response signal.
  • the start signal when SCL is kept at a high level, SDA appears a falling edge; the start signal is used to start I2C bus communication. After the start signal appears, the I2C bus is considered "busy", and subsequent I 2 C can be carried out. Bus addressing or data transmission, etc.
  • Stop signal When SCL is maintained at a high level, SDA has a rising edge; the stop signal is used to terminate I2C bus communication. After the stop signal, the bus is considered "idle”.
  • Response signal After receiving 8-bit data, the device receiving the data sends a specific low-level pulse to the device sending the data, indicating that the data has been received.
  • the communication between the I2C master device and the I2C slave device may include the I2C master device controlling the I2C slave device to read data (ie read process), and may also include the I2C master device controlling the I2C slave device to write data (ie write process).
  • the read process and the write process are described below respectively.
  • a possible writing process of the I2C bus may include the following steps:
  • Step 1 The I2C master device sends a START signal.
  • Step 2 The I2C master sends a byte and waits for ACK.
  • the first 7 bits of this byte carry the address of the I2C slave device to be controlled (I2C ADDR), and the last bit is the read and write control bit (R/W); when the read and write control bit is 1, it means the read command, read When the write control bit is 0, it means a write command.
  • Step 3 The I2C slave device (the I2C slave device is the I2C slave device to be controlled) sends an ACK.
  • Step 4 The I2C master sends a byte and waits for ACK. Among them, this byte carries the address of the register (such as register 1) of the I2C slave device.
  • Step 5 The I2C slave sends an ACK.
  • Step 6 The I2C master sends a byte and waits for ACK. Among them, this byte carries the data to be written to the I2C slave device.
  • Step 7 The I2C slave device writes data into register 1, and sends an ACK.
  • Step 8 The I2C master sends a STOP signal.
  • the read process of the I2C bus can include two processes.
  • Process 1 specifies the register address
  • process 2 reads the register data.
  • a possible reading process may include the following steps:
  • Step 1 The I2C master device sends a start signal.
  • Step 2 The I2C master device sends I2C ADDR (7bit) and write command (1bit), and waits for ACK.
  • Step 3 The I2C slave sends an ACK.
  • Step 4 The I2C master device sends the address (8bit) of the register (such as register 1) that carries the I2C slave device, and waits for an ACK.
  • the register such as register 1
  • Step 5 The I2C slave sends an ACK.
  • Step 6 The I2C master device sends a stop signal.
  • Step 7 I2C bus initialization state.
  • Step 8 The I2C master device sends a start signal.
  • Step 9 The I2C master device sends I2C ADDR (7bit) and read command (1bit), and waits for ACK.
  • Step 10 The I2C slave sends an ACK.
  • Step 11 The I2C slave sends the data (8bit) stored in register 1 and waits for ACK.
  • Step 12 The I2C master device sends an ACK.
  • Step 13 The I2C master device sends a stop signal.
  • the host can be an I2C master device, and the master control device can be an I2C slave device; the transmission device can be an I2C master device, and the peripheral device connected to the transmission device can be I2C slave device.
  • the I2C master device or the I2C slave device can include multiple registers, and each of the multiple registers can store one byte, that is, 8 bits.
  • Multiple registers can include one or more control registers.
  • multiple registers include control register 1 and control register 2. When 00000001 is written in control register 1, it means that a memory clear operation needs to be performed; when in control register 2 When 00000001 is written in, it means that a reset operation is required.
  • multiple registers include control register 3. When 00000001 is written in the control register 3, it means that a memory clear operation is required; when 00000010 is written in the control register 3, it means that a reset operation is required.
  • the system architecture applicable to the embodiments of this application includes a host, P+1 transmission devices (including a master control device and P slave devices), and N peripheral devices (N peripheral devices are connected to at least of P slave devices).
  • the host determines the target device to be controlled, it can send instruction information, control commands, and the address of the register of the target device to the master device through the I2C interface, and the master device can send the instruction information,
  • the control command and the address of the register of the target device are encapsulated and sent to the slave device connected to the master device.
  • the target device is a slave device
  • the slave device can perform the first operation according to the control command.
  • the slave device connected to the peripheral device can control the peripheral device to perform the first operation.
  • the master device can send the instruction information, the control command, and the address of the target device's register to the slave device through a message (or one-time), and the slave device determines whether the target device is itself based on the instruction information.
  • the peripheral device connected by itself which can realize the rapid control of the slave device or the peripheral device, and has strong adaptability, for example, it can be applied to various complicated topological structures.
  • the above method can be executed again, so that the switching efficiency is higher.
  • the host may obtain the first mapping relationship information, and send indication information to the master control device according to the first mapping relationship information.
  • the first mapping relationship information may be stored in the host, or may also be stored in a storage device that is independent of the host and can be accessed by the host.
  • the host stores the first mapping relationship information
  • the transmission device (such as the slave device) may store the second mapping relationship information.
  • the second mapping relationship information may also be stored in a storage device that is independent of the transmission device and can be accessed by the transmission device.
  • the first mapping relationship information and the second mapping relationship information are described below.
  • the first mapping relationship information may include a mapping relationship between identification information, index information, and address information.
  • the identification information may also include a preset number (including the first preset number and the second preset number), such as the number 3.
  • the address information may include the addresses of N peripheral devices.
  • preset number and preset index please refer to the following text.
  • the identification of the transmission device can correspond to the address of one or more peripheral devices connected to the transmission device.
  • the number of slave device 0 corresponds to PER-1 (the address of peripheral device 0) and PER-2 (the address of peripheral device 1)
  • the slave device The number of 1 corresponds to PER-1 (the address of peripheral device 2), PER-2 (the address of peripheral device 3) and PER-3 (the address of peripheral device 4)
  • the number of slave device 2 corresponds to PER-1 (peripheral device 5).
  • PER-2 the address of peripheral device 6
  • PER-3 the address of peripheral device 7).
  • the addresses of multiple peripheral devices correspond to the indexes of multiple peripheral devices one-to-one.
  • PER-1 (address of peripheral device 0) corresponds to index 1
  • PER-2 (address of peripheral device 1) corresponds to index 2.
  • the addresses of multiple peripheral devices connected to different slave devices may be completely the same or partly the same or completely different, and the indexes of the addresses of multiple peripheral devices connected to different slave devices may be completely the same or partly the same. Or completely different, the specifics are not limited.
  • the "identification" in the embodiments of the present application can also be referred to as an "index.”
  • the identifier of the slave device can also be called the index of the slave device, and similarly, the index of the address of the peripheral device can also be called the peripheral device.
  • the identification of the address or the identification of the peripheral device can also be called the specific name.
  • the second mapping relationship information may include a mapping relationship between address information and index information.
  • the address information may include the address of the peripheral device connected to the transmission device
  • the index information may include the index of the address of the peripheral device connected to the transmission device, and may also include a preset index.
  • the address of each peripheral device corresponds to the index of the address of each peripheral device.
  • each slave device can store the second mapping relationship information.
  • the second mapping relationship information stored by slave device 0 can be seen in Table 2
  • the second mapping relationship information stored by slave device 1 can be seen in Table 3
  • the second mapping relationship information stored by slave device 2 can be seen in Table 4. Shown.
  • Table 2 Example of the second mapping relationship information stored in slave 0
  • Table 3 Example of the second mapping relationship information stored in slave device 1
  • Table 4 Example of second mapping relationship information stored in slave 2
  • each slave device can also store the number and preset number of the slave device.
  • slave device 0 can store the number and preset number of slave device 0
  • slave device 1 can store The number and preset number of the slave device 1
  • the slave device 2 can store the slave device 2 number and the preset number.
  • the host may store the first mapping relationship information, and further, the transmission device may no longer store the second mapping relationship information.
  • the first mapping relationship information may include a mapping relationship between identification information and address information.
  • the identifier of each slave device in the P slave devices corresponds to the address of one or more peripheral devices connected to each slave device. See Table 5, which is an example of the first mapping relationship information.
  • the indication information sent by the host according to the first mapping relationship information may include two bytes, of which one byte (referred to as byte 1) may indicate the transmission device, Another byte (called byte 2) can indicate the peripheral device that the transmission device is connected to.
  • byte 1 may include the number of the slave device 1
  • byte 2 may include the index of the address of the peripheral device 3.
  • byte 1 may include the number of slave device 1
  • byte 2 may include the first preset index (the first preset index may be predefined and does not correspond to slave device 1 connection
  • the address of any peripheral device for example, the first preset index can be 4).
  • the first preset index may be the same or different.
  • the first preset index may be 3, and for slave device 1, the first preset index The preset index may be 4, and for the slave device 2, the first preset index may be 4.
  • byte 1 may include the first preset number (the first preset number may be predefined and does not belong to For any slave device number, for example, the first preset number is 3), byte 2 can include a second preset index (the second preset index can be predefined and does not correspond to the address of any peripheral device, such as the first The second preset index can be 4).
  • byte 1 may include the second preset number (the second preset number may be predefined and does not belong to any slave device Number, for example, the second preset number is 3), byte 2 may include a third preset index (the third preset index may be predefined, does not correspond to the address of any peripheral device, and is different from the first preset index And the second preset index, for example, the third preset index may be 5).
  • the target device includes all slave devices and all peripheral devices (that is, from device 0 to slave device 2, peripheral device 1 to peripheral device 7), byte 1 may include the third preset number (the third preset number may be A pre-defined number that does not belong to any slave device, for example, the third preset number is 3), byte 2 can include the fourth preset index (the fourth preset index can be predefined and does not correspond to any peripheral device
  • the address is different from the first preset index, the second preset index, and the third preset index.
  • the fourth preset index may be 6).
  • the indication information may include one byte or two bytes.
  • the indication information when the target device is a transmission device, the indication information may include byte 1 instead of byte 2; for example, when the target device is a slave device 0, the indication information may include byte 1 instead of byte 2.
  • byte 1 can include the number of slave device 0, that is, 0; when the target device is slave device 1, the indication information can include byte 1 instead of byte 2, and byte 1 can include slave device 1.
  • the indication information can include byte 1 instead of byte 2
  • byte 1 can include the number of slave device 2, namely 2.
  • the indication information may include two bytes. See Table 7 for multiple possible examples of the indication information indicating the target device.
  • Table 7 Multiple possible examples of the indication information indicating the target device
  • the indication information sent by the host according to the first mapping relationship information may include two bytes, one of which (referred to as byte 1) may indicate the transmission device, Another byte (called byte 2) can indicate the peripheral device that the transmission device is connected to.
  • byte 1 may include the number of slave device 1
  • byte 2 may include the address of peripheral device 3.
  • byte 1 when the target device is slave device 1, byte 1 may include the label of slave device 1, and byte 2 may include the first preset address (the first preset address may be predefined and is not connected to slave device 1.
  • the address of any peripheral device, for example, the first preset address can be PER-3).
  • byte 1 may include the first preset number (the first preset number may be predefined and does not belong to The number of any slave device, for example, the first preset number is 3), byte 2 can include the second preset address (the second preset address can be predefined, and is not the address of any peripheral device, such as the second The preset address can be PER-4).
  • byte 1 may include the second preset number (the second preset number may be predefined and does not belong to any slave device Number, for example, the second preset number is 3), byte 2 may include a third preset address (the third preset address may be predefined, not the address of any peripheral device, and is different from the first preset address and The second preset address, for example, the third preset address may be PER-5).
  • the target device includes all slave devices and all peripheral devices (that is, from device 0 to slave device 2, peripheral device 1 to peripheral device 7), byte 1 may include the third preset number (for example, the third preset number is 3) Byte 2 may include a fourth preset address (the fourth preset address may be predefined, not the address of any peripheral device, and is different from the first preset address, the second preset address, and the third preset address). Set the address, for example, the fourth preset address can be PER-6).
  • Table 8 Multiple possible examples of the indication information indicating the target device
  • Byte 1 Byte 2 Indicated target device 0 PER-1 Peripherals 0 0 PER-2 Peripheral equipment 1 1 PER-1 Peripheral equipment 2 1 PER-2 Peripheral equipment 3 1 PER-3 Peripheral equipment 4 2 PER-1 Peripheral equipment 5 2 PER-2 Peripheral equipment 6 2 PER-3 Peripheral equipment 7 0 PER-3 (First preset address) Slave 0 1 PER-4 (First preset address) Slave 1 2 PER-4 (First preset address) Slave 2 3 (First preset number) PER-4 (second preset address) Slave 0 to Slave 2 3 (second preset number) PER-5 (third preset address) Peripheral 1 to 7 3 (second preset number) PER-6 (fourth preset address) Peripheral 1 to 7
  • the difference between the instruction information sent based on the first mapping relationship information described in the implementation manner 2 and the instruction information sent based on the first mapping relationship information described in the implementation manner 1 is that the former byte 2 The address is carried in, and the index is carried in byte 2 of the latter.
  • an example of sending the instruction information based on the first mapping relationship information described in the implementation manner 1 is used for introduction.
  • the control command is used to control the target device.
  • the control command may include 1 bit. When the value of the bit is 1, it means a read command, and when the value is 0, it means a write command.
  • the control command is a read command, the first operation may be a read operation.
  • the control command is a write command, the first operation may be a write operation, a memory clearing operation, or a reset operation.
  • the control command can occupy a single byte, or the control command can also be carried in byte 1 or byte 2, thereby effectively reducing the number of bits that need to be transmitted and improving transmission efficiency.
  • the following description takes the control command carried in byte 1 as an example.
  • FIG. 5 is a schematic diagram of a flow corresponding to the control method provided by an embodiment of the application. As shown in Figure 5, the method includes:
  • step 501 the host determines that the target device to be controlled is the peripheral device 3.
  • Step 502 The host sends instruction information, a read command, and the address of the register of the peripheral device 3 to the master control device; the instruction information is used to indicate the peripheral device 3, as shown in Table 6, the instruction information may include byte 1 and byte 2. Byte 1 includes number 1, and byte 2 includes index 2. The read command is used to read the first data from the register of the peripheral device 3, and the read command can be carried in byte 1.
  • the master control device receives the instruction information, the read command, and the address of the register of the peripheral device 3.
  • Step 504 The master control device sends a first message to the slave device (ie slave device 0) connected to the master control device.
  • the first message includes indication information, a read command, and the address of the peripheral device 3 register.
  • Step 505 Slave device 0 receives the first message from the master control device.
  • Step 506 the slave device 0 determines that the target device is neither the slave device 0 nor the peripheral device of the slave device 0 (such as the peripheral device 0 or the peripheral device 1).
  • the slave device 0 may determine whether the target device is the slave device 0 or a peripheral device of the slave device 0 according to the second mapping relationship information stored by the slave device 0. For example, after receiving the instruction information from device 0, it can be judged whether the number in byte 1 is the number of slave device 0 or the preset number. If it is not the number of slave device 0 or the preset number, the reading may not be executed. operating.
  • Step 507 Slave device 0 forwards the first message to the lower-level transmission device of slave device 0 (that is, slave device 1).
  • slave device 0 can forward the first message to the lower-level transmission device of slave device 0 while determining whether the target device is slave device 0 or a peripheral device of slave device 0; or, slave device 0 can determine whether the target device is Whether it is slave device 0 or a peripheral device of slave device 0, forward the first message to the lower-level transmission device of slave device 0; or, after determining that it is neither slave device 0 nor a peripheral device of slave device 0, The first message is forwarded to the lower-level transmission device of slave device 0, which is not specifically limited.
  • step 508 the slave device 1 determines that the target device is the peripheral device 3, and controls the peripheral device 3 to perform a read operation, thereby obtaining the first data.
  • the slave device 1 may determine whether the target device is the slave device 1 or a peripheral device connected to the slave device 1 according to the second mapping relationship information stored by the slave device 1. For example, after receiving the instruction information from device 1, it is determined that the number in byte 1 is the number of slave device 1, and then the address of the peripheral device to be controlled (per-3) can be determined according to the index carried by byte 2 Then, the peripheral device 3 can be controlled to perform a read operation according to the PER-3 and the address of the register of the peripheral device 3 carried in the first message.
  • the flow of the slave device 1 controlling the peripheral device 3 to perform the read operation can refer to the I2C bus reading flow described above, and the details will not be repeated.
  • Step 509 The slave device 1 sends the first data to the master device.
  • the slave device 1 may first send the first data to the slave device 0, and then the slave device 0 forwards it to the master control device.
  • Step 510 The master control device sends the first data to the host.
  • the host After sending the start signal and before sending the stop signal, the host can send the instruction information, the control command (ie read command) and the register address of the target device (ie peripheral device 3) to the host device, and receive the first data.
  • the communication between the host and the master control device may include the following steps:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends instruction information, a control command (ie, a read command) and the address of the register of the peripheral device 3 to the master control device.
  • a control command ie, a read command
  • Step 3 The master control device sends the first data to the host.
  • Step 4 The host sends a stop signal to the main control device.
  • the host and the main control device can communicate through the I2C bus
  • the following describes the communication between the host and the main control device in detail based on the I2C communication process, for example, the following steps may be included:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends the address and write command of the master device to the master device, and waits for the ACK. Among them, the write command is used to control the main control device to perform the write operation.
  • Step 3 The master device sends an ACK.
  • Step 4 The host sends the address of register 1 of the master device to the master device and waits for the ACK.
  • Step 5 The master device sends an ACK.
  • Step 6 The host sends byte 1 to the master control device and waits for ACK.
  • byte 1 can include number 1 and read commands.
  • Step 7 The master device sends an ACK.
  • the master device can write the content carried by byte 1 into register 1.
  • Step 8 The host sends byte 2 to the master control device and waits for ACK.
  • byte 2 may include index 2.
  • Step 9 The master device sends an ACK.
  • the master control device can sequentially write the content carried by byte 2 into register 2 of the master control device.
  • Step 10 The host sends the address of the register of the peripheral device 3 to the master control device and waits for the ACK.
  • Step 11 The master device sends an ACK.
  • the master control device After the master control device receives the instruction information, the control command, and the address of the register of the peripheral device 3, it can execute the above steps 504 to 509 to obtain the first data from the register of the peripheral device 3.
  • Step 12 The master control device sends the first data to the host.
  • Step 13 The host sends an ACK to the master control device.
  • step 14 the host sends a stop signal to the master control device.
  • the order of the host sending instruction information, control commands, and the address of the register of the target device is not limited.
  • the host first sends the node number and reads to the master device. Command, then send the index of the target device's address, and then send the address of the target device's register as an example; in other embodiments, it can also be other possible sequences, for example, the host sends the target device to the master device first Then send the node number and read command, and then send the address of the register of the target device.
  • the host since the host sends the instruction information, the control command and the address of the register of the target device to the main control device after sending the start signal and before sending the stop signal, the transmission efficiency can be effectively improved and the target device (such as the rapid control of slave devices and/or peripheral devices.
  • the host can send the start signal and stop signal multiple times. Between each group of start signal and stop signal, one or more bytes of information can be sent.
  • the communication between the host and the master control device may include the following steps:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends instruction information and control commands to the main control device.
  • Step 3 The host sends a stop signal to the main control device.
  • Step 4 The host sends a start signal to the master control device.
  • Step 5 The host sends the address of the register of the target device (ie, peripheral device 3) to the master control device.
  • Step 6 The master control device sends the first data to the host.
  • Step 7 The host sends a stop signal to the main control device.
  • the following describes the communication between the host and the main control device in detail based on the I2C communication process. For example, the following steps may be included:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends the address and write command of the master device to the master device, and waits for the ACK. Among them, the write command is used to control the main control device to perform the write operation.
  • Step 3 The master device sends an ACK.
  • Step 4 The host sends the address of register 1 of the master device to the master device and waits for the ACK.
  • Step 5 The master device sends an ACK.
  • Step 6 The host sends byte 1 to the master control device and waits for ACK.
  • byte 1 can include number 1 and read commands.
  • Step 7 The master device sends an ACK.
  • the master device can write the content carried by byte 1 into register 1.
  • Step 8 The host sends byte 2 to the master control device and waits for ACK.
  • byte 2 may include index 2.
  • Step 9 The master device sends an ACK.
  • the master control device can sequentially write the content carried by byte 2 into register 2 of the master control device.
  • Step 10 The host sends a stop signal to the main control device.
  • Step 11 The host sends a start signal to the master control device.
  • Step 12 The host sends the address of the register of the peripheral device 3 to the master device and waits for the ACK.
  • Step 13 The master device sends an ACK.
  • Step 14 The master control device sends the first data to the host.
  • Step 15 The host sends an ACK to the master control device.
  • Step 16 The host sends a stop signal to the master control device.
  • the host since the host can send the start signal and the stop signal multiple times, and send one or more bytes of information between each group of start signal and stop signal, it can be sent after a certain start signal.
  • you can re-send the information sent after the start signal for example, if the address of the register of the peripheral device 3 sent by the host to the master device in the above step 12 is wrong, you can re-execute steps 11 and 12 , Without re-executing steps 1 to 10), which can effectively ensure timely correction in the case of information errors.
  • the host writes the instruction information, the read command, and the address of the register of the target device into the master device
  • the master device can send the instruction information, the read command, and the address of the register of the target device to the master device through a message.
  • the slave device and then the slave device determines whether the target device is itself or a peripheral device connected to itself based on the instruction information, so that data can be quickly read from the slave device or peripheral device, and it has strong adaptability, such as Applicable to various complex topological structures.
  • the above method can be executed again, so that the switching efficiency is higher.
  • FIG. 6 is a schematic diagram of a flow corresponding to the control method provided by an embodiment of the application. As shown in Figure 6, the method includes:
  • step 601 the host determines that the target device to be controlled is the peripheral device 3.
  • Step 602 The host sends instruction information, a write command, the address of the register of the peripheral device 3, and the second data to the master control device; the instruction information is used to instruct the peripheral device 3, as shown in Table 6, the instruction information may include byte 1 and Byte 2, byte 1 includes number 1, and byte 2 includes index 2.
  • the write command is used to write the second data into the register of the peripheral device 3, and the write command can be carried in byte 1.
  • the master control device receives the instruction information, the write command, the address of the register of the peripheral device 3, and the second data.
  • Step 604 The master control device sends a first message to the slave device (ie slave device 0) connected to the master control device.
  • the first message includes the indication information, the address of the register of the peripheral device 3, the write command and the second data.
  • Step 606 Slave device 0 receives the first message from the master device.
  • step 606 the slave device 0 determines that the target device is neither the slave device 0 nor the peripheral device of the slave device 0.
  • Step 607 Slave device 0 forwards the first message to the lower-level transmission device of slave device 0 (that is, slave device 1).
  • step 608 the slave device 1 determines that the target device is the peripheral device 3, and controls the peripheral device 3 to perform a write operation, that is, controls the peripheral device 3 to write the second data into the register of the peripheral device 3.
  • the process of the slave device 1 controlling the peripheral device 3 to perform the write operation can refer to the I2C bus write process described above, and the details will not be repeated.
  • Step 609 The slave device 1 sends response information (such as ACK) to the master device.
  • response information such as ACK
  • Step 610 The master control device sends response information (such as ACK) to the host.
  • response information such as ACK
  • the communication between the host and the master control device in this embodiment will be described in detail below.
  • the communication between the host and the master control device may include the following steps:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends instruction information, a control command (ie, a write command), the address of the register of the peripheral device 3, and the second data to the main control device.
  • a control command ie, a write command
  • Step 3 The master control device sends an ACK to the host.
  • Step 4 The host sends a stop signal to the main control device.
  • the following describes the communication between the host and the main control device in detail based on the I2C communication process. For example, the following steps may be included:
  • Step 1 The host sends a start signal to the main control device.
  • Step 2 The host sends the address and write command of the master device to the master device, and waits for the ACK. Among them, the write command is used to control the main control device to perform the write operation.
  • Step 3 The master device sends an ACK.
  • Step 4 The host sends the address of register 1 of the master device to the master device and waits for the ACK.
  • Step 5 The master device sends an ACK.
  • Step 6 The host sends byte 1 to the master control device and waits for ACK.
  • byte 1 can include number 1 and write commands.
  • Step 7 The master device sends an ACK.
  • the master device can write the content carried by byte 1 into register 1.
  • Step 8 The host sends byte 2 to the master control device and waits for ACK.
  • byte 2 may include index 2.
  • Step 9 The master device sends an ACK.
  • the master control device can sequentially write the content carried by byte 2 into register 2 of the master control device.
  • Step 10 The host sends the address of the register of the peripheral device 3 to the master control device and waits for the ACK.
  • Step 11 The master device sends an ACK.
  • Step 12 The host sends the second data to the master control device and waits for the ACK.
  • step 604 to step 609 can be executed.
  • Step 13 the master control device sends an ACK, that is, the master control device sends a response message to the host.
  • step 14 the host sends a stop signal to the master control device.
  • the host writes the instruction information, the write command, the address of the register of the target device, and the second data into the master control device
  • the master device can send the instruction information, the address of the register of the target device, and the address of the register of the target device through a message.
  • the write command and the second data are sent to the slave device, and then the slave device determines whether the target device is itself or a peripheral device connected to itself based on the instruction information, so that data can be written to the slave device or peripheral device quickly, and has a relatively high performance. Strong adaptability, for example, it can be applied to various complex topological structures.
  • the above method can be executed again, so that the switching efficiency is higher.
  • FIG. 7 is a schematic diagram of a flow corresponding to the control method provided by an embodiment of the application. As shown in Figure 7, the method includes:
  • step 701 the host determines that the target devices to be controlled are slave device 0, slave device 1, and slave device 2.
  • Step 702 The host sends instruction information, a write command, the address of the register of the target device (such as the control register 1 of the target device), and third data to the master control device; the instruction information is used to indicate slave device 0, slave device 1, and slave device 2.
  • the indication information may include byte 1 and byte 2, byte 1 includes a first preset number (for example, 3), and byte 2 includes a second preset index (for example, 4).
  • the write command is used to write the third data into the control register 1 of the target device, thereby controlling the target device to perform the operation of clearing the memory.
  • the write command can be carried in byte 1.
  • the master control device receives the instruction information, the write command, the address of the register of the target device, and the third data.
  • Step 704 The master control device sends a first message to the slave device (ie slave device 0) connected to the master control device.
  • the first message includes indication information, a write command, an address of a register of the target device, and third data.
  • Step 705 Slave device 0 receives the first message from the master device.
  • step 706 the slave device 0 determines that the number carried in the instruction information is number 3, and then it can be learned that the target device includes the slave device 0, and executes a memory clear operation.
  • Step 707 Slave device 0 forwards the first message to the lower-level transmission device of slave device 0 (that is, slave device 1).
  • step 708 the slave device 1 determines that the number carried in the instruction information is number 3, and then it can be learned that the target device includes the slave device 1, and executes the operation of clearing the memory.
  • Step 709 The slave device 1 forwards the first message to the lower-level transmission device of the slave device 1 (that is, the slave device 2).
  • step 710 the slave device 2 determines that the number carried in the instruction information is number 3, and then it can be learned that the target device includes the slave device 2, and executes a memory clearing operation.
  • Step 711 The master control device sends an ACK to the host.
  • slave device 0 slave device 1
  • slave device 2 After the above-mentioned slave device 0, slave device 1, and slave device 2 perform the operation of clearing the memory, they can all send ACK to the master device.
  • the master device receives slave device 0, slave device 1 and slave device 2 After ACK, ACK can be sent to the host.
  • the communication between the host and the master control device in this embodiment will be described in detail below.
  • the communication between the host and the master control device may include the following steps:
  • Step 1 The host sends a start signal to the master control device.
  • Step 2 The host sends the address and write command of the master device to the master device, and waits for the ACK. Among them, the write command is used to control the main control device to perform the write operation.
  • Step 3 The master device sends an ACK.
  • Step 4 The host sends the address of register 1 of the master device to the master device and waits for the ACK.
  • Step 5 The master device sends an ACK.
  • Step 6 The host sends byte 1 to the master control device and waits for ACK.
  • byte 1 can include number 3 and write commands.
  • Step 7 The master device sends an ACK.
  • the master device can write the content carried by byte 1 into register 1.
  • Step 8 The host sends byte 2 to the master control device and waits for ACK.
  • byte 2 may include index 4.
  • Step 9 The master device sends an ACK.
  • the master control device can sequentially write the content carried by byte 2 into register 2 of the master control device.
  • Step 10 The host sends the address of the register of the target device to the master device and waits for the ACK.
  • Step 11 The master device sends an ACK.
  • Step 12 The host sends the third data to the master control device and waits for the ACK.
  • step 704 to step 710 may be executed.
  • Step 13 the master control device sends an ACK, that is, the master control device sends a response message to the host.
  • step 14 the host sends a stop signal to the master control device.
  • the host writes the instruction information, the write command, the address of the register of the target device, and the third data into the master control device, and the master control device can send the instruction information, the write command, and the register of the target device through a message.
  • the address and the third data are sent to the slave device, and then the slave device determines whether the target device is itself or a peripheral device connected to it based on the instruction information. Since the target device indicated by the indication information may include all slave devices, it is possible to quickly control all the slave devices, and has strong adaptability, such as being applicable to various complex topological structures.
  • control command may also be a write command (control the target device to execute Reset operation), for another example, the target device can also be other possible slave devices or peripheral devices, or it can also be all slave devices and all peripheral devices; the details will not be listed one by one.
  • the difference between the first embodiment and the third embodiment above is that the control command is different and/or the target device is different.
  • the first embodiment to the third embodiment can refer to each other.
  • N peripheral devices are connected to at least one of the P slave devices (that is, the master device is not connected to the peripheral device) as an example.
  • the main control device can also be connected to peripheral devices.
  • the main control device can be assigned a number, and then when the main control device receives the instruction information (byte 1 carries the number of the main control device, byte 2 carries After the index of the address of the peripheral device connected to the master control device), if the target device is determined to be the peripheral device connected to the master control device, the peripheral device can be controlled to perform the first operation.
  • the master control device may no longer send the first message to the slave device, thereby saving transmission resources.
  • the register of the master control device may include a preset register (the preset register may include multiple registers).
  • the control command and the address of the register of the target device indicate that the target device that needs to be controlled is the peripheral device connected to the master device, specifically which peripheral device is connected to the master device, which can be determined according to the address of the target device .
  • the host, the control device, and the slave device may include corresponding hardware structures and/or software modules that perform each function.
  • the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
  • the embodiments of the present application can divide the host, the control device, and the slave device into functional units according to the above method examples.
  • each functional unit can be divided corresponding to each function, or two or more functions can be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • FIG. 8 shows a possible exemplary block diagram of a device involved in an embodiment of the present application.
  • the apparatus 800 may include: a processing unit 802 and a communication unit 803.
  • the processing unit 802 is used to control and manage the actions of the device 800.
  • the communication unit 803 is used to support communication between the apparatus 800 and other devices.
  • the communication unit 803 is also called a transceiving unit, and may include a receiving unit and/or a sending unit, which are used to perform receiving and sending operations, respectively.
  • the device 800 may further include a storage unit 801 for storing program codes and/or data of the device 800.
  • the apparatus 800 may be the host (or a chip set in the host) in any of the above-mentioned embodiments, and the host may be connected to the host control device through an I 2 C bus.
  • the processing unit 802 can support the device 800 to execute the actions of the host in the above method examples; or, the processing unit 802 mainly executes the internal actions of the host in the method examples, and the communication unit 803 can support the communication between the device 800 and the master control device. Communication.
  • the processing unit 802 is configured to: determine the target device that needs to be controlled, the target device includes at least one of the P slave devices and/or at least one of the N peripheral devices; N peripheral devices Connect at least one of the P slave devices and the master device; the communication unit 803 is used to: send a start signal to the master device, send instruction information, a control command, and the address of the register of the target device to the master device; To instruct the target device, the control command is a read command or a write command; and, a stop signal is sent to the master control device; where P and N are integers greater than or equal to 1.
  • the target device is the first peripheral device among the N peripheral devices;
  • the indication information includes the identification of the device connected to the first peripheral device, and also includes the index of the address of the first peripheral device or the first peripheral device. The address of the device.
  • the target device is the first slave device among the P slave devices; the indication information includes the identification of the first slave device.
  • the indication information also includes a preset index or a preset address.
  • the processing unit 802 is configured to: obtain mapping relationship information; the mapping relationship information includes the mapping relationship between identification information, index information, and address information, or the mapping relationship information includes the mapping relationship between identification information and address information.
  • the identification information includes the identification of the P slave devices, the index information includes the index of the addresses of the N peripheral devices, and the address information includes the addresses of the N peripheral devices; the communication unit 803 is used to: according to the mapping relationship information, to The main control device sends instructions.
  • mapping relationship information includes the mapping relationship between identification information, index information, and address information
  • the identification of each slave device in the P slave devices and the peripheral device connected to each slave device
  • the mapping relationship information includes the mapping relationship between the identification information and the address information
  • the identification of each slave device in the P slave devices is associated with each Corresponds to the address of the peripheral device connected to the slave device.
  • the index information further includes a preset index
  • the address information further includes a preset address
  • control command is a read command
  • the communication unit 803 before the communication unit 803 sends a stop signal to the master control device, it is also used to: receive the first data sent by the master control device; where the first data is from the target The data of the device; or, if the control command is a write command, the communication unit 803 is also used to send the second data to the main control device before sending the stop signal to the main control device.
  • the apparatus 800 may be the main control device (or a chip set in the main control device) in any of the above embodiments, and the main control device may be connected to the host through an I 2 C bus.
  • the processing unit 802 can support the apparatus 800 to perform the actions of the master control device in the above method examples; or, the processing unit 802 mainly executes the internal actions of the master control device in the method examples, and the communication unit 803 can support the device 800 and other devices. (For example, the communication between the host and the slave).
  • the communication unit 803 is configured to: receive instruction information from the host, a control command, and the address of a register of the target device; the instruction information is used to indicate the target device, and the control command is a read command or a write command; the target device includes a P At least one of the slave devices and/or at least one of the N peripheral devices; the N peripheral devices are connected to at least one of the P slave devices; the first device is sent to the slave device connected to the master device Message, the first message includes indication information, a control command, and the address of a register of the target device; where P and N are integers greater than or equal to 1.
  • the target device is the first peripheral device among the N peripheral devices;
  • the indication information includes the identification of the device connected to the first peripheral device, and also includes the index of the address of the first peripheral device or the first peripheral device. The address of the device.
  • the processing unit 802 is configured to: write the identification of the device connected to the first peripheral device and the control command into the same register; or, write the index of the address of the first peripheral device or the address of the first peripheral device Write the same register as the control command.
  • the target device is the first slave device among the P slave devices; the indication information includes the identification of the first slave device.
  • the indication information also includes a preset index or a preset address.
  • the processing unit 802 is configured to: write the identification of the first slave device and the control command into the same register; or, the master control device writes the preset index or the preset address and the control command into the same register.
  • the communication unit 803 is specifically configured to first receive the start signal from the host, then receive the instruction information, the control command, and the address of the register of the target device from the host, and finally receive the stop signal from the host.
  • the communication unit 803 is further used to: receive the first data from the target device and send the first data to the host; or, if the control command is a write command, Then the communication unit 803 is further configured to: receive the second data from the host, and the first message further includes the second data.
  • the apparatus 800 may be the slave device (or a chip set in the slave device) in any of the above embodiments, wherein the processing unit 802 may support the apparatus 800 to perform the actions of the slave device in the above method examples; or, the processing unit 802 mainly executes the internal actions of the slave device in the method example, and the communication unit 803 can support communication between the apparatus 800 and other devices (such as the master control device, the next-level transmission device of the slave device, or the upper-level transmission device).
  • the processing unit 802 may support the apparatus 800 to perform the actions of the slave device in the above method examples; or, the processing unit 802 mainly executes the internal actions of the slave device in the method example, and the communication unit 803 can support communication between the apparatus 800 and other devices (such as the master control device, the next-level transmission device of the slave device, or the upper-level transmission device).
  • the communication unit 803 is configured to: receive a first message from the master control device, the first message includes indication information, a control command, and the address of a register of the target device; the indication information is used to indicate the target device, and the control command is A read command or a write command; the target device includes at least one of the P slave devices and/or at least one of the N peripheral devices; the N peripheral devices are connected to at least one of the P slave devices; first The slave device is any one of the P slave devices; the processing unit 802 is configured to: if it is determined that the target device is the first slave device, execute the first operation according to the control command; where P and N are greater than or equal to 1 Integer.
  • the processing unit 802 is further configured to: determine that the indication information includes the identification of the first slave device and the preset index or the preset address, and then determine that the target device is the first slave device.
  • the processing unit 802 is further configured to: if it is determined that the target device is the first peripheral device connected to the first slave device, control the first peripheral device to perform the first operation.
  • the processing unit 802 is further configured to: if it is determined that the indication information includes the identification of the first slave device and the index of the address of the first peripheral device or the address of the first peripheral device, determine that the target device is the first peripheral device. peripheral equipment.
  • the first message also includes the second data.
  • the first operation is at least one of a write operation, a memory clearing operation, or a read operation.
  • connection between the master control device and the P slave devices constitutes a daisy chain topology, or a ring topology, or a tree topology.
  • each unit in the device can be all implemented in the form of software called by processing elements; they can also be all implemented in the form of hardware; part of the units can also be implemented in the form of software called by the processing elements, and some of the units can be implemented in the form of hardware.
  • each unit can be a separate processing element, or it can be integrated in a certain chip of the device for implementation.
  • it can also be stored in the memory in the form of a program, which is called by a certain processing element of the device and executed Features.
  • all or part of these units can be integrated together or implemented independently.
  • the processing element described here can also become a processor, which can be an integrated circuit with signal processing capabilities.
  • each step of the above method or each of the above units can be implemented by the integrated logic circuit of the hardware in the processor element or implemented in the form of software calling through the processing element.
  • the unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, for example: one or more application specific integrated circuits (ASICs), or, one or Multiple microprocessors (digital singnal processors, DSPs), or, one or more field programmable gate arrays (Field Programmable Gate Arrays, FPGAs), or a combination of at least two of these integrated circuits.
  • ASICs application specific integrated circuits
  • DSPs digital singnal processors
  • FPGAs Field Programmable Gate Arrays
  • the unit in the device can be implemented in the form of a processing element scheduler
  • the processing element can be a processor, such as a general-purpose central processing unit (central processing unit, CPU), or other processors that can call programs.
  • CPU central processing unit
  • these units can be integrated together and implemented in the form of a system-on-a-chip (SOC).
  • the above receiving unit is an interface circuit of the device for receiving signals from other devices.
  • the receiving unit is an interface circuit used by the chip to receive signals from other chips or devices.
  • the above unit for sending is an interface circuit of the device for sending signals to other devices.
  • the sending unit is an interface circuit used by the chip to send signals to other chips or devices.
  • the apparatus 900 may be the host, master control device, or slave device in the foregoing embodiment.
  • the device 900 includes a processor 902, a communication interface 903, and may also include a memory 901 or have a coupling relationship with the memory 901.
  • the apparatus 900 may further include a communication line 904.
  • the communication interface 903, the processor 902, and the memory 901 may be connected to each other through a communication line 904;
  • the communication line 904 may be a peripheral component interconnection standard (peripheral component interconnect, PCI for short) bus or an extended industry standard architecture (extended industry standard architecture) , Referred to as EISA) bus and so on.
  • the communication line 904 can be divided into an address bus, a data bus, a control bus, and so on. For ease of representation, only one thick line is used in FIG. 9, but it does not mean that there is only one bus or one type of bus.
  • the processor 902 may be a CPU, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the program of the present application.
  • the function of the processor 902 may be the same as the function of the processing unit described in FIG. 8.
  • the communication interface 903 uses any device such as a transceiver to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), Wired access network, etc.
  • RAN radio access network
  • WLAN wireless local area networks
  • Wired access network etc.
  • the function of the communication interface 903 may be the same as the function of the communication unit described in FIG. 8.
  • the memory 901 may be a ROM or other types of static storage devices that can store static information and instructions, RAM or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (electrically erasable programmable read-only memory).
  • read-only memory EEPROM
  • compact disc read-only memory, CD-ROM
  • optical disc storage including compact discs, laser discs, optical discs, digital universal discs, Blu-ray discs, etc.
  • magnetic disks A storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the memory may exist independently, and is connected to the processor through a communication line 904. The memory can also be integrated with the processor.
  • the memory 901 may have the same function as the storage unit described in FIG. 8.
  • the memory 901 is used to store computer-executable instructions for executing the solution of the present application, and the processor 902 controls the execution.
  • the processor 902 is configured to execute computer-executable instructions stored in the memory 901, so as to implement the method provided in the foregoing embodiment of the present application.
  • the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
  • the embodiments of the present application also provide a computer-readable storage medium for storing computer software instructions required to execute the above-mentioned processor, which contains a program required to execute the above-mentioned processor.
  • "and/or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone. , Where A and B can be singular or plural.
  • the character "/” generally indicates that the associated objects before and after are in an "or” relationship.
  • the ordinal numbers such as "first” and “second” mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, timing, priority, or importance of multiple objects. degree.
  • the first data and the second data are only for distinguishing different data, but do not indicate the difference in priority or importance of the two types of data.
  • this application can be provided as methods, systems, or computer program products. Therefore, this application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device.
  • the device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment.
  • the instructions provide steps for implementing the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

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Abstract

本申请公开了一种控制方法及装置，其中方法包括：主机确定需要控制的目标设备后，可以通过I2C接口向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，进而主控设备可以将指示信息、控制命令和目标设备的寄存器的地址封装后发送给主控设备连接的从设备。采用该方法，由于主控设备可以通过一条消息将指示信息、控制命令和目标设备的寄存器的地址发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备，从而能够实现对从设备或外围设备的快速控制，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。此外，当需要切换目标设备时，可以再次执行上述方法，从而使得切换效率较高。

Description

一种控制方法及装置 技术领域
本申请涉及电子通信技术领域，特别涉及一种控制方法及装置。
背景技术
内部集成电路(inter integrated circuit，I 2C)总线是一种双向串行总线，用于连接微控制器及其外围设备，I 2C总线有两根信号线，一根是串行数据线(serial data line，SDA)，一根是串行时钟线(serial clock line，SCL)，所有接到I 2C总线上的设备的数据线都连接到I 2C总线中的SDA，所有接到I 2C总线上的设备的时钟线均连接到I 2C总线中的SCL。
I 2C总线可以应用到多种可能的场景中，比如可以应用于车内音频系统。车内音频系统可以包括：音频处理(digital signal process，DSP)设备、传输系统以及与传输系统连接的外围设备，传输系统中可以包括多个传输设备；主机可以通过I 2C总线与一个传输设备连接。进一步地，由于车内空间极其有限，且菊花链拓扑结构可以减少连接线缆的长度、降低布线难度、减少DSP设备的数量，提升设备部署的灵活性，因此传输系统中的多个传输设备一般采用菊花链拓扑结构。
然而，当采用菊花链拓扑结构等复杂的拓扑结构时，如何实现DSP设备对传输设备和/或外围设备的控制，目前仍需进一步的研究。
发明内容
有鉴于此，本申请提供了一种控制方法及装置，用以实现对从设备和/或外围设备的快速控制。
第一方面，本申请实施例提供一种控制方法，该控制方法可以适用于主机，主机通过I 2C总线与主控设备连接；在该控制方法中，主机确定需要控制的目标设备，目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备和主控设备中的至少一个设备；主机向主控设备发送开始信号；主机向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，指示信息用于指示目标设备，控制命令为读命令或写命令；以及，主机向主控设备发送停止信号；其中，P、N为大于或等于1的整数。
采用上述方法，由于主机是在发送开始信号之后，发送停止信号之前，向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，从而能够有效提高传输效率，实现对目标设备(比如从设备和/或外围设备)的快速控制。需要说明的是，本申请实施例中对主机发送指示信息、控制命令和目标设备的寄存器的地址等三者的顺序不做限定。
在一种可能的设计中，目标设备为N个外围设备中的第一外围设备；指示信息包括与第一外围设备连接的设备的标识，还包括第一外围设备的地址的索引或者第一外围设备的地址。
在一种可能的设计中，目标设备为P个从设备中的第一从设备；指示信息包括第一从设备的标识。
在一种可能的设计中，指示信息还包括预设索引或者预设地址。
在一种可能的设计中，主机向主控设备发送指示信息，包括：主机获取映射关系信息；映射关系信息包括标识信息、索引信息和地址信息之间的映射关系，或者，映射关系信息包括标识信息和地址信息之间的映射关系；其中，标识信息包括P个从设备的标识，索引信息包括N个外围设备的地址的索引，地址信息包括N个外围设备的地址；主机根据映射关系信息，向主控设备发送指示信息。
采用上述方法，主机可以根据映射关系信息来确定用于指示目标设备的指示信息所包括的内容，从而能够有效保证准确指示信息目标设备。示例性地，指示信息指示目标设备的方式可以是预先定义的，或者主机、主控设备和从设备预先约定的。
在一种可能的设计中，当映射关系信息包括标识信息、索引信息和地址信息之间的映射关系时，P个从设备中每个从设备的标识、与每个从设备连接的外围设备的地址、以及与每个从设备连接的外围设备的地址的索引对应；当映射关系信息包括标识信息和地址信息之间的映射关系时，P个从设备中每个从设备的标识、与每个从设备连接的外围设备的地址对应。
在一种可能的设计中，索引信息还包括预设索引，地址信息还包括预设地址。
在一种可能的设计中，若控制命令为读命令，则主机向主控设备发送停止信号之前，还包括：主机接收主控设备发送的第一数据；其中，第一数据是来自目标设备的数据；或者，若控制命令为写命令，则主机向主控设备发送停止信号之前，还包括：主机向主控设备发送第二数据。
第二方面，本申请实施例提供一种控制方法，该控制方法可以适用于主控设备，主控设备通过I 2C总线与主机连接；在该控制方法中，主控设备接收来自主机的指示信息、控制命令和目标设备的寄存器的地址；指示信息用于指示目标设备，控制命令为读命令或写命令；目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备中的至少一个设备；主控设备向与主控设备连接的从设备发送第一消息，第一消息包括指示信息、控制命令和目标设备的寄存器的地址；其中，P、N为大于或等于1的整数。
采用该方法，由于主控设备可以通过一条消息将指示信息、控制命令和目标设备的寄存器的地址发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备，从而能够实现对从设备或外围设备的快速控制，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。
在一种可能的设计中，目标设备为N个外围设备中的第一外围设备；指示信息包括与第一外围设备连接的设备的标识，还包括第一外围设备的地址的索引或者第一外围设备的地址。
在一种可能的设计中，该方法还包括：主控设备将第一外围设备连接的设备的标识与控制命令写入同一寄存器；或者，主控设备将第一外围设备的地址的索引或者第一外围设备的地址与控制命令写入同一寄存器。
采用上述方法，第一外围设备连接的设备的标识与控制命令占用一个寄存器，或者，第一外围设备的地址的索引或者第一外围设备的地址与控制命令占用一个寄存器，从而能够有效节省寄存器资源，且还能够降低主机向主控设备传输的比特数量，提高传输效率。
在一种可能的设计中，目标设备为P个从设备中的第一从设备；指示信息包括第一从设备的标识。
在一种可能的设计中，指示信息还包括预设索引或者预设地址。
在一种可能的设计中，该方法还包括：主控设备将第一从设备的标识与控制命令写入同一寄存器；或者，主控设备将预设索引或者预设地址与控制命令写入同一寄存器。
在一种可能的设计中，主控设备接收来自主机的指示信息、控制命令和目标设备的寄存器的地址，包括：主控设备接收来自主机的开始信号；主控设备接收来自主机的指示信息、控制命令和目标设备的寄存器的地址；主控设备接收来自主机的停止信号。
采用上述方法，由于主机是在发送开始信号之后，发送停止信号之前，向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，从而能够有效提高传输效率，实现对目标设备(比如从设备和/或外围设备)的快速控制。
在一种可能的设计中，若控制命令为读命令，则该方法还包括：主控设备接收来自目标设备的第一数据，并将第一数据发送给主机；或者，若控制命令为写命令，则该方法还包括：主控设备接收来自主机的第二数据，第一消息还包括第二数据。
第三方面，本申请实施例提供一种控制方法，该控制方法可以适用于第一从设备，在该控制方法中，第一从设备接收来自主控设备的第一消息，第一消息包括指示信息、控制命令和目标设备的寄存器的地址；指示信息用于指示目标设备，控制命令为读命令或写命令；目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备中的至少一个设备；第一从设备为P个从设备中的任一从设备；第一从设备若确定目标设备为第一从设备，则根据控制命令执行第一操作；其中，P、N为大于或等于1的整数。
采用上述方法，从设备接收到来自主控设备的第一消息后，可以基于指示信息来确定目标设备是否为自身或自身连接的外围设备，当指示信息指示目标设备包括自身时，可以根据控制命令执行第一操作，从而实现主机对从设备的快速控制，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。
在一种可能的设计中，第一从设备确定目标设备为第一从设备，包括：第一从设备若确定指示信息包括第一从设备的标识以及预设索引或预设地址，则确定目标设备为第一从设备。
在一种可能的设计中，该方法还包括：第一从设备若确定目标设备为第一从设备连接的第一外围设备，则控制第一外围设备执行第一操作。
采用上述方法，从设备接收到来自主控设备的第一消息后，基于指示信息确定目标设备包括自身连接的外围设备时，可以根据控制命令控制外围设备执行第一操作，从而实现主机对外围设备的快速控制。
在一种可能的设计中，第一从设备确定目标设备为第一外围设备，包括：第一从设备若确定指示信息包括第一从设备的标识以及第一外围设备的地址的索引或者第一外围设备的地址，则确定目标设备为第一外围设备。
在一种可能的设计中，若控制命令为写命令，则第一消息还包括第二数据。
在一种可能的设计中，若控制命令为写命令，则第一操作为写操作、清空内存操作或读操作中的至少一项。
在一种可能的设计中，主控设备和P个从设备之间的连接构成菊花链拓扑结构，或者环形拓扑结构，或者树形拓扑结构。
第四方面，本申请提供一种装置，该装置具备实现上述第一方面至第三方面的任一种 可能的设计的功能，比如，该装置包括执行上述第一方面至第三方面的任一种可能的设计涉及的步骤所对应的模块或单元或手段(means)，功能或单元或手段可以通过软件实现，或者通过硬件实现，也可以通过硬件执行相应的软件实现。
在一种可能的设计中，该装置包括处理单元、通信单元，其中，通信单元可以用于收发信号，以实现该装置和其它装置之间的通信；处理单元可以用于执行该装置的一些内部操作。处理单元、通信单元执行的功能可以和上述第一方面至第三方面的任一种可能的设计涉及的步骤相对应。
在一种可能的设计中，该装置包括处理器，还可以包括收发器，收发器用于收发信号，处理器执行程序指令，以完成上述第一方面至第三方面中任意可能的设计或实现方式中的方法。其中，该装置还可以包括一个或多个存储器或者与一个或多个存储器耦合。一个或多个存储器可以和处理器集成在一起，也可以与处理器分离设置，本申请并不限定。存储器可以保存实现上述第一方面至第三方面涉及的功能的必要计算机程序或指令。处理器可执行存储器存储的计算机程序或指令，当计算机程序或指令被执行时，使得该装置实现上述第一方面至第三方面任意可能的设计或实现方式中的方法。
在一种可能的设计中，该装置包括处理器和存储器，存储器可以保存实现上述第一方面至第三方面涉及的功能的必要计算机程序或指令。处理器可执行所述存储器存储的计算机程序或指令，当计算机程序或指令被执行时，使得该装置实现上述第一方面至第三方面任意可能的设计或实现方式中的方法。
在一种可能的设计中，该装置包括至少一个处理器和接口电路，其中，至少一个处理器用于通过所述接口电路与其它装置通信，并执行上述第一方面至第三方面任意可能的设计或实现方式中的方法。
第五方面，本申请实施例中还提供一种通信系统，该通信系统中包括主机、主控设备和一个或多个从设备，主机与主控设备之间可以通过I 2C总线连接；示例性地，主控设备和一个或多个从设备可以与一个或多个外围设备连接。其中，主机可以用于执行上述第一方面的任一种可能的设计所述的方法，主控设备可以用于执行上述第二方面的任一种可能的设计所述的方法，从设备可以用于执行上述第三方面的任一种可能的设计所述的方法。
第六方面，本申请实施例中还提供一种计算机存储介质，该存储介质中存储软件程序，该软件程序在被一个或多个处理器读取并执行时可实现第一方面至第三方面的任一种可能的设计提供的方法。
第七方面，本申请实施例还提供了一种计算机程序，当所述计算机程序在计算机上运行时，使得所述计算机执行上述第一方面至第三方面的任一种可能的设计提供的方法。
第八方面，本申请实施例还提供了一种芯片，所述芯片用于读取存储器中存储的计算机程序，执行上述第一方面至第三方面的任一种可能的设计提供的方法。
第九方面，本申请实施例提供了一种芯片系统，该芯片系统包括处理器，用于支持控制装置实现上述方面中所涉及的功能。在一种可能的设计中，所述芯片系统还包括存储器，所述存储器，用于保存所述管理设备必要的程序指令和数据。该芯片系统，可以由芯片构成，也可以包含芯片和其他分立器件。
本申请的这些方面或其它方面在以下实施例的描述中会更加简明易懂。
附图说明
图1为本申请实施例适用的一种可能的系统架构示意图；
图2a为本申请实施例提供的菊花链拓扑结构示意图；
图2b为本申请实施例提供的环形拓扑结构示意图；
图3为本申请实施例适用的又一种可能的系统架构示意图；
图4为本申请实施例适用的又一种可能的系统架构示意图；
图5为本申请实施例一提供的控制方法所对应的流程示意图；
图6为本申请实施例二提供的控制方法所对应的流程示意图；
图7为本申请实施例三提供的控制方法所对应的流程示意图；
图8为本申请实施例中所涉及的装置的可能的示例性框图；
图9为本申请实施例提供的一种控制装置示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
图1为本申请实施例适用的一种系统架构图，如图1所示，该系统架构包括：主机(Host)、与主机连接的传输系统和与传输系统连接的一个或多个外围设备。其中，传输系统中可以包括一个或多个传输设备，一个或多个传输设备中包括主控设备，除主控设备以外的其它传输设备可以称为从设备。示例性地，传输设备也可以称为传输节点或节点，主控设备也可以称为主设备或主节点(Master)，从设备可以称为从节点(Slave)。外围设备也可以称为外围器件、外接器件外接设备或外设。
下面对图1所示意的系统架构中不同设备之间的连接关系和连接方式进行说明。
示例性地，主机可以通过I2C(也可以写为I2C)总线与主控设备连接。主控设备可以与从设备连接，不同从设备之间可以逐级连接。其中，主控设备与从设备之间以及从设备与从设备之间可以通过双绞线(twisted pair，TP)连接，或者也可以其它方式连接，如同轴线(coaxial)等，具体不做限定。
传输设备(比如主控设备或从设备)可以通过一根或多根I2C总线与外围设备连接，以传输设备1为例，传输设备1可以通过一根I2C总线与1个外围设备连接，或者，通过一根I2C总线与多个外围设备连接，又或者，通过多根I2C总线与多个外围设备连接。需要说明的是，一个或多个传输设备中也可以存在某些不连接外围设备的传输设备，比如主控设备可以连接外围设备，或者也可以不连接外围设备，从设备可以连接外围设备，或者也可以不连接外围设备。本申请实施例中以一个或多个传输设备中均连接外围设备为例进行描述。
下面对上述各个设备进行解释说明，以便于本领域技术人员理解。
主机：主机可以控制传输系统中的传输设备，也可以控制外围设备。例如，主机可以对传输系统中传输设备进行读写控制。再例如，主机可以对传输系统连接的外围设备进行读写控制。此外，主机还可以实现其他功能，这里不再一一列举。示例性地，主机中可以包括处理器，处理器可以是一个通用中央处理器(central processing unit，CPU)、微处理器、特定应用集成电路(application-specific integrated circuit，ASIC)或一个或多个用于控 制本申请方案程序执行的集成电路。
主控设备：主控设备可以接收主机发送的数据，并将主机发送的数据进行封装后传输给各个从设备，还可以接收各个从设备发送的数据，并将各个从设备发送的数据进行解封装后发送给主机。如果主控设备连接了外围设备，还可以与外围设备之间传输数据，如获取外围设备采集的数据、向外围设备发送数据。主控设备还可以将该主控设备连接的外围设备采集的数据进行封装后发送给主机，还可以将主机发送的数据进行解封装后发送给连接的外围设备。此外，主控设备还可以实现其他功能，这里不再一一列举。
从设备：从设备可以获取外围设备采集的数据并发送给主控设备，还可以将主控设备发送的数据发送给连接的外围设备。若从设备为菊花链中的中间节点，则从设备还可以将下级从设备发送的数据转发给主控设备，或者将主控设备发送的数据转发给下级从设备。此外，从设备还可以实现其他功能，这里不再一一列举。
外围设备：可以包括以下至少一项：麦克风、毫米波雷达、激光雷达、超声波雷达、摄像头、定位系统、惯性传感器、速度传感器、加速度传感器、湿度传感器、光强度传感器，还可以包括播放设备，如显示屏、外置功放、扬声器等。在其它可能的实施例中，外围设备还可以包括其它可能的设备，此处不再一一列举。
需要说明的是：(1)本申请实施例中涉及的主机、主控设备、从设备等网元可以是逻辑概念或者也可以实体概念。比如，主机、主控设备、从设备等网元的形态可以是实体设备；进一步地，多个网元可以分别是多个实体设备，或者也可以是多个网元集合成一个实体设备，例如从设备1和从设备2可能在一个电路板上。又比如，主机、主控设备、从设备等网元的形态也可以是一块电路板或电路板上的一个芯片或一个芯片区域所实现的功能。(2)图1所描述的系统架构可以适用于多种可能的场景，比如可以适用于车内音频系统。当上述系统架构应用于车内音频系统时，主机可以为DSP设备，外围设备可以包括麦克风阵列(MIC array)、扬声器(SPK)等。
基于图1所示意的系统架构，以系统架构中包括P个从设备和N个外围设备为例，P和N均为大于或等于1的整数，P可能大于N或者也可能小于N又或者也可能等于N。P个从设备可以分别为从设备0、从设备1、从设备2、……、从设备P-1；其中，0、1、2、……、P-1可以理解为为从设备分配的编号。本申请实施例中，也可以为主控设备分配编号，比如为主控设备分配的编号为P。需要说明的是，为主控设备和从设备编号可以有多种可能的实现，比如若为从设备分配的起始编号为1，则为主控设备分配的编号也可以为0。N个外围设备可以分别为外围设备0、外围设备1、外围设备2、……、从设备N-1，其中，0、1、2、、……、N-1可以理解为为外围设备分配的编号。
示例性地，当传输系统中所包括的传输设备个数较多时，多个传输设备之间的连接可以构成多种可能的拓扑结构，比如菊花链拓扑结构，参见图2a所示；又比如环形拓扑结构，采用图2b所示；又比如树形拓扑结构。
为便于对本申请实施例进行介绍，下面以P＝3，N＝4为例，描述一种可能的系统架构，系统架构可以适用于车内音频系统。参见图3所示，主机与主控设备之间通过I2C总线连接，此外，主机与主控设备之间还可以通过集成音频接口(integrated interchip sound，I2S)/时分多路复用(time-division multiplexing，TDM)/脉冲编码调制(pulse code modulation，PCM)/脉冲密度调制(pulse density modulation，PDM)/通用输入/输出(general-purpose input/output，GPIO)接口连接。主控设备与从设备0之间通过双绞线连接，从设备0与从 设备1之间通过双绞线连接，从设备1与从设备2之间通过双绞线连接。从设备0通过I2C总线连接外围设备1(比如为MIC阵列)、从设备1通过I2C总线连接外围设备2(比如为SPK)、从设备2通过I2C总线连接外围设备3(比如为SPK)和外围设备4(比如为MIC阵列)。此外，传输设备与外围设备之间还可以通过I2S/TDM/PCM/PDM/GPIO接口相连。其中，从设备0可以理解为从设备1的上级传输设备，相应地，从设备1可以理解为从设备0的下级传输设备；从设备1可以理解为从设备2的上级传输设备，相应地，从设备2可以理解为从设备1的下级传输设备。
示例性地，主控设备还可以连接电源，电源为主控设备供电，主控设备可以为从设备供电，各个传输设备还可以为其连接的外设供电。主控设备可以通过AP/AN接口与电源相连，或者也可以通过其他接口与电源相连。上级传输设备可以通过BP/BN接口与下级传输设备的AP/AN接口相连，从而实现上级传输设备与下级传输设备之间的电传输以及信号传输。
以图3所示意的系统架构为例，主机可以用于对麦克风等外围设备传输的数据进行处理，如对麦克风采集的语音数据进行滤波、降噪等处理。主控设备可以用于将经过处理器处理的数据封装后发送到各个从设备，还可以接收各个从设备发送的数据并解封装后发送给主机。从设备可以用于将外围设备采集的数据发送给主控设备，还可以接收来自主控设备的数据。也就是说，音频等下行数据流可以由主机发送给主控设备，进而由主控设备发送给各个从设备，再由从设备传输给外围设备，其传输路径可描述为Slave2->Slave1->Slave0->Master->DSP。音频等上行数据流由麦克风采集传输给从设备，由从设备发送到主控设备，再由主控设备中转给DSP，传输的路径可描述为Slave2->Slave1->Slave0->Master->DSP。除数据流外，主机还需要对主控设备、从设备以及外围设备进行控制。比如主机可以通过I2C接口对主控设备进行控制。然而，主机如何对从设备以及外围设备进行快速控制，目前仍需进一步的研究。
基于此，本申请实施例提供一种控制方法，用于实现对从设备和/或外围设备的快速控制。
下面先对本申请实施例所涉及的相关技术特征进行介绍。需要说明的是，这些解释是为了让本申请实施例更容易被理解，而不应该视为对本申请所要求的保护范围的限定。
(1)I2C通信
在I2C总线通信架构中，多个设备可以在硬件上共享总线，比如可以由一个I2C主器件与一个或多个I2C从器件共享同一I2C总线，即一个I2C主器件与一个或多个I2C从器件都通过SCL和SDA连接在I2C总线上。不同的I2C从器件可以通过地址来区分，也就是说，每个I2C从器件可以具有唯一的地址，该地址可以包括7个比特(bit)或10个比特，本申请实施例中以7个比特为例进行说明。由于I2C主器件与一个或多个I2C从器件共享同一I2C总线，因此，I2C主器件在进行通信时需要通过寻址选择需要通信的从器件。
I2C主器件与I2C从器件在通信过程中包括三种类型信号，分别为开始信号、停止信号和应答信号。其中，开始信号：SCL保持在高电平的状态下，SDA出现下降沿；开始信号用于开始I2C总线通信，出现开始信号以后，I2C总线被认为“忙”，进而可以进行后续的I 2C总线寻址或数据传输等。停止信号：SCL保持在高电平的状态下，SDA出现上升沿； 停止信号用于终止I2C总线通信，停止信号过后，总线被认为“空闲”。应答信号：接收数据的器件在接收到8位数据后，向发送数据的器件发出特定的低电平脉冲，表示已经收到数据。
I2C主器件与I2C从器件之间的通信可以包括I2C主器件控制I2C从器件读数据(即读流程)，还可以包括I2C主器件控制I2C从器件写数据(即写流程)。下面分别对读流程和写流程进行说明。
I2C总线的一种可能的写流程可以包括如下步骤：
步骤1，I2C主器件发送开始(START)信号。
步骤2，I2C主器件发送一个字节，并等待ACK。其中，该字节的前7位携带待控制的I2C从器件的地址(I2C ADDR)，最后一位为读写控制位(R/W)；读写控制位为1时，表示读命令，读写控制位为0时，表示写命令。
步骤3，I2C从器件(该I2C从器件即为待控制的I2C从器件)发送ACK。
步骤4，I2C主器件发送一个字节，并等待ACK。其中，该字节携带I2C从器件的寄存器(比如寄存器1)的地址。
步骤5，I2C从器件发送ACK。
步骤6，I2C主器件发送一个字节，并等待ACK。其中，该字节携带要写入I2C从器件的数据。
步骤7，I2C从器件将数据写入寄存器1，并发送ACK。
步骤8，I2C主器件发出结束(STOP)信号。
需要说明的是：上述步骤6和步骤7可以连续进行，即顺序写入寄存器。
I2C总线的读流程可以包括2个过程，过程1制定寄存器地址，过程2读取寄存器数据。一种可能的读流程可以包括如下步骤：
步骤1，I2C主器件发送开始信号。
步骤2，I2C主器件发送I2C ADDR(7bit)和写命令(1bit)，等待ACK。
步骤3，I2C从器件发送ACK。
步骤4，I2C主器件发送携带I2C从器件的寄存器(比如寄存器1)的地址(8bit)，并等待ACK。
步骤5，I2C从器件发送ACK。
步骤6，I2C主器件发送停止信号。
步骤7，I2C总线初始化状态。
步骤8，I2C主器件发送开始信号。
步骤9，I2C主器件发送I2C ADDR(7bit)和读命令(1bit)，等待ACK。
步骤10，I2C从器件发送ACK。
步骤11，I2C从器件发送寄存器1中存储的数据(8bit)，等待ACK。
步骤12，I2C主器件发送ACK。
步骤13，I2C主器件发送停止信号。
示例性地，在上述图1或图3所示意的系统架构中，主机可以为I2C主器件，主控设备可以为I2C从器件；传输设备可以为I2C主器件，传输设备连接的外围设备可以为I2C从器件。
(2)寄存器
I2C主器件或I2C从器件中可以包括多个寄存器，多个寄存器中的每个寄存器可以存储一个字节，即8个比特。多个寄存器中可以包括一个或多个控制寄存器，比如多个寄存器中包括控制寄存器1和控制寄存器2，当在控制寄存器1中写入00000001时，代表需要执行清空内存操作；当在控制寄存器2中写入00000001时，代表需要执行复位操作。又比如，多个寄存器中包括控制寄存器3，当在控制寄存器3中写入00000001时，代表需要执行清空内存操作；当在控制寄存器3中写入00000010时，代表需要执行复位操作。
下面将以本申请实施例适用的系统架构中包括主机、P+1个传输设备(包括主控设备和P个从设备)、N个外围设备(N个外围设备连接P个从设备中的至少一个从设备)为例进行描述。其中，P＝3，N＝7，参见图4所示，从设备0连接外围设备0和外围设备1，从设备1连接外围设备2、外围设备3和外围设备4，从设备2连接外围设备5、外围设备6和外围设备7。
本申请实施例提供的控制方法中，主机确定需要控制的目标设备后，可以通过I2C接口向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，进而主控设备可以将指示信息、控制命令和目标设备的寄存器的地址封装后发送给主控设备连接的从设备。当目标设备为从设备时，从设备可以根据控制命令执行第一操作，当目标设备为外围设备时，外围设备连接的从设备可以控制外围设备执行第一操作。采用该方法，由于主控设备可以通过一条消息(或者说一次性)将指示信息、控制命令和目标设备的寄存器的地址发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备，从而能够实现对从设备或外围设备的快速控制，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。此外，当需要切换目标设备时，可以再次执行上述方法，从而使得切换效率较高。
示例性地，主机可以获取第一映射关系信息，并根据第一映射关系信息向主控设备发送指示信息。可以理解地，第一映射关系信息可以存储在主机中，或者也可以存储在独立于主机且主机可以访问的存储装置中。
在一种可能的实现方式(称为实现方式1)中，主机存储有第一映射关系信息，进一步地，传输设备(比如从设备)可以存储有第二映射关系信息。可以理解地，第二映射关系信息也可以存储在独立于传输设备且传输设备可以访问的存储装置中。
下面对第一映射关系信息和第二映射关系信息进行说明。
(1)第一映射关系信息
第一映射关系信息可以包括标识信息、索引信息和地址信息之间的映射关系。标识信息可以包括P(P＝3)个从设备的标识，其中从设备的标识可以为为从设备分配的编号，或者其它能够标识从设备的信息。本申请实施例中以从设备的标识为编号为例进行描述。标识信息还可以包括预设编号(包括第一预设编号和第二预设编号)，比如编号3。索引信息可以包括N(N＝7)个外围设备的地址的索引，还可以包括预设索引(包括第一预设索引、第二预设索引和第三预设索引)，比如从设备0对应的索引3、从设备1对应的索引4、从设备2对应的索引4。地址信息可以包括N个外围设备的地址。其中有关预设编号和预设索引的介绍可以参见后文。
示例性地，P个从设备中每个从设备的标识、与每个从设备连接的一个或多个外围设 备的地址、以及与每个从设备连接的一个或多个外围设备的地址的索引对应；参见表1所示，为第一映射关系信息的一种示例。
表1：第一映射关系信息示例1
Figure PCTCN2020070145-appb-000001
根据表1可以看出，从设备0的编号为0，从设备1的编号为1，从设备2的编号为2。传输设备的标识可以对应传输设备连接的一个或多个外围设备的地址，比如从设备0的编号对应PER-1(外围设备0的地址)和PER-2(外围设备1的地址)，从设备1的编号对应PER-1(外围设备2的地址)、PER-2(外围设备3的地址)和PER-3(外围设备4的地址)，从设备2的编号对应PER-1(外围设备5的地址)、PER-2(外围设备6的地址)和PER-3(外围设备7的地址)。多个外围设备的地址与多个外围设备的地址的索引一一对应，比如，PER-1(外围设备0的地址)对应索引1，PER-2(外围设备1的地址)对应索引2。
可以理解地，本申请实施例中，不同从设备连接的多个外围设备的地址可以完全相同或部分相同或完全不同，不同从设备连接的多个外围设备的地址的索引可以完全相同或部分相同或完全不同，具体不做限定。
可以理解地，本申请实施例中的“标识”也可以称为“索引”，比如从设备的标识也可以称为从设备的索引，类似地，外围设备的地址的索引也可以称为外围设备的地址的标识或者外围设备的标识。本申请各实施例对具体名称不作具体限定。
(2)第二映射关系信息
第二映射关系信息可以包括地址信息和索引信息之间的映射关系。其中，地址信息可以包括传输设备连接的外围设备的地址，索引信息可以包括传输设备连接的外围设备的地址的索引，还可以包括预设索引。其中，每个外围设备的地址与每个外围设备的地址的索引对应。
示例性地，各个从设备均可以存储第二映射关系信息。其中，从设备0存储的第二映射关系信息可以参见表2所示，从设备1存储的第二映射关系信息可以参见表3所示，从设备2存储的第二映射关系信息可以参见表4所示。
表2：从设备0存储的第二映射关系信息示例
Figure PCTCN2020070145-appb-000002
表3：从设备1存储的第二映射关系信息示例
Figure PCTCN2020070145-appb-000003
表4：从设备2存储的第二映射关系信息示例
Figure PCTCN2020070145-appb-000004
需要说明的是，各个从设备除了存储第二映射关系信息外，还可以存储从设备的编号以及预设编号，比如从设备0可以存储从设备0的编号和预设编号，从设备1可以存储从设备1的编号和预设编号，从设备2可以存储从设备2编号和预设编号。
在又一种可能的实现方式(称为实现方式2)中，主机可以存储有第一映射关系信息，进一步地，传输设备中可以不再存储第二映射关系信息。第一映射关系信息可以包括标识信息和地址信息之间的映射关系。其中标识信息可以包括P(P＝3)个从设备的编号，还可以包括预设编号；地址信息可以包括7个外围设备的地址，还可以包括预设地址。
示例性地，P个从设备中每个从设备的标识、与每个从设备连接的一个或多个外围设备的地址对应。参见表5所示，为第一映射关系信息的一种示例。
表5：第一映射关系信息示例2
Figure PCTCN2020070145-appb-000005
针对于上述实现方式1中所描述的第一映射关系信息，主机根据第一映射关系信息发送的指示信息可以包括两个字节，其中一个字节(称为字节1)可以指示传输设备、另一个字节(称为字节2)可以指示该传输设备连接的外围设备。
比如，目标设备为外围设备3时，字节1可以包括从设备1的编号，字节2可以包括外围设备3的地址的索引。
又比如，目标设备为从设备1时，字节1可以包括从设备1的编号，字节2可以包括第一预设索引(第一预设索引可以为预先定义的，且不对应从设备1连接的任何外围设备的地址，比如第一预设索引可以为4)。可以理解地，对于不同从设备来说，第一预设索引可以是相同的或者不同的，比如对于从设备0来说，第一预设索引可以为3，对于从设备1来说，第一预设索引可以为4，对于从设备2来说，第一预设索引可以为4。
又比如，目标设备包括所有从设备(即从设备0、从设备1、从设备2)时，字节1可以包括第一预设编号(第一预设编号可以为预先定义的，且不属于任何一个从设备的编号，比如第一预设编号为3)，字节2可以包括第二预设索引(第二预设索引可以为预先定义的，且不对应任何外围设备的地址，比如第二预设索引可以为4)。
又比如，目标设备包括所有外围设备(即外围设备1至外围设备7)时，字节1可以包括第二预设编号(第二预设编号可以为预先定义的，不属于任何一个从设备的编号，比如第二预设编号为3)，字节2可以包括第三预设索引(第三预设索引可以为预先定义的，不对应任何外围设备的地址，且不同于第一预设索引和第二预设索引，比如第三预设索引可以为5)。
又比如，目标设备包括所有从设备和所有外围设备(即从设备0至从设备2、外围设备1至外围设备7)，字节1可以包括第三预设编号(第三预设编号可以为预先定义的，不属于任何一个从设备的编号，比如第三预设编号为3)，字节2可以包括第四预设索引(第四预设索引可以为预先定义的，不对应任何外围设备的地址，且不同于第一预设索引、第二预设索引和第三预设索引，比如第四预设索引可以为6)。
参见表6所示，为指示信息指示目标设备的多种可能的示例。
表6：指示信息指示目标设备的多种可能的示例
Figure PCTCN2020070145-appb-000006
在其它可能的示例中，指示信息可以包括一个字节或两个字节。比如，当目标设备为传输设备时，指示信息可以包括字节1，而不再包括字节2；示例性地，当目标设备为从设备0时，指示信息可以包括字节1而不再包括字节2，字节1可以包括从设备0的编号，即0；当目标设备为从设备1时，指示信息可以包括字节1而不再包括字节2，字节1可以包括从设备1的编号，即1；当目标设备为从设备2时，指示信息可以包括字节1而不再包括字节2，字节1可以包括从设备2的编号，即2。而在其它情形中，指示信息可以包括两个字节。参见表7所示，为指示信息指示目标设备的多种可能的示例。
表7：指示信息指示目标设备的多种可能的示例
Figure PCTCN2020070145-appb-000007
需要说明的是，上述表6或表7所给出的指示信息的指示方式仅为一些可能的示例，本领域技术人员可以根据实际需要在此基础上进行变形，本申请实施例对此不做限定。
针对于上述实现方式2中所描述的第一映射关系信息，主机根据第一映射关系信息发送的指示信息可以包括两个字节，其中一个字节(称为字节1)可以指示传输设备、另一个字节(称为字节2)可以指示该传输设备连接的外围设备。
比如，目标设备为外围设备3时，字节1可以包括从设备1的编号，字节2可以包括外围设备3的地址。
又比如，目标设备为从设备1时，字节1可以包括从设备1的标号，字节2可以包括第一预设地址(第一预设地址可以为预先定义的，且不是从设备1连接的任何外围设备的地址，比如第一预设地址可以为PER-3)。
又比如，目标设备包括所有从设备(即从设备0、从设备1、从设备2)时，字节1可以包括第一预设编号(第一预设编号可以为预先定义的，且不属于任何一个从设备的编号，比如第一预设编号为3)，字节2可以包括第二预设地址(第二预设地址可以为预先定义的，且不是任何外围设备的地址，比如第二预设地址可以为PER-4)。
又比如，目标设备包括所有外围设备(即外围设备1至外围设备7)时，字节1可以 包括第二预设编号(第二预设编号可以为预先定义的，不属于任何一个从设备的编号，比如第二预设编号为3)，字节2可以包括第三预设地址(第三预设地址可以为预先定义的，不是任何外围设备的地址，且不同于第一预设地址和第二预设地址，比如第三预设地址可以为PER-5)。
又比如，目标设备包括所有从设备和所有外围设备(即从设备0至从设备2、外围设备1至外围设备7)，字节1可以包括第三预设编号(比如第三预设编号为3)，字节2可以包括第四预设地址(第四预设地址可以为预先定义的，不是任何外围设备的地址，且不同于第一预设地址、第二预设地址和第三预设地址，比如第四预设地址可以为PER-6)。
参见表8所示，为指示信息指示目标设备的多种可能的示例。
表8：指示信息指示目标设备的多种可能的示例
字节1 字节2 指示的目标设备
0 PER-1 外围设备0
0 PER-2 外围设备1
1 PER-1 外围设备2
1 PER-2 外围设备3
1 PER-3 外围设备4
2 PER-1 外围设备5
2 PER-2 外围设备6
2 PER-3 外围设备7
0 PER-3(第一预设地址) 从设备0
1 PER-4(第一预设地址) 从设备1
2 PER-4(第一预设地址) 从设备2
3(第一预设编号) PER-4(第二预设地址) 从设备0至从设备2
3(第二预设编号) PER-5(第三预设地址) 外围设备1至外围设备7
3(第二预设编号) PER-6(第四预设地址) 外围设备1至外围设备7
需要说明的是，基于实现方式2中所描述的第一映射关系信息发送的指示信息与基于实现方式1中所描述的第一映射关系信息发送的指示信息的差异之处在于，前者字节2中承载的是地址，后者字节2中承载的是索引。下文中以基于实现方式1中所描述的第一映射关系信息来发送指示信息为例进行介绍。
本申请实施例中，控制命令用于对目标设备进行控制，比如控制命令可以包括1个比特，当该比特的取值为1时，表示读命令，取值为0时，表示写命令。当控制命令为读命令时，第一操作可以为读操作，当控制命令为写命令时，第一操作可以为写操作、清空内存操作或复位操作。控制命令可以占用一个单独的字节，或者控制命令也可以承载在字节1中或字节2中，从而能够有效降低需要传输的比特数量，提高传输效率。下文中以控制命令承载在字节1中为例进行描述。
基于上述内容，下面结合实施例一至实施例三对本申请实施例提供的控制方法进行描述。
实施例一
在实施例一中，以控制命令为读命令、目标设备为外围设备3为例，结合图5对本申 请实施例提供的控制方法进行介绍。图5为本申请实施例提供的控制方法所对应的流程示意图。如图5所示，该方法包括：
步骤501，主机确定需要控制的目标设备为外围设备3。
步骤502，主机向主控设备发送指示信息、读命令和外围设备3的寄存器的地址；指示信息用于指示外围设备3，参见表6所示，指示信息可以包括字节1和字节2，字节1中包括编号1，字节2中包括索引2。读命令用于从外围设备3的寄存器中读取第一数据，读命令可以承载在字节1中。
相应地，在步骤503中，主控设备接收指示信息、读命令和外围设备3的寄存器的地址。
步骤504，主控设备向与主控设备连接的从设备(即从设备0)发送第一消息，第一消息包括指示信息、读命令和外围设备3的寄存器的地址。
步骤505，从设备0接收来自主控设备的第一消息。
步骤506，从设备0确定目标设备既不是从设备0也不是从设备0的外围设备(比如外围设备0或外围设备1)。
示例性地，从设备0可以根据从设备0存储的第二映射关系信息，确定目标设备是否为从设备0或者从设备0的外围设备。比如，从设备0接收到指示信息后，可以判断字节1中的编号是否为从设备0的编号或预设编号，若不是从设备0的编号，也不是预设编号，则可以不执行读操作。
步骤507，从设备0将第一消息转发给从设备0的下级传输设备(即从设备1)。
可以理解地，从设备0可以在确定目标设备是否为从设备0或者从设备0的外围设备的同时将第一消息转发给从设备0的下级传输设备；或者，从设备0可以在确定目标设备是否为从设备0或者从设备0的外围设备之前先将第一消息转发给从设备0的下级传输设备；又或者，也可以在确定既不是从设备0也不是从设备0的外围设备后，将第一消息转发给从设备0的下级传输设备，具体不做限定。
步骤508，从设备1确定目标设备为外围设备3，并控制外围设备3执行读操作，进而获取第一数据。
示例性地，从设备1可以根据从设备1存储的第二映射关系信息，确定目标设备是否为从设备1或从设备1连接的外围设备。比如，从设备1接收到指示信息后，确定字节1中的编号为从设备1的编号，进而可以根据字节2所携带的索引，确定需要控制的外围设备的地址(即PER-3)，进而可以根据PER-3和第一消息中携带的外围设备3的寄存器的地址控制外围设备3执行读操作。
其中，从设备1控制外围设备3执行读操作的流程可以参见前文所描述的I2C总线读流程，具体不做赘述。
步骤509，从设备1向主控设备发送第一数据。
示例性地，从设备1可以先将第一数据发送给从设备0，进而由从设备0转发给主控设备。
步骤510，主控设备向主机发送第一数据。
针对于上述步骤501至步骤510，下面结合实现方式1和实现方式2对该实施例中主机和主控设备之间的通信进行详细描述。
实现方式1
主机可以在发送开始信号之后，发送停止信号之前，向主控设备发送指示信息、控制命令(即读命令)和目标设备(即外围设备3)的寄存器的地址，以及接收第一数据。示例性地，主机和主控设备之间的通信可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送指示信息、控制命令(即读命令)和外围设备3的寄存器的地址。
步骤3，主控设备向主机发送第一数据。
步骤4，主机向主控设备发送停止信号。
示例性地，由于主机和主控设备之间可以通过I2C总线进行通信，下面基于I2C通信流程对主机和主控设备之间的通信进行详细描述，比如可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送主控设备的地址和写命令，并等待ACK。其中，写命令用于控制主控设备执行写操作。
步骤3，主控设备发送ACK。
步骤4，主机向主控设备发送主控设备的寄存器1的地址，并等待ACK。
步骤5，主控设备发送ACK。
步骤6，主机向主控设备发送字节1，并等待ACK。其中，字节1可以包括编号1和读命令。
步骤7，主控设备发送ACK。
此处，主控设备可以将字节1所承载的内容写入寄存器1。
步骤8，主机向主控设备发送字节2，并等待ACK。其中，字节2可以包括索引2。
步骤9，主控设备发送ACK。
此处，主控设备可以将字节2所承载的内容顺序写入主控设备的寄存器2。
步骤10，主机向主控设备发送外围设备3的寄存器的地址，并等待ACK。
步骤11，主控设备发送ACK。
此处，主控设备接收到指示信息、控制命令和外围设备3的寄存器的地址后，可以将执行上述步骤504至步骤509，进而获取到来自外围设备3的寄存器的第一数据。
步骤12，主控设备向主机发送第一数据。
步骤13，主机向主控设备发送ACK。
步骤14，主机向主控设备停止信号。
需要说明的是，本申请实施例中对主机发送指示信息、控制命令和目标设备的寄存器的地址等三者的顺序不做限定，上述步骤中是以主机先向主控设备发送节点编号和读命令，然后发送目标设备的地址的索引，再然后发送目标设备的寄存器的地址为例进行描述的；在其它实施例中，也可以是其它可能的顺序，比如主机先向主控设备发送目标设备的地址的索引，然后发送节点编号和读命令，再然后发送目标设备的寄存器的地址。
上述实现方式1中，由于主机是在发送开始信号之后，发送停止信号之前，向主控设备发送指示信息、控制命令和目标设备的寄存器的地址，从而能够有效提高传输效率，实现对目标设备(比如从设备和/或外围设备)的快速控制。
实现方式2
在实现方式2中，主机可以多次发送开始信号和停止信号，每一组开始信号和停止信 号之间，可以发送一个或多个字节的信息。比如，主机和主控设备之间的通信可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送指示信息和控制命令。
步骤3，主机向主控设备发送停止信号。
步骤4，主机向主控设备发送开始信号。
步骤5，主机向主控设备发送目标设备(即外围设备3)的寄存器的地址。
步骤6，主控设备向主机发送第一数据。
步骤7，主机向主控设备发送停止信号。
下面基于I2C通信流程对主机和主控设备之间的通信进行详细描述，比如可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送主控设备的地址和写命令，并等待ACK。其中，写命令用于控制主控设备执行写操作。
步骤3，主控设备发送ACK。
步骤4，主机向主控设备发送主控设备的寄存器1的地址，并等待ACK。
步骤5，主控设备发送ACK。
步骤6，主机向主控设备发送字节1，并等待ACK。其中，字节1可以包括编号1和读命令。
步骤7，主控设备发送ACK。
此处，主控设备可以将字节1所承载的内容写入寄存器1。
步骤8，主机向主控设备发送字节2，并等待ACK。其中，字节2可以包括索引2。
步骤9，主控设备发送ACK。
此处，主控设备可以将字节2所承载的内容顺序写入主控设备的寄存器2。
步骤10，主机向主控设备发送停止信号。
步骤11，主机向主控设备发送开始信号。
步骤12：主机向主控设备发送外围设备3的寄存器的地址，并等待ACK。
步骤13，主控设备发送ACK。
步骤14，主控设备向主机发送第一数据。
步骤15，主机向主控设备发送ACK。
步骤16，主机向主控设备停止信号。
在实现方式2中，由于主机可以多次发送开始信号和停止信号，并在每一组开始信号和停止信号之间发送一个或多个字节的信息，从而可以在某一次开始信号后发送的信息发生错误的情况下，重新发送该开始信号后所发送的信息即可(比如上述步骤12中主机向主控设备发送外围设备3的寄存器的地址发生错误，则可以重新执行步骤11和步骤12，而无需重新执行步骤1至步骤10)，从而能够有效保证信息发生错误情况下的及时更正。
上述实施例一中，主机将指示信息、读命令、目标设备的寄存器的地址写入主控设备中，进而主控设备可以通过一条消息将指示信息、读命令、目标设备的寄存器的地址发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备，从而能够实现快速地从从设备或外围设备中读取数据，且具有较强的适应性，比如可以适 用于各种复杂的拓扑结构。此外，当需要切换目标设备时，可以再次执行上述方法，从而使得切换效率较高。
实施例二
在实施例二中，以控制命令为写命令、目标设备为外围设备3为例，结合图6对本申请实施例提供的控制方法进行介绍。图6为本申请实施例提供的控制方法所对应的流程示意图。如图6所示，该方法包括：
步骤601，主机确定需要控制的目标设备为外围设备3。
步骤602，主机向主控设备发送指示信息、写命令、外围设备3的寄存器的地址和第二数据；指示信息用于指示外围设备3，参见表6所示，指示信息可以包括字节1和字节2，字节1中包括编号1，字节2中包括索引2。写命令用于将第二数据写入外围设备3的寄存器，写命令可以承载在字节1中。
相应地，在步骤603中，主控设备接收指示信息、写命令、外围设备3的寄存器的地址和第二数据。
步骤604，主控设备向与主控设备连接的从设备(即从设备0)发送第一消息，第一消息包括指示信息、外围设备3的寄存器的地址、写命令和第二数据。
步骤606，从设备0接收来自主控设备的第一消息。
步骤606，从设备0确定目标设备既不是从设备0也不是从设备0的外围设备。
步骤607，从设备0将第一消息转发给从设备0的下级传输设备(即从设备1)。
步骤608，从设备1确定目标设备为外围设备3，控制外围设备3执行写操作，即控制外围设备3将第二数据写入外围设备3的寄存器。
其中，从设备1控制外围设备3执行写操作的流程可以参见前文所描述的I2C总线写流程，具体不做赘述。
步骤609，从设备1向主控设备发送响应信息(比如ACK)。
步骤610，主控设备向主机发送响应信息(比如ACK)。
针对于上述步骤601至步骤610，下面对该实施例中主机和主控设备之间的通信进行详细描述。在一个示例中，主机和主控设备之间的通信可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送指示信息、控制命令(即写命令)、外围设备3的寄存器的地址和第二数据。
步骤3，主控设备向主机发送ACK。
步骤4，主机向主控设备发送停止信号。
下面基于I2C通信流程对主机和主控设备之间的通信进行详细描述，比如可以包括如下步骤：
步骤1，主机向主控设备发送开始信号。
步骤2，主机向主控设备发送主控设备的地址和写命令，并等待ACK。其中，写命令用于控制主控设备执行写操作。
步骤3，主控设备发送ACK。
步骤4，主机向主控设备发送主控设备的寄存器1的地址，并等待ACK。
步骤5，主控设备发送ACK。
步骤6，主机向主控设备发送字节1，并等待ACK。其中，字节1可以包括编号1和写命令。
步骤7，主控设备发送ACK。
此处，主控设备可以将字节1所承载的内容写入寄存器1。
步骤8，主机向主控设备发送字节2，并等待ACK。其中，字节2可以包括索引2。
步骤9，主控设备发送ACK。
此处，主控设备可以将字节2所承载的内容顺序写入主控设备的寄存器2。
步骤10，主机向主控设备发送外围设备3的寄存器的地址，并等待ACK。
步骤11，主控设备发送ACK。
步骤12，主机向主控设备发送第二数据，并等待ACK。
此处，主控设备接收到指示信息、写命令、外围设备3的寄存器的地址和第二数据后，可以执行上述步骤604至步骤609。
步骤13，主控设备发送ACK，即主控设备向主机发送响应信息。
步骤14，主机向主控设备停止信号。
上述实施例二中，主机将指示信息、写命令、目标设备的寄存器的地址和第二数据写入主控设备中，进而主控设备可以通过一条消息将指示信息、目标设备的寄存器的地址、写命令和第二数据发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备，从而能够实现快速地将数据写入从设备或外围设备，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。此外，当需要切换目标设备时，可以再次执行上述方法，从而使得切换效率较高。
实施例三
在实施例三中，以控制命令为写命令(控制目标设备执行清空内存操作)、目标设备为所有从设备(比如从设备0、从设备1和从设备2)为例，结合图7对本申请实施例提供的控制方法进行介绍。图7为本申请实施例提供的控制方法所对应的流程示意图。如图7所示，该方法包括：
步骤701，主机确定需要控制的目标设备为从设备0、从设备1和从设备2。
步骤702，主机向主控设备发送指示信息、写命令、目标设备的寄存器(比如目标设备的控制寄存器1)的地址和第三数据；指示信息用于指示从设备0、从设备1和从设备2，参见表6所示，指示信息可以包括字节1和字节2，字节1中包括第一预设编号(比如3)，字节2中包括第二预设索引(比如4)。写命令用于将第三数据写入目标设备的控制寄存器1，进而控制目标设备执行清空内存操作，写命令可以承载在字节1中。
相应地，在步骤703中，主控设备接收指示信息、写命令、目标设备的寄存器的地址和第三数据。
步骤704，主控设备向与主控设备连接的从设备(即从设备0)发送第一消息，第一消息包括指示信息、写命令、目标设备的寄存器的地址和第三数据。
步骤705，从设备0接收来自主控设备的第一消息。
步骤706，从设备0确定指示信息中所携带的编号为编号3，进而可以获知目标设备包括从设备0，并执行清空内存操作。
步骤707，从设备0将第一消息转发给从设备0的下级传输设备(即从设备1)。
步骤708，从设备1确定指示信息中所携带的编号为编号3，进而可以获知目标设备包括从设备1，并执行清空内存操作。
步骤709，从设备1将第一消息转发给从设备1的下级传输设备(即从设备2)。
步骤710，从设备2确定指示信息中所携带的编号为编号3，进而可以获知目标设备包括从设备2，并执行清空内存操作。
步骤711，主控设备向主机发送ACK。
需要说明的是，上述从设备0、从设备1和从设备2执行清空内存操作后，均可以向主控设备发送ACK，主控设备在接收到从设备0、从设备1和从设备2的ACK后，可以向主机发送ACK。
针对于上述步骤701至步骤711，下面对该实施例中主机和主控设备之间的通信进行详细描述。在一个示例中，主机和主控设备之间的通信可以包括如下步骤：
步骤1：主机向主控设备发送开始信号。
步骤2：主机向主控设备发送主控设备的地址和写命令，并等待ACK。其中，写命令用于控制主控设备执行写操作。
步骤3，主控设备发送ACK。
步骤4：主机向主控设备发送主控设备的寄存器1的地址，并等待ACK。
步骤5，主控设备发送ACK。
步骤6：主机向主控设备发送字节1，并等待ACK。其中，字节1可以包括编号3和写命令。
步骤7，主控设备发送ACK。
此处，主控设备可以将字节1所承载的内容写入寄存器1。
步骤8：主机向主控设备发送字节2，并等待ACK。其中，字节2可以包括索引4。
步骤9，主控设备发送ACK。
此处，主控设备可以将字节2所承载的内容顺序写入主控设备的寄存器2。
步骤10：主机向主控设备发送目标设备的寄存器的地址，并等待ACK。
步骤11，主控设备发送ACK。
步骤12，主机向主控设备发送第三数据，并等待ACK。
此处，主控设备接收到指示信息、写命令、目标设备的寄存器的地址和第三数据后，可以执行上述步骤704至步骤710。
步骤13，主控设备发送ACK，即主控设备向主机发送响应信息。
步骤14，主机向主控设备停止信号。
上述实施例三中，主机将指示信息、写命令、目标设备的寄存器的地址和第三数据写入主控设备中，进而主控设备可以通过一条消息将指示信息、写命令、目标设备的寄存器的地址和第三数据发送给从设备，进而由从设备基于指示信息来确定目标设备是否为自身或自身连接的外围设备。由于指示信息所指示的目标设备可以包括所有从设备，从而能够实现快速地控制所有从设备，且具有较强的适应性，比如可以适用于各种复杂的拓扑结构。
需要说明的是：(1)上述实施例一至实施例三所描述的为本申请实施例的一些可能的实现，在其它可能的实施例中，比如控制命令还可以为写命令(控制目标设备执行复位操作)，又比如目标设备还可以为其它可能的从设备或外围设备，或者还可以为所有从设备 和所有外围设备；具体不再一一列举。
(2)上述实施例一至实施例三的差异之处在于，控制命令不同和/或目标设备不同，除此差异之外的其它内容，实施例一至实施例三之间可以相互参照。
(3)上述实施例一至实施例三中是以N个外围设备连接P个从设备中的至少一个从设备(即主控设备不连接外围设备)为例进行描述的，在其它可能的实施例中，主控设备也可以连接外围设备。当主控设备连接外围设备时，在一种可能的实现方式中，可以为主控设备分配编号，进而当主控设备接收到指示信息(字节1携带主控设备的编号，字节2携带主控设备连接的外围设备的地址的索引)后，若确定目标设备为主控设备连接的外围设备，则可以控制外围设备执行第一操作。进一步地，主控设备可以不再向从设备发送第一消息，从而节省传输资源。在又一种可能的实现方式中，主控设备的寄存器中可以包括预设寄存器(预设寄存器可以包括多个寄存器)，当主机向预设寄存器中写入目标设备的地址(或目标设备的地址的索引)、控制命令和目标设备的寄存器的地址时，表示需要控制的目标设备为主控设备连接的外围设备，具体是主控设备连接的哪个外围设备，可以根据目标设备的地址来确定。
上述主要从主机、控制设备和从设备之间交互的角度对本申请实施例提供的方案进行了介绍。可以理解的是，为了实现上述功能，主机、控制设备和从设备可以包括执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请的实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对主机、控制设备和从设备进行功能单元的划分，例如，可以对应各个功能划分各个功能单元，也可以将两个或两个以上的功能集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
在采用集成的单元的情况下，图8示出了本申请实施例中所涉及的装置的可能的示例性框图。如图8所示，装置800可以包括：处理单元802和通信单元803。处理单元802用于对装置800的动作进行控制管理。通信单元803用于支持装置800与其他设备的通信。可选地，通信单元803也称为收发单元，可以包括接收单元和/或发送单元，分别用于执行接收和发送操作。装置800还可以包括存储单元801，用于存储装置800的程序代码和/或数据。
该装置800可以为上述任一实施例中的主机(或设置在主机中的芯片)，主机可以通过I 2C总线与主控设备连接。其中，处理单元802可以支持装置800执行上文中各方法示例中主机的动作；或者，处理单元802主要执行方法示例中的主机的内部动作，通信单元803可以支持装置800与主控设备之间的通信。
在一个实施例中，处理单元802用于：确定需要控制的目标设备，目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备和主控设备中的至少一个设备；通信单元803用于：向主控设备发送开始信号，向主控设备发送指示信息、控制命令和目标设备的寄存器的地址；指示信息用于指示目标 设备，控制命令为读命令或写命令；以及，向主控设备发送停止信号；其中，P、N为大于或等于1的整数。
在一种可能的设计中，目标设备为N个外围设备中的第一外围设备；指示信息包括与第一外围设备连接的设备的标识，还包括第一外围设备的地址的索引或者第一外围设备的地址。
在一种可能的设计中，目标设备为P个从设备中的第一从设备；指示信息包括第一从设备的标识。
在一种可能的设计中，指示信息还包括预设索引或者预设地址。
在一种可能的设计中，处理单元802用于：获取映射关系信息；映射关系信息包括标识信息、索引信息和地址信息之间的映射关系，或者，映射关系信息包括标识信息和地址信息之间的映射关系；其中，标识信息包括P个从设备的标识，索引信息包括N个外围设备的地址的索引，地址信息包括N个外围设备的地址；通信单元803用于：根据映射关系信息，向主控设备发送指示信息。
在一种可能的设计中，当映射关系信息包括标识信息、索引信息和地址信息之间的映射关系时，P个从设备中每个从设备的标识、与每个从设备连接的外围设备的地址、以及与每个从设备连接的外围设备的地址的索引对应；当映射关系信息包括标识信息和地址信息之间的映射关系时，P个从设备中每个从设备的标识、与每个从设备连接的外围设备的地址对应。
在一种可能的设计中，索引信息还包括预设索引，地址信息还包括预设地址。
在一种可能的设计中，若控制命令为读命令，则通信单元803向主控设备发送停止信号之前，还用于：接收主控设备发送的第一数据；其中，第一数据是来自目标设备的数据；或者，若控制命令为写命令，则通信单元803向主控设备发送停止信号之前，还用于：向主控设备发送第二数据。
该装置800可以为上述任一实施例中的主控设备(或设置在主控设备中的芯片)，主控设备可以通过I 2C总线与主机连接。其中，处理单元802可以支持装置800执行上文中各方法示例中主控设备的动作；或者，处理单元802主要执行方法示例中的主控设备的内部动作，通信单元803可以支持装置800与其它设备(比如主机、从设备)之间的通信。
在一个实施例中，通信单元803用于：接收来自主机的指示信息、控制命令和目标设备的寄存器的地址；指示信息用于指示目标设备，控制命令为读命令或写命令；目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备中的至少一个设备；向与主控设备连接的从设备发送第一消息，第一消息包括指示信息、控制命令和目标设备的寄存器的地址；其中，P、N为大于或等于1的整数。
在一种可能的设计中，目标设备为N个外围设备中的第一外围设备；指示信息包括与第一外围设备连接的设备的标识，还包括第一外围设备的地址的索引或者第一外围设备的地址。
在一种可能的设计中，处理单元802用于：将第一外围设备连接的设备的标识与控制命令写入同一寄存器；或者，将第一外围设备的地址的索引或者第一外围设备的地址与控制命令写入同一寄存器。
在一种可能的设计中，目标设备为P个从设备中的第一从设备；指示信息包括第一从 设备的标识。
在一种可能的设计中，指示信息还包括预设索引或者预设地址。
在一种可能的设计中，处理单元802用于：将第一从设备的标识与控制命令写入同一寄存器；或者，主控设备将预设索引或者预设地址与控制命令写入同一寄存器。
在一种可能的设计中，通信单元803具体用于：先接收来自主机的开始信号，然后接收来自主机的指示信息、控制命令和目标设备的寄存器的地址，最后接收来自主机的停止信号。
在一种可能的设计中，若控制命令为读命令，则通信单元803还用于：接收来自目标设备的第一数据，并将第一数据发送给主机；或者，若控制命令为写命令，则通信单元803还用于：接收来自主机的第二数据，第一消息还包括第二数据。
该装置800可以为上述任一实施例中的从设备(或设置在从设备中的芯片)，其中，处理单元802可以支持装置800执行上文中各方法示例中从设备的动作；或者，处理单元802主要执行方法示例中的从设备的内部动作，通信单元803可以支持装置800与其它设备(比如主控设备、该从设备的下一级传输设备或上一级传输设备)之间的通信。
在一个实施例中，通信单元803用于：接收来自主控设备的第一消息，第一消息包括指示信息、控制命令和目标设备的寄存器的地址；指示信息用于指示目标设备，控制命令为读命令或写命令；目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；N个外围设备连接P个从设备中的至少一个设备；第一从设备为P个从设备中的任一从设备；处理单元802用于：若确定目标设备为第一从设备，则根据控制命令执行第一操作；其中，P、N为大于或等于1的整数。
在一种可能的设计中，处理单元802还用于：确定指示信息包括第一从设备的标识以及预设索引或预设地址，则确定目标设备为第一从设备。
在一种可能的设计中，处理单元802还用于：若确定目标设备为第一从设备连接的第一外围设备，则控制第一外围设备执行第一操作。
在一种可能的设计中，处理单元802还用于：若确定指示信息包括第一从设备的标识以及第一外围设备的地址的索引或者第一外围设备的地址，则确定目标设备为第一外围设备。
在一种可能的设计中，若控制命令为写命令，则第一消息还包括第二数据。
在一种可能的设计中，若控制命令为写命令，则第一操作为写操作、清空内存操作或读操作中的至少一项。
在一种可能的设计中，主控设备和P个从设备之间的连接构成菊花链拓扑结构，或者环形拓扑结构，或者树形拓扑结构。
应理解以上装置中单元的划分仅仅是一种逻辑功能的划分，实际实现时可以全部或部分集成到一个物理实体上，也可以物理上分开。且装置中的单元可以全部以软件通过处理元件调用的形式实现；也可以全部以硬件的形式实现；还可以部分单元以软件通过处理元件调用的形式实现，部分单元以硬件的形式实现。例如，各个单元可以为单独设立的处理元件，也可以集成在装置的某一个芯片中实现，此外，也可以以程序的形式存储于存储器中，由装置的某一个处理元件调用并执行该单元的功能。此外这些单元全部或部分可以集成在一起，也可以独立实现。这里所述的处理元件又可以成为处理器，可以是一种具有信号的处理能力的集成电路。在实现过程中，上述方法的各步骤或以上各个单元可以通过处 理器元件中的硬件的集成逻辑电路实现或者以软件通过处理元件调用的形式实现。
在一个例子中，以上任一装置中的单元可以是被配置成实施以上方法的一个或多个集成电路，例如：一个或多个特定集成电路(Application Specific Integrated Circuit，ASIC)，或，一个或多个微处理器(digital singnal processor，DSP)，或，一个或者多个现场可编程门阵列(Field Programmable Gate Array，FPGA)，或这些集成电路形式中至少两种的组合。再如，当装置中的单元可以通过处理元件调度程序的形式实现时，该处理元件可以是处理器，比如通用中央处理器(central processing unit，CPU)，或其它可以调用程序的处理器。再如，这些单元可以集成在一起，以片上系统(system-on-a-chip，SOC)的形式实现。
以上用于接收的单元是一种该装置的接口电路，用于从其它装置接收信号。例如，当该装置以芯片的方式实现时，该接收单元是该芯片用于从其它芯片或装置接收信号的接口电路。以上用于发送的单元是一种该装置的接口电路，用于向其它装置发送信号。例如，当该装置以芯片的方式实现时，该发送单元是该芯片用于向其它芯片或装置发送信号的接口电路。
参见图9所示，为本申请实施例提供的一种控制装置示意图，该装置900可以是上述实施例中的主机、主控设备或者从设备。该装置900包括：处理器902、通信接口903，还可以包括存储器901或者与存储器901存在耦合关系。可选的，装置900还可以包括通信线路904。其中，通信接口903、处理器902以及存储器901可以通过通信线路904相互连接；通信线路904可以是外设部件互连标准(peripheral component interconnect，简称PCI)总线或扩展工业标准结构(extended industry standard architecture，简称EISA)总线等。所述通信线路904可以分为地址总线、数据总线、控制总线等。为便于表示，图9中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
处理器902可以是一个CPU，微处理器，ASIC，或一个或多个用于控制本申请方案程序执行的集成电路。处理器902的功能可以和图8中所描述的处理单元的功能相同。
通信接口903，使用任何收发器一类的装置，用于与其他设备或通信网络通信，如以太网，无线接入网(radio access network，RAN)，无线局域网(wireless local area networks，WLAN)，有线接入网等。通信接口903的功能可以和图8中所描述的通信单元的功能相同。
存储器901可以是ROM或可存储静态信息和指令的其它类型的静态存储设备，RAM或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。存储器可以是独立存在，通过通信线路904与处理器相连接。存储器也可以和处理器集成在一起。存储器901可以和图8中所描述的存储单元的功能相同。
其中，存储器901用于存储执行本申请方案的计算机执行指令，并由处理器902来控制执行。处理器902用于执行存储器901中存储的计算机执行指令，从而实现本申请上述实施例提供的方法。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
本申请实施例还提供了一种计算机可读存储介质，用于存储为执行上述处理器所需执行的计算机软件指令，其包含用于执行上述处理器所需执行的程序。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A、同时存在A和B、单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。以及，除非有特别说明，本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。例如，第一数据和第二数据，只是为了区分不同的数据，而并不是表示这两种数据的优先级或者重要程度等的不同。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (27)

  1. 一种控制方法，其特征在于，所述方法适用于主机，所述主机通过内部集成电路I 2C总线与主控设备连接；所述方法包括：
    所述主机确定需要控制的目标设备，所述目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；所述N个外围设备连接所述P个从设备和所述主控设备中的至少一个设备；
    所述主机向所述主控设备发送开始信号；
    所述主机向所述主控设备发送指示信息、控制命令和所述目标设备的寄存器的地址；所述指示信息用于指示所述目标设备，所述控制命令为读命令或写命令；
    所述主机向所述主控设备发送停止信号；
    其中，P、N为大于或等于1的整数。
  2. 根据权利要求1所述的方法，其特征在于，所述目标设备为所述N个外围设备中的第一外围设备；
    所述指示信息包括与所述第一外围设备连接的设备的标识，还包括所述第一外围设备的地址的索引或者所述第一外围设备的地址。
  3. 根据权利要求1所述的方法，其特征在于，所述目标设备为所述P个从设备中的第一从设备；
    所述指示信息包括所述第一从设备的标识。
  4. 根据权利要求3所述的方法，其特征在于，所述指示信息还包括预设索引或者预设地址。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述主机向所述主控设备发送所述指示信息，包括：
    所述主机获取映射关系信息；所述映射关系信息包括标识信息、索引信息和地址信息之间的映射关系，或者，所述映射关系信息包括标识信息和地址信息之间的映射关系；其中，所述标识信息包括所述P个从设备的标识，所述索引信息包括所述N个外围设备的地址的索引，所述地址信息包括所述N个外围设备的地址；
    所述主机根据所述映射关系信息，向所述主控设备发送所述指示信息。
  6. 根据权利要求5所述的方法，其特征在于，当所述映射关系信息包括标识信息、索引信息和地址信息之间的映射关系时，所述P个从设备中每个从设备的标识、与所述每个从设备连接的外围设备的地址、以及与所述每个从设备连接的外围设备的地址的索引对应；
    当所述映射关系信息包括标识信息和地址信息之间的映射关系时，所述P个从设备中每个从设备的标识、与所述每个从设备连接的外围设备的地址对应。
  7. 根据权利要求5或6所述的方法，其特征在于，所述索引信息还包括预设索引，所述地址信息还包括预设地址。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于：
    若所述控制命令为读命令，则所述主机向所述主控设备发送停止信号之前，还包括：所述主机接收所述主控设备发送的第一数据；其中，所述第一数据是来自所述目标设备的数据；或者，
    若所述控制命令为写命令，则所述主机向所述主控设备发送停止信号之前，还包括：所述主机向所述主控设备发送第二数据。
  9. 一种控制方法，其特征在于，所述方法适用于主控设备，所述主控设备通过I 2C总线与主机连接；所述方法包括：
    所述主控设备接收来自所述主机的指示信息、控制命令和目标设备的寄存器的地址；所述指示信息用于指示所述目标设备，所述控制命令为读命令或写命令；所述目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；所述N个外围设备连接所述P个从设备中的至少一个设备；
    所述主控设备向与所述主控设备连接的从设备发送第一消息，所述第一消息包括所述指示信息、所述目标设备的寄存器的地址和所述控制命令；
    其中，P、N为大于或等于1的整数。
  10. 根据权利要求9所述的方法，其特征在于，所述目标设备为所述N个外围设备中的第一外围设备；
    所述指示信息包括与所述第一外围设备连接的设备的标识，还包括所述第一外围设备的地址的索引或者所述第一外围设备的地址。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    所述主控设备将所述第一外围设备连接的设备的标识与所述控制命令写入同一寄存器；或者，
    所述主控设备将所述第一外围设备的地址的索引或者所述第一外围设备的地址与所述控制命令写入同一寄存器。
  12. 根据权利要求9所述的方法，其特征在于，所述目标设备为所述P个从设备中的第一从设备；
    所述指示信息包括所述第一从设备的标识。
  13. 根据权利要求12所述的方法，其特征在于，所述指示信息还包括预设索引或者预设地址。
  14. 根据权利要求12或13所述的方法，其特征在于，所述方法还包括：
    所述主控设备将所述第一从设备的标识与所述控制命令写入同一寄存器；或者，
    所述主控设备将所述预设索引或者所述预设地址与所述控制命令写入同一寄存器。
  15. 根据权利要求9至14中任一项所述的方法，其特征在于，所述主控设备接收来自所述主机的指示信息、控制命令和目标设备的寄存器的地址，包括：
    所述主控设备接收来自所述主机的开始信号；
    所述主控设备接收来自所述主机的指示信息、控制命令和目标设备的寄存器的地址；
    所述主控设备接收来自所述主机的停止信号。
  16. 根据权利要求9至15中任一项所述的方法，其特征在于：
    若所述控制命令为读命令，则所述方法还包括：所述主控设备接收来自所述目标设备的第一数据，并将所述第一数据发送给所述主机；或者，
    若所述控制命令为写命令，则所述方法还包括：所述主控设备接收来自所述主机的第二数据，所述第一消息还包括所述第二数据。
  17. 一种控制方法，其特征在于，所述方法包括：
    第一从设备接收来自主控设备的第一消息，所述第一消息包括指示信息、控制命令和 目标设备的寄存器的地址；所述指示信息用于指示所述目标设备，所述控制命令为读命令或写命令；所述目标设备包括P个从设备中的至少一个从设备和/或N个外围设备中的至少一个外围设备；所述N个外围设备连接所述P个从设备中的至少一个设备；所述第一从设备为所述P个从设备中的任一从设备；
    所述第一从设备若确定所述目标设备为所述第一从设备，则根据所述控制命令执行第一操作；
    其中，P、N为大于或等于1的整数。
  18. 根据权利要求17所述的方法，其特征在于，所述第一从设备确定所述目标设备为所述第一从设备，包括：
    所述第一从设备若确定所述指示信息包括所述第一从设备的标识以及预设索引或预设地址，则确定所述目标设备为所述第一从设备。
  19. 根据权利要求17或18所述的方法，其特征在于，所述方法还包括：
    所述第一从设备若确定所述目标设备为所述第一从设备连接的第一外围设备，则控制所述第一外围设备执行第一操作。
  20. 根据权利要求19所述的方法，其特征在于，所述第一从设备确定所述目标设备为所述第一外围设备，包括：
    所述第一从设备若确定所述指示信息包括第一从设备的标识以及第一外围设备的地址的索引或者第一外围设备的地址，则确定所述目标设备为所述第一外围设备。
  21. 根据权利要求17至20中任一项所述的方法，其特征在于：
    若所述控制命令为写命令，则所述第一消息还包括第二数据。
  22. 根据权利要求17至21中任一项所述的方法，其特征在于：
    若所述控制命令为写命令，则所述第一操作为写操作、清空内存操作或读操作中的至少一项。
  23. 根据权利要求17至22中任一项所述的方法，其特征在于，所述主控设备和所述P个从设备之间的连接构成菊花链拓扑结构，或者环形拓扑结构，或者树形拓扑结构。
  24. 一种控制装置，其特征在于，包括用于执行如权利要求1至23中任一项所述的方法的各步骤的单元。
  25. 一种控制装置，其特征在于，包括：
    通信接口，用于与其它装置通信；
    处理器，用于读取并运行存储器中的计算机程序，通过所述通信接口执行如权利要求1-23任一项所述的方法。
  26. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储程序或指令，所述程序或所述指令在被一个或多个处理器读取并执行时可实现权利要求1至23任一项所述的方法。
  27. 一种计算机程序产品，其特征在于，当所述计算机程序产品在主机上运行时，使得所述主机执行权利要求1至8任一项所述的方法；或者，
    当所述计算机程序产品在主控设备上运行时，使得所述主控设备执行权利要求9至16任一项所述的方法；或者，
    当所述计算机程序产品在第一从设备上运行时，使得所述第一从设备执行权利要求17至23任一项所述的方法。
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