WO2021128910A1 - 产生符合iec61000-4-2标准双峰波形的电路 - Google Patents

产生符合iec61000-4-2标准双峰波形的电路 Download PDF

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WO2021128910A1
WO2021128910A1 PCT/CN2020/111572 CN2020111572W WO2021128910A1 WO 2021128910 A1 WO2021128910 A1 WO 2021128910A1 CN 2020111572 W CN2020111572 W CN 2020111572W WO 2021128910 A1 WO2021128910 A1 WO 2021128910A1
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tlp
voltage
circuit
resistor
double
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PCT/CN2020/111572
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English (en)
French (fr)
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王源
王艺泽
田明
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北京大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses

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  • This application relates to the technical field of component-level electronic device testing, and in particular, to a circuit and method for generating a double-peak waveform that meets the IEC61000-4-2 standard.
  • ESD Electro Static Discharge, electrostatic discharge
  • HBM Human Body Model
  • CDM Charge Device Model
  • MM Machine Model
  • the preferred double-peak waveform is a waveform that conforms to the IEC 61000-4-2 standard.
  • Figure 1 is a schematic diagram of the IEC 61000-4-2 standard waveform provided by the prior art. As shown in Figure 1, the horizontal axis is Time (time), the unit is ns, the vertical axis is Current (current), and the unit is A. The waveform conforms to the IEC 61000-4-2 standard. The waveform is a double-peak waveform.
  • the peak value of the first wave peak is 30A ⁇ 10% ;
  • the rise time of the peak value of the first peak is 0.8ns ⁇ 25%; at 30ns, the amplitude of the waveform is 16A ⁇ 30%; at 60ns, the amplitude of the waveform is 8A ⁇ 30%.
  • ESD guns For electrostatic machines that can produce double-peak waveforms that meet the IEC61000-4-2 standard, the most commonly used is ESD guns, but ESD guns are usually hand-held, and accuracy and stability need to be improved.
  • a better method currently available is based on the modification of the internal circuit structure of the TLP (Transmission Line Pulse) electrostatic generator, but this kind of internal modification will damage the TLP machine. Risk, in addition, the modification process is also very troublesome.
  • TLP Transmission Line Pulse
  • the embodiment of the present application provides a circuit that generates a double-peak waveform conforming to the IEC61000-4-2 standard to solve the modification of the existing internal circuit structure based on the TLP electrostatic generator to generate a double-peak waveform conforming to the IEC61000-4-2 standard There is a risk of damaging the TLP machine, and the modification process is complicated.
  • an embodiment of the present application provides a circuit that generates a double-peak waveform that complies with the IEC61000-4-2 standard, including: a TLP generator circuit and a TLP external circuit, where:
  • the TLP generator circuit is configured to generate TLP excitation
  • the TLP external circuit is configured to store the energy generated by the TLP excitation and release the electrostatic excitation in the form of a double-peak waveform.
  • the TLP external circuit includes a first resistor, a first inductor, a first capacitor, a second inductor, a second capacitor, a second resistor, a first voltage-controlled switch, a third capacitor, and a third capacitor. Resistance, where
  • the first resistor, the first inductor, and the first capacitor are connected in series to form a first branch of the TLP external circuit;
  • the second capacitor forms a second branch of the TLP external circuit
  • the third resistor and the third capacitor are connected in parallel and then connected in series with the second inductor, the second resistor and the first voltage-controlled switch to form a third branch of the TLP external circuit;
  • One end of the first branch, the second branch, and the third branch is the input end of the TLP external circuit, and the first branch, the second branch and the third branch are The other end is grounded.
  • the TLP generator circuit and the TLP external circuit are connected through a diode, the output terminal of the TLP generator circuit is connected to the anode of the diode, and the cathode of the diode is connected to the TLP external circuit ⁇ input terminal.
  • the resistance value of the first resistor is 150 ⁇
  • the inductance value of the first inductor is 3.5uH
  • the capacitance value of the first capacitor is 150pF
  • the capacitance value of the second capacitor is 8pF
  • the inductance value of the second inductor is 150nH
  • the resistance value of the second resistor is 130 ⁇
  • the turn-on voltage of the first voltage-controlled switch is 1V
  • the cut-off voltage of the first voltage-controlled switch is 0V
  • the capacitance value of the third capacitor is 1.5 nF
  • the resistance value of the third resistor is 2 ⁇ .
  • the TLP generator circuit includes a DC voltage source, a fourth resistor, a second voltage-controlled switch, a transmission line unit, a third voltage-controlled switch, a fourth capacitor, and a fifth resistor, wherein,
  • the negative pole of the DC voltage source is grounded, the positive pole of the DC voltage source is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to one end of the second voltage-controlled switch.
  • the other end of the switch is connected to one end of the transmission line unit, the other end of the transmission line unit is connected to one end of the fourth capacitor, the other end of the transmission line unit is also connected to one end of the fifth resistor, the fourth capacitor
  • the other end of the fifth resistor is grounded, and the other end of the fifth resistor is the output end of the TLP generator circuit.
  • the resistance of the fourth resistor is 1k ⁇
  • the turn-on voltage of the second voltage-controlled switch is 1V
  • the cut-off voltage of the second voltage-controlled switch is 0V.
  • the characteristics of the transmission line unit The impedance value is 50 ⁇ , the time delay of the transmission line unit is 50ns, the turn-on voltage of the third voltage-controlled switch is 1V, the cut-off voltage of the third voltage-controlled switch is 0V, and the capacitance value of the fourth capacitor is 400pF, the resistance value of the fifth resistor is 50 ⁇ .
  • the embodiments of the present application provide a method for generating a bimodal waveform conforming to the IEC61000-4-2 standard based on the circuit for generating a bimodal waveform conforming to the IEC61000-4-2 standard provided in the first aspect, including:
  • a third rectangular pulse excitation is loaded on the first voltage-controlled switch to generate a double-peak waveform.
  • the high voltage of the first rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 0
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 15ns
  • the high voltage of the second rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 20ns
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 1000ns;
  • the resulting double-peak waveform is a double-peak waveform that complies with the IEC 61000-4-2 electrostatic standard.
  • an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor.
  • the processor executes the program as described in the second aspect.
  • an embodiment of the present application provides a non-transitory computer-readable storage medium on which a computer program is stored.
  • the computer program When the computer program is executed by a processor, it can realize the generation as provided in the second aspect and comply with IEC61000-4-2. Steps of the standard bimodal waveform method.
  • the circuit for generating a double-peak waveform in accordance with the IEC61000-4-2 standard provided by the embodiment of the application is connected to a TLP external circuit outside the TLP generator circuit, wherein the TLP generator circuit is used to generate TLP excitation; the TLP external The circuit is used to store the energy generated by the TLP excitation and release the electrostatic excitation in the form of a double-peak waveform, which realizes the double-peak waveform generation method based on the TLP electrostatic generator and avoids the modification of the internal circuit structure of the TLP electrostatic generator The risk of damage to the TLP machine.
  • the circuit provided by the embodiment of the present application realizes the process of simplifying the circuit structure of the TLP electrostatic generator.
  • FIG. 1 is a schematic diagram of the IEC 61000-4-2 standard waveform provided by the prior art
  • FIG. 2 is a schematic structural diagram of a circuit that generates a double-peak waveform in accordance with the IEC61000-4-2 standard provided by an embodiment of the application;
  • FIG. 3 is a schematic structural diagram of a TLP external circuit provided by an embodiment of the application.
  • Fig. 4 is a schematic structural diagram of a TLP generator circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic flowchart of a method for generating a double-peak waveform conforming to the IEC61000-4-2 standard provided by an embodiment of the application;
  • FIG. 6 is a schematic diagram of a circuit structure for generating a double-peak waveform conforming to the IEC 61000-4-2 electrostatic standard provided by an embodiment of the application;
  • Fig. 7 is a schematic structural diagram of a device for generating a double-peak waveform conforming to the IEC61000-4-2 standard provided by an embodiment of the application;
  • FIG. 8 is a schematic diagram of the physical structure of an electronic device provided by an embodiment of the application.
  • Fig. 2 is a schematic structural diagram of a circuit for generating a double-peak waveform in accordance with the IEC61000-4-2 standard provided by an embodiment of the application. As shown in Fig. 2, the circuit includes a TLP generator circuit 210 and a TLP external circuit 220, wherein,
  • the TLP generator circuit 210 is configured to generate TLP excitation
  • the TLP external circuit 220 is configured to store the energy generated by the TLP excitation and release the electrostatic excitation in the form of a double-peak waveform.
  • the TLP generator circuit 210 connect an external TLP external circuit 220, where the TLP generator circuit 210 generates TLP excitation, and the TLP external circuit 220 stores the energy generated by the TLP excitation, and generates a bimodal waveform by releasing the energy The electrostatic excitation.
  • a TLP external circuit 220 can generate a double-peak waveform in accordance with the IEC61000-4-2 standard based on the TLP generator circuit without improving the internal structure of the TLP generator circuit.
  • the circuit provided by the embodiment of the present application includes a TLP generator circuit 210 and a TLP external circuit 220, wherein the TLP generator circuit 210 is used to generate TLP excitation; the TLP external circuit 220 is used to store the TLP Excite the energy generated and release the electrostatic excitation in accordance with the IEC61000-4-2 standard double-peak waveform form, which realizes the double-peak waveform generation method based on the TLP electrostatic generator, and avoids the modification of the internal circuit structure of the TLP electrostatic generator The risk of damage to the TLP machine.
  • the circuit provided by the embodiment of the present application realizes the process of simplifying the circuit structure of the TLP electrostatic generator.
  • FIG. 3 is a schematic structural diagram of a TLP external circuit provided by an embodiment of the application.
  • the TLP external circuit includes a first resistor R1, a first inductor L1, a first capacitor C1, a second inductor L2, a second capacitor C2, a second resistor R2, a first voltage-controlled switch K1, and The third capacitor C3 and the third resistor R3, in which,
  • the first resistor R1, the first inductor L1, and the first capacitor C1 are connected in series to form a first branch of the TLP external circuit;
  • the second capacitor C2 forms a second branch of the TLP external circuit
  • the third resistor R3 and the third capacitor C3 are connected in parallel and then connected in series with the second inductor L2, the second resistor R2 and the first voltage-controlled switch K1 to form the third branch of the TLP external circuit;
  • Point A of one end of the first branch, the second branch and the third branch is the input end of the TLP external circuit, and the first branch, the second branch and the third branch are The other end of the branch is grounded.
  • the TLP external circuit is composed of two RCL circuits and a voltage-controlled switch circuit K1, a third capacitor C3, and a third resistor R3.
  • the two RCL circuits are used to store the energy generated by the TLP and discharge when the switch is turned on. Two peaks are formed respectively. Specifically, the discharge of the second capacitor C2 forms the first peak, and the discharge of the first capacitor C1 forms the second peak.
  • the third resistor R3 is used to be equivalent to the actual load, which is usually achieved by setting it to 2 ⁇ .
  • the third capacitor C3 is used to fine-tune the rise time and peak value of the first peak of the final waveform to meet the requirements.
  • a double-peak waveform is formed at the end of the third resistor R3.
  • the TLP generator circuit and the TLP external circuit are connected through a diode, the output end of the TLP generator circuit is connected to the anode of the diode, and the cathode of the diode is connected to the The input terminal of the external circuit of the TLP.
  • adding a diode between the TLP generator circuit and the TLP external circuit can prevent the current of the TLP external circuit from flowing backward into the TLP generator circuit to burn out the components in the TLP generator circuit.
  • the resistance of the first resistor is 150 ⁇
  • the inductance of the first inductor is 3.5uH
  • the capacitance of the first capacitor is 150pF
  • the second capacitor The capacitance value of the second inductor is 8pF
  • the inductance value of the second inductor is 150nH
  • the resistance value of the second resistor is 130 ⁇
  • the turn-on voltage of the first voltage-controlled switch is 1V
  • the turn-off of the first voltage-controlled switch The voltage is 0V
  • the capacitance value of the third capacitor is 1.5 nF
  • the resistance value of the third resistor is 2 ⁇ .
  • FIG. 4 is a schematic structural diagram of a TLP generator circuit provided by an embodiment of this application.
  • the TLP generator circuit includes a DC voltage source V1, a fourth resistor R4, a second voltage-controlled switch K2, a transmission line unit T1, a third voltage-controlled switch K3, and a fourth capacitor C4.
  • the fifth resistor R5 where,
  • the negative pole of the DC voltage source V1 is grounded, the positive pole of the DC voltage source V1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to one end of the second voltage-controlled switch K2, so The other end of the second voltage-controlled switch K2 is connected to one end of the transmission line unit T1, the other end of the transmission line unit T1 is connected to one end of the fourth capacitor C4, and the other end of the transmission line unit T1 is also connected to the first end.
  • One end of the five resistor R5, the other end of the fourth capacitor C4 is grounded, and the other end point B of the fifth resistor R5 is the output end of the TLP generator circuit.
  • the TLP generator circuit is the equivalent circuit structure of the TLP excitation generator, which is composed of a transmission line unit, two voltage-controlled switches, a DC voltage source, and a resistor.
  • the principle of TLP waveform generation is based on the charging and discharging formation of the transmission line.
  • the impedance of the transmission line is preferably 50 ⁇ .
  • Two voltage-controlled switches are used to control the charging and discharging of the transmission line unit.
  • the DC voltage source charges the transmission line unit through the fourth resistor R4.
  • the function of the fourth capacitor C4 is to adjust the rise time of the TLP excitation.
  • the superposition of the incident wave and the reflected wave during the discharge of the transmission line unit forms a DC-like TLP excitation with a pulse width of 100ns.
  • the resistance of the fourth resistor is 1k ⁇
  • the turn-on voltage of the second voltage-controlled switch is 1V
  • the cut-off voltage of the second voltage-controlled switch is 0V.
  • the characteristic impedance value of the transmission line unit is 50 ⁇
  • the time delay of the transmission line unit is 50ns
  • the turn-on voltage of the third voltage-controlled switch is 1V
  • the cut-off voltage of the third voltage-controlled switch is 0V
  • the fourth capacitor The capacitance value of is 400pF
  • the resistance value of the fifth resistor is 50 ⁇ .
  • FIG. 5 is a schematic flowchart of a method for generating a double-peaked waveform conforming to the IEC61000-4-2 standard provided by an embodiment of the application.
  • an embodiment of the present application provides a method for generating a bimodal waveform based on any of the foregoing embodiments, including:
  • Step 510 Load a first rectangular pulse excitation on the second voltage-controlled switch
  • Step 520 Load a second rectangular pulse excitation on the third voltage-controlled switch
  • Step 530 Load a third rectangular pulse excitation on the first voltage-controlled switch to generate a double-peak waveform.
  • the excitation of the voltage-controlled switch loaded on both ends of the transmission line unit is to control the charging and discharging of the transmission line unit.
  • the excitation of the voltage-controlled switch of the circuit is to control the discharge of the first capacitor and the second capacitor to form two peaks.
  • rectangular pulse excitation is applied to the voltage-controlled switch in the TLP generator circuit and the voltage-controlled switch of the TLP external circuit to realize the generation of the double-peak waveform and avoid the damage to the internal circuit of the TLP generator.
  • the risk of damage to the TLP machine brought about by the modification simplifies the modification process.
  • the high voltage of the first rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 0
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 15ns
  • the high voltage of the second rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 20ns
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 1000ns;
  • the resulting double-peak waveform is a double-peak waveform that complies with the IEC 61000-4-2 electrostatic standard.
  • FIG. 6 is a schematic diagram of a circuit structure for generating a double-peak waveform conforming to the IEC 61000-4-2 electrostatic standard provided by an embodiment of the application.
  • the left side of the dotted line is the TLP generator circuit
  • the right side of the dotted line is the TLP external circuit connected through the diode D1 .
  • the resistance of R 1 in the TLP generator circuit is 1k ⁇
  • the characteristic impedance Z 0 of the transmission line unit is 50 ⁇ .
  • the capacitance value of C 2 is 150pF
  • the inductance value of L 1 is 3.5uH
  • the IEC Stress Output (IEC stress output) output at the end of R 5 is a double-peak waveform that meets the IEC 61000-4-2 electrostatic standard.
  • FIG. 7 is a schematic structural diagram of the device for generating a double-peaked waveform provided by an embodiment of the application.
  • the device includes The first loading unit 710, the second loading unit 720 and the third loading unit 730, wherein
  • the first loading unit 710 is configured to load a first rectangular pulse excitation on the second voltage-controlled switch
  • the second loading unit 720 is configured to load a second rectangular pulse excitation on the third voltage-controlled switch
  • the third loading unit 730 is configured to load a third rectangular pulse excitation on the first voltage-controlled switch to generate a double-peak waveform.
  • the device for generating a double-peak waveform provided by the embodiment of the application realizes the generation of a double-peak waveform by loading a rectangular pulse excitation on the voltage-controlled switch in the TLP generator circuit and the voltage-controlled switch of the TLP external circuit, thereby avoiding the need for TLP
  • the risk of damage to the TLP machine caused by the modification of the internal circuit of the generator simplifies the modification process.
  • the high voltage of the first rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 0
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 15ns
  • the high voltage of the second rectangular pulse is 1V
  • the low voltage is 0V
  • the time delay TD 20ns
  • the rise time is 0.1ps
  • the fall time is 0.1ps
  • the rectangular width PW 1000ns;
  • the resulting double-peak waveform is a double-peak waveform that complies with the IEC 61000-4-2 electrostatic standard.
  • FIG. 8 is a schematic diagram of the physical structure of an electronic device provided by an embodiment of the application.
  • the electronic device may include: a processor 801, a communication interface 802, a memory (memory) 803, and communication The bus 804, in which the processor 801, the communication interface 802, and the memory 803 communicate with each other through the communication bus 804.
  • the processor 801 can call a computer program stored in the memory 803 and run on the processor 801 to execute the method for generating bimodal waveforms in compliance with the IEC61000-4-2 standard provided by the foregoing embodiments, for example, including: Load a first rectangular pulse excitation on the second voltage control switch; load a second rectangular pulse excitation on the third voltage control switch; load a third rectangular pulse excitation on the first voltage control switch to generate a double peak waveform .
  • the above-mentioned logical instructions in the memory 803 can be implemented in the form of a software functional unit and when sold or used as an independent product, they can be stored in a computer readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium.
  • Including several instructions to make a computer device for example, a personal computer, a server, or a network device, etc.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .
  • the embodiments of the present application also provide a non-transitory computer-readable storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the computer program is implemented to perform the generation provided by the above-mentioned embodiments to meet the IEC61000-4-2 standard.
  • the peak waveform method for example, includes: loading a first rectangular pulse excitation on the second voltage-controlled switch; loading a second rectangular pulse excitation on the third voltage-controlled switch; loading on the first voltage-controlled switch The third rectangular pulse is excited to produce a double-peak waveform.
  • the device embodiments described above are merely illustrative.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One location, or it can be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement it without creative work.
  • each implementation manner can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware.
  • the above technical solution essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM/RAM, magnetic A disc, an optical disc, etc., include a number of instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiment.

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Abstract

本申请实施例提供一种产生符合IEC61000-4-2标准双峰波形的电路和方法，该电路包括：TLP发生器电路和TLP外接电路，其中，所述TLP发生器电路用于产生TLP激励；所述TLP外接电路用于存储所述TLP激励产生的能量，并释放双峰波形形态的静电激励。本申请实施例提供的电路和方法，避免了对TLP静电发生器的内部电路结构进行改装带来的损坏TLP机台的风险，同时，相对于TLP静电发生器的内部改装，外部添加电路结构的方式更为简单。

Description

产生符合IEC61000-4-2标准双峰波形的电路
相关申请的交叉引用
本申请要求于2019年12月23日提交的申请号为201911338815X，发明名称为“产生符合IEC61000-4-2标准双峰波形的电路”的中国专利申请的优先权，其通过引用方式全部并入本文。
技术领域
本申请涉及部件级电子器件检测技术领域，尤其涉及一种产生符合IEC61000-4-2标准双峰波形的电路和方法。
背景技术
在IC(integrated circuit，集成电路)芯片的封装、测试、运输、制造等过程中，都会出现不同程度的ESD(Electronic Static Discharge，静电放电)事件，而静电放电带来的芯片失效问题是集成电路产业不容忽视的问题。静电放电的测试模型分为部件级和系统级。对于部件级来说，常用的静电模型为人体模型(Human Body Model，缩写HBM),充电器件模型(Charge Device Model，简称CDM)和机械模型(Machine Model，缩写MM)，这些模型广泛用于检测部件级电子器件的鲁棒性。对于系统级来说，常用的检测方法为产生双峰波形的系统级ESD应力，用来检测电子产品的鲁棒性，优选的双峰波形为符合IEC 61000-4-2标准波形。图1为现有技术提供的IEC 61000-4-2标准波形的示意图，如图1所示，横轴是Time(时间)，单位为ns，纵轴是Current(电流)，单位是A，产生的波形即符合IEC 61000-4-2标准波形是双波峰波形。以一个预充电电压为8kV的产生符合IEC 61000-4-2标准的ESD枪发生器为例，最常见的需要满足的参数主要体现在四个方面：第一个波峰的峰值为30A±10％；第一个波峰的峰值的上升时间为0.8ns±25％；30ns时，波形的幅值16A±30％；60ns时，波形的幅值8A±30％。
对于能产生符合IEC61000-4-2标准双峰波形的静电机台来说，最常用的为ESD枪，但ESD枪通常是手持造成，精准性和稳定性有待提高。一 种目前已有的更好的一种方式为，基于TLP(Transmission Line Pulse，传输线脉冲)静电发生器的内部电路结构的改装来实现，但这种内部改装的方式会有损坏TLP机台的风险，此外改装过程也是十分麻烦的。
因此，如何避免基于TLP静电发生器的内部电路结构的改装来产生符合IEC61000-4-2标准双峰波形带来的损坏TLP机台的风险，简化改装过程，仍然是本领域技术人员亟待解决的问题。
发明内容
本申请实施例提供一种产生符合IEC61000-4-2标准双峰波形的电路，用以解决现有的基于TLP静电发生器的内部电路结构的改装来产生符合IEC61000-4-2标准双峰波形存在损坏TLP机台的风险，改装过程复杂的问题。
第一方面，本申请实施例提供一种产生符合IEC61000-4-2标准双峰波形的电路，包括：TLP发生器电路和TLP外接电路，其中，
所述TLP发生器电路被配置成产生TLP激励；
所述TLP外接电路被配置成存储所述TLP激励产生的能量，并释放双峰波形形态的静电激励。
优选地，该电路中，所述TLP外接电路，包括第一电阻、第一电感、第一电容、第二电感、第二电容、第二电阻、第一压控开关、第三电容和第三电阻，其中，
所述第一电阻、所述第一电感和所述第一电容串联形成所述TLP外接电路的第一支路；
所述第二电容形成所述TLP外接电路的第二支路；
所述第三电阻和所述第三电容并联后再与所述第二电感、第二电阻和第一压控开关串联形成所述TLP外接电路的第三支路；
所述第一支路、所述第二支路和所述第三支路的一端为TLP外接电路的输入端，所述第一支路、所述第二支路和所述第三支路的另一端接地。
优选地，该电路中，所述TLP发生器电路和所述TLP外接电路通过二极管相连，所述TLP发生器电路的输出端连接所述二极管的正极，所述二极管的负极连接所述TLP外接电路的输入端。
优选地，该电路中，所述第一电阻的阻值为150Ω，所述第一电感的 电感值为3.5uH，所述第一电容的电容值为150pF，所述第二电容的电容值为8pF，所述第二电感的电感值为150nH，所述第二电阻的阻值为130Ω，所述第一压控开关的开启电压为1V，所述第一压控开关的截止电压为0V，所述第三电容的电容值为1.5nF，所述第三电阻的阻值为2Ω。
优选地，该电路中，所述TLP发生器电路，包括直流电压源、第四电阻、第二压控开关、传输线单元、第三压控开关、第四电容和第五电阻，其中，
所述直流电压源的负极接地，所述直流电压源的正极连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二压控开关的一端，所述第二压控开关的另一端连接所述传输线单元的一端，所述传输线单元的另一端连接所述第四电容的一端，所述传输线单元的另一端还连接所述第五电阻的一端，所述第四电容的另一端接地，所述第五电阻的另一端为所述TLP发生器电路的输出端。
优选地，该电路中，所述第四电阻的阻值为1kΩ，所述第二压控开关的开启电压为1V，所述第二压控开关的截止电压为0V，所述传输线单元的特征阻抗值为50Ω，所述传输线单元的时延为50ns，所述第三压控开关的开启电压为1V，所述第三压控开关的截止电压为0V，所述第四电容的电容值为400pF，所述第五电阻的阻值为50Ω。
第二方面，本申请实施例提供基于第一方面所提供的产生符合IEC61000-4-2标准双峰波形的电路的一种产生符合IEC61000-4-2标准双峰波形的方法，包括：
在所述第二压控开关上加载第一矩形脉冲激励；
在所述第三压控开关上加载第二矩形脉冲激励；
在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
优选地，该方法中，所述第一矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝0，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
所述第二矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝20ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝1000ns；
所述第三矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝140ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
对应地，产生的双峰波形为符合IEC 61000-4-2静电标准的双峰波形。
第三方面，本申请实施例提供一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述程序时实现如第二方面所提供的产生符合IEC61000-4-2标准双峰波形的方法的步骤。
第四方面，本申请实施例提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现如第二方面所提供的产生符合IEC61000-4-2标准双峰波形的方法的步骤。
本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的电路，通过在TLP发生器电路外部连接TLP外接电路，其中，所述TLP发生器电路用于产生TLP激励；所述TLP外接电路用于存储所述TLP激励产生的能量，并释放双峰波形形态的静电激励，实现了基于TLP静电发生器的双峰波形的产生方法，避免了对TLP静电发生器的内部电路结构进行改装带来的损坏TLP机台的风险。如此，本申请实施例提供的电路，实现了简化改装TLP静电发生器的电路结构的过程。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图做一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的IEC 61000-4-2标准波形的示意图；
图2为本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的电路的结构示意图；
图3为本申请实施例提供的TLP外接电路的结构示意图；
图4为本申请实施例提供的TLP发生器电路的结构示意图；
图5为本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的方法的流程示意图；
图6为本申请实施例提供的产生符合IEC 61000-4-2静电标准的双峰波形的电路结构示意图；
图7为本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的装 置的结构示意图；
图8为本申请实施例提供的电子设备的实体结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
现有的基于TLP静电发生器的电路结构的改装获得能产生双峰波形的电路的方法通常会带来损坏TLP机台的风险，且改装过程复杂。对此，本申请实施例提供了一种产生双峰波形的电路。图2为本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的电路的结构示意图，如图2所示，该电路包括TLP发生器电路210和TLP外接电路220，其中，
所述TLP发生器电路210被配置成产生TLP激励；
所述TLP外接电路220被配置成存储所述TLP激励产生的能量，并释放双峰波形形态的静电激励。
具体地，让TLP发生器电路210外接一个TLP外接电路220，其中，TLP发生器电路210产生TLP激励，TLP外接电路220存储所述TLP激励产生的能量，并通过释放该能量产生双峰波形形态的静电激励。
现有技术中基于TLP发生器电路产生双峰波形的方法都是对TLP发生器电路的内部结构进行改进，而本申请实施例提供的方法是在已有的TLP发生器电路210的输出端外接一个TLP外接电路220，无需对TLP发生器电路的内部结构进行改进就可以基于TLP发生器电路产生符合IEC61000-4-2标准双峰波形。
因此，本申请实施例提供的电路，通过包括TLP发生器电路210和TLP外接电路220，其中，所述TLP发生器电路210用于产生TLP激励；所述TLP外接电路220用于存储所述TLP激励产生的能量，并释放符合IEC61000-4-2标准双峰波形形态的静电激励，实现了基于TLP静电发生器的双峰波形的产生方法，避免了对TLP静电发生器的内部电路结构进行改装带来的损坏TLP机台的风险。如此，本申请实施例提供的电路，实现了 简化改装TLP静电发生器的电路结构的过程。
基于上述实施例，图3为本申请实施例提供的TLP外接电路的结构示意图。如图3所示，所述TLP外接电路，包括第一电阻R1、第一电感L1、第一电容C1、第二电感L2、第二电容C2、第二电阻R2、第一压控开关K1、第三电容C3和第三电阻R3，其中，
所述第一电阻R1、所述第一电感L1和所述第一电容C1串联形成所述TLP外接电路的第一支路；
所述第二电容C2形成所述TLP外接电路的第二支路；
所述第三电阻R3和所述第三电容C3并联后再与所述第二电感L2、第二电阻R2和第一压控开关K1串联形成所述TLP外接电路的第三支路；
所述第一支路、所述第二支路和所述第三支路的一端A点为TLP外接电路的输入端，所述第一支路、所述第二支路和所述第三支路的另一端接地。
具体地，该TLP外接电路由两个RCL的电路以及压控开关电路K1、第三电容C3和第三电阻R3构成，两个RCL电路用于存储TLP产生的能量，开关接通时进行放电，分别形成两个波峰，具体来说第二电容C2放电形成第一个波峰，第一电容C1放电形成第二个波峰。第三电阻R3是用于等效实际的负载，通常通过设置其为2Ω来实现，第三电容C3是用于对最终波形的第一波峰上升时间和峰值来进行微调以满足需求，最终，当压控开关电路K1导通时，在第三电阻R3端形成双峰波形。
基于上述任一实施例，该电路中，所述TLP发生器电路和所述TLP外接电路通过二极管相连，所述TLP发生器电路的输出端连接所述二极管的正极，所述二极管的负极连接所述TLP外接电路的输入端。
具体地，在TLP发生器电路和所述TLP外接电路之间加一个二极管，可以避免TLP外接电路电流反向流入TLP发生器电路烧坏TLP发生器电路中的元器件。
基于上述任一实施例，该电路中，所述第一电阻的阻值为150Ω，所述第一电感的电感值为3.5uH，所述第一电容的电容值为150pF，所述第二电容的电容值为8pF，所述第二电感的电感值为150nH，所述第二电阻的阻值为130Ω，所述第一压控开关的开启电压为1V，所述第一压控开关 的截止电压为0V，所述第三电容的电容值为1.5nF，所述第三电阻的阻值为2Ω。
基于上述任一实施例，图4为本申请实施例提供的TLP发生器电路的结构示意图。如图4所示，该电路中，所述TLP发生器电路，包括直流电压源V1、第四电阻R4、第二压控开关K2、传输线单元T1、第三压控开关K3、第四电容C4和第五电阻R5，其中，
所述直流电压源V1的负极接地，所述直流电压源V1的正极连接所述第四电阻R4的一端，所述第四电阻R4的另一端连接所述第二压控开关K2的一端，所述第二压控开关K2的另一端连接所述传输线单元T1的一端，所述传输线单元T1的另一端连接所述第四电容C4的一端，所述传输线单元T1的另一端还连接所述第五电阻R5的一端，所述第四电容C4的另一端接地，所述第五电阻R5的另一端B点为所述TLP发生器电路的输出端。
具体地，TLP发生器电路是TLP激励发生器的等效电路结构，由传输线单元、两个压控开关、直流电压源和电阻构成。其中，TLP波形的才产生原理是基于传输线的充放电形成，该传输线的阻抗优选50Ω，两个压控开关用于控制传输线单元的充放电，直流电压源通过第四电阻R4给传输线单元充电，第四电容C4的作用是调节TLP激励的上升时间。最终，通过传输线单元放电过程中的入射波和反射波的叠加形成类似直流方式的TLP激励，脉宽为100ns。
基于上述任一实施例，该电路中，所述第四电阻的阻值为1kΩ，所述第二压控开关的开启电压为1V，所述第二压控开关的截止电压为0V，所述传输线单元的特征阻抗值为50Ω，所述传输线单元的时延为50ns，所述第三压控开关的开启电压为1V，所述第三压控开关的截止电压为0V，所述第四电容的电容值为400pF，所述第五电阻的阻值为50Ω。
基于上述任一实施例，图5为本申请实施例提供的产生符合IEC61000-4-2标准双峰波形的方法的流程示意图。如图5所示，本申请实施例提供一种基于上述任一实施例产生双峰波形的方法，包括：
步骤510，在所述第二压控开关上加载第一矩形脉冲激励；
步骤520，在所述第三压控开关上加载第二矩形脉冲激励；
步骤530，在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
具体地，要产生双峰波形需要在TLP发生器电路和TLP外接电路的压控开关上加载激励，加载在传输线单元两端的压控开关的激励是为了控制传输线单元的充放电，加载在TLP外接电路的压控开关的激励是为了控制第一电容和第二电容的放电形成两个波峰。
本申请实施例提供的方法，通过在TLP发生器电路中的压控开关和TLP外接电路的压控开关上加载矩形脉冲激励，实现了双峰波形的产生，避免了对TLP发生器内部电路的改装带来的TLP机台被破坏的风险，简化了改装过程。
基于上述任一实施例，该方法中，所述第一矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝0，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
所述第二矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝20ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝1000ns；
所述第三矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝140ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
对应地，产生的双峰波形为符合IEC 61000-4-2静电标准的双峰波形。
具体地，图6为本申请实施例提供的产生符合IEC 61000-4-2静电标准的双峰波形的电路结构示意图。如图6所示，虚线左边是TLP发生器电路，虚线右边是通过二极管D1连接的TLP外接电路，在TLP发生器电路中的R 1的阻值为1kΩ，传输线单元的特征阻抗Z 0为50Ω，延时Delay为50ns，C 1为400pF，R 2为50Ω，压控开关S 1的开启电压V on＝1V，截止电压V off＝0V，压控开关S 2的开启电压V on＝1V，截止电压V off＝0V，在压控开关S 1上加载矩形脉冲V pulse1，其高电压为1V，低电压为0V，时间延迟TD＝0，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns，在压控开关S 2上加载矩形脉冲V pulse2，其高电压为1V，低电压为0V，时间延迟TD＝20ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝1000ns；在TLP外接电路中，C 2的电容值为150pF，L 1的电感值为3.5uH，R 3的电阻值为150Ω，C 3的电容值为8pF，L 2的电感值为150nH，R 4的电阻值为 130Ω，压控开关S 3的开启电压V on＝1V，截止电压V off＝0V，C 4的电容值为1.5nF，R 5的电阻值为2Ω，在压控开关S 3上加载矩形脉冲V pulse3，其高电压为1V，低电压为0V，时间延迟TD＝140ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns。在R 5一端输出的IEC Stress Output(IEC应力输出)即符合IEC 61000-4-2静电标准的双峰波形。
基于上述任一实施例，本申请实施例提供一种产生符合IEC61000-4-2标准双峰波形的装置，图7为本申请实施例提供的产生双峰波形的装置的结构示意图，该装置包括第一加载单元710、第二加载单元720和第三加载单元730，其中，
所述第一加载单元710，被配置成在所述第二压控开关上加载第一矩形脉冲激励；
所述第二加载单元720，被配置成在所述第三压控开关上加载第二矩形脉冲激励；
所述第三加载单元730，被配置成在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
本申请实施例提供的产生双峰波形的装置，通过在TLP发生器电路中的压控开关和TLP外接电路的压控开关上加载矩形脉冲激励，实现了双峰波形的产生，避免了对TLP发生器内部电路的改装带来的TLP机台被破坏的风险，简化了改装过程。
基于上述任一实施例，该装置中，所述第一矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝0，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
所述第二矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝20ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝1000ns；
所述第三矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝140ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
对应地，产生的双峰波形为符合IEC 61000-4-2静电标准的双峰波形。
图8为本申请实施例提供的电子设备的实体结构示意图，如图8所示，该电子设备可以包括：处理器(processor)801、通信接口(Communications Interface)802、存储器(memory)803和通信总线804，其中，处理器801， 通信接口802，存储器803通过通信总线804完成相互间的通信。处理器801可以调用存储在存储器803上并可在处理器801上运行的计算机程序，以执行上述各实施例提供的产生符合IEC61000-4-2标准双峰波形的方法，例如包括：在所述第二压控开关上加载第一矩形脉冲激励；在所述第三压控开关上加载第二矩形脉冲激励；在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
此外，上述的存储器803中的逻辑指令可以通过软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(例如，个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本申请实施例还提供一种非暂态计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现以执行上述各实施例提供的产生符合IEC61000-4-2标准双峰波形的方法，例如包括：在所述第二压控开关上加载第一矩形脉冲激励；在所述第三压控开关上加载第二矩形脉冲激励；在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个位置，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡 献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，包括TLP发生器电路和TLP外接电路，其中，
    所述TLP发生器电路，被配置成产生TLP激励；
    所述TLP外接电路，被配置成存储所述TLP激励产生的能量，并释放双峰波形形态的静电激励。
  2. 根据权利要求1所述的产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，所述TLP外接电路，包括第一电阻、第一电感、第一电容、第二电感、第二电容、第二电阻、第一压控开关、第三电容和第三电阻，其中，
    所述第一电阻、所述第一电感和所述第一电容串联形成所述TLP外接电路的第一支路；
    所述第二电容形成所述TLP外接电路的第二支路；
    所述第三电阻和所述第三电容并联后再与所述第二电感、第二电阻和第一压控开关串联形成所述TLP外接电路的第三支路；
    所述第一支路、所述第二支路和所述第三支路的一端为TLP外接电路的输入端，所述第一支路、所述第二支路和所述第三支路的另一端接地。
  3. 根据权利要求2所述的产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，所述TLP发生器电路和所述TLP外接电路通过二极管相连，所述TLP发生器电路的输出端连接所述二极管的正极，所述二极管的负极连接所述TLP外接电路的输入端。
  4. 根据权利要求2或3所述的产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，所述第一电阻的阻值为150Ω，所述第一电感的电感值为3.5uH，所述第一电容的电容值为150pF，所述第二电容的电容值为8pF，所述第二电感的电感值为150nH，所述第二电阻的阻值为130Ω，所述第一压控开关的开启电压为1V，所述第一压控开关的截止电压为0V，所述第三电容的电容值为1.5nF，所述第三电阻的阻值为2Ω。
  5. 根据权利要求4所述的产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，所述TLP发生器电路，包括直流电压源、第四电阻、第二压控开关、传输线单元、第三压控开关、第四电容和第五电阻，其中，
    所述直流电压源的负极接地，所述直流电压源的正极连接所述第四电阻的一端，所述第四电阻的另一端连接所述第二压控开关的一端，所述第二压控开关的另一端连接所述传输线单元的一端，所述传输线单元的另一端连接所述第四电容的一端，所述传输线单元的另一端还连接所述第五电阻的一端，所述第四电容的另一端接地，所述第五电阻的另一端为所述TLP发生器电路的输出端。
  6. 根据权利要求5所述的产生符合IEC61000-4-2标准双峰波形的电路，其特征在于，所述第四电阻的阻值为1kΩ，所述第二压控开关的开启电压为1V，所述第二压控开关的截止电压为0V，所述传输线单元的特征阻抗值为50Ω，所述传输线单元的时延为50ns，所述第三压控开关的开启电压为1V，所述第三压控开关的截止电压为0V，所述第四电容的电容值为400pF，所述第五电阻的阻值为50Ω。
  7. 基于权利要求5或6所述的产生符合IEC61000-4-2标准双峰波形的电路的产生符合IEC61000-4-2标准双峰波形的方法，其特征在于，包括：
    在所述第二压控开关上加载第一矩形脉冲激励；
    在所述第三压控开关上加载第二矩形脉冲激励；
    在所述第一压控开关上加载第三矩形脉冲激励，以产生双峰波形。
  8. 根据权利要求7所述的产生符合IEC61000-4-2标准双峰波形的方法，其特征在于，
    所述第一矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝0，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
    所述第二矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝20ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝1000ns；
    所述第三矩形脉冲的高电压为1V，低电压为0V，时间延迟TD＝140ns，上升时间为0.1ps，下降时间为0.1ps，矩形宽度PW＝15ns；
    对应地，产生的双峰波形为符合IEC 61000-4-2静电标准的双峰波形。
  9. 一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其特征在于，所述处理器执行所述程序时实现如权利要求7或8所述的产生符合IEC61000-4-2标准双峰波形的方法的步骤。
  10. 一种非暂态计算机可读存储介质，其上存储有计算机程序，其特征在于，该计算机程序被处理器执行时实现如权利要求7或8所述的产生符合IEC61000-4-2标准双峰波形的方法的步骤。
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