WO2018107568A1 - 一种保护装置、供电装置及终端 - Google Patents

一种保护装置、供电装置及终端 Download PDF

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Publication number
WO2018107568A1
WO2018107568A1 PCT/CN2017/072571 CN2017072571W WO2018107568A1 WO 2018107568 A1 WO2018107568 A1 WO 2018107568A1 CN 2017072571 W CN2017072571 W CN 2017072571W WO 2018107568 A1 WO2018107568 A1 WO 2018107568A1
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Prior art keywords
unit
protection unit
overvoltage protection
voltage
surge
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PCT/CN2017/072571
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English (en)
French (fr)
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涂瑞
高思
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宇龙计算机通信科技(深圳)有限公司
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Publication of WO2018107568A1 publication Critical patent/WO2018107568A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/047—Free-wheeling circuits

Definitions

  • the present invention relates to the field of terminal technologies, and in particular, to a protection device, a power supply device, and a terminal.
  • Solution 1 Connect a high-power surge tube to the GND (ground) on the VBUS (USB voltage) line;
  • Solution 3 Connect the high-power surge tube to the GND on the VBUS line first, and then connect the OVP chip to the GND after the high-power surge tube.
  • the high-power surge tube only protects the surge voltage or surge current of the us (microsecond) level. Although the peak power is high, the average power is low, and the DC high voltage of the ms (millisecond) level is encountered. It will burn out soon, causing VBUS to short-circuit to GND. At this time, the mobile phone will be retired due to the inability to charge;
  • the OVP chip when there is DC high voltage on the VBUS line, the OVP chip can disconnect the VBUS and the back-end PMU (Power Management Unit) chip in the 100 ns (nanosecond) level to protect the back-end chip; Due to the area of the OVP chip, the surge protection capability is weak; when a large surge voltage occurs, the OVP chip will burn out, that is, the OVP chip is short-circuited to the GND, that is, the VBUS is short-circuited to the GND, and the mobile phone cannot be used at this time. Charging leads to customer return;
  • PMU Power Management Unit
  • the technical problem to be solved by the present invention is to provide a protection device, a power supply device and a terminal.
  • the VBUS in the event of a surge or a DC high voltage, the VBUS is short-circuited to the GND, causing the terminal to be retired due to the inability to charge.
  • the present invention provides a protection device including a first overvoltage protection unit, a surge protection unit and a second overvoltage protection unit, a first overvoltage protection unit, a surge protection unit, and a second overvoltage
  • the protection unit and the unit to be protected are sequentially connected in parallel between the power supply terminal VBUS and the ground end in a sequence from the near end to the far end of the power supply terminal VBUS;
  • the first overvoltage protection unit and the second overvoltage protection unit are respectively used to load the DC voltage between the power supply terminal VBUS and the ground terminal and the power supply terminal VBUS further away from itself when the DC voltage is equal to or greater than the corresponding threshold value.
  • the unit is protected from DC voltage;
  • the surge protection unit is used to protect the unit connected in parallel between the power supply terminal VBUS and the ground terminal and farther from the power supply terminal VBUS than itself from the surge when the voltage or current surge occurs.
  • the threshold corresponding to the first overvoltage protection unit is equal to the threshold corresponding to the second overvoltage protection unit, or the threshold corresponding to the first overvoltage protection unit is greater than the threshold corresponding to the second overvoltage protection unit.
  • At least one of the first overvoltage protection unit and the second overvoltage protection unit comprises an OVP chip.
  • At least one of the first overvoltage protection unit and the second overvoltage protection unit further comprises: two resistance units, wherein one of the resistance units is connected in parallel with the OVP chip, and the circuit after the parallel connection is further connected in series with the other resistance unit.
  • the first overvoltage protection unit includes: a first OVP chip, a first resistor unit, and a second resistor unit, the first resistor unit is connected in parallel with the first OVP chip, and the parallel circuit is connected in series with the second resistor unit;
  • the overvoltage protection unit includes: a second OVP chip, a third resistance unit and a fourth resistance unit, the third resistance unit is connected in parallel with the second OVP chip, and the parallel circuit is connected in series with the fourth resistance unit; the first OVP chip and the first The protection voltage of the two OVP chips is the same.
  • the method further includes: a fifth resistor unit, a sixth resistor unit, a first capacitor unit, and/or a second capacitor unit, which are sequentially connected in parallel between the power supply terminal VBUS and the ground end in the following order: the first capacitor unit and the fifth unit.
  • the sum of the capacitance values of the first capacitor unit and the second capacitor unit is less than 6.5 microfarads.
  • the surge protection unit includes a surge tube.
  • the present invention provides a power supply device, comprising the protection device of any of the above, further comprising a unit to be protected, the unit to be protected comprising a power management unit.
  • the present invention provides a terminal, including a terminal body and the above-described power supply device.
  • a protection device includes a first overvoltage protection unit, a surge protection unit and a second overvoltage protection unit, a first overvoltage protection unit, a surge protection unit,
  • the second overvoltage protection unit and the unit to be protected are sequentially connected in parallel between the power supply terminal VBUS and the ground end in a sequence from the near end to the power supply terminal VBUS;
  • the first overvoltage protection unit and the second overvoltage protection unit are respectively used for loading
  • the DC voltage of the DC voltage is equal to or greater than the corresponding threshold
  • the unit connected in parallel between the power supply terminal VBUS and the ground terminal and farther from the power supply terminal VBUS than the DC voltage is protected from the DC voltage;
  • the surge protection unit is used to load itself When a voltage or current surge occurs, the unit connected in parallel between the power supply terminal VBUS and the ground terminal and farther from the power supply terminal VBUS than itself is protected from the surge; the above solution can solve the wave on the VBUS line
  • FIG. 1 is a schematic diagram of a protection device according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a power supply device according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of a terminal according to Embodiment 3 of the present invention.
  • the terminal described in the present invention may include a terminal such as a smartphone, a notebook computer, or a PAD (Tablet Computer).
  • a terminal such as a smartphone, a notebook computer, or a PAD (Tablet Computer).
  • PAD Tablet Computer
  • FIG. 1 is a schematic diagram of a protection device according to an embodiment.
  • the protection device includes: a first overvoltage protection unit 11 , a surge protection unit 12 , and a second The voltage protection unit 13; the first overvoltage protection unit 11, the surge protection unit 12, the second overvoltage protection unit 13, and the unit to be protected (not shown in FIG. 1) are arranged in order from the near end to the far end of the power supply terminal VBUS. Parallel between the power supply terminal VBUS and the ground terminal;
  • the unit to be protected includes a power management unit, that is, a PMU chip.
  • the first overvoltage protection unit 11 and the second overvoltage protection unit 13 are respectively used to load the DC voltage between the power supply terminal VBUS and the ground terminal and the power supply terminal VBUS more than itself when the DC voltage is equal to or greater than the corresponding threshold value.
  • the far unit is protected from DC voltage;
  • the voltage of each unit is limited to a voltage range that can withstand each other, so that each The unit continues to work; or, short-circuit between the power supply terminal VBUS and the ground, the rear unit stops working, and the protected unit is protected from impact and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the surge protection unit 12 and the second overvoltage protection unit. 13. Unit to be protected, etc.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the unit to be protected and the like.
  • the threshold corresponding to the first overvoltage protection unit 11 is equal to the threshold corresponding to the second overvoltage protection unit 13, or the threshold corresponding to the first overvoltage protection unit 11 is greater than the threshold corresponding to the second overvoltage protection unit 13.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 comprises an OVP chip. That is, the first overvoltage protection unit 11 includes an OVP chip, or the second overvoltage protection unit 13 includes an OVP chip, or both the first overvoltage protection unit 11 and the second overvoltage protection unit 13 include an OVP chip.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 further includes: two resistance units, wherein one of the resistance units is connected in parallel with the OVP chip, and the circuit connected in parallel is connected in series with another resistance unit. .
  • the first overvoltage protection unit 11 includes: a first OVP chip (U1) 111, a first resistance unit (R1) 112, and a second resistance unit (R2) 113, and the first resistance unit 112 and the first An OVP chip 111 is connected in parallel, and the circuit after the parallel connection is further connected in series with the second resistance unit 113;
  • the second overvoltage protection unit 13 includes a second OVP chip (U2) 131, a third resistance unit (R3) 132, and a fourth resistance unit (R4) 133.
  • the third resistance unit 132 is connected in parallel with the second OVP chip 131.
  • the subsequent circuit is further connected in series with the fourth resistance unit 133;
  • the first OVP chip 111 has the same protection voltage as the second OVP chip 131.
  • the method further includes: a fifth resistor unit (R5) 14, a sixth resistor unit (R6) 15, a first capacitor unit (C1) 16, and/or a second capacitor unit (C2) 17, each unit
  • the power supply terminal VBUS and the ground terminal are sequentially connected in parallel in the following order: the first capacitor unit 16, the fifth resistor unit 15, the first overvoltage protection unit 11, the surge protection unit (D1) 12, and the second overvoltage protection.
  • the first capacitor unit 16 and the second capacitor unit 17 are voltage stabilizing capacitors on the VBUS line, and the sum of the capacitance values of the first capacitor unit 16 and the second capacitor unit 17 is less than 6.5 uF (microfarad), that is, C1+C2 ⁇ 6.5 uF.
  • the fifth resistance unit 14 and the sixth resistance unit 15 are bleeder resistors in the range of several tens of K ohms.
  • the first OVP chip 111 disconnects the VBUS and the back-end surge protection unit 12 and the second OVP chip 131 in a few hundred ns. And the connection of the unit to be protected, the surge protection unit 12 can be protected from being damaged by the DC high voltage for a long time.
  • the surge protection unit 12 is configured to protect a unit connected in parallel between the power supply terminal VBUS and the ground terminal and further away from the power supply terminal VBUS than itself from the surge when a surge of its own voltage or current occurs.
  • each single will be The voltage and current of the element are limited to the voltage and current range that it can withstand; or, a powerful lightning current is discharged into the ground to protect the protected unit from impact and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the second overvoltage protection unit 13, the unit to be protected, and the like.
  • the surge protection unit 12 includes a surge tube, and the surge tube can be a high power TVS (Transient Voltage Suppressor) tube.
  • TVS Transient Voltage Suppressor
  • the first OVP chip 111 and the second OVP chip 131 are turned on, and the surge protection unit 12 clamps the surge voltage to a lower voltage to protect the PMU at the back end. chip.
  • the surge problem on the VBUS line can be solved, and the DC high voltage problem on the VBUS line can be solved, the problem of short circuit between VBUS and GND caused by the existing solution is avoided, and the customer retreat rate is lowered and the speed is improved.
  • the user experience can be implemented using the following steps:
  • FIG. 2 is a schematic diagram of a power supply device according to the embodiment.
  • the power supply device includes the protection device 20 in the first embodiment, and further includes a unit 21 to be protected.
  • the protection unit 21 includes a power management unit, that is, the PMU chip in FIG.
  • the protection device 20 includes: a first overvoltage protection unit 11, a surge protection unit 12 and a second overvoltage protection unit 13; a first overvoltage protection unit 11, a surge protection unit 12, a second overvoltage protection unit 13 and The unit to be protected 21 is sequentially connected in parallel between the power supply terminal VBUS and the ground end in the order of the power supply terminal VBUS from near to far;
  • the first overvoltage protection unit 11 and the second overvoltage protection unit 13 are respectively used to load the DC voltage between the power supply terminal VBUS and the ground terminal and the power supply terminal VBUS more than itself when the DC voltage is equal to or greater than the corresponding threshold value.
  • the far unit is protected from DC voltage;
  • the voltage of each unit is limited to a voltage range that can withstand each other, so that each The unit continues to work; or, short-circuit between the power supply terminal VBUS and the ground, the rear unit stops working, and the protected unit is protected from impact and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the surge protection unit 12 and the second pass.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the unit 21 to be protected and the like.
  • the threshold corresponding to the first overvoltage protection unit 11 is equal to the threshold corresponding to the second overvoltage protection unit 13, or the threshold corresponding to the first overvoltage protection unit 11 is greater than the threshold corresponding to the second overvoltage protection unit 13.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 comprises an OVP chip. That is, the first overvoltage protection unit 11 includes an OVP chip, or the second overvoltage protection unit 13 includes an OVP chip, or both the first overvoltage protection unit 11 and the second overvoltage protection unit 13 include an OVP chip.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 further includes: two resistance units, wherein one of the resistance units is connected in parallel with the OVP chip, and the circuit connected in parallel is connected in series with another resistance unit. .
  • the first overvoltage protection unit 11 includes: a first OVP chip (U1) 111, a first resistance unit (R1) 112, and a second resistance unit (R2) 113, and the first resistance unit 112 and the first An OVP chip 111 is connected in parallel, and the circuit after the parallel connection is further connected in series with the second resistance unit 113;
  • the second overvoltage protection unit 13 includes a second OVP chip (U2) 131, a third resistance unit (R3) 132, and a fourth resistance unit (R4) 133.
  • the third resistance unit 132 is connected in parallel with the second OVP chip 131.
  • the subsequent circuit is further connected in series with the fourth resistance unit 133;
  • the first OVP chip 111 has the same protection voltage as the second OVP chip 131.
  • the method further includes: a fifth resistor unit (R5) 14, a sixth resistor unit (R6) 15, a first capacitor unit (C1) 16, and/or a second capacitor unit (C2) 17, each unit
  • the power supply terminal VBUS and the ground terminal are sequentially connected in parallel in the following order: the first capacitor unit 16, the fifth resistor unit 15, the first overvoltage protection unit 11, the surge protection unit (D1) 12, and the second overvoltage protection.
  • the first capacitor unit 16 and the second capacitor unit 17 are voltage stabilizing capacitors on the VBUS line, and the first power
  • the sum of the capacitance values of the volume unit 16 and the second capacitor unit 17 is less than 6.5 uF (microfarad), that is, C1 + C2 ⁇ 6.5 uF.
  • the fifth resistance unit 14 and the sixth resistance unit 15 are bleeder resistors in the range of several tens of K ohms.
  • the first OVP chip 111 disconnects the VBUS and the back-end surge protection unit 12 and the second OVP chip 131 in a few hundred ns. And the connection of the unit 21 to be protected, the surge protection unit 12 can be protected from being damaged by DC high voltage for a long time.
  • the surge protection unit 12 is configured to protect a unit connected in parallel between the power supply terminal VBUS and the ground terminal and further away from the power supply terminal VBUS than itself from the surge when a surge of its own voltage or current occurs.
  • the voltage and current of each unit are limited to a voltage and current range that can be withstood by itself; or a powerful lightning current is discharged into the current. Ground, protect the protected unit from damage and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the second overvoltage protection unit 13, the unit 21 to be protected, and the like.
  • the surge protection unit 12 includes a surge tube, and the surge tube can be a high power TVS tube.
  • the first OVP chip 111 and the second OVP chip 131 are turned on, and the surge protection unit 12 clamps the surge voltage to a lower voltage to protect the PMU at the back end. chip.
  • the surge problem on the VBUS line can be solved, and the DC high voltage problem on the VBUS line can be solved, the problem of short circuit between VBUS and GND caused by the existing solution is avoided, and the customer retreat rate is lowered and the speed is improved.
  • the user experience can be implemented using the following steps:
  • FIG. 3 is a schematic diagram of a terminal according to the embodiment.
  • the terminal includes a terminal body 31 and a power supply device 32 in the second embodiment.
  • the power supply device 32 includes the protection device 20 in the first embodiment, and further includes a unit 21 to be protected.
  • the unit to be protected 21 includes a power management unit, that is, the PMU chip in FIG.
  • the protection device 20 includes: a first overvoltage protection unit 11, a surge protection unit 12, and a second overvoltage protection unit 13; a first overvoltage protection unit 11, a surge protection unit 12, and a second overvoltage protection unit 13 And the unit to be protected 21 is sequentially connected in parallel between the power supply terminal VBUS and the ground end in a sequence from the near end to the far end of the power supply terminal VBUS;
  • the first overvoltage protection unit 11 and the second overvoltage protection unit 13 are respectively used to load the DC voltage between the power supply terminal VBUS and the ground terminal and the power supply terminal VBUS more than itself when the DC voltage is equal to or greater than the corresponding threshold value.
  • the far unit is protected from DC voltage;
  • the voltage of each unit is limited to a voltage range that can withstand each other, so that each The unit continues to work; or, short-circuit between the power supply terminal VBUS and the ground, the rear unit stops working, and the protected unit is protected from impact and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the surge protection unit 12 and the second overvoltage protection unit. 13.
  • the unit 21 to be protected (the PMU chip in Fig. 2) and the like.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the unit 21 to be protected and the like.
  • the threshold corresponding to the first overvoltage protection unit 11 is equal to the threshold corresponding to the second overvoltage protection unit 13, or the threshold corresponding to the first overvoltage protection unit 11 is greater than the threshold corresponding to the second overvoltage protection unit 13.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 comprises an OVP chip. That is, the first overvoltage protection unit 11 includes an OVP chip, or the second overvoltage protection unit 13 includes an OVP chip, or both the first overvoltage protection unit 11 and the second overvoltage protection unit 13 include an OVP chip.
  • At least one of the first overvoltage protection unit 11 and the second overvoltage protection unit 13 further includes: two resistance units, wherein one of the resistance units is connected in parallel with the OVP chip, and the circuit connected in parallel is connected in series with another resistance unit. .
  • the first overvoltage protection unit 11 includes: a first OVP chip (U1) 111, a first resistance unit (R1) 112, and a second resistance unit (R2) 113, and the first resistance unit 112 and the first An OVP chip 111 is connected in parallel, and the circuit after the parallel connection is further connected in series with the second resistance unit 113;
  • the second overvoltage protection unit 13 includes a second OVP chip (U2) 131, a third resistance unit (R3) 132, and a fourth resistance unit (R4) 133.
  • the third resistance unit 132 is connected in parallel with the second OVP chip 131.
  • the subsequent circuit is further connected in series with the fourth resistance unit 133;
  • the first OVP chip 111 has the same protection voltage as the second OVP chip 131.
  • the method further includes: a fifth resistor unit (R5) 14, a sixth resistor unit (R6) 15, a first capacitor unit (C1) 16, and/or a second capacitor unit (C2) 17, each unit
  • the power supply terminal VBUS and the ground terminal are sequentially connected in parallel in the following order: the first capacitor unit 16, the fifth resistor unit 15, the first overvoltage protection unit 11, the surge protection unit (D1) 12, and the second overvoltage protection.
  • the first capacitor unit 16 and the second capacitor unit 17 are voltage stabilizing capacitors on the VBUS line, and the sum of the capacitance values of the first capacitor unit 16 and the second capacitor unit 17 is less than 6.5 uF (microfarad), that is, C1+C2 ⁇ 6.5 uF.
  • the fifth resistance unit 14 and the sixth resistance unit 15 are bleeder resistors in the range of several tens of K ohms.
  • the first OVP chip 111 disconnects the VBUS and the back-end surge protection unit 12 and the second OVP chip 131 in a few hundred ns. And the connection of the unit 21 to be protected, the surge protection unit 12 can be protected from being damaged by DC high voltage for a long time.
  • the surge protection unit 12 is configured to protect a unit connected in parallel between the power supply terminal VBUS and the ground terminal and further away from the power supply terminal VBUS than itself from the surge when a surge of its own voltage or current occurs.
  • the voltage and current of each unit are limited to a voltage and current range that can be withstood by itself; or a powerful lightning current is discharged into the current. Ground, protect the protected unit from damage and damage.
  • the above-mentioned unit farther from the power supply terminal VBUS than itself includes the second overvoltage protection unit 13, the unit 21 to be protected, and the like.
  • the surge protection unit 12 includes a surge tube, and the surge tube can be a high power TVS tube.
  • the first OVP chip 111 and the second OVP chip 131 are turned on, and the surge protection unit 12 clamps the surge voltage to a lower voltage to protect the PMU at the back end. chip.
  • the surge problem on the VBUS line can be solved, and the DC high voltage problem on the VBUS line can be solved, the problem of short circuit between VBUS and GND caused by the existing solution is avoided, and the customer retreat rate is lowered and the speed is improved.
  • the user experience can be implemented using the following steps:
  • modules or steps of the above embodiments of the present invention can be implemented by a general computing device, which can be concentrated on a single computing device or distributed among multiple computing devices.
  • they may be implemented by program code executable by the computing device, such that they may be stored in a storage medium (ROM/RAM, disk, optical disk) by a computing device, and in some
  • the steps shown or described may be performed in an order different from that herein, or they may be separately fabricated into individual integrated circuit modules, or a plurality of the modules or steps may be implemented as a single integrated circuit module. Therefore, the invention is not limited to any particular combination of hardware and software.

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Abstract

一种保护装置、供电装置及终端，该保护装置包括第一过压保护单元（11）、浪涌保护单元（12）和第二过压保护单元（13），第一过压保护单元、浪涌保护单元、第二过压保护单元以及待保护单元（21）按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；第一过压保护单元、第二过压保护单元分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；浪涌保护单元用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响；解决了VBUS线路上的浪涌问题，也可解决VBUS线路上的直流高压问题，降低了客退率，提升用户体验。

Description

一种保护装置、供电装置及终端
本申请要求2016年12月16日在中国国家知识产权局提交的申请号为201611170222.3、发明名称为“一种保护装置、供电装置及终端”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及终端技术领域，尤其涉及一种保护装置、供电装置及终端。
背景技术
目前，手机防浪涌方案有3种：
方案1、在VBUS(USB电压)线路上对GND(地端)并联大功率浪涌管；
方案2、在VBUS线路上对GND并联OVP(Over Voltage Protection，过压保护)芯片；
方案3、在VBUS线路上对GND先并联大功率浪涌管，在大功率浪涌管后边再对GND并联OVP芯片。
现有技术的缺陷：
方案1、大功率浪涌管只对us(微秒)级别的浪涌电压或浪涌电流有防护作用，虽然峰值功率很高，但平均功率较低，遇到ms(毫秒)级别的直流高压时很快会烧毁，导致VBUS对GND短路，此时手机由于无法充电导致客退；
方案2、VBUS线路上有直流高压时，OVP芯片能够在100ns(纳秒)级别的时间内断开VBUS与后端PMU(Power Management Unit，电源管理单元)芯片的连接，保护后端芯片；但受限于OVP芯片的面积，其浪涌防护能力较弱；当出现较大的浪涌电压时，OVP芯片会烧毁，即OVP芯片对GND短路，亦即VBUS对GND短路，此时手机由于无法充电导致客退；
方案3、虽然具有较高的浪涌以及直流高压的防护能力，当VBUS线路上出 现ms级别以上的直流高压时，OVP芯片会断开VBUS与后端芯片的连接，但OVP断开以后，如果VBUS上的直流高压依然存在，那么OVP前端的大功率浪涌也会很快烧毁而导致VBUS与GND的短路，此时手机由于无法充电导致客退。
发明内容
本发明主要解决的技术问题是，提供一种保护装置、供电装置及终端，解决现有技术中，在出现浪涌或直流高压导致VBUS对GND短路，造成终端由于无法充电导致客退的问题。
为解决上述技术问题，本发明提供一种保护装置，包括第一过压保护单元、浪涌保护单元和第二过压保护单元，第一过压保护单元、浪涌保护单元、第二过压保护单元以及待保护单元按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；
第一过压保护单元、第二过压保护单元分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；
浪涌保护单元用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响。
其中，第一过压保护单元对应的阈值与第二过压保护单元对应的阈值相等，或者第一过压保护单元对应的阈值大于第二过压保护单元对应的阈值。
其中，第一过压保护单元和第二过压保护单元中的至少一者包括OVP芯片。
其中，第一过压保护单元和第二过压保护单元中的至少一者还包括：两个电阻单元，其中一个电阻单元与OVP芯片并联，并联后的电路再与另一个电阻单元串联。
其中，第一过压保护单元包括：第一OVP芯片、第一电阻单元和第二电阻单元，第一电阻单元与第一OVP芯片并联，并联后的电路再与第二电阻单元串联；第二过压保护单元包括：第二OVP芯片、第三电阻单元和第四电阻单元，第三电阻单元与第二OVP芯片并联，并联后的电路再与第四电阻单元串联；第一OVP芯片与第二OVP芯片的保护电压相同。
其中，还包括：第五电阻单元、第六电阻单元、第一电容单元和/或第二电容单元，分别按照以下顺序依次并联在电源端VBUS和地端之间：第一电容单元、第五电阻单元、第一过压保护单元、浪涌保护单元、第二过压保护单元、第六电阻单元、第二电容单元、待保护单元。
其中，第一电容单元和第二电容单元的电容值之和小于6.5微法。
其中，浪涌保护单元包括浪涌管。
为解决上述技术问题，本发明提供一种供电装置，包括上述任一项的保护装置，还包括待保护单元，待保护单元包括电源管理单元。
为解决上述技术问题，本发明提供一种终端，包括终端本体以及上述的供电装置。
根据本发明提供的一种保护装置、供电装置及终端，该保护装置包括第一过压保护单元、浪涌保护单元和第二过压保护单元，第一过压保护单元、浪涌保护单元、第二过压保护单元以及待保护单元按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；第一过压保护单元、第二过压保护单元分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；浪涌保护单元用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响；采用上述方案，既可解决VBUS线路上的浪涌问题，也可解决VBUS线路上的直流高压问题，避免了现有方案导致的VBUS与GND短路的问题，降低了客退率，提升了用户体验。
附图说明
图1为本发明实施例一提供的一种保护装置的示意图；
图2为本发明实施例二提供的一种供电装置的示意图；
图3为本发明实施例三提供的一种终端的示意图。
具体实施方式
应当理解的是，此处所描述的具体实施例仅用于解释本发明，并不用于限定本发明。
本发明中描述的终端可包括智能手机、笔记本电脑、PAD(平板电脑)等终端。下面通过具体实施方式结合附图对本发明作进一步详细说明。
实施例一
本实施例提供一种保护装置，参见图1，图1为本实施例提供的一种保护装置的示意图，该保护装置包括：第一过压保护单元11、浪涌保护单元12和第二过压保护单元13；第一过压保护单元11、浪涌保护单元12、第二过压保护单元13以及待保护单元(图1中未示出)按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；
待保护单元包括电源管理单元，即PMU芯片。
第一过压保护单元11、第二过压保护单元13分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；
示例性的，当加载在第一过压保护单元11或第二过压保护单元13的直流电压等于或大于对应阈值时，将各个单元的电压限制在各自所能承受的电压范围内，让各个单元继续工作；或者，将电源端VBUS和地端之间短路，后面的单元停止工作，保护被保护的单元不受冲击而损坏。
在图1中，当加载在第一过压保护单元11的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括浪涌保护单元12、第二过压保护单元13、待保护单元等。
在图1中，当加载在第二过压保护单元13的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括待保护单元等。
其中，第一过压保护单元11对应的阈值与第二过压保护单元13对应的阈值相等，或者第一过压保护单元11对应的阈值大于第二过压保护单元13对应的阈值。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者包括OVP芯片。即第一过压保护单元11包括OVP芯片，或者第二过压保护单元13包括OVP芯片，或者第一过压保护单元11和第二过压保护单元13都包括OVP芯片。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者还包括：两个电阻单元，其中一个电阻单元与OVP芯片并联，并联后的电路再与另一个电阻单元串联。
在一种实施方式中，第一过压保护单元11包括：第一OVP芯片(U1)111、第一电阻单元(R1)112和第二电阻单元(R2)113，第一电阻单元112与第一OVP芯片111并联，并联后的电路再与第二电阻单元113串联；
第二过压保护单元13包括：第二OVP芯片(U2)131、第三电阻单元(R3)132和第四电阻单元(R4)133，第三电阻单元132与第二OVP芯片131并联，并联后的电路再与第四电阻单元133串联；
第一OVP芯片111与第二OVP芯片131的保护电压相同。
第一电阻单元112、第二电阻单元113设置了第一OVP芯片111的OVP防护电压Vovp1＝Vref*R2/(R1+R2)，Vref为基准电压。第三电阻单元132、第四电阻单元133设置了第二OVP芯片131的OVP防护电压Vovp2＝Vref*R4/(R3+R4)；本方案中设置Vovp1＝Vovp2。
在一种实施方式中，还包括：第五电阻单元(R5)14、第六电阻单元(R6)15、第一电容单元(C1)16和/或第二电容单元(C2)17，各个单元分别按照以下顺序依次并联在电源端VBUS和地端之间：第一电容单元16、第五电阻单元15、第一过压保护单元11、浪涌保护单元(D1)12、第二过压保护单元13、第六电阻单元15、第二电容单元17、待保护单元。
第一电容单元16和第二电容单元17是VBUS线路上的稳压电容，第一电容单元16和第二电容单元17的电容值之和小于6.5uF(微法)，即C1+C2<6.5uF。第五电阻单元14和第六电阻单元15是泄放电阻，在几十K欧姆范围。
当VBUS上出现意外的ms级别的大于Vovp1或Vovp2的直流高压时，此时第一OVP芯片111在几百ns的时间内会断开VBUS与后端浪涌保护单元12、第二OVP芯片131以及待保护单元的连接，可保护浪涌保护单元12不被长时间的直流高压损坏。
浪涌保护单元12用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响。
示例性的，当加载在浪涌保护单元12的电压或电流出现浪涌时，将各个单 元的电压、电流限制在自身所能承受的电压、电流范围内；或者，将强大的雷电流泄流入地，保护被保护的单元不受冲击而损坏。
在图1中，当加载在浪涌保护单元12的电压或电流出现浪涌时，上述的距离电源端VBUS比自身更远的单元包括第二过压保护单元13、待保护单元等。
可选的，浪涌保护单元12包括浪涌管，浪涌管可以为大功率TVS(Transient Voltage Suppressor，瞬变电压抑制二极管)管。
在出现正常的8/20us浪涌电压时，第一OVP芯片111和第二OVP芯片131是导通的，浪涌保护单元12把浪涌电压钳位在较低的电压上，保护后端的PMU芯片。
通过本实施例的实施，既可解决VBUS线路上的浪涌问题，也可解决VBUS线路上的直流高压问题，避免了现有方案导致的VBUS与GND短路的问题，降低了客退率，提升了用户体验。
实施例二
本实施例提供一种供电装置，请参见图2，图2为本实施例提供的一种供电装置的示意图，该供电装置包括实施例一中的保护装置20，还包括待保护单元21，待保护单元21包括电源管理单元，即图2中的PMU芯片。
该保护装置20包括：第一过压保护单元11、浪涌保护单元12和第二过压保护单元13；第一过压保护单元11、浪涌保护单元12、第二过压保护单元13以及待保护单元21按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；
第一过压保护单元11、第二过压保护单元13分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；
示例性的，当加载在第一过压保护单元11或第二过压保护单元13的直流电压等于或大于对应阈值时，将各个单元的电压限制在各自所能承受的电压范围内，让各个单元继续工作；或者，将电源端VBUS和地端之间短路，后面的单元停止工作，保护被保护的单元不受冲击而损坏。
在图2中，当加载在第一过压保护单元11的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括浪涌保护单元12、第二过 压保护单元13、待保护单元21(图2中的PMU芯片)等。
在图2中，当加载在第二过压保护单元13的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括待保护单元21等。
其中，第一过压保护单元11对应的阈值与第二过压保护单元13对应的阈值相等，或者第一过压保护单元11对应的阈值大于第二过压保护单元13对应的阈值。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者包括OVP芯片。即第一过压保护单元11包括OVP芯片，或者第二过压保护单元13包括OVP芯片，或者第一过压保护单元11和第二过压保护单元13都包括OVP芯片。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者还包括：两个电阻单元，其中一个电阻单元与OVP芯片并联，并联后的电路再与另一个电阻单元串联。
在一种实施方式中，第一过压保护单元11包括：第一OVP芯片(U1)111、第一电阻单元(R1)112和第二电阻单元(R2)113，第一电阻单元112与第一OVP芯片111并联，并联后的电路再与第二电阻单元113串联；
第二过压保护单元13包括：第二OVP芯片(U2)131、第三电阻单元(R3)132和第四电阻单元(R4)133，第三电阻单元132与第二OVP芯片131并联，并联后的电路再与第四电阻单元133串联；
第一OVP芯片111与第二OVP芯片131的保护电压相同。
第一电阻单元112、第二电阻单元113设置了第一OVP芯片111的OVP防护电压Vovp1＝Vref*R2/(R1+R2)，Vref为基准电压。第三电阻单元132、第四电阻单元133设置了第二OVP芯片131的OVP防护电压Vovp2＝Vref*R4/(R3+R4)；本方案中设置Vovp1＝Vovp2。
在一种实施方式中，还包括：第五电阻单元(R5)14、第六电阻单元(R6)15、第一电容单元(C1)16和/或第二电容单元(C2)17，各个单元分别按照以下顺序依次并联在电源端VBUS和地端之间：第一电容单元16、第五电阻单元15、第一过压保护单元11、浪涌保护单元(D1)12、第二过压保护单元13、第六电阻单元15、第二电容单元17、待保护单元21。
第一电容单元16和第二电容单元17是VBUS线路上的稳压电容，第一电 容单元16和第二电容单元17的电容值之和小于6.5uF(微法)，即C1+C2<6.5uF。第五电阻单元14和第六电阻单元15是泄放电阻，在几十K欧姆范围。
当VBUS上出现意外的ms级别的大于Vovp1或Vovp2的直流高压时，此时第一OVP芯片111在几百ns的时间内会断开VBUS与后端浪涌保护单元12、第二OVP芯片131以及待保护单元21的连接，可保护浪涌保护单元12不被长时间的直流高压损坏。
浪涌保护单元12用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响。
示例性的，当加载在浪涌保护单元12的电压或电流出现浪涌时，将各个单元的电压、电流限制在自身所能承受的电压、电流范围内；或者，将强大的雷电流泄流入地，保护被保护的单元不受冲击而损坏。
在图2中，当加载在浪涌保护单元12的电压或电流出现浪涌时，上述的距离电源端VBUS比自身更远的单元包括第二过压保护单元13、待保护单元21等。
可选的，浪涌保护单元12包括浪涌管，浪涌管可以为大功率TVS管。
在出现正常的8/20us浪涌电压时，第一OVP芯片111和第二OVP芯片131是导通的，浪涌保护单元12把浪涌电压钳位在较低的电压上，保护后端的PMU芯片。
通过本实施例的实施，既可解决VBUS线路上的浪涌问题，也可解决VBUS线路上的直流高压问题，避免了现有方案导致的VBUS与GND短路的问题，降低了客退率，提升了用户体验。
实施例三
本实施例提供一种终端，参见图3，图3为本实施例提供的一种终端的示意图，该终端包括终端本体31以及实施例二中的供电装置32。
该供电装置32包括实施例一中的保护装置20，还包括待保护单元21，待保护单元21包括电源管理单元，即图2中的PMU芯片。
该保护装置20包括：第一过压保护单元11、浪涌保护单元12和第二过压保护单元13；第一过压保护单元11、浪涌保护单元12、第二过压保护单元13 以及待保护单元21按照距离电源端VBUS由近到远的顺序依次并联在电源端VBUS和地端之间；
第一过压保护单元11、第二过压保护单元13分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受直流电压的影响；
示例性的，当加载在第一过压保护单元11或第二过压保护单元13的直流电压等于或大于对应阈值时，将各个单元的电压限制在各自所能承受的电压范围内，让各个单元继续工作；或者，将电源端VBUS和地端之间短路，后面的单元停止工作，保护被保护的单元不受冲击而损坏。
在图2中，当加载在第一过压保护单元11的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括浪涌保护单元12、第二过压保护单元13、待保护单元21(图2中的PMU芯片)等。
在图2中，当加载在第二过压保护单元13的直流电压等于或大于对应阈值时，上述的距离电源端VBUS比自身更远的单元包括待保护单元21等。
其中，第一过压保护单元11对应的阈值与第二过压保护单元13对应的阈值相等，或者第一过压保护单元11对应的阈值大于第二过压保护单元13对应的阈值。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者包括OVP芯片。即第一过压保护单元11包括OVP芯片，或者第二过压保护单元13包括OVP芯片，或者第一过压保护单元11和第二过压保护单元13都包括OVP芯片。
其中，第一过压保护单元11和第二过压保护单元13中的至少一者还包括：两个电阻单元，其中一个电阻单元与OVP芯片并联，并联后的电路再与另一个电阻单元串联。
在一种实施方式中，第一过压保护单元11包括：第一OVP芯片(U1)111、第一电阻单元(R1)112和第二电阻单元(R2)113，第一电阻单元112与第一OVP芯片111并联，并联后的电路再与第二电阻单元113串联；
第二过压保护单元13包括：第二OVP芯片(U2)131、第三电阻单元(R3)132和第四电阻单元(R4)133，第三电阻单元132与第二OVP芯片131并联，并联后的电路再与第四电阻单元133串联；
第一OVP芯片111与第二OVP芯片131的保护电压相同。
第一电阻单元112、第二电阻单元113设置了第一OVP芯片111的OVP防护电压Vovp1＝Vref*R2/(R1+R2)，Vref为基准电压。第三电阻单元132、第四电阻单元133设置了第二OVP芯片131的OVP防护电压Vovp2＝Vref*R4/(R3+R4)；本方案中设置Vovp1＝Vovp2。
在一种实施方式中，还包括：第五电阻单元(R5)14、第六电阻单元(R6)15、第一电容单元(C1)16和/或第二电容单元(C2)17，各个单元分别按照以下顺序依次并联在电源端VBUS和地端之间：第一电容单元16、第五电阻单元15、第一过压保护单元11、浪涌保护单元(D1)12、第二过压保护单元13、第六电阻单元15、第二电容单元17、待保护单元21。
第一电容单元16和第二电容单元17是VBUS线路上的稳压电容，第一电容单元16和第二电容单元17的电容值之和小于6.5uF(微法)，即C1+C2<6.5uF。第五电阻单元14和第六电阻单元15是泄放电阻，在几十K欧姆范围。
当VBUS上出现意外的ms级别的大于Vovp1或Vovp2的直流高压时，此时第一OVP芯片111在几百ns的时间内会断开VBUS与后端浪涌保护单元12、第二OVP芯片131以及待保护单元21的连接，可保护浪涌保护单元12不被长时间的直流高压损坏。
浪涌保护单元12用于加载在自身的电压或电流出现浪涌时，保护并联在电源端VBUS和地端之间且距离电源端VBUS比自身更远的单元免受浪涌的影响。
示例性的，当加载在浪涌保护单元12的电压或电流出现浪涌时，将各个单元的电压、电流限制在自身所能承受的电压、电流范围内；或者，将强大的雷电流泄流入地，保护被保护的单元不受冲击而损坏。
在图2中，当加载在浪涌保护单元12的电压或电流出现浪涌时，上述的距离电源端VBUS比自身更远的单元包括第二过压保护单元13、待保护单元21等。
可选的，浪涌保护单元12包括浪涌管，浪涌管可以为大功率TVS管。
在出现正常的8/20us浪涌电压时，第一OVP芯片111和第二OVP芯片131是导通的，浪涌保护单元12把浪涌电压钳位在较低的电压上，保护后端的PMU芯片。
通过本实施例的实施，既可解决VBUS线路上的浪涌问题，也可解决VBUS线路上的直流高压问题，避免了现有方案导致的VBUS与GND短路的问题，降低了客退率，提升了用户体验。
显然，本领域的技术人员应该明白，上述本发明实施例的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储介质(ROM/RAM、磁碟、光盘)中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。所以，本发明不限制于任何特定的硬件和软件结合。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种保护装置，其特征在于，包括第一过压保护单元、浪涌保护单元和第二过压保护单元，所述第一过压保护单元、浪涌保护单元、第二过压保护单元以及待保护单元按照距离电源端VBUS由近到远的顺序依次并联在所述电源端VBUS和地端之间；
    所述第一过压保护单元、第二过压保护单元分别用于加载在自身的直流电压等于或大于对应阈值时，保护并联在所述电源端VBUS和所述地端之间且距离所述电源端VBUS比自身更远的单元免受所述直流电压的影响；
    所述浪涌保护单元用于加载在自身的电压或电流出现浪涌时，保护并联在所述电源端VBUS和所述地端之间且距离所述电源端VBUS比自身更远的单元免受浪涌的影响。
  2. 如权利要求1所述的保护装置，其特征在于，所述第一过压保护单元对应的阈值与所述第二过压保护单元对应的阈值相等，或者所述第一过压保护单元对应的阈值大于所述第二过压保护单元对应的阈值。
  3. 如权利要求1或2所述的保护装置，其特征在于，所述第一过压保护单元和所述第二过压保护单元中的至少一者包括OVP芯片。
  4. 如权利要求3所述的保护装置，其特征在于，所述第一过压保护单元和所述第二过压保护单元中的所述至少一者还包括：两个电阻单元，其中一个电阻单元与所述OVP芯片并联，并联后的电路再与另一个电阻单元串联。
  5. 如权利要求4所述的保护装置，其特征在于，所述第一过压保护单元包括：第一OVP芯片、第一电阻单元和第二电阻单元，所述第一电阻单元与所述第一OVP芯片并联，并联后的电路再与所述第二电阻单元串联；所述第二过压保护单元包括：第二OVP芯片、第三电阻单元和第四电阻单元，所述第三电阻单元与所述第二OVP芯片并联，并联后的电路再与所述第四电阻单元串联；所述第一OVP芯片与所述第二OVP芯片的保护电压相同。
  6. 如权利要求1至5任一项所述的保护装置，其特征在于，还包括：第五电阻单元、第六电阻单元、第一电容单元和/或第二电容单元，分别按照以下顺序依次并联在所述电源端VBUS和地端之间：所述第一电容单元、所述第五电阻单元、所述第一过压保护单元、所述浪涌保护单元、所述第二过压保护单元、所述第六电阻单元、所述第二电容单元、所述待保护单元。
  7. 如权利要求6所述的保护装置，其特征在于，所述第一电容单元和第二电容单元的电容值之和小于6.5微法。
  8. 如权利要求1至7任一项所述的保护装置，其特征在于，所述浪涌保护单元包括浪涌管。
  9. 一种供电装置，其特征在于，包括如权利要求1至8任一项所述的保护装置，还包括待保护单元，所述待保护单元包括电源管理单元。
  10. 一种终端，包括终端本体以及如权利要求9所述的供电装置。
PCT/CN2017/072571 2016-12-16 2017-01-25 一种保护装置、供电装置及终端 WO2018107568A1 (zh)

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