WO2021128715A1 - 一种均衡驱动电路以及电子设备 - Google Patents

一种均衡驱动电路以及电子设备 Download PDF

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Publication number
WO2021128715A1
WO2021128715A1 PCT/CN2020/091104 CN2020091104W WO2021128715A1 WO 2021128715 A1 WO2021128715 A1 WO 2021128715A1 CN 2020091104 W CN2020091104 W CN 2020091104W WO 2021128715 A1 WO2021128715 A1 WO 2021128715A1
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Prior art keywords
electrically connected
drive circuit
equalization
subunit
processor
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PCT/CN2020/091104
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English (en)
French (fr)
Inventor
姚斌
施璐
李番军
曹笑吟
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上海派能能源科技股份有限公司
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Priority claimed from CN201911363505.3A external-priority patent/CN110932363A/zh
Priority claimed from CN201922375750.8U external-priority patent/CN211456725U/zh
Application filed by 上海派能能源科技股份有限公司 filed Critical 上海派能能源科技股份有限公司
Publication of WO2021128715A1 publication Critical patent/WO2021128715A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

Definitions

  • the embodiments of the present invention relate to the field of circuit technology, and in particular to an equalizing drive circuit and electronic equipment.
  • lithium batteries With the advancement of science and technology, the application of lithium batteries in equipment in various industries has become more and more widespread. In applications where 6 or less lithium batteries are connected in series for applications such as power tools, the Internet of Things, and drones, it is necessary to balance a single battery to extend its service life.
  • a non-isolated power supply scheme that is, the ground terminal of the micro control unit (MCU) and the negative electrode of the first battery are shared; however, due to non-isolation Isolation and common ground cause the MCU to drive the passive equalization MOS tube of the battery.
  • the MCU cannot directly turn on the equalization MOS tube of Section 2-Section 6. It can only be controlled by the isolation optocoupler method. However, the isolation optocoupler method will turn on the second The circuit of section 1 to section 6 cannot achieve the balance of the circuit of section 2 to section 6, and the circuit is cumbersome, high in cost, and low in reliability.
  • the embodiment of the present invention provides a balanced driving circuit and electronic equipment, which reduces the process fault tolerance and ensures the operating characteristics of the device.
  • an equalization driving circuit including:
  • Each equalization drive circuit unit includes a capacitor, an equalization circuit subunit, and a drive circuit subunit; the first end of each capacitor is electrically connected to an output end of the processor, and the second end of each capacitor is electrically connected to an output end of the processor. Terminal is electrically connected to the corresponding control terminal of the equalizing circuit subunit;
  • each of the capacitors is electrically connected to the input sub-terminal of the corresponding driving circuit sub-unit, and the output sub-terminal of the first driving circuit sub-unit is electrically connected to the ground terminal of the processor. Closed loop; the output sub-terminal of the Nth drive circuit subunit is electrically connected with the previous balanced drive circuit unit to be indirectly electrically connected with the ground terminal of the processor to form a closed loop.
  • each of the equalizing circuit subunits includes:
  • each of the capacitors is electrically connected to the corresponding control end of the switch tube, the first end of the switch tube is electrically connected to the positive electrode of the battery, and the second end of the switch tube is electrically connected to the control terminal of the switch tube.
  • the negative pole of the battery is electrically connected, and the negative pole of the battery of the first equalizing circuit subunit is electrically connected to the ground terminal of the processor; the negative pole of the battery of the Nth equalizing circuit subunit is electrically connected to the previous equalizing circuit subunit.
  • the positive electrode of the battery of the unit is electrically connected.
  • each of the equalizing circuit subunits further includes a first resistor, the first end of the first resistor is electrically connected to the positive electrode of the battery corresponding to it, and the second end of the first resistor is connected to the positive electrode of the battery. The first end of the corresponding switch tube is electrically connected.
  • the switch tube is an N-type field effect tube.
  • each of the driving circuit subunits includes a second resistor, the first end of the second resistor is electrically connected to the second end of the corresponding capacitor, and the second end of the second resistor is electrically connected to the second end of the capacitor.
  • the corresponding second end of the switch tube and the corresponding negative electrode of the battery are electrically connected.
  • the second end of the second resistor of the Nth drive circuit subunit is also connected to the positive electrode of the battery of the previous equalization circuit subunit and the first resistor of the previous equalization circuit subunit. Terminals are electrically connected.
  • the signal output by the processor output terminal is a PWM square wave.
  • an embodiment of the present invention provides an electronic device, including the equalizing drive circuit described in any one of the embodiments in the first aspect.
  • the embodiments of the present invention provide an equalization drive circuit and electronic equipment, wherein the equalization drive circuit includes a processor and a plurality of equalization drive circuit units; each equalization drive circuit unit includes a capacitor, an equalization circuit subunit, and a drive circuit subunit; each The first end of each capacitor is electrically connected to an output end of the processor, the second end of each capacitor is electrically connected to the control end of the corresponding equalization circuit subunit; the second end of each capacitor is electrically connected to the corresponding drive circuit
  • the input sub-terminal of the sub-unit is electrically connected, and the output sub-terminal of the first driving circuit sub-unit is electrically connected to the ground terminal of the processor to form a closed loop; the output sub-terminal of the N-th driving circuit sub-unit is electrically connected to the previous balanced driving circuit unit.
  • the connection is indirectly electrically connected with the ground terminal of the processor to form a closed loop.
  • the balance driving circuit is simplified, the balance of all batteries is realized, the cost is reduced, and the reliability is improved
  • FIG. 1 is a schematic diagram of a balanced driving circuit provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of another balanced driving circuit provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another balanced driving circuit provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another balanced driving circuit provided by an embodiment of the present invention.
  • Fig. 5 is a waveform diagram of a different position provided by an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an equalization drive circuit provided by an embodiment of the present invention.
  • the equalization drive circuit includes:
  • Each equalization drive circuit unit includes a capacitor C, an equalization circuit subunit 21, and a drive circuit subunit 22; the first end of each capacitor C is electrically connected to an output end of the processor, and the second end of each capacitor corresponds to it.
  • the control terminal of the equalizing circuit subunit 21 is electrically connected;
  • each capacitor C is electrically connected to the input sub-terminal of the corresponding driving circuit sub-unit 22, and the output sub-terminal of the first driving circuit sub-unit 20 is electrically connected to the ground terminal B of the processor to form a closed loop;
  • the output sub-terminals of the N drive circuit sub-units 20 are electrically connected to the previous equalization drive circuit unit 20 so as to be indirectly electrically connected with the ground terminal of the processor 10 to form a closed loop.
  • the equalization drive circuit includes: a processor 10, a plurality of equalization drive circuit units 20; the processor 10 is electrically connected to a plurality of equalization drive circuit units 20, and the signal output by the processor 10 controls the conduction of the plurality of equalization drive circuit units 20.
  • each balanced driving circuit unit 20 includes a capacitor C, an equalizing circuit subunit 21, and a driving circuit subunit 22;
  • the first end is electrically connected to an output end of the processor 10, for example, the capacitor C of the first equalization drive circuit unit 20 is electrically connected to the first output end A1 of the processor, and the capacitor of the second equalization drive circuit unit 20 C is electrically connected to the second output terminal A2 of the processor, and the capacitor C of the Nth equalizing drive circuit unit 20 is electrically connected to the Nth output terminal AN of the processor.
  • each capacitor C is electrically connected to the control end of the corresponding equalization circuit subunit 21, the processor 10 outputs a signal through the output end, and the signal is transmitted to the control end of the equalization circuit subunit 21 after passing through the capacitor C.
  • the equalizing circuit sub-unit 21 can be switched on and off; the second end of each capacitor C is electrically connected to the input sub-terminal of the corresponding driving circuit sub-unit 22, and the output sub-terminal of the first driving circuit sub-unit 22 is connected to the processing
  • the ground terminal B of the processor 10 is electrically connected to form a closed loop; the output terminal of the Nth drive circuit subunit 22 is electrically connected to the previous balanced drive circuit unit 20 so as to be indirectly electrically connected to the ground terminal B of the processor 10 to form a closed loop.
  • All drive circuit sub-units are turned on.
  • the use of the capacitor C can delay the signal transmission to the driving circuit sub-unit 22 and the equalizing circuit sub-unit 21, thereby controlling the timing of each equalizing circuit sub-unit 21 being turned on, realizing the effect of equalizing all the equalizing circuit sub-units 21 at the same time, simplifying In order to balance the driving circuit, the cost is reduced and the reliability is improved.
  • the embodiment of the present invention provides an equalization drive circuit, including: a processor 10, a plurality of equalization drive circuit units 20; each equalization drive circuit unit includes a capacitor C, an equalization circuit subunit 21, and a drive circuit subunit 21; each The first end of the capacitor C is electrically connected to an output end of the processor 10, the second end of each capacitor C is electrically connected to the control end of the corresponding equalizing circuit subunit 21; the second end of each capacitor C is electrically connected to the The input sub-terminal of the corresponding drive circuit sub-unit 22 is electrically connected, the output sub-terminal of the first drive circuit sub-unit 22 is electrically connected to the ground terminal B of the processor 10 to form a closed loop; the N-th drive circuit sub-unit 22 outputs the sub-terminal The terminal is electrically connected with the previous equalization drive circuit unit 20 to be indirectly electrically connected with the ground terminal B of the processor 10 to form a closed loop.
  • the embodiment of the present invention can delay the signal transmission to the driving circuit subunit 22 and the equalizing circuit subunit 21, thereby controlling the timing when each equalizing driving circuit unit 20 is turned on, and realizes the effect of equalizing all the equalizing circuit subunits 21 at the same time, which simplifies The drive circuit is balanced, cost is reduced, and reliability is improved.
  • FIG. 2 is a schematic diagram of another equalization driving circuit provided by an embodiment of the present invention.
  • each of the equalization circuit subunits includes:
  • each capacitor C is electrically connected to the control end of the corresponding switch tube Q, the first end of the switch tube Q is electrically connected to the positive electrode of the battery U, and the second end of the switch tube Q is electrically connected to the negative electrode of the battery U ,
  • the negative electrode of battery U of the first equalizing circuit subunit 21 is electrically connected to the ground terminal B of the processor 10; the negative electrode of battery U of the Nth equalizing circuit subunit 21 is connected to the positive electrode of battery U of the previous equalizing circuit subunit 21 Electric connection.
  • each capacitor C is electrically connected to the control end of the corresponding switch Q, that is, the control end of the switch Q is the control end of the equalization circuit subunit 21, and the switch Q is based on the output of the processor 10
  • the signal switches its own on state and off state, thereby realizing the on and off of the equalizing circuit subunit 21; the first end of the switch tube Q is electrically connected to the positive electrode of the battery U, and the second end of the switch tube Q is connected to The negative electrode of the battery U is electrically connected.
  • the switch Q is turned on, the circuit of the equalizing circuit subunit 21 is turned on to form a return flow.
  • FIG. 3 is a schematic diagram of another equalization drive circuit provided by an embodiment of the present invention.
  • each equalization circuit subunit 21 further includes a first resistor R1, and a first end of the first resistor R1 corresponds to it.
  • the positive electrode of the battery U is electrically connected, and the second end of the first resistor R1 is electrically connected to the first end of the switch tube Q corresponding to it.
  • each equalization circuit subunit 21 further includes a first resistor R1, the first end of the first resistor R1 is electrically connected to the positive electrode of the battery U, and the second end of the first resistor R1 is connected to the corresponding switch tube.
  • the first end of Q is electrically connected. If the switching tube Q is turned on, the first resistor R1 is connected in parallel to both ends of the battery U; for example, when the voltage of the battery U is too high, the processor 10 outputs a signal to turn on the switching tube Q The switch tube Q is turned on, and the current is shunted through the set first resistor R1, so that the charging current of the battery U with a high voltage is small, and the voltage balance of the battery U is realized.
  • the switching tube Q is an N-type field effect tube.
  • the switching tube Q is an N-type field effect tube.
  • the gate of the N-type field effect tube receives a high level, the source and drain of the N-type field effect tube are turned on to realize the conduction of the equalizing circuit subunit 21. To balance the battery voltage.
  • FIG. 4 is a schematic diagram of another balanced driving circuit provided by an embodiment of the present invention.
  • each driving circuit subunit 22 includes a second resistor R2, and the first end of the second resistor R2 corresponds to the first end of the second resistor R2.
  • the second end of the capacitor C is electrically connected, and the second end of the second resistor R2 is electrically connected to the second end of the switch tube Q corresponding to it and the negative electrode of the battery U corresponding to it.
  • each driving circuit subunit 22 includes a second resistor R2, the first end of the second resistor R2 is electrically connected to the second end of the corresponding capacitor C, and the second end of the second resistor R2 is connected to the corresponding switch.
  • the second end of the tube Q and the negative electrode of the battery U corresponding to it are electrically connected; the setting of the second resistor R2 can realize the effective power-off of the switch tube Q.
  • the output terminal of the processor 10 suddenly stops responding to the N-type field
  • the gate of the effect tube outputs a high level, and there is a certain residual voltage between the gate and drain of the N-type field effect tube, and the N-type field effect tube cannot be normally disconnected in time.
  • the second resistor R2 the N-type field effect tube is consumed. There is a certain residual voltage between the gate and drain of the field effect tube, which in turn realizes the effective power-off of the N-type field effect tube.
  • the negative electrode of the battery U in the first driving circuit subunit 22 is electrically connected to the ground terminal of the processor 10, that is, the second terminal of the second resistor R2 in the first driving circuit subunit 22 is connected to the ground terminal of the processor 10. Electric connection.
  • the second end of the second resistor R2 of the Nth drive circuit subunit 22 is also connected to the positive electrode of the battery U of the previous equalization circuit subunit 21 and the first resistor of the previous equalization circuit subunit 21.
  • the first end of R1 is electrically connected.
  • the second end of the second resistor R2 of the Nth driving circuit subunit 22 is also connected to the positive electrode of the battery U of the previous equalizing circuit subunit 21 and the first end of the first resistor R1 of the last equalizing circuit subunit 21 Electrically connected; the second end of the second resistor R2 of the Nth drive circuit subunit 21 is electrically connected to the positive electrode of the battery U of the previous equalization circuit subunit 21, that is, the second resistor R2 of the Nth drive circuit subunit 22
  • the second end passes through the battery U of the N-1th equalizing circuit subunit 21 to the negative pole of the first equalizing circuit subunit battery U, and then passes through the negative pole of the first equalizing circuit subunit 21 of the battery U and the processor 10
  • the ground terminal B is electrically connected to realize the conduction of the N th drive circuit subunit 22.
  • the signal output by the processor output is a PWM square wave.
  • FIG. 5 is a waveform diagram of a different position provided by an embodiment of the present invention.
  • the PWM square wave signal is delayed when it is transmitted to the capacitor C and passes through different positions.
  • the waveform diagrams of are inconsistent, the PWM square wave transmitted to the second resistor R2 is later than the output PWM square wave at the output of the processor 10, and the PWM square wave transmitted to the first resistor R1 is later than the PWM square wave of the second resistor R2.
  • the equalizing circuit subunit 21 is turned on, thereby realizing the equalizing effect of the equalizing circuit subunit 21 on the battery U.
  • An embodiment of the present invention also provides an electronic device, which includes the equalization drive circuit described in any of the foregoing embodiments, and has the same technical effect as the foregoing embodiment, and will not be repeated here.

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  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

一种均衡驱动电路以及电子设备，其中均衡驱动电路包括处理器（10）、多数个均衡驱动电路单元（20）；每个均衡驱动电路单元（20）包括电容（C）、均衡电路子单元（21）和驱动电路子单元（22）；每个电容（C）的第一端与处理器（10）的一个输出端电连接，每个电容（C）的第二端与与其对应的均衡电路子单元（21）的控制端电连接；每个电容（C）的第二端与与其对应的驱动电路子单元（22）的输入子端电连接，第一个驱动电路子单元（22）的输出子端与处理器（10）的接地端（B）电连接形成闭合回路；第N个驱动电路子单元（22）输出子端与上一个均衡驱动电路单元（20）电连接以间接与处理器（10）的接地端（B）电连接形成闭合回路。上述电路结构简化了均衡驱动电路，实现了对所有电池的均衡，降低成本，提高了可靠性。

Description

一种均衡驱动电路以及电子设备 技术领域
本发明实施例涉及电路技术领域，尤其涉及一种均衡驱动电路以及电子设备。
背景技术
随着科学技术的进步，各个行业设备应用锂电池越来越广泛，电动工具、物联网、无人机等应用6节及以下锂电池串联场合，需要对单节电池进行均衡延长使用寿命。
6节及以下锂电池串联应用中，为降低产品功耗与成本，均采用非隔离供电方案，即微控制单元(Micro Control Unit，MCU)接地端与第1节电池负极共地；但是由于非隔离共地导致MCU驱动电池被动均衡MOS管，MCU无法直接导通第2节-第6节的均衡MOS管，只能采用隔离光耦方式进行控制，然而采用隔离光耦方式会同时导通第1节-第6节的电路，不能实现第2节-第6节电路的均衡，而且电路繁琐，成本较高，可靠性低。
发明内容
本发明实施例提供了一种均衡驱动电路以及电子设备，降低工艺容错度，保证器件工作特性。
第一方面，本发明实施例提供了一种均衡驱动电路，包括：
处理器、多数个均衡驱动电路单元；
每个所述均衡驱动电路单元包括电容、均衡电路子单元和驱动电路子单元；每个所述电容的第一端与所述处理器的一个输出端电连接，每个所述电容的第二端与与其对应的所述均衡电路子单元的控制端电连接；
每个所述电容的第二端与与其对应的所述驱动电路子单元的输入子端电连接，第一个所述驱动电路子单元的输出子端与所述处理器的接地端电连接形成闭合回路；第N个所述驱动电路子单元输出子端与上一个均衡驱动电路单元电连接以间接与所述处理器的接地端电连接形成闭合回路。
可选的，每个所述均衡电路子单元包括：
开关管和电池；
每个所述电容的第二端与与其对应的所述开关管的控制端电连接，所述开关管的第一端与所述电池的正极电连接，所述开关管的第二端与所述电池的负极电连接，第一个所述均衡电路子单元的电池负极与所述处理器的接地端电连接；第N个所述均衡电路子单元的电池负极与上一个所述均衡电路子单元的电池正极电连接。
可选的，每个所述均衡电路子单元还包括第一电阻，所述第一电阻的第一端与与其对应的所述电池的正极电连接，所述第一电阻的第二端与与其对应的所述开关管的第一端电连接。
可选的，所述开关管为N型场效应管。
可选的，每个所述驱动电路子单元包括第二电阻，所述第二电阻的第一端与与其对应的所述电容的第二端电连接，所述第二电阻的第二端与与其对应的所述开关管的第二端以及与其对应的所述电池的负极电连接。
可选的，第N个所述驱动电路子单元的第二电阻的第二端还与上一个所述 均衡电路子单元的电池正极以及上一个所述均衡电路子单元的第一电阻的第一端电连接。
可选的，所述处理器输出端输出的信号为PWM方波。
第二方面，本发明实施例提供了一种电子设备，包括第一方面任一实施例所述的均衡驱动电路。
本发明实施例提供了一种均衡驱动电路以及电子设备，其中均衡驱动电路包括处理器、多数个均衡驱动电路单元；每个均衡驱动电路单元包括电容、均衡电路子单元和驱动电路子单元；每个电容的第一端与处理器的一个输出端电连接，每个电容的第二端与与其对应的均衡电路子单元的控制端电连接；每个电容的第二端与与其对应的驱动电路子单元的输入子端电连接，第一个驱动电路子单元的输出子端与处理器的接地端电连接形成闭合回路；第N个驱动电路子单元输出子端与上一个均衡驱动电路单元电连接以间接与处理器的接地端电连接形成闭合回路。简化了均衡驱动电路，实现了对所有电池的均衡，降低成本，提高了可靠性。
附图说明
图1是本发明实施例提供的一种均衡驱动电路示意图；
图2是本发明实施例提供的另一种均衡驱动电路示意图；
图3是本发明实施例提供的另一种均衡驱动电路示意图；
图4是本发明实施例提供的另一种均衡驱动电路示意图；
图5是本发明实施例提供的一种不同位置的波形图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
本发明实施例提供了一种均衡驱动电路，图1是本发明实施例提供的一种均衡驱动电路示意图，参考图1，均衡驱动电路包括：
处理器10、多数个均衡驱动电路单元20；
每个均衡驱动电路单元包括电容C、均衡电路子单元21和驱动电路子单元22；每个电容C的第一端与处理器的一个输出端电连接，每个电容的第二端与与其对应的均衡电路子单元21的控制端电连接；
每个电容C的第二端与与其对应的驱动电路子单元22的输入子端电连接，第一个驱动电路子单元20的输出子端与处理器的接地端B电连接形成闭合回路；第N个驱动电路子单元20输出子端与上一个均衡驱动电路单元20电连接以间接与处理器10的接地端电连接形成闭合回路。
具体的，均衡驱动电路包括：处理器10、多数个均衡驱动电路单元20；处理器10与多数个均衡驱动电路单元20电连接，处理器10输出的信号控制多数个均衡驱动电路单元20的导通和断开，导通时可以实现均衡驱动电路单元20电路的均衡性；其中，每个均衡驱动电路单元20包括电容C、均衡电路子单元21和驱动电路子单元22；每个电容C的第一端与处理器10的一个输出端电连接，例如，第一个均衡驱动电路单元20的电容C与处理器的第一个输出端A1 电连接，第二个均衡驱动电路单元20的电容C与处理器的第二个输出端A2电连接，第N个均衡驱动电路单元20的电容C与处理器的第N个输出端AN电连接。每个电容C的第二端与与其对应的均衡电路子单元21的控制端电连接，处理器10通过输出端输出信号，信号通过电容C后传输到均衡电路子单元21的控制端，根据信号可以切换均衡电路子单元21的开闭；每个电容C的第二端与与其对应的驱动电路子单元22的输入子端电连接，其中第一个驱动电路子单元22的输出子端与处理器10的接地端B电连接形成闭合回路；第N个驱动电路子单元22输出子端与上一个均衡驱动电路单元20电连接以间接与处理器10的接地端B电连接形成闭合回路，实现所有驱动电路子单元的导通。电容C的使用，可以延迟信号传输到驱动电路子单元22和均衡电路子单元21，进而控制每个均衡电路子单元21导通的时机，实现了所有均衡电路子单元21同时均衡的效果，简化了均衡驱动电路，降低成本，提高了可靠性。
本发明实施例提供了一种均衡驱动电路，包括：处理器10、多数个均衡驱动电路单元20；每个均衡驱动电路单元包括电容C、均衡电路子单元21和驱动电路子单元21；每个电容C的第一端与处理器10的一个输出端电连接，每个电容C的第二端与与其对应的均衡电路子单元21的控制端电连接；每个电容C的第二端与与其对应的驱动电路子单元22的输入子端电连接，第一个驱动电路子单元22的输出子端与处理器10的接地端B电连接形成闭合回路；第N个驱动电路子单元22输出子端与上一个均衡驱动电路单元20电连接以间接与处理器10的接地端B电连接形成闭合回路。本发明实施例可以延迟信号传输到驱动电路子单元22和均衡电路子单元21，进而控制每个均衡驱动电路单元20导通的时机，实现了所有均衡电路子单元21同时均衡的效果，简化了均衡驱动电路， 降低成本，提高了可靠性。
可选的，图2是本发明实施例提供的另一种均衡驱动电路示意图，参考图2，每个所述均衡电路子单元包括：
开关管Q和电池U；
每个电容C的第二端与与其对应的开关管Q的控制端电连接，开关管Q的第一端与电池U的正极电连接，开关管Q的第二端与电池U的负极电连接，第一个均衡电路子单元21的电池U负极与处理器10的接地端B电连接；第N个均衡电路子单元21的电池U负极与上一个所述均衡电路子单元21的电池U正极电连接。
具体的，每个电容C的第二端与与其对应的开关管Q的控制端电连接，即开关管Q的控制端为均衡电路子单元21的控制端，开关管Q根据处理器10输出的信号切换其本身的导通状态和断开状态，进而实现均衡电路子单元21的导通和断开；开关管Q的第一端与电池U的正极电连接，开关管Q的第二端与电池U的负极电连接，当开关管Q导通后，均衡电路子单元21的电路导通形成回流。
可选的，图3是本发明实施例提供的另一种均衡驱动电路示意图，参考图3，每个均衡电路子单元21还包括第一电阻R1，第一电阻R1的第一端与与其对应的电池U的正极电连接，第一电阻R1的第二端与与其对应的开关管Q的第一端电连接。
具体的，每个均衡电路子单元21还包括第一电阻R1，第一电阻R1的第一端与与其对应的电池U的正极电连接，第一电阻R1的第二端与与其对应的开关管Q的第一端电连接，若开关管Q导通，则第一电阻R1并联在电池U两端； 示例性地，当电池U电压过高时，处理器10输出导通开关管Q的信号导通开关管Q，电流通过设置的第一电阻R1进行分流，这样电压高的电池U充电电流小，实现电池U电压的均衡。
可选的，参考图3，开关管Q为N型场效应管。
具体的，开关管Q为N型场效应管，当N型场效应管的栅极接收到高电平时，N型场效应管的源极与漏极导通，实现均衡电路子单元21的导通，进而均衡电池电压。
可选的，图4是本发明实施例提供的另一种均衡驱动电路示意图，参考图4，每个驱动电路子单22包括第二电阻R2，第二电阻R2的第一端与与其对应的电容C的第二端电连接，第二电阻R2的第二端与与其对应的开关管Q的第二端以及与其对应的电池U的负极电连接。
具体的，每个驱动电路子单元22包括第二电阻R2，第二电阻R2的第一端与与其对应的电容C的第二端电连接，第二电阻R2的第二端与与其对应的开关管Q的第二端以及与其对应的电池U的负极电连接；第二电阻R2的设置可以实现开关管Q的有效断电，示例性地，若处理器10的输出端突然停止对N型场效应管的栅极输出高电平，N型场效应管的栅极和漏极之间具有一定残留电压，不能及时正常断开N型场效应管，通过设置第二电阻R2，消耗掉N型场效应管的栅极和漏极之间具有的一定残留电压，进而实现N型场效应管的有效断电。
其中，第一个驱动电路子单元22中电池U的负极与处理器10的接地端电连接，即第一个驱动电路子单元22中第二电阻R2的第二端与处理器10的接地端电连接。
可选的，参考图4，第N个驱动电路子单22的第二电阻R2的第二端还与上一个均衡电路子单元21的电池U正极以及上一个均衡电路子单元21的第一电阻R1的第一端电连接。
具体的，第N个驱动电路子单元22的第二电阻R2的第二端还与上一个均衡电路子单元21的电池U正极以及上一个均衡电路子单元21的第一电阻R1的第一端电连接；第N个驱动电路子单元21的第二电阻R2的第二端与上一个均衡电路子单元21的电池U正极电连接，即第N个驱动电路子单元22的第二电阻R2的第二端通过第N-1个均衡电路子单元21的电池U一直到第一个均衡电路子单元电池U的负极，再通过第一个均衡电路子单元21电池U的负极与处理器10的接地端B电连接，进而实现第N个驱动电路子单元22的导通。
可选的，处理器输出端输出的信号为PWM方波。
示例性地，图5是本发明实施例提供的一种不同位置的波形图，参考图5，处理器10输出端输出PWM方波后，传输到电容C时延迟PWM方波信号，通过不同位置的波形图不一致，传输到第二电阻R2的PWM方波迟于处理器10输出端输出PWM方波，传输到第一电阻R1的PWM方波迟于第二电阻R2的PWM方波。驱动电路子单元22导通后，均衡电路子单元21导通，进而实现均衡电路子单元21对电池U的均衡效果。
本发明实施例还提供了一种电子设备，包括上述任一实施例所述的均衡驱动电路，并与上述实施例具有相同的技术效果，这里不再赘述。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员 会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (8)

  1. 一种均衡驱动电路，其特征在于，包括：
    处理器、多数个均衡驱动电路单元；
    每个所述均衡驱动电路单元包括电容、均衡电路子单元和驱动电路子单元；每个所述电容的第一端与所述处理器的一个输出端电连接，每个所述电容的第二端与与其对应的所述均衡电路子单元的控制端电连接；
    每个所述电容的第二端与与其对应的所述驱动电路子单元的输入子端电连接，第一个所述驱动电路子单元的输出子端与所述处理器的接地端电连接形成闭合回路；第N个所述驱动电路子单元输出子端与上一个均衡驱动电路单元电连接以间接与所述处理器的接地端电连接形成闭合回路。
  2. 根据权利要求1所述的均衡驱动电路，其特征在于，每个所述均衡电路子单元包括：
    开关管和电池；
    每个所述电容的第二端与与其对应的所述开关管的控制端电连接，所述开关管的第一端与所述电池的正极电连接，所述开关管的第二端与所述电池的负极电连接，第一个所述均衡电路子单元的电池负极与所述处理器的接地端电连接；第N个所述均衡电路子单元的电池负极与上一个所述均衡电路子单元的电池正极电连接。
  3. 根据权利要求1所述的均衡驱动电路，其特征在于，每个所述均衡电路子单元还包括第一电阻，所述第一电阻的第一端与与其对应的所述电池的正极电连接，所述第一电阻的第二端与与其对应的所述开关管的第一端电连接。
  4. 根据权利要求3所述的均衡驱动电路，其特征在于，所述开关管为N型场效应管。
  5. 根据权利要求1或2所述的均衡驱动电路，其特征在于，每个所述驱动电路子单元包括第二电阻，所述第二电阻的第一端与与其对应的所述电容的第二端电连接，所述第二电阻的第二端与与其对应的所述开关管的第二端以及与其对应的所述电池的负极电连接。
  6. 根据权利要求3或5所述的均衡驱动电路，其特征在于，第N个所述驱动电路子单元的第二电阻的第二端还与上一个所述均衡电路子单元的电池正极以及上一个所述均衡电路子单元的第一电阻的第一端电连接。
  7. 根据权利要求1所述的均衡驱动电路，其特征在于，所述处理器输出端输出的信号为PWM方波。
  8. 一种电子设备，其特征在于，包括权利要求1-7任一所述的均衡驱动电路。
PCT/CN2020/091104 2019-12-26 2020-05-19 一种均衡驱动电路以及电子设备 WO2021128715A1 (zh)

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