WO2021128518A1 - 薄膜晶体管的图案制作方法、薄膜晶体管以及光罩 - Google Patents

薄膜晶体管的图案制作方法、薄膜晶体管以及光罩 Download PDF

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Publication number
WO2021128518A1
WO2021128518A1 PCT/CN2020/072361 CN2020072361W WO2021128518A1 WO 2021128518 A1 WO2021128518 A1 WO 2021128518A1 CN 2020072361 W CN2020072361 W CN 2020072361W WO 2021128518 A1 WO2021128518 A1 WO 2021128518A1
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Prior art keywords
sub
pixels
tft
pixel
light
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PCT/CN2020/072361
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English (en)
French (fr)
Inventor
钟舒婷
张宁
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Tcl华星光电技术有限公司
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Priority to US16/647,537 priority Critical patent/US11322528B2/en
Publication of WO2021128518A1 publication Critical patent/WO2021128518A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
    • G03F7/0007—Filters, e.g. additive colour filters; Components for display devices
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7096—Arrangement, mounting, housing, environment, cleaning or maintenance of apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor

Definitions

  • This application relates to the field of liquid crystal display technology, and in particular to a method for fabricating a pattern of a thin film transistor, a thin film transistor and a photomask.
  • the photomask is made of quartz glass as the substrate, on which a layer of metallic chromium and photosensitive glue is plated to become a photosensitive material.
  • the already made circuit pattern is exposed to the photosensitive glue through electronic laser equipment, and the exposed area will be It is developed to form a circuit pattern on the metal chromium, which becomes a photomask similar to the exposed film.
  • the production and processing procedures of the photomask are: exposure, development, photoresist removal, and finally applied to photoetching.
  • thin film transistors Thin film transistor, TFT
  • TFT thin film transistor liquid crystal display
  • TFT-LCD thin film transistor liquid crystal display
  • the TFT-LCD panel can be regarded as a layer of liquid crystal sandwiched between two glass substrates, the upper glass substrate is a color filter, and the lower glass has transistors embedded in the glass.
  • the upper glass is attached to the color filter to form sub-pixels each containing red, blue and green. These red, blue and green pixels form the video image on the panel.
  • a photomask is covered above the TFT.
  • the photomask is usually composed of a sub-mask covering at least two sets of pixel color blocks, and each group of pixel color blocks consists of red (R), The green (G) and blue (B) colors are combined by one column of sub-pixels, and the mask is composed of 3N adjacent different time point receiving exposure devices corresponding to three types of exposure, where N ⁇ 1, the
  • the method includes the following steps:
  • the TFT receives the first exposure of the exposure device through the first type of photomask.
  • the first type is that in the pixel color block, there is no light-shielding layer above the first column of sub-pixels, and both the second column of sub-pixels and the third column of sub-pixels are above. Have a light-shielding layer;
  • TFT is developed for the first time to form a first pattern
  • the TFT receiving spraying device coats the second photoresist on the first pattern
  • the TFT receives the second exposure of the exposure device through a second type of photomask.
  • the second type is that there is no light-shielding layer above the second column of sub-pixels, and there are light-shielding layers above the first column of sub-pixels and the second column of sub-pixels;
  • the TFT receiving spraying device coats the third photoresist on the second pattern
  • the TFT receives the third exposure of the exposure device through a third type of photomask.
  • the third type is that there is no light-shielding layer above the third column of sub-pixels, and there is a light-shielding layer above the first column of sub-pixels and the second column of sub-pixels;
  • FIG. 1 is a top view of the photomask
  • FIG. 1 is the photomask 100 covering two sets of pixel color blocks. It can be seen from Figure 1 that each group of pixel color blocks covering the mask is composed of a column of pixels of red (R), green (G), and blue (B).
  • the TFT structure in the array substrate shown in FIG. 2 can be obtained through the known photomask.
  • FIG. 2 is a cross-sectional view of the array substrate 200 corresponding to the pixel color blocks.
  • the cross-sectional view of the array substrate 200 includes a cross-sectional view of the TFT. Please refer to FIG. 2.
  • the left picture shows the array substrate corresponding to the R pixel
  • the middle picture shows the array substrate corresponding to the G pixel
  • the right picture shows the array substrate corresponding to the B pixel.
  • the array substrate 200 consists of the base substrate 201, the gate layer 202, the first insulating layer 203, the first semiconductor layer 204 (As layer), and the second semiconductor layer 205 indicated in the left figure of FIG. 2 from bottom to top.
  • the pixel layer 210 is electrically connected to the drain D in the TFT.
  • the corresponding levels in the middle and right pictures are the same as those in the left picture, and the details are not repeated here, but 208G in the middle picture is the G photoresist layer, and 208B in the right picture is the B photoresist layer.
  • the cross-sectional view of the TFT shown in FIG. 2 is the cross-sectional view of the TFT area under the R pixel in the left picture, the cross-sectional view of the TFT area under the G pixel in the middle picture, and the TFT under the B pixel in the right picture.
  • the cross-sectional view of the area there is a TFT area of the array substrate under each column of pixels.
  • FIG. 2 only shows the structure of the array substrate including the TFT structure corresponding to a group of pixel color blocks.
  • the lateral light from the lower glass substrate to the upper glass substrate will be reflected to the first semiconductor layer of the TFT-LCD array substrate, that is, the arsenic (AS) layer (as shown in Figure 1 ), resulting in the generation of photo-generated carriers, leading to an increase in the off-state current I off , resulting in a vertical crosstalk image when the TFT-LCD is lit, which affects the original electrical performance of the TFT.
  • AS arsenic
  • a TFT pattern manufacturing method provided by this application includes:
  • the TFT receiving spraying device coats the first photoresist
  • the TFT receives the first exposure of the exposure device through a first type of photomask covering the TFT, and the first type is that in the pixel color block, there is no light-shielding layer above the first column of sub-pixels , The second row of sub-pixels and the third row of sub-pixels are provided with the light-shielding layer, and the photomask is composed of three types corresponding to the exposure device at different time points adjacent to each other;
  • the TFT is developed for the first time to form a first pattern
  • the TFT receives the spraying device to coat the second photoresist on the first pattern
  • the TFT receives the second exposure of the exposure device through the second type of photomask.
  • the second type is that there is no light shielding layer above the second column of sub-pixels, and the first column of sub-pixels and the The light shielding layer is provided above the third row of sub-pixels;
  • the TFT is developed for a second time to form a second pattern
  • the TFT receives the spraying device to coat the third photoresist on the second pattern
  • the TFT receives the third exposure of the exposure device through the third type of photomask.
  • the third type is that there is no light shielding layer above the third column of sub-pixels, and the first column of sub-pixels and the The light shielding layer is provided above the second row of sub-pixels;
  • the TFT undergoes a third development to form a target pattern, wherein, in two of the three types of the photomask, on the light shielding layer of the two rows of the pixels, at least one row A hole is opened on the light shielding layer of the pixel, and the position of the hole corresponds to the position of the TFT.
  • An array substrate provided by the present application includes:
  • a photoresist layer covers the TFT, and the photoresist layer is composed of at least two photoresist layers of different colors;
  • a pixel layer covers the photoresist layer, and the pixel layer is electrically connected to the drain D of the TFT.
  • the embodiment of the present application provides a photomask, the photomask is composed of three types corresponding to the exposure of the adjacent receiving exposure devices at different time points, and the three types are respectively:
  • the first type is that when the thin film transistor TFT receives the first exposure of the exposure device through the first type of the photomask, there is no light-shielding layer above the first column of sub-pixels, and the second column of sub-pixels and The light shielding layer is provided above the third column of sub-pixels, and the first column of sub-pixels, the second column of sub-pixels, and the third column of sub-pixels form a set of pixel color blocks;
  • the second type is that when the TFT receives the second exposure of the exposure device through the second type of the photomask, there is no light shielding layer above the second column of sub-pixels, so The first row of sub-pixels and the third row of sub-pixels are provided with the light-shielding layer;
  • the third type is that when the TFT receives the third exposure of the exposure device through the third type of the mask, there is no light-shielding layer above the third column of sub-pixels, so The first column of sub-pixels and the second column of sub-pixels are provided with the light shielding layer, wherein, in two of the three types of the mask, in the two columns of the sub-pixels On the light-shielding layer, the light-shielding layer of at least one column of the sub-pixels is provided with holes, and the position of the holes corresponds to the position of the thin film transistor TFT, and the TFT is the TFT area on the thin film transistor display TFT-LCD substrate , The photomask is covered above the TFT.
  • This application changes the production of the photomask.
  • holes are provided on the light-shielding layer of at least one column of sub-pixels in the light-shielding layer of two columns of sub-pixels, so that each group of pixel color blocks corresponds to the TFT
  • two layers of different types of photoresist can be superimposed on the TFT under each sub-pixel, so that when the upper glass plate or plastic composite plate has reflected light reflected to the AS layer of the TFT, because The superposition of the two photoresists on the TFT can have a delustering effect on the reflected light, and the reflected light is almost completely offset, which cannot affect the electrical properties of the TFT, so the normal operation of the TFT can be guaranteed.
  • Figure 1 is a top view of the photomask corresponding to the pixel color block before the improvement
  • FIG. 2 is a cross-sectional view of the array substrate corresponding to the pixel color block before the improvement
  • FIG. 3 is a top view of the R/B mask corresponding to the pixel color block in an embodiment of the application
  • FIG. 5 is a schematic diagram of an embodiment of a TFT pattern manufacturing method based on an R/B mask in an embodiment of the application;
  • Fig. 6 is a top view of a G/B mask corresponding to a pixel color block in an embodiment of the application
  • FIG. 8 is a schematic diagram of an embodiment of a TFT pattern manufacturing method based on a G/B mask in an embodiment of the application;
  • FIG. 9 is a top view of the R/G mask corresponding to the pixel color block in an embodiment of the application.
  • FIG. 10 is a cross-sectional view of the array substrate corresponding to the R/G mask in an embodiment of the application;
  • FIG. 11 is a schematic diagram of an embodiment of a TFT pattern manufacturing method based on an R/G mask in an embodiment of the application;
  • FIG. 12 is a top view of the R/G/B mask corresponding to the pixel color block in an embodiment of the application.
  • FIG. 13 is a cross-sectional view of the array substrate corresponding to the R/G/B mask in the embodiment of the application;
  • FIG. 14 is a schematic diagram of an embodiment of a method for making patterns of TFTs based on R/G/B masks in an embodiment of the application;
  • FIG. 15 is a schematic diagram of an embodiment of an array substrate in an embodiment of the application.
  • the embodiments of the present application provide a TFT patterning method, an array substrate, and a photomask, which are used to pass light on the TFT through a hole corresponding to the position of the TFT on the photomask above the TFT, thereby generating more than two types on the TFT.
  • the photoresist is superimposed to offset the reflected light on the semiconductor AS layer and ensure the normal operation of the TFT.
  • the known photomask is located under many pixel color blocks.
  • Each group of pixel color blocks is composed of a column of sub-pixels of red, green, blue, etc., and a TFT area is provided under each sub-pixel. Therefore, how many For each pixel, you can know how many TFT areas there are on the TFT-LCD array substrate.
  • the TFT area can be arranged at different positions under each sub-pixel, but under each sub-pixel, the TFT area is usually arranged at a position corresponding to the upper right of each sub-pixel.
  • the photomask in the embodiment of the present application is composed of three types corresponding to the exposure of the adjacent receiving exposure devices at different time points, and the three types are:
  • the TFT when the TFT receives the first exposure of the exposure device through the first type of photomask, in each group of pixel color blocks, there is no light-shielding layer above the first column of sub-pixels, and the second column of sub-pixels and the third column of sub-pixels There are shading layers on top;
  • the TFT when the TFT receives the second exposure of the exposure device through the second type of photomask, there is no light-shielding layer above the second column of sub-pixels, and there is a light-shielding layer above the first column of sub-pixels and the third column of sub-pixels;
  • the TFT when the TFT receives the third exposure of the exposure device through the third type of photomask, there is no light-shielding layer above the third column of sub-pixels, and there is a light-shielding layer above the first column of sub-pixels and the second column of sub-pixels.
  • At least one column of the light-shielding layer of the sub-pixels is provided with a hole, and the position of the hole is the same as that of the TFT. The location corresponds.
  • FIG. 3 is a top view of the R/B mask 300 corresponding to the pixel color block in an embodiment of the application.
  • FIG. 3 only shows the mask 300 above the two sets of pixel color blocks.
  • the first type is the top diagram in FIG. 3. As can be seen from the top diagram, the light-shielding layer is on the sub-pixels G and B, and the sub-pixel B A hole is opened on the upper right of the light-shielding layer; the second type is the middle image in Figure 3, the light-shielding layer is on the sub-pixels R and B, and the light-shielding layers of the sub-pixels R and B have no holes; the third type is the one in Figure 3 In the figure below, the light-shielding layer is on the sub-pixels R and G, and the light-shielding layer of the sub-pixels R and G has holes on the upper right.
  • FIG. 6 is a top view of the G/B mask 600 corresponding to the pixel color block in an embodiment of the application.
  • the first type is the top image in FIG. 6, the light shielding layer is on the sub-pixels G and B, and the light shielding layers of the sub-pixels G and B have no holes;
  • the second type is the middle image in FIG. 6, The light-shielding layer is on the sub-pixels R and B, and the light-shielding layer of the sub-pixel B is provided with a hole on the upper right side;
  • the third type is the lower diagram in FIG. 6, the light-shielding layer is on the sub-pixels R, G, and the sub-pixels R, Holes are provided on the upper right of the light-shielding layer of G.
  • FIG. 9 is a top view of the R/G mask 900 corresponding to the pixel color block in an embodiment of the application.
  • the first type is the upper diagram in FIG. 9, the light shielding layer is on the sub-pixels G and B, and the light shielding layer of the sub-pixel G is provided with a hole on the upper right side;
  • the second type is the center in FIG. 9 In the figure, the light-shielding layer is on the sub-pixels R and B, and the light-shielding layers of the sub-pixels R and B are provided with holes on the upper right side;
  • the third type is the lower diagram in FIG. 9, and the light-shielding layer is on the sub-pixels R and G, The light-shielding layers of the sub-pixels R and G have no holes.
  • FIG. 12 is a top view of the R/G/B mask 1200 corresponding to the pixel color block in an embodiment of the application, and is also a schematic diagram of the R/G/B mask in an embodiment of the application.
  • the first type is the upper diagram in FIG. 12, the light-shielding layer is on the sub-pixels G and B, and the light-shielding layer of the sub-pixel G is provided with a hole on the upper right;
  • the second type is the middle in FIG. In the figure, the light-shielding layer is on the sub-pixels R and B, and the light-shielding layer of the sub-pixel B is provided with holes on the upper right side;
  • the third type is the lower diagram in FIG. 12, the light-shielding layer is on the sub-pixels R and G, and the sub-pixel The light-shielding layers of R and G are provided with holes on the upper right.
  • FIG. 4 is a cross-sectional view of the array substrate 400 corresponding to the R/B mask in an embodiment of the application
  • FIG. 5 is an example of a method for making patterns of TFTs based on the R/B mask in an embodiment of the application Schematic diagram of the embodiment.
  • a cross-sectional view of the array substrate 400 containing TFTs corresponding to the R/B mask in FIG. 4 can be produced.
  • the left image is a cross-sectional view of the TFT area under the R pixel, which corresponds to the photomask type in the upper image in FIG. 3; It is a cross-sectional view of the TFT area under the G pixel, which corresponds to the middle photomask type in FIG.
  • the array substrate 400 consists of the base substrate 401, the gate layer 402, the first insulating layer 403, the first semiconductor layer 404 (As layer), the second semiconductor layer 405,
  • the source electrode 406, the drain electrode 407, the R photoresist layer 408R, the B photoresist layer 408Rb, the flat layer 409, the pixel layer 410, and the alignment layer 411 are composed, and the TFT includes a gate layer 402, a first insulating layer 403, and a first insulating layer 403.
  • the pixel layer 410 is electrically connected to the drain in the TFT.
  • the corresponding levels in the middle and right pictures are the same as those in the left picture. The details will not be repeated here, but 408G in the middle picture is the G photoresist layer, and 408Gb is the B photoresist layer covering the G photoresist layer, the right picture 408B is the B photoresist layer, and 408Br is the R photoresist layer covering the B photoresist layer.
  • 408G in the middle picture is the G photoresist layer
  • 408Gb is the B photoresist layer covering the G photoresist layer
  • the right picture 408B is the B photoresist layer
  • 408Br is the R photoresist layer covering the B photoresist layer.
  • FIG. 4 only shows an array substrate structure including a TFT structure corresponding to a group of pixel color blocks.
  • FIG. 4 in this embodiment shows the alignment layer 411
  • the array substrate may not be provided with the alignment layer 411, which is not specifically limited here.
  • the TFT is the TFT area on the array substrate of the TFT-LCD, and the TFT is covered with a photomask.
  • the photomask is composed of three types corresponding to the exposure of the adjacent exposure devices at different time points.
  • An example of a method for making patterns of TFTs based on R/B photomasks is:
  • the TFT receiving spraying device coats the first photoresist
  • the first photoresist may be a red photoresist, which is hereinafter referred to as R photoresist.
  • the TFT receives the first exposure of the exposure device through the first type of photomask.
  • the first type is that in the pixel color block, there is no light-shielding layer above the first column of sub-pixels, and both the second column of sub-pixels and the third column of sub-pixels are above.
  • the sub-pixels in the first column are R pixels with no light-shielding layer above
  • the sub-pixels in the second column are G pixels
  • the sub-pixels in the third column are B pixels. Both G and B pixels are above. Shading layer.
  • a hole is opened at the upper right of the light shielding layer on the B pixel.
  • the TFT is developed for the first time to form a first pattern
  • the positions where holes are provided on the light-shielding layer of the pixels of the photomask can adopt a grayscale photomask design or a slit photomask design. Both of these designs can be used to obtain an array substrate containing TFTs in Figure 4 Sectional view.
  • the mask design adopted by the mask there is no specific limitation here.
  • the gray-scale photomask design is adopted. Therefore, the TFT under the small hole receives weaker light due to the gray-scale. Therefore, a thin layer of R-color photoresist can be formed on the TFT under the B pixel.
  • the photoresist patterns formed on the three TFTs under the three columns of pixels after the first exposure constitute the first pattern.
  • the TFT receiving spraying device coats the second photoresist on the first pattern.
  • the spraying device coats the second photoresist on the first pattern on the TFT.
  • the second photoresist in this embodiment is green.
  • the TFT receives the second exposure of the exposure device through a second type of photomask, where the second type is that there is no light-shielding layer above the second column of sub-pixels, and the first column of sub-pixels and the third column of sub-pixels have a light-shielding layer;
  • the TFT performs a second development to form a second pattern
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the second exposure constitute the second pattern.
  • the TFT receiving spraying device coats the third photoresist on the second pattern
  • the spraying device coats the third photoresist on the second pattern of the TFT.
  • the third photoresist in this embodiment is blue.
  • the TFT receives the third exposure of the exposure device through a third type of photomask.
  • the third type is that there is no light-shielding layer above the third column of sub-pixels, and the first column of sub-pixels and the second column of sub-pixels have a light-shielding layer;
  • the TFT is developed for the third time to form a target pattern.
  • at least one column of pixels is provided with holes on the light-shielding layer, and the position of the holes is Corresponds to the position of the TFT.
  • holes are provided at the upper right of the light shielding layer above the B pixels in the first type and at the upper right of the light shielding layer above the R and G pixels of the third type.
  • the TFT under the small hole receives weak light due to the gray-scale, so a thin B-color photoresist pattern can be formed on the TFT under the R pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the third exposure constitute the target pattern.
  • the TFTs under each column of pixels have two kinds of photoresist superimposed.
  • the reflected light can be offset, and the reflected light can be offset. The role of extinction.
  • the mask can be made by changing the mask to open holes in the upper right of the light shielding layer above the B pixels of the first type, and the light shielding layer above the R and G pixels of the third type to make
  • the TFT corresponding to each group of pixel color blocks undergoes three consecutive exposures at different time points
  • two layers of different types of photoresist can be generated on the TFT under each pixel to overlap each other, so that when the upper glass plate reflects light to the AS of the TFT
  • the two photoresistors on the TFT are superimposed, they can have a matting effect on the reflected light, and the reflected light is almost canceled out, which cannot affect the electrical properties of the TFT, so the normal operation of the TFT can be ensured.
  • FIG. 6 is the G/B photomask corresponding to the pixel color block in the embodiment of the present application.
  • 7 is a cross-sectional view of the array substrate corresponding to the G/B mask
  • FIG. 8 is a schematic diagram of an embodiment of a method for making a TFT pattern based on a G/B mask in an embodiment of the application.
  • the cross-sectional view of the TFT of the array substrate 700 shown in FIG. 7 is a cross-sectional view of the TFT area under the R pixel, which corresponds to the mask type in the upper image in FIG. 5; the middle image is under the G pixel A cross-sectional view of the TFT area in FIG. 5, which corresponds to the middle photo mask type in FIG. 5; the right image is a cross-sectional view of the TFT below the B pixel, which corresponds to the bottom photo mask type in FIG. 5.
  • the array substrate 700 consists of the base substrate 701, the gate layer 702, the first insulating layer 703, the first semiconductor layer 704, the second semiconductor layer 705, the source electrode 706, and the base substrate 701, the gate layer 702, the first insulating layer 703, the first semiconductor layer 704, the second semiconductor layer 705, the source electrode 706 and Drain 707.
  • the pixel layer 710 is electrically connected to the drain in the TFT.
  • the corresponding levels in the middle and right pictures are the same as those in the left picture. The details are not repeated here, but 708G in the middle picture is the G photoresist layer, 708Gb is the B photoresist layer, and 708B in the right picture is the B photoresist.
  • Layer, 708Bg is the G photoresist layer covering the B photoresist layer.
  • the cross-sectional view of the TFT shown in FIG. 7 is the cross-sectional view of the TFT area under the R pixel in the left picture, the cross-sectional view of the TFT area under the G pixel in the middle, and the cross-sectional view of the TFT area under the B pixel in the right picture. There is a TFT area corresponding to a column of pixels.
  • FIG. 7 in this embodiment shows the alignment layer 711
  • the array substrate may not be provided with the alignment layer 711, which is not specifically limited here.
  • the embodiment of the pattern manufacturing method of TFT based on G/B photomask is:
  • the TFT receiving spraying device coats R color photoresist
  • the TFT receives the first exposure of the exposure device through the first type of photomask, and there is no hole on the light shielding layer above the first type of G and B pixels;
  • the first type is that in the pixel color block, there is no light-shielding layer above the R pixel, the light-shielding layer above the G pixel and the B pixel, and the light-shielding layer above the G and B pixels of the first type has no holes.
  • the TFT is developed for the first time to form a first pattern
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the first exposure constitute the first pattern.
  • the TFT receiving spraying device coats the G color photoresist on the first pattern
  • the TFT receives the second exposure of the exposure device through the second type of photomask, and a hole is opened at the upper right of the light shielding layer above the second type of B pixel;
  • the second type is that in the pixel color block, there is no light-shielding layer above the G pixel, the light-shielding layer above the R and B pixels, and the light-shielding layer above the B pixel of the second type has a hole at the upper right.
  • the TFT performs a second development to form a second pattern
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the second exposure constitute the second pattern.
  • the TFT receiving spraying device coats the B photoresist on the second pattern
  • the spraying device coats the B photoresist on the second pattern of the TFT.
  • the TFT receives the third exposure of the exposure device through the third type of photomask, and holes are opened at the upper right of the light-shielding layer of the R and G pixels;
  • the third type is that there is no light-shielding layer above the B pixel, and both the R pixel and the G pixel have a light-shielding layer. In addition, holes are opened at the upper right of the light-shielding layer of the R and G pixels.
  • the TFT is developed for the third time to form a target pattern.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the third exposure constitute the target pattern.
  • holes are opened at the upper right of the light-shielding layer above the B pixels of the first type, and at the upper right of the light-shielding layer above the R and G pixels of the third type, so that the TFTs corresponding to the color blocks of each group of pixels are not available.
  • two layers of different types of photoresist can be superimposed on the TFT under each pixel, so that the reflected light reflected on the semiconductor As layer can be extinct to ensure the normal operation of the TFT.
  • FIG. 9 is the R/G mask corresponding to the pixel color block in the embodiment of the present application.
  • 10 is a cross-sectional view of the array substrate 1000 corresponding to the R/G mask
  • FIG. 11 is a schematic diagram of an embodiment of a method for manufacturing a TFT pattern based on an R/G mask in an embodiment of the present application.
  • a cross-sectional view of the array substrate 1000 containing TFTs corresponding to the R/G mask in FIG. 10 can be produced.
  • the left image is a cross-sectional view of the TFT area under the R pixel, which corresponds to the photomask type in the upper image in FIG. 9; It is a cross-sectional view of the TFT area under the G pixel, which corresponds to the middle photo mask type in FIG.
  • the array substrate 1000 consists of the base substrate 1001, the gate layer 1002, the first insulating layer 1003, the first semiconductor layer 1004 (As layer), the second semiconductor layer 1005,
  • the source electrode 1006, the drain electrode 1007, the R photoresist layer 1008R, the G photoresist layer 1008Rg, the flat layer 1009, the pixel layer 1010, and the alignment layer 1011 are composed, and the TFT includes the gate layer 1002, the first insulating layer 1003, and the first insulating layer 1003.
  • the pixel layer 1010 is electrically connected to the drain in the TFT.
  • the corresponding levels in the middle and right pictures are the same as those in the left picture. The details are not repeated here, but 1008G in the middle picture is the G photoresist layer, 1008Gr is the R photoresist layer covering the G photoresist layer, and the right 1008B in the figure red is the B photoresist layer, and 1008Bg is the G photoresist layer covering the B photoresist layer.
  • 1008G in the middle picture is the G photoresist layer
  • 1008Gr is the R photoresist layer covering the G photoresist layer
  • the right 1008B in the figure red is the B photoresist layer
  • 1008Bg is the G photoresist layer covering the B photoresist layer.
  • the left image is a cross-sectional view of the TFT area under the R pixel
  • the middle image is a cross-sectional view of the TFT area under the G pixel
  • the right image is a cross-sectional view of the TFT area under the B pixel.
  • FIG. 10 in this embodiment shows the alignment layer 1011
  • the array substrate may not be provided with the alignment layer 1011, which is not specifically limited here.
  • TFT receiving spraying device to coat R color photoresist
  • the TFT receives the first exposure of the exposure device through the first type of photomask, and a hole is provided at the upper right of the light shielding layer above the first type of G pixel;
  • the first type is that in the pixel color block, there is no light-shielding layer above the R pixel, the light-shielding layer above the G and B pixels, and the light-shielding layer above the G pixel has a hole at the upper right.
  • the TFT is developed for the first time to form a first pattern
  • a layer of R-color photoresist pattern is formed on the TFT under the R pixel; since the light-shielding layer above the G pixel has a hole at the upper right, the G pixel The lower TFT will form a thin layer of R-color photoresist pattern; and the B pixel has a light-shielding layer above, so no R-color photoresist pattern will be formed under the B pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the first exposure constitute the first pattern.
  • the TFT receiving spraying device coats G color photoresist on the first pattern
  • the TFT receives the second exposure of the exposure device through the second type of photomask, and holes are opened at the upper right of the light-shielding layer above the R and B pixels;
  • the second type is that in the pixel color block, there is no light-shielding layer above the G pixel, and the light-shielding layer above the R and B pixels has a light-shielding layer, and the light-shielding layer above the R and B pixels has holes in the upper right.
  • the TFT is developed for the second time to form a second pattern
  • a thinner G-color photoresist pattern will be formed on the R-color photoresist pattern of the TFT; and the R-color light of the TFT under the G pixel A layer of G-color photoresist pattern will also be formed on the resist pattern; a thinner layer of G-color photoresist pattern will be formed on the TFT below the B pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the second exposure constitute the second pattern.
  • the TFT receiving spraying device coats the B photoresist on the second pattern
  • the TFT receives the third exposure of the exposure device through the third type of photomask, and there is no hole on the light shielding layer of the R and G pixels;
  • the third type is that there is no light-shielding layer above the B pixel, and there are light-shielding layers above the R and G pixels. There are no holes in the light-shielding layer of the R and G pixels.
  • the TFT is developed for the third time to form a target pattern.
  • the G color photoresist pattern of the TFT under the R pixel will not form a layer of B color photoresist pattern; similarly, the G color photoresist pattern of the TFT under the G pixel The pattern of the color photoresist will not form a layer of B-color photoresist pattern; and the pattern of the G-color photoresist of the TFT below the B pixel will form a layer of B-color photoresist pattern.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the third exposure constitute the target pattern.
  • the reflected light from the upper glass plate to the semiconductor As layer can also be offset, thereby ensuring the normal operation of the TFT.
  • the TFT in the embodiment of the present application includes a substrate and a photoresist layer.
  • the photoresist layer is composed of at least two photoresist layers of different colors, and the photoresist layer covers the TFT substrate. ...
  • FIG. 12 is a top view of the R/G/B mask corresponding to the pixel color block in an embodiment of the application
  • FIG. 13 is an array substrate corresponding to the R/G/B mask A cross-sectional view of 1300
  • FIG. 14 is a schematic diagram of an embodiment of a method for making patterns of TFTs based on R/G/B masks in an embodiment of the present application.
  • the array substrate 1300 containing TFTs corresponding to the R/G/B mask in Fig. 12 can be produced. Cutaway view.
  • the left image is a cross-sectional view of the TFT area under the R pixel, which corresponds to the photomask type in the upper image in FIG. 12; It is a cross-sectional view of the TFT area under the G pixel, which corresponds to the middle photo mask type in FIG.
  • the array substrate 1300 consists of the base substrate 1301, the gate layer 1302, the first insulating layer 1303, the first semiconductor layer 1304 (As layer), the second semiconductor layer 1305,
  • the source electrode 1306, the drain electrode 1307, the R photoresist layer 1308R, the B photoresist layer 1308Rb, the planarization layer 1309, the pixel layer 1310 and the alignment layer 1311 are composed, and the TFT includes a gate layer 1302, a first insulating layer 1303, and a first insulating layer 1303.
  • the pixel layer 1310 is electrically connected to the drain in the TFT.
  • the corresponding levels in the middle and right pictures are the same as those in the left picture. The details are not repeated here, but 1308G in the middle picture is the G photoresist layer, 1308rG is the R photoresist layer covered by the G photoresist layer, and the right picture 1308rGb in is the B photoresist layer covering the G photoresist layer.
  • the left image is a cross-sectional view of the TFT area under the R pixel
  • the middle image is a cross-sectional view of the TFT area under the G pixel
  • the right image is a cross-sectional view of the TFT area under the B pixel.
  • FIG. 13 in this embodiment shows the alignment layer 1311
  • the array substrate may not be provided with the alignment layer 1311, which is not specifically limited here.
  • the photomask in this embodiment is as described above ( Figure 12).
  • An example of a method for making patterns of TFTs based on R/G/B photomasks is:
  • TFT receiving spraying device coats R color photoresist
  • the TFT receives the first exposure of the exposure device through the first type of photomask, and a hole is provided at the upper right of the light shielding layer above the first type of G pixel;
  • the first type is that in the pixel color block, there is no light-shielding layer above the R pixel, the light-shielding layer above the G and B pixels, and the light-shielding layer above the G pixel has a hole at the upper right.
  • the TFT is developed for the first time to form a first pattern
  • a layer of R-color photoresist pattern is formed on the TFT under the R pixel; since the light-shielding layer above the G pixel has a hole at the upper right, the G pixel The lower TFT will form a thin layer of R-color photoresist pattern; and the B pixel has a light-shielding layer above, so no R-color photoresist pattern will be formed under the B pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the first exposure constitute the first pattern.
  • the TFT receiving spraying device coats G color photoresist on the first pattern
  • the TFT receives the second exposure of the exposure device through the second type photomask, and a hole is opened at the upper right of the light shielding layer above the B pixel;
  • the second type is that in the pixel color block, there is no light-shielding layer above the G pixel, the light-shielding layer above the R and B pixels, and the light-shielding layer above the B pixel has a hole at the upper right.
  • the TFT is developed for the second time to form a second pattern
  • the pattern of G color photoresist will not be formed on the R color photoresist of the TFT; and a layer will be formed on the R color photoresist of the TFT under the G pixel G-color photoresist pattern; A layer of G-color photoresist pattern will be formed on the TFT below the B pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the second exposure constitute the second pattern.
  • the TFT receiving spraying device coats the B photoresist on the second pattern
  • the TFT receives the third exposure of the exposure device through the third type of photomask, and holes are provided at the upper right of the light-shielding layer above the R and G pixels;
  • the third type is that there is no light-shielding layer above the B pixel, and there are light-shielding layers above the R and G pixels. Holes are provided on the upper right side of the light-shielding layer above the R and G pixels.
  • the TFT is developed for the third time to form a target pattern.
  • the pattern of the R-color photoresist of the TFT under the R pixel will form a thinner pattern of the B-color photoresist; and the TFT under the G pixel
  • the pattern of the G-color photoresist will also form a thinner pattern of the B-color photoresist; a layer of the B-color photoresist pattern will be formed on the G-color photoresist pattern of the TFT under the B pixel.
  • the photoresist patterns respectively formed on the three TFTs under the three columns of pixels after the third exposure constitute the target pattern.
  • the reflected light reflected to the semiconductor As layer of the TFT can be further offset, thereby further ensuring the normal operation of the TFT.
  • FIG. 15 is a schematic diagram of an embodiment of the array substrate in the embodiment of the application.
  • the array substrate 1500 in the embodiment of the present application can be made by using a half-gray-scale photomask, or can be made by using a slit photomask, which is not specifically limited here.
  • a TFT 1502 is formed on the base substrate 1501, where each sub-pixel color block is covered with a TFT 1502, and each group of pixel color blocks can include three sub-pixels R, G, and B. In this way, each group of pixel color blocks Three TFTs 1502 may be covered below, and each group of pixel color blocks may also include more different sub-pixels, such as white, which is not specifically limited here.
  • the second step is to coat the first photoresist on the TFT1502;
  • the first photoresist may be coated on the sub-pixels R, G, and B in each group.
  • the first photoresist is R photoresist.
  • the first photoresist on the TFT 1502 is exposed for the first time through the first type of R/B photomask.
  • the R/B mask used in this embodiment is composed of three types corresponding to the exposure of the adjacent receiving exposure devices at different time points.
  • the sub-pixels of the two columns are A hole is opened on the light shielding layer, and the position of the hole corresponds to the position of the TFT 1502.
  • the R/B mask used in the first exposure is the first type.
  • the first type is that there is no light-shielding layer above the R pixel, and the light-shielding layer above the G and B pixels, and on the light-shielding layer at the upper right of the B pixel Holes are provided.
  • the fourth step is to develop the TFT 1502 for the first time to form a first pattern on the TFT 1502;
  • the first pattern includes 1503A, 1503C, and no pattern on the TFT corresponding to the G pixel.
  • the TFT corresponding to the R pixel is formed with an R photoresist 1503A
  • the TFT corresponding to the B pixel is formed with an R photoresist 1503C.
  • the fifth step is to coat a second photoresist on the first pattern of TFT1502;
  • the second photoresist is a G photoresist. That is to say, G photoresist is coated on 1503A, 1503C, and G photoresist is coated on the R photoresist of the TFT of the G pixel;
  • the second photoresist on the first pattern 1503A, 1503C, and the second photoresist on the first photoresist on the TFT corresponding to the G pixel is subjected to a second exposure through the second type of photomask;
  • the second type is that there is no light-shielding layer above the G pixels, and there are light-shielding layers above the R pixels and B pixels.
  • the TFT 1502 is developed a second time to form a second pattern on the first pattern of the TFT 1502;
  • the second pattern includes 1503B formed by G photoresist.
  • the 1503B is formed on the TFT corresponding to the G pixel. Since there is no pattern formed on 1503A, 1503C, the second pattern is composed of 1503A, 1503B, and 1503C.
  • a third photoresist is coated on the second patterns 1503A, 1503B, and 1503C of the TFT 1502;
  • the third photoresist is B photoresist.
  • the second patterns 1503A, 1503B are applied to the second pattern 1503A, 1503B through the third type of mask , 1503C for the third exposure;
  • the third type is that there is no light-shielding layer above the B pixel, and the light-shielding layer above the R pixel and the G pixel, and holes are provided at the upper right of the light-shielding layer above the R pixel and the G pixel.
  • the tenth step is to develop the TFT 1502 for the third time to form a target pattern on the TFT 1502;
  • a target pattern is formed on the second pattern of the TFT 1502, and the target pattern includes 1503Ax, 1503By, and 1503Cz.
  • 1503Ax of B photoresist is formed on 1503A of the R pixel of the second pattern
  • 1503By of B photoresist is formed on 1503B of the G pixel
  • 1503Cz of B photoresist is formed on 1503C of the B pixel.
  • target patterns 1503Ax, 1503By, and 1503Cz are formed by the photoresist layer 1503.
  • a pixel layer 1504 is formed on the photoresist layer 1503;
  • the target patterns 1503Ax, 1503By, and 1503Cz are formed by the photoresist layer 1503, so the pixel layer 1504 is formed on the photoresist layer 1503.
  • an alignment layer 1505 is formed on the pixel layer 1504.
  • the alignment layer 1505 may or may not be formed on the array substrate 1500, which is not specifically limited here.
  • the array substrate 1500 in the embodiment of the present application is formed.
  • R/B masks can be used in the embodiments of this application, but also the aforementioned G/B masks and R/G masks. All three types of masks can be formed on the TFT 1502. A pattern formed by stacking color resists. Further, the aforementioned R/G/B photomask can also be used in the embodiments of the present application, and this photomask can be used to form a pattern formed by stacking three color resists on the TFT 1502. The foregoing embodiments shown in FIGS. 12 to 14 have been specifically described, and will not be repeated here.
  • the array substrate 1500 has a half-gray-scale photomask or a slit photomask that can be changed at different time points, two or more photoresist patterns are formed on the array substrate 1500, Since the two or more photoresists on the array substrate 1500 are superimposed, the reflected light can have a delustering effect, and the reflected light is almost canceled out, so that the electrical properties of the TFT cannot be affected, and therefore, the normal operation of the TFT can be ensured.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • features defined with “first” and “second” may explicitly or implicitly include one or more features.
  • “multiple” means two or more than two, unless otherwise specifically defined.

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Abstract

本申请公开一种TFT的图案制作方法以及光罩，用于使光通过位于TFT上方的光罩上设置的与TFT位置对应的孔，在TFT上产生两种及以上光阻叠加，抵消半导体AS层上的反射光，保证TFT正常工作。

Description

薄膜晶体管的图案制作方法、薄膜晶体管以及光罩 技术领域
本申请涉及液晶显示技术领域，具体涉及一种薄膜晶体管的图案的制作方法、薄膜晶体管以及光罩。
 背景技术
光罩由石英玻璃作为衬底，在其上面镀上一层金属铬和感光胶，成为一种感光材料，把已制作好的电路图形通过电子激光设备曝光在感光胶上，被曝光的区域会被显影出来，在金属铬上形成电路图形，成为类似曝光后的底片的光罩。光罩的生产加工工序为：曝光，显影，去感光胶，最后应用于光蚀刻。而其中，薄膜晶体管（Thin film transistor ,TFT）为薄膜晶体管液晶显示器（Thin film transistor liquid crystal display, TFT-LCD）的阵列基板上的TFT区域。TFT-LCD的面板可视为两片玻璃基板中间夹着一层液晶，上层的玻璃基板是彩色滤光片，而下层的玻璃则有晶体管镶嵌在玻璃上。上层玻璃因与彩色滤光片贴合，形成每个像素各包含红蓝绿三颜色的子像素，这些发出红蓝绿色彩的像素便构成了面板上的视频画面。
目前已知的TFT的图案制作方法中，在TFT上方覆盖有光罩，该光罩通常由覆盖在至少两组像素色块上的子光罩组成，每组像素色块由红（R）、绿（G）、蓝（B）色各一列子像素组合而成，并且，光罩由3N个相邻的不同时点接收曝光装置曝光时对应的三种类型构成，其中，N≥1，该方法包括如下步骤：
S1：TFT接收喷涂装置涂布第一光阻；
S2：TFT通过第一类型的光罩接收曝光装置的第一次曝光，该第一类型为在像素色块中，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有遮光层；
S3：TFT进行第一次显影，形成第一图案；
S4：TFT接收喷涂装置在第一图案上涂布第二光阻；
S5：TFT通过第二类型的光罩接收曝光装置的第二次曝光，该第二类型为第二列子像素上方无遮光层，第一列子像素和第二列子像素上方均有遮光层；
S6：TFT进行第二次显影，形成第二图案；
S7：TFT接收喷涂装置在第二图案上涂布第三光阻；
S8：TFT通过第三类型的光罩接收曝光装置的第三次曝光，该第三类型为第三列子像素上方无遮光层，第一列子像素和第二列子像素上方均有遮光层；
S9：TFT进行第三次显影，形成目标图案。
已知的光罩如图1所示，图1为光罩的俯视图，图1中是覆盖在两组像素色块上方的光罩100。由图1可知，覆盖着光罩的每组像素色块分别由红（R）、绿（G）、蓝（B）色各一列像素组合而成。而通过该已知光罩可以得到图2所示的阵列基板中的TFT结构，图2为像素色块对应的阵列基板200的剖视图，阵列基板200的剖视图中包括TFT的剖视图。请参阅图2，左图为R像素对应的阵列基板，中图为G像素对应的阵列基板，右图为B像素对应的阵列基板。其中，阵列基板200自下而上依次由图2左图中标示的衬底基板201、栅极层202、第一绝缘层203、第一半导体层204层（As层）、第二半导体层205、源极（Source）206、漏极（Drain）207、R光阻层208R、平坦层209、像素层210以及配向层211构成，而TFT则包括栅极层202、第一绝缘层203、第一半导体层204、第二半导体层205、源极206以及漏极207。并且，像素层210与TFT中的漏极D电连接。中图和右图相应的层级与左图中的相同，具体此处不再赘述，但中图中的208G为G光阻层，右图中的208B为B光阻层。也就是说，图2中所示的TFT的剖视图部分，左图中为R像素下方的TFT区域的剖视图，中图中为G像素下方的TFT区域的剖视图，右图中为B像素下方的TFT区域的剖视图，每一列像素下方都对应有一个阵列基板的TFT区域。图2中仅示出一组像素色块对应的包含有TFT结构的阵列基板结构。
然而，TFT-LCD在点灯时从下层的玻璃基板照射到上层的玻璃基板的侧向光会反射到TFT-LCD的阵列基板的第一半导体层即砷（AS）层上（如图1所示），产生光生载流子，导致关态电流I off提高，从而在TFT-LCD点灯时出现垂直串扰图像，影响TFT原本的电性能。
技术问题
现有技术在TFT-LCD点灯时出现垂直串扰图像的问题。
 技术解决方案
本申请提供的一种TFT的图案制作方法，包括：
所述TFT接收喷涂装置涂布第一光阻；
所述TFT通过覆盖在所述TFT上的第一类型的光罩接收所述曝光装置的第一次曝光，所述第一类型为在所述像素色块中，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有所述遮光层，所述光罩由相邻的不同时点接收曝光装置时对应的三种类型构成；
所述TFT进行第一次显影，形成第一图案；
所述TFT接收所述喷涂装置在所述第一图案上涂布第二光阻；
所述TFT通过所述第二类型的光罩接收所述曝光装置的第二次曝光，所述第二类型为所述第二列子像素上方无所述遮光层，所述第一列子像素和所述第三列子像素上方均有所述遮光层；
所述TFT进行第二次显影，形成第二图案；
所述TFT接收所述喷涂装置在所述第二图案上涂布第三光阻；
所述TFT通过所述第三类型的光罩接收所述曝光装置的第三次曝光，所述第三类型为所述第三列子像素上方无所述遮光层，所述第一列子像素和所述第二列子像素上方均有所述遮光层；
所述TFT进行第三次显影，形成目标图案，其中，在所述光罩的所述三种类型的其中两个类型中，在两列所述像素的所述遮光层上，至少有一列所述像素的所述遮光层上开设有孔，所述孔的位置与所述TFT的位置相对应。
本申请提供的一种阵列基板，包括：
衬底基板；
光阻层，所述光阻层覆盖在TFT上，所述光阻层由至少两种不同颜色的光阻层叠构成；
像素层，所述像素层覆盖在所述光阻层上，所述像素层与所述TFT的漏极D电连接。
本申请实施例提供了一种光罩， 所述光罩由相邻的不同时点接收曝光装置曝光时对应的三种类型构成，所述三种类型分别为：
第一类型，所述第一类型为薄膜晶体管TFT通过所述光罩的所述第一类型接收所述曝光装置的第一次曝光时，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有所述遮光层，所述第一列子像素、所述第二列子像素、所述第三列子像素组成一组像素色块；
第二类型，所述第二类型为所述TFT通过所述光罩的所述第二类型接收所述曝光装置的第二次曝光时，所述第二列子像素上方无所述遮光层，所述第一列子像素和所述第三列子像素上方均有所述遮光层；
第三类型，所述第三类型为所述TFT通过所述光罩的所述第三类型接收所述曝光装置的第三次曝光时，所述第三列子像素上方无所述遮光层，所述第一列子像素和所述第二列子像素上方均有所述遮光层，其中，在所述光罩的所述三种类型的其中两个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔，所述孔的位置与薄膜晶体管TFT的位置相对应，所述TFT为薄膜晶体管显示器TFT-LCD基板上的TFT区域，所述TFT上方覆盖有所述光罩。
 有益效果
本申请通过改变光罩制作，在三种光罩类型的其中两个类型中，在两列子像素的遮光层上，至少有一列子像素的遮光层上开设孔，使每组像素色块对应的TFT在不同时点依次经历三次曝光后，可以在各个子像素下方的TFT上产生两层不同种类的光阻相互叠加，这样当上层玻璃板或塑料合板有反射光反射至TFT的AS层时，由于TFT上的两种光阻叠加，能够对反射光起到消光效果，反射光几乎全部被抵消，从而无法影响TFT的电性，因此能够保证TFT正常工作。
 附图说明
图1为改进前与像素色块对应的光罩的俯视图；
图2为改进前像素色块对应的阵列基板的剖视图；
图3为本申请实施例中与像素色块对应的R/B光罩的俯视图；
图4为本申请实施例中与R/B光罩对应的阵列基板的剖视图；
图5为本申请实施例中基于R/B光罩的TFT的图案制作方法的实施例示意图；
图6为本申请实施例中与像素色块对应的G/B光罩的俯视图；
图7为本申请实施例中与G/B光罩对应的阵列基板的剖视图；
图8为本申请实施例中基于G/B光罩的TFT的图案制作方法的实施例示意图；
图9为本申请实施例中与像素色块对应的R/G光罩的俯视图；
图10为本申请实施例中与R/G光罩对应的阵列基板的剖视图；
图11为本申请实施例中基于R/G光罩的TFT的图案制作方法的实施例示意图；
图12为本申请实施例中与像素色块对应的R/G/B光罩的俯视图；
图13为本申请实施例中与R/G/B光罩对应的阵列基板的剖视图；
图14为本申请实施例中基于R/G/B光罩的TFT的图案制作方法的实施例示意图；
图15为本申请实施例中阵列基板的实施例示意图。
 本发明的实施方式
本申请实施例提供了TFT的图案制作方法、阵列基板以及光罩，用于在TFT上使光通过位于TFT上方的光罩上设置的与TFT位置对应的孔，从而在TFT上产生两种以上光阻叠加，抵消半导体AS层上的反射光，保证TFT正常工作。
如上所述，已知光罩位于众多像素色块下方，每组像素色块由红绿蓝等色的各一列子像素组合而成，每个子像素下方均设置有一个TFT区域，因此，有多少个像素，就可知在TFT-LCD的阵列基板上有多少个TFT区域。需要说明的是，该TFT区域可以设置在各个子像素下方的不同位置，但在各个子像素下方，TFT区域通常设置在与各个子像素的右上方所对应的位置。
本申请实施例中的光罩，由相邻的不同时点接收曝光装置曝光时对应的三种类型构成，该三种类型分别为：
第一类型，当TFT通过第一类型的光罩接收曝光装置的第一次曝光时，在每一组像素色块中，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有遮光层；
第二类型，当TFT通过第二类型的光罩接收曝光装置的第二次曝光时，第二列子像素上方无遮光层，第一列子像素和第三列子像素上方均有遮光层；
第三类型，当TFT通过第三类型的光罩接收曝光装置的第三次曝光时，第三列子像素上方无遮光层，第一列子像素和第二列子像素上方均有遮光层。
而其中，在第一类型、第二类型、第三类型的其中两个类型中，在两列子像素的遮光层上，至少有一列子像素的遮光层上开设有孔，该孔的位置与TFT的位置相对应。
需要说明的是，本申请实施例中的第一列子像素、第二列子像素和第三列子像素没有固定的先后顺序之分，对此具体此处不做限定。
以下通过本申请实施例对这三种类型结合附图依次进行描述。
请参阅图3，图3为本申请实施例中与像素色块对应的R/B光罩300的俯视图。
需要说明的是，本申请中的所有实施例，均以TFT区域对应于各个像素的右上方的位置为例进行说明，但TFT区域不仅限于设置在此位置。
图3中仅标示出两组像素色块上方的光罩300，其中，第一类型为图3中的上图，由上图可知，遮光层在子像素G、B上，且子像素B的遮光层右上方上开设有孔；第二类型为图3中的中图，遮光层在子像素R、B上，子像素R、B的遮光层上无孔；第三类型为图3中的下图，遮光层在子像素R、G上，且子像素R、G的遮光层右上方上均开设有孔。
以上为本申请实施例中与像素色块对应的R/B光罩的说明，其技术效果将在下文中有关TFT的图案制作方法中详细介绍。
接着，请参阅图6，图6为本申请实施例中与像素色块对应的G/B光罩600的俯视图。
如图6所示，第一类型为图6中的上图，遮光层在子像素G、B上，子像素G、B的遮光层上无孔；第二类型为图6中的中图，遮光层在子像素R、B上，且子像素B的遮光层右上方上开设有孔；第三类型为图6中的下图，遮光层在子像素R、G上，且子像素R、G的遮光层右上方上均开设有孔。
接着，请参阅图9，图9为本申请实施例中与像素色块对应的R/G光罩900的俯视图。
如图9所示，第一类型为图9中的上图，遮光层在子像素G、B上，且子像素G的遮光层右上方上开设有孔；第二类型为图9中的中图，遮光层在子像素R、B上，且子像素R、B的遮光层右上方上均开设有孔；第三类型为图9中的下图，遮光层在子像素R、G上，子像素R、G的遮光层上无孔。
最后，请参阅图12，图12为本申请实施例中与像素色块对应的R/G/B光罩1200的俯视图，也是本申请实施例中R/G/B光罩的示意图。
如图12所示，第一类型为图12中的上图，遮光层在子像素G、B上，且子像素G的遮光层右上方上开设有孔；第二类型为图12中的中图，遮光层在子像素R、B上，且子像素B的遮光层右上方上均开设有孔；第三类型为图12中的下图，遮光层在子像素R、G上，子像素R、G的遮光层右上方均开设有孔。
以上对本申请实施例中各个实施例中的光罩类型进行了说明，以下基于上述各个实施例中的光罩类型，对TFT的图案制作方法的各个实施例进行详细说明。
参见图4和图5，图4为本申请实施例中与R/B光罩对应的阵列基板400的剖视图，图5为本申请实施例中基于R/B光罩的TFT的图案制作方法的实施例示意图。
基于图3以及R/B光罩的说明，通过每一组不同时点的连续三次曝光，可以制作出图4中与R/B光罩相对应的包含有TFT的阵列基板400的剖视图。需要说明的是，图4中所示的阵列基板400的TFT的剖面图部分，左图中为R像素下方的TFT区域的剖视图，其对应于图3中的上图光罩类型；中图中为G像素下方的TFT区域的剖视图，其对应于图3中的中图光罩类型；右图中为B像素下方的TFT剖视图，其对应于图3中的下图光罩类型。其中，阵列基板400自上而下依次由图4左图中标示的衬底基板401、栅极层402、第一绝缘层403、第一半导体层404（As层）、第二半导体层405、源极406、漏极407、R光阻层408R、B光阻层408Rb、平坦层409、像素层410以及配向层411构成，而TFT则包括栅极层402、第一绝缘层403、第一半导体层404、第二半导体层405、源极406以及漏极407。并且，像素层410与TFT中的漏极电连接。中图和右图相应的层级与左图中的相同，具体此处不再赘述，但中图中的408G为G光阻层，408Gb为覆盖在G光阻层上B光阻层，右图中的408B为B光阻层，408Br为覆盖在B光阻层上的R光阻层。图4中所示的TFT的剖视图部分，左图中为R像素下方的TFT区域的剖视图，中图中为G像素下方的TFT区域的剖视图，右图中为B像素下方的TFT区域的剖视图，每一列像素下方都对应有一个TFT区域。图4中仅示出一组像素色块对应的包含由TFT结构的阵列基板结构。
需要说明的是，本实施例中的图4虽然示出了配向层411，但阵列基板也可以不设置该配向层411，具体此处不做限定。
如上所述，TFT为TFT-LCD的阵列基板上的TFT区域，TFT上方覆盖有光罩，光罩由相邻的不同时点接收曝光装置曝光时对应的三种类型构成。
基于R/B光罩的TFT的图案制作方法的实施例为：
501、TFT接收喷涂装置涂布第一光阻；
本实施例中，该第一光阻可以为红色光阻，以下称为R光阻。
502、TFT通过第一类型的光罩接收曝光装置的第一次曝光，该第一类型为在像素色块中，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有遮光层；本实施例中，第一列子像素、第二列子像素、第三列子像素组成一组像素色块，而TFT是基于R/B光罩通过三次曝光得到图4中的TFT剖面图。请参见图4，本实施例的第一类型中，第一列子像素为R像素，上方无遮光层，第二列子像素为G像素，第三列子像素为B像素，G、B像素上方均有遮光层。
此外，B像素上的遮光层右上方开设有孔。
503、TFT进行第一次显影，形成第一图案；
本实施例中，R像素下方的TFT在进行第一次显影后，由于第一次曝光时R像素上方无遮光层，因此在TFT上会形成一层R色光阻；而由于第一次曝光时G像素上方有遮光层，因此G像素下方的TFT上不会形成R色光阻的图案；此外，由于第一次曝光时B像素上方有遮光层，且右上方开设有孔，因此B像素下方的TFT上会形成一层R色光阻的图案。
需要说明的是，光罩的像素的遮光层上开设有孔的位置，可以采用灰阶光罩设计或者狭缝光罩设计，这两种设计均可以得到图4中包含有TFT的阵列基板的剖视图。有关光罩所采用的光罩设计，具体此处不做限定。
本实施例中采用的是灰阶光罩设计，因此在小孔下方的TFT处因灰阶受光较弱，因此B像素下方的TFT上可以形成一层较薄的R色光阻。
这样，由第一次曝光后的三列像素下方的三个TFT上各自形成的光阻的图案就构成了第一图案。
504、TFT接收喷涂装置在第一图案上涂布第二光阻；
接着，喷涂装置在TFT上的第一图案上涂布第二光阻，本实施例中的第二光阻为绿色。
505、TFT通过第二类型的光罩接收曝光装置的第二次曝光，该第二类型为第二列子像素上方无遮光层，第一列子像素和第三列子像素上方均有遮光层；
本实施例的第二类型中，G像素上方无遮光层，R、B像素上方均有遮光层。
506、TFT进行第二次显影，形成第二图案；
本实施例中，R像素下方的TFT在进行第二次显影后，由于第二次曝光时R像素上方有遮光层，因此在TFT的R色光阻的图案上没有形成G色光阻的图案，还是仅有R色光阻的图案；而由于第二次曝光时G像素上方无遮光层，因此G像素下方的TFT上会形成一层G色光阻的图案；此外，由于第二次曝光时B像素上方也有遮光层，因此B像素下方的TFT的R色光阻的图案上也没有形成G色光阻的图案，仍然是仅有一层较薄的R色光阻的图案。
这样，由第二次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第二图案。
507、TFT接收喷涂装置在第二图案上涂布第三光阻；
接着，喷涂装置在TFT的第二图案上涂布第三光阻，本实施例中的第三光阻为蓝色。
508、TFT通过第三类型的光罩接收曝光装置的第三次曝光，该第三类型为第三列子像素上方无遮光层，第一列子像素和第二列子像素上方均有遮光层；
本实施例的第三类型中，B像素上方无遮光层，R、G像素上方均有遮光层。
509、TFT进行第三次显影，形成目标图案，其中，在三种类型的其中两个类型中，在两列像素的遮光层上，至少有一列像素的遮光层上开设有孔，孔的位置与TFT的位置相对应。
本实施例中，如前所述，在第一类型中的B像素上方的遮光层右上方、以及在第三类型的R、G像素上方的遮光层右上方均开设有孔。
本实施例中，R像素下方的TFT在进行第三次显影后，由于第三次曝光时R像素上方的遮光层右上方开设有孔，因此在R色光阻的图案上会形成一层B色光阻的图案。同样，G像素上方的遮光层右上方开设有孔，因此在G色光阻的图案上也会形成一层B色光阻的图案。并且，由于在B像素上方无遮光层，因此在B像素下方的TFT的R色光阻的图案上也会形成一层B色光阻的图案。
由于本实施例中采用的是灰阶光罩设计，因此在小孔下方的TFT处因灰阶受光较弱，因此R像素下方的TFT上可以形成一层较薄的B色光阻的图案。
这样，由第三次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了目标图案。
由该目标图案可知，在各列像素下的TFT均有两种光阻叠加。这样，当有光照射到TFT-LCD上层玻璃板时，就会有光反射到TFT半导体As层上，然而，由于TFT上形成有两种光阻的叠加，因此可以将反射光抵消，起到消光的作用。
基于上述说明，在本实施例中，可以通过改变光罩制作，在第一类型的B像素上方的遮光层右上方、以及第三类型的R、G像素上方的遮光层右上方开设孔，使每组像素色块对应的TFT在不同时点连续经历三次曝光后，可以在各个像素下方的TFT上产生两层不同种类的光阻相互叠加，这样当上层玻璃版有反射光反射至TFT 的AS层上时，由于TFT上的两种光阻叠加，能够对反射光起到消光效果，反射光几乎全部被抵消，从而无法影响TFT的电性，因此能够保证TFT正常工作。
以上是本申请实施例中基于R/B光罩的TFT的图案制作方法的实施例，以下参见图6至图8，图6为本申请实施例中与像素色块对应的G/B光罩的俯视图，图7为与G/B光罩对应的阵列基板的剖视图，图8为本申请实施例中基于G/B光罩的TFT的图案制作方法的实施例示意图。
基于图6以及G/B光罩的说明，通过每一组不同时点的连续三次曝光，可以制作出图7中与G/B光罩相对应的包含有TFT的阵列基板700的剖视图。其中，图7中所示的阵列基板700的TFT的剖面图部分，左图中为R像素下方的TFT区域的剖视图，其对应图5中的上图光罩类型；中图中为G像素下方的TFT区域的剖视图，其对应于图5中的中图光罩类型；右图中为B像素下方的TFT剖视图，其对应于图5中的下图光罩类型。其中，阵列基板700自上而下依次由图7左图中标示的衬底基板701、栅极层702、第一绝缘层703、第一半导体层704、第二半导体层705、源极706以及漏极707。并且，像素层710与TFT中的漏极电连接。中图和右图相应的层级与左图中的相同，具体此处不再赘述，但中图中的708G为G光阻层，708Gb为B光阻层，右图中的708B为B光阻层，708Bg为覆盖在B光阻层上的G光阻层。图7中所示的TFT的剖视图部分，左图中为R像素下方的TFT区域的剖视图，中途中为G像素下方的TFT区域的剖视图，右图中为B像素下方的TFT区域的剖视图，每一列像素下方都对应有一个TFT区域。
需要说明的是，本实施例中的图7虽然示出了配向层711，但阵列基板也可以不设置该配向层711，具体此处不做限定。
基于G/B光罩的TFT的图案制作方法的实施例为：
801、TFT接收喷涂装置涂布R色光阻；
802、TFT通过第一类型的光罩接收曝光装置的第一次曝光，第一类型的G、B像素上方的遮光层上无孔；
本实施例中，该第一类型为在像素色块中，R像素上方无遮光层，G像素和B像素上方均有遮光层，第一类型的G、B像素上方的遮光层上无孔。
803、TFT进行第一次显影，形成第一图案；
本实施例中，R像素下方的TFT在进行第一次显影后，由于第一次曝光时R像素上方无遮光层，因此在TFT上会形成一层R色光阻的图案；而由于第一次曝光时G、B像素上方均有遮光层，因此G、B像素下方的TFT上均不会形成R色光阻的图案。
这样，由第一次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第一图案。
804、TFT接收喷涂装置在第一图案上涂布G色光阻；
805、TFT通过第二类型的光罩接收曝光装置的第二次曝光，第二类型的B像素上方的遮光层右上方开设有孔；
本实施例中，该第二类型为在像素色块中，G像素上方无遮光层，R、B像素上方均有遮光层，第二类型的B像素上方的遮光层右上方开设有孔。
806、TFT进行第二次显影，形成第二图案；
本实施例中，R像素下方的TFT在进行第二次显影后，由于第二次曝光时R像素上方有遮光层，因此在TFT的R色光阻上没有形成G色光阻的图案，仍然仅有R色光阻的图案；而由于第二次曝光时G像素上方无遮光层，因此G像素下方的TFT上会形成一层G色光阻的图案；此外，由于第二次曝光时B像素上方虽然有遮光层，但右上方开设有孔，因此B像素下方的TFT上会形成一层较薄的G色光阻的图案。
这样，由第二次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第二图案。
807、TFT接收喷涂装置在第二图案上涂布B光阻；
接着，喷涂装置在TFT的第二图案上涂布B光阻。
808、TFT通过第三类型的光罩接收曝光装置的第三次曝光，R、G像素的遮光层右上方均开设有孔；
本实施例中，该第三类型为B像素上方无遮光层，R像素和G像素上方均有遮光层。并且，R、G像素的遮光层右上方均开设有孔。
809、TFT进行第三次显影，形成目标图案。
本实施例中，R像素下方的TFT在进行第三次显影后，由于第三次曝光时R像素上方的遮光层右上方开设有孔，因此在R色光阻的图案上会形成一层B色光阻的图案。同样，G像素上方的遮光层右上方开设有孔，因此在G色光阻的图案上也会形成一层B色光阻的图案。并且，由于在B像素上方无遮光层，因此在B像素下方的TFT的G色光阻的图案上会形成一层B色光阻的图案。
这样，由第三次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了目标图案。
同样，由该目标图案可知，在各列像素下的TFT均有两种光阻叠加。
在本实施例中，在第一类型的B像素上方的遮光层右上方，以及在第三类型的R、G像素上方的遮光层右上方开设孔，使每组像素色块对应的TFT在不同时点连续经历三次曝光后，可以在各个像素下方的TFT上产生两层不同种类的光阻相互叠加，这样能够对反射到半导体As层上的反射光起到消光作用，保证TFT正常工作。
以上是本申请实施例中基于G/B光罩的TFT的图案制作方法的实施例，以下参见图9至图11，图9为本申请实施例中与像素色块对应的R/G光罩的俯视图，图10为与R/G光罩对应的阵列基板1000的剖视图，图11为本申请实施例中基于R/G光罩的TFT的图案制作方法的实施例示意图。
基于图9以及R/G光罩的说明，通过每一组不同时点的连续三次曝光，可以制作出图10中与R/G光罩相对应的包含有TFT的阵列基板1000的剖视图。需要说明的是，图10中所示的阵列基板1000的TFT的剖面图部分，左图中为R像素下方的TFT区域的剖视图，其对应于图9中的上图光罩类型；中图中为G像素下方的TFT区域的剖视图，其对应于图9中的中图光罩类型；右图中为B像素下方的TFT区域的剖视图，其对应于图9中的下图光罩类型。其中，阵列基板1000自上而下依次由图10左图中标示的衬底基板1001、栅极层1002、第一绝缘层1003、第一半导体层1004（As层）、第二半导体层1005、源极1006、漏极1007、R光阻层1008R、G光阻层1008Rg、平坦层1009、像素层1010以及配向层1011构成，而TFT则包括栅极层1002、第一绝缘层1003、第一半导体层1004、第二半导体层1005、源极1006以及漏极1007。并且，像素层1010与TFT中的漏极电连接。中图和右图相应的层级与左图中的相同，具体此处不再赘述，但中图中的1008G为G光阻层，1008Gr为覆盖在G光阻层上的R光阻层，右图红的1008B为B光阻层，1008Bg为覆盖在B光阻层上的G光阻层。图10中所示的TFT的剖视图部分，左图中为R像素下方的TFT区域的剖视图，中图中为G像素下方的TFT区域的剖视图，右图中为B像素下方的TFT区域的剖视图，每一列像素下方都对应有一个TFT区域。
需要说明的是，本实施例中的图10虽然示出了配向层1011，但阵列基板也可以不设置该配向层1011，具体此处不做限定。
参照图11，本实施例中的光罩如前所述（图9）。基于R/G光罩的TFT的图案制作方法的实施例为：
1101、TFT接收喷涂装置涂布R色光阻；
1102、TFT通过第一类型的光罩接收曝光装置的第一次曝光，第一类型的G像素上方的遮光层右上方设有孔；
本实施例中，该第一类型为在像素色块中，R像素上方无遮光层，G、B像素上方均有遮光层，G像素上方的遮光层右上方设有孔。
1103、TFT进行第一次显影，形成第一图案；
本实施例中，R像素下方的TFT在进行第一次显影后，R像素下方的TFT上会形成一层R色光阻的图案；由于G像素上方的遮光层右上方设有孔，因此G像素下方的TFT会形成一层较薄的R色光阻的图案；而B像素上方有遮光层，因此B像素下方不会形成R色光阻的图案。
这样，由第一次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第一图案。
1104、TFT接收喷涂装置在第一图案上涂布G色光阻；
1105、TFT通过第二类型的光罩接收曝光装置的第二次曝光，R、B像素上方的遮光层右上方均开设有孔；
本实施例中，该第二类型为在像素色块中，G像素上方无遮光层，R、B像素上方均有遮光层，R、B像素上方的遮光层右上方均开设有孔。
1106、TFT进行第二次显影，形成第二图案；
本实施例中，R像素下方的TFT在进行第二次显影后，会在TFT的R色光阻的图案上形成一层较薄的G色光阻的图案；而在G像素下方的TFT的R色光阻的图案上也会形成一层G色光阻的图案；在B像素下方的TFT上会形成一层较薄的G色光阻的图案。
这样，由第二次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第二图案。
1107、TFT接收喷涂装置在第二图案上涂布B光阻；
1108、TFT通过第三类型的光罩接收曝光装置的第三次曝光，R、G像素的遮光层上均无孔；
本实施例中，该第三类型为B像素上方无遮光层，R、G像素上方均有遮光层。R、G像素的遮光层上均无孔。
1109、TFT进行第三次显影，形成目标图案。
本实施例中，R像素下方的TFT在进行第三次显影后，R像素下方的TFT的G色光阻的图案上不会形成一层B色光阻的图案；同样，G像素下方的TFT的G色光阻的图案上也不会形成一层B色光阻的图案；而在B像素下方的TFT的G色光阻的图案上则会形成一层B色光阻的图案。
这样，由第三次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了目标图案。
 本实施例中，由于经过三次曝光后每列像素下方的TFT上均有两层光阻重叠，因此同样可以抵消来自上层玻璃板的反射到半导体As层的反射光，从而保证TFT正常工作。
由上述实施例可知，本申请实施例中的TFT，包括基板以及光阻层，该光阻层由至少两种不同颜色的光阻层构成，该光阻层覆盖于该TFT基板上。   
以上是本申请实施例中基于R/G光罩的TFT的图案制作方法的实施例。
进一步地，以下参见图12至图14，图12为本申请实施例中与像素色块对应的R/G/B光罩的俯视图，图13为与R/G/B光罩对应的阵列基板1300的剖视图，图14为本申请实施例中基于R/G/B光罩的TFT的图案制作方法的实施例示意图。
基于图12以及R/G/B光罩的说明，通过每一组不同时点的连续三次曝光，可以制作出图12中与R/G/B光罩相对应的包含有TFT的阵列基板1300的剖视图。需要说明的是，图13中所示的阵列基板1300的TFT的剖面图部分，左图中为R像素下方的TFT区域的剖视图，其对应于图12中的上图光罩类型；中图中为G像素下方的TFT区域的剖视图，其对应于图12中的中图光罩类型；右图中为B像素下方的TFT区域的剖视图，其对应于图12中的下图光罩类型。其中，阵列基板1300自上而下依次由图13左图中标示的衬底基板1301、栅极层1302、第一绝缘层1303、第一半导体层1304（As层）、第二半导体层1305、源极1306、漏极1307、R光阻层1308R、B光阻层1308Rb、平坦层1309、像素层1310以及配向层1311构成，而TFT则包括栅极层1302、第一绝缘层1303、第一半导体层1304、第二半导体层1305、源极1306以及漏极1307。并且，像素层1310与TFT中的漏极电连接。中图和右图相应的层级与左图中的相同，具体此处不再赘述，但中图中的1308G为G光阻层，1308rG为被G光阻层覆盖的R光阻层，右图中的1308rGb为覆盖在G光阻层上的B光阻层。图13中所示的TFT的剖视图部分，左图中为R像素下方的TFT区域的剖视图，中图中为G像素下方的TFT区域的剖视图，右图中为B像素下方的TFT区域的剖视图，每一列像素下方都对应有一个TFT区域。
需要说明的是，本实施例中的图13虽然示出了配向层1311，但阵列基板也可以不设置该配向层1311，具体此处不做限定。
参照图14，本实施例中的光罩如前所述（图12）。基于R/G/B光罩的TFT的图案制作方法的实施例为：
1401、TFT接收喷涂装置涂布R色光阻；
1402、TFT通过第一类型的光罩接收曝光装置的第一次曝光，第一类型的G像素上方的遮光层右上方设有孔；
本实施例中，该第一类型为在像素色块中，R像素上方无遮光层，G、B像素上方均有遮光层，G像素上方的遮光层右上方设有孔。
1403、TFT进行第一次显影，形成第一图案；
本实施例中，R像素下方的TFT在进行第一次显影后，R像素下方的TFT上会形成一层R色光阻的图案；由于G像素上方的遮光层右上方设有孔，因此G像素下方的TFT会形成一层较薄的R色光阻的图案；而B像素上方有遮光层，因此B像素下方不会形成R色光阻的图案。
这样，由第一次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第一图案。
1404、TFT接收喷涂装置在第一图案上涂布G色光阻；
1405、TFT通过第二类型的光罩接收曝光装置的第二次曝光，B像素上方的遮光层右上方开设有孔；
本实施例中，该第二类型为在像素色块中，G像素上方无遮光层，R、B像素上方均有遮光层，且B像素上方的遮光层右上方开设有孔。
1406、TFT进行第二次显影，形成第二图案；
本实施例中，R像素下方的TFT在进行第二次显影后，不会在TFT的R色光阻上形成G色光阻的图案；而在G像素下方的TFT的R色光阻上会形成一层G色光阻的图案；在B像素下方的TFT上会形成一层G色光阻的图案。
这样，由第二次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了第二图案。
1407、TFT接收喷涂装置在第二图案上涂布B光阻；
1408、TFT通过第三类型的光罩接收曝光装置的第三次曝光，R、G像素上方的遮光层右上方均设有孔；
本实施例中，该第三类型为B像素上方无遮光层，R、G像素上方均有遮光层。R、G像素上方的遮光层右上方均设有孔。
1409、TFT进行第三次显影，形成目标图案。
本实施例中，R像素下方的TFT在进行第三次显影后，R像素下方的TFT的R色光阻的图案上会形成一层较薄的B色光阻的图案；而G像素下方的TFT的G色光阻的图案上还会形成一层较薄的B色光阻的图案；在B像素下方的TFT的G色光阻的图案上会形成一层B色光阻的图案。
这样，由第三次曝光后的三列像素下方的三个TFT上各自形成的光阻图案就构成了目标图案。
本实施例中，由于经过三次曝光后B像素下方的TFT上有三层光阻重叠，因此能够更进一步抵消反射到TFT的半导体As层的反射光，从而能够更进一步保证TFT正常工作。
本申请还提供一个实施例的阵列基板，请参见图15，图15为本申请实施例中阵列基板的一个实施例示意图。
本申请实施例中的阵列基板1500可以采用半灰阶光罩制成，也可以采用狭缝光罩制成，具体此处不做限定。
以下对采用R/B光罩刻蚀制程（包括成膜、曝光、显影及刻蚀工艺）制作阵列基板1500的过程，具体而言：
第一步，在衬底基板1501上形成TFT1502，其中，每个子像素色块下方覆盖有一个TFT1502，而每组像素色块可以包括3个子像素R、G、B，这样，每组像素色块下方可以覆盖有三个TFT1502，每组像素色块也可以包括更多不同的子像素，例如白色，具体此处不做限定。
第二步，在TFT1502上涂布第一光阻；
本实施例中，可以分别在每组的子像素R、G、B上涂布第一光阻。本实施例中，第一光阻为R光阻。
第三步，通过第一类型的R/B光罩对TFT1502上的第一光阻进行第一次曝光。
本实施例中采用的R/B光罩，由相邻的不同时点接收曝光装置曝光时对应的三种类型构成，在光罩的三种类型的其中两个类型中，在两列子像素的遮光层上开设有孔，孔的位置与TFT1502的位置相对应。在第一次曝光时采用的R/B光罩为第一类型，该第一类型为R像素上方无遮光层，G、B像素上方均有遮光层，且在B像素右上方的遮光层上开设有孔。
第四步，对TFT1502进行第一次显影，在TFT1502上形成第一图案；
该第一图案包括1503A、1503C、以及对应于G像素的TFT上的无图案。其中，对应于R像素的TFT上形成为R光阻的1503A，对应于B像素的TFT上形成为R光阻的1503C。
第五步，在TFT1502的第一图案上涂布第二光阻；
本实施例中，第二光阻为G光阻。也就是说，在1503A、1503C上涂布G光阻，并在G像素的TFT的R光阻上涂布G光阻；
第六步，通过第二类型的光罩对第一图案1503A、1503C、以及对应于G像素的TFT上第一光阻上的第二光阻进行第二次曝光；
该第二类型为G像素上方无遮光层，R像素和B像素上方均有遮光层。
第七步，对TFT1502进行第二次显影，在TFT1502的第一图案上形成第二图案；
该第二图案包括G光阻形成的1503B，该1503B是对应于G像素的TFT上而形成，而由于1503A、1503C上没有形成图案，因此该第二图案由1503A、1503B 、1503C构成。
第八步，在TFT1502的第二图案1503A、1503B 、1503C上涂布第三光阻；
本实施例中第三光阻为B光阻。
第九步，通过第三类型的光罩对第二图案1503A、1503B 、1503C进行第三次曝光；
该第三类型为B像素上方无遮光层，R像素和G像素上方均有遮光层，且在R像素和G像素上方的遮光层的右上方均设有孔。
第十步，对TFT1502进行第三次显影，在TFT1502上形成目标图案；
本实施例中，经过第三次显影，在TFT1502的第二图案上形成目标图案，该目标图案包括1503Ax、1503By、1503Cz。也就是说，在第二图案的R像素上的1503A上形成B光阻的1503Ax，在G像素上的1503B上形成B光阻的1503By，在B像素的1503C上形成B光阻的1503Cz。
需要说明的是，该目标图案1503Ax、1503By、1503Cz就是由光阻层1503形成。
第十一步，在光阻层1503上形成一层像素层1504；
本实施例中，目标图案1503Ax、1503By、1503Cz是由光阻层1503形成，因此像素层1504形成于光阻层1503之上。
第十二步，在像素层1504上形成一层配向层1505。
需要说明的是，本申请实施例中，阵列基板1500上可以形成该配向层1505，也可以不形成该配向层1505，具体此处不做限定。
这样，通过上述步骤，就构成了本申请实施例中的阵列基板1500。
需要说明的是，本申请实施例中不仅可以采用R/B光罩，还可以采用前述G/B光罩、R/G光罩，采用这三种光罩均可在TFT1502上形成由两种色阻层叠而成的图案。进一步地，本申请实施例中还可以采用前述R/G/B光罩，采用此光罩可以在TFT1502上形成三种色阻层叠而成的图案。前述图12至14所示的实施例中已有具体描述，此处不再赘述。
本申请实施例中，由于该阵列基板1500上通过可以在不同时间点改变类型的半灰阶光罩或狭缝光罩，从而在阵列基板1500上形成两层或者两层以上光阻的图案，由于阵列基板1500上的两种或者两种以上光阻叠加，能够对反射光起到消光效果，反射光几乎全部被抵消，从而无法影响TFT的电性，因此能够保证TFT正常工作。
在以上描述中，为了解释的目的而列出了各个细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实施例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
尽管已经相对于一个或多个实现方式示出并描述了本申请，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本申请包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。
即，以上所述仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。
另外，在本申请的描述中，需要理解的是，术语 “上”、“下”、“上方”、“下方”、“右上方”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。另外，对于特性相同或相似的结构元件，本申请可采用相同或者不相同的标号进行标识。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了使本领域任何技术人员能够实现和使用本申请，本申请给出了以上描述。在以上描述中，为了解释的目的而列出了各个细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实施例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。

Claims (13)

  1. 一种薄膜晶体管TFT的图案制作方法，其中，所述方法包括：
    所述TFT接收喷涂装置涂布第一光阻；
    所述TFT通过覆盖在所述TFT上的第一类型的光罩接收所述曝光装置的第一次曝光，所述第一类型为第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有所述遮光层，所述第一列子像素、所述第二列子像素、所述第三列子像素组成一组像素色块，所述光罩由相邻的不同时点接收曝光装置曝光时对应的三种类型构成；
    所述TFT进行第一次显影，形成第一图案；
    所述TFT接收所述喷涂装置在所述第一图案上涂布第二光阻；
    所述TFT通过所述第二类型的光罩接收所述曝光装置的第二次曝光，所述第二类型为所述第二列子像素上方无所述遮光层，所述第一列子像素和所述第三列子像素上方均有所述遮光层；
    所述TFT进行第二次显影，形成第二图案；
    所述TFT接收所述喷涂装置在所述第二图案上涂布第三光阻；
    所述TFT通过所述第三类型的光罩接收所述曝光装置的第三次曝光，所述第三类型为所述第三列子像素上方无所述遮光层，所述第一列子像素和所述第二列子像素上方均有所述遮光层；
    所述TFT进行第三次显影，形成目标图案，其中，在所述光罩的所述三种类型的其中两个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔，所述孔的位置与所述TFT的位置相对应。
  2. 根据权利要求1所述的方法，其中，所述在所述光罩的所述三种类型的其中两个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔进一步为：
    在所述三种类型的各个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔。
  3. 根据权利要求1所述的方法，其中，所述孔位于所述遮光层上与所述子像素对应的右上方。
  4. 根据权利要求1所述的方法，其中，所述第一光阻、所述第二光阻以及所述第三光阻依次分别为红色光阻、绿色光阻以及蓝色光阻。
  5. 根据权利要求1所述的方法，其中，所述第一列子像素、所述第二列子像素以及所述第三列子像素依次分别为红色像素、绿色像素以及蓝色像素。
  6. 一种阵列基板，其中，包括：
    衬底基板；
    薄膜晶体管TFT，所述TFT设置在所述衬底基板上，所述TFT包括栅极以及漏极；
    光阻层，所述光阻层覆盖在所述TFT上，所述光阻层由至少两种不同颜色的光阻层构成；
    像素层，所述像素层覆盖在所述光阻层上，所述像素层与所述TFT的漏极电连接。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括：
    配向层，所述配向层覆盖在所述像素层上。
  8. 根据权利要求6所述的阵列基板，其中，在阵列基板的红色子像素中，所述光阻层包括红色光阻层和设置于所述红色光阻层上的蓝色光阻层；在阵列基板的绿色子像素中，所述光阻层包括绿色光阻层和设置于所述绿色光阻层上的蓝色光阻层；在阵列基板的蓝色子像素中，所述光阻层包括蓝色光阻层和设置于所述蓝色光阻层上的绿色光阻层。
  9. 根据权利要求6所述的阵列基板，其中，在阵列基板的红色子像素中，所述光阻层包括红色光阻层和设置于所述红色光阻层上的绿色光阻层；在阵列基板的绿色子像素中，所述光阻层包括绿色光阻层和设置于所述绿色光阻层上的红色光阻层；在阵列基板的蓝色子像素中，所述光阻层包括蓝色光阻层和设置于所述蓝色光阻层上的绿色光阻层。
  10. 根据权利要求6所述的阵列基板，其中，在阵列基板的红色子像素中，所述光阻层包括红色光阻层和设置于所述红色光阻层上的蓝色光阻层；在阵列基板的绿色子像素中，所述光阻层包括红色光阻层、设置于所述红色光阻层上的绿色光阻层、以及设置于所述绿色光阻层上的蓝色光阻层；在阵列基板的蓝色子像素中，所述光阻层包括蓝色光阻层和设置于所述蓝色光阻层上的绿色光阻层。
  11. 一种光罩，其中，包括：
    所述光罩由相邻的不同时点接收曝光装置曝光时对应的三种类型构成，所述三种类型分别为：
    第一类型，所述第一类型为薄膜晶体管TFT通过所述光罩的所述第一类型接收所述曝光装置的第一次曝光时，第一列子像素上方无遮光层，第二列子像素和第三列子像素上方均有所述遮光层，所述第一列子像素、所述第二列子像素、所述第三列子像素组成一组像素色块；
    第二类型，所述第二类型为所述TFT通过所述光罩的所述第二类型接收所述曝光装置的第二次曝光时，所述第二列子像素上方无所述遮光层，所述第一列子像素和所述第三列子像素上方均有所述遮光层；
    第三类型，所述第三类型为所述TFT通过所述光罩的所述第三类型接收所述曝光装置的第三次曝光时，所述第三列子像素上方无所述遮光层，所述第一列子像素和所述第二列子像素上方均有所述遮光层，其中，在所述光罩的所述三种类型的其中两个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔，所述孔的位置与薄膜晶体管TFT的位置相对应，所述TFT为薄膜晶体管显示器TFT-LCD基板上的TFT区域，所述TFT上方覆盖有所述光罩。
  12. 根据权利要求11所述的光罩，其中，所述在所述光罩的所述三种类型的其中两个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔进一步为：
    在所述三种类型的各个类型中，在两列所述子像素的所述遮光层上，至少有一列所述子像素的所述遮光层上开设有孔。
  13. 根据权利要求12所述的光罩，其中，所述孔位于所述遮光层上与所述子像素对应的右上方。
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US20090111199A1 (en) * 2007-10-30 2009-04-30 Chunghwa Picture Tubes, Ltd. Method of manufacturing flat panel display
CN101609227A (zh) * 2009-07-08 2009-12-23 友达光电股份有限公司 彩色滤光层及其制造方法
CN102628973A (zh) * 2011-07-19 2012-08-08 京东方科技集团股份有限公司 一种彩膜基板的制作方法和彩膜基板
CN108363233A (zh) * 2018-02-06 2018-08-03 武汉华星光电技术有限公司 彩色滤光片基板及其制作方法

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