WO2021120623A1 - 一种数据传输方法、装置及相关组件 - Google Patents

一种数据传输方法、装置及相关组件 Download PDF

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Publication number
WO2021120623A1
WO2021120623A1 PCT/CN2020/103999 CN2020103999W WO2021120623A1 WO 2021120623 A1 WO2021120623 A1 WO 2021120623A1 CN 2020103999 W CN2020103999 W CN 2020103999W WO 2021120623 A1 WO2021120623 A1 WO 2021120623A1
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Prior art keywords
bus
phase
data
data transmission
address
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PCT/CN2020/103999
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English (en)
French (fr)
Inventor
王朝辉
刘同强
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苏州浪潮智能科技有限公司
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Priority to US17/785,199 priority Critical patent/US20230009095A1/en
Publication of WO2021120623A1 publication Critical patent/WO2021120623A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

Definitions

  • the present invention relates to the field of AMBA bus, in particular to a data transmission method, device and related components.
  • a processor is integrated inside the BMC (Baseboard Management Controller) chip, and the processor communicates with external devices through a data bus.
  • the ARM processor communicates with external devices through the AMBA (Advanced Microcontroller Bus Architecture) bus.
  • AMBA Advanced Microcontroller Bus Architecture
  • the AHB Advanced High Performance Bus, advanced high performance
  • the data on the bus is transmitted to the APB (Advanced Peripheral Bus, peripheral bus) bus, and the conversion and transmission of the data on the two buses are generally realized through the Bridge.
  • Figure 1 is a transmission timing diagram of the AHB bus
  • Figure 2 is a transmission timing diagram of the APB bus.
  • the address information and Control information transmit data in the next clock cycle, and only one clock cycle is required to transmit address information and control information, while data transmission requires multiple clock cycles.
  • the address is transmitted at the same time for the same transaction.
  • Information, control information and data so it is necessary to buffer the address information and control information sent by the AHB bus in the APB bridge, and wait until all the information and data are received before transmitting, which will use too much buffer isolation. Take up storage space.
  • the purpose of this application is to provide a data transmission method, device, and electronic equipment without the need to cache address information and control information and data, thereby reducing the occupation of storage space.
  • this application provides a data transmission method, which is applied to the APB bridge connecting the APB bus and the AHB bus, including:
  • the transmission is divided into an address phase phase and a data phase phase
  • the address phase phase when the AHB bus meets the address transmission conditions corresponding to the current operation, the address information and control information sent by the AHB bus are transmitted to the APB bus;
  • the received data is sent to the bus corresponding to the current operation, and the bus is the APB bus or the AHB bus.
  • the data transmission method further includes:
  • the current transmission is the address phase phase or the data phase phase.
  • the address transmission condition includes that the HTRANS of the AHB bus is 2'b02, and the HREADY of the AHB bus is valid.
  • the current operation includes a read operation or a write operation
  • the data transmission valid conditions include:
  • PREADY, PENABLE and PSEL are all high level
  • the data transmission valid conditions include:
  • the PREADY is high.
  • the data transmission method further includes:
  • the data transmission method further includes:
  • the data transmission method further includes:
  • the second identifier is valid.
  • the data transmission method further includes:
  • this application also provides a data transmission device, which is applied to an APB bridge connecting the APB bus and the AHB bus, including:
  • the dividing module is used to divide the transmission into an address phase phase and a data phase phase according to the characteristics of the AHB bus;
  • the first transmission module is configured to transmit the address information and control information sent by the AHB bus to the APB bus when the AHB bus meets the address transmission conditions corresponding to the current operation during the address phase phase;
  • the second transmission module is configured to send the received data to the bus corresponding to the current operation when the APB bus meets the valid data transmission conditions corresponding to the current operation, and the bus is the APB Bus or the AHB bus.
  • this application also provides an electronic device, including:
  • Memory used to store computer programs
  • the processor is configured to implement the steps of the data transmission method described in any one of the above when executing the computer program.
  • This application provides a data transmission method, which is applied to the APB bridge connecting the APB bus and the AHB bus.
  • the transmission process is divided into an address phase phase and a data phase phase according to the characteristics of the AHB bus, so as to transmit address information in their respective clock cycles. , Control information and data.
  • this application after receiving the information or data, it will be transmitted when the conditions corresponding to the current phase phase are met, thereby reducing the cache time of address information, control information and data, and thereby reducing the occupation of storage space.
  • This application also provides a data transmission device and electronic equipment, which have the same beneficial effects as the above data transmission method.
  • FIG. 1 is a transmission sequence diagram of an AHB bus provided by this application.
  • FIG. 2 is a transmission sequence diagram of an APB bus provided by this application.
  • FIG. 3 is a schematic structural diagram of a data transmission system provided by this application.
  • FIG. 4 is a flowchart of the steps of a data transmission method provided by this application.
  • FIG. 5 is a timing diagram of a read operation from AHB bus to APB bus provided by this application.
  • FIG. 6 is a timing diagram of a write operation from AHB bus to APB bus provided by this application.
  • FIG. 7 is a multi-transaction sequence diagram of AHB bus to APB bus in the prior art
  • FIG. 8 is a multi-transaction sequence diagram of AHB bus to APB bus provided by this application.
  • FIG. 9 is a schematic structural diagram of a data transmission device provided by this application.
  • FIG. 10 is a schematic structural diagram of an electronic device provided by this application.
  • the core of the present invention is to provide a data transmission method, device and electronic equipment without the need to cache address information and control information and data, thereby reducing the occupation of storage space.
  • FIG. 3 shows a schematic structural diagram of a data transmission system according to an embodiment of the present application.
  • the AHB bus is mounted with high-bandwidth memory interface High-bandwidth Memory Interface, high-performance ARM processor High-performance ARM processor, high-bandwidth RAM chip High-bandwidth on-chip RAM, DMA bus master DMA bus master, APB bus is mounted with UART (Universal Asynchronous Receiver Transmitter), keyboard Keypad, timer Timer, computer PIO (Parts In One, a new type of quasi-computer that can be freely assembled into an all-in-one computer), etc.
  • the AHB bus and the APB bus are connected through the AHB to APB Bridge, which is hereinafter referred to as the APB bridge.
  • the data transmission method provided by this application can be implemented by the APB bridge, which can be regarded as the slave device of the AHB bus and the master device of the APB bus.
  • FIG. 4 is a flow chart of the steps of a data transmission method provided by this application.
  • the data transmission method includes:
  • the transmission is divided into two phases, one is the address phase phase and the other is the data phase phase.
  • the current operation can include a read operation or a write operation.
  • Figure 5 is a timing diagram corresponding to the read operation from the AHB bus to the APB bus.
  • Figure 6 is the write operation from the AHB bus to the APB bus.
  • the timing diagram corresponding to the operation, in the address phase phase for example, when HTRANS is 2'b01 and HREADY is valid (high level), assign HADDR to PADDR, assign HWRITE to PWRITE, and enable PENABLE at the same time, when PREADY After being high, PENABLE returns to low level, HWRITE is the write control signal (ie control information) of the AHB bus, when HWRITE is high, the current operation is a write operation, when HWRITE is low, the current operation is a read operation .
  • the current operation is a read operation, as shown in Figure 5, only the first clock cycle is the address phase phase.
  • the data phase phase wait for the PREADY signal of the APB bus to be high, and the data is valid at the same time.
  • PSEL is high and PENABLE is high, and the data is fed back to HRDATA on the AHB bus.
  • the operation in the address phase phase is the same as the read operation.
  • the operation in the data phase phase you need to wait for the PREADY to be valid, and then directly assign the HWDATA of the AHB bus to the PWDATA on the APB bus. , And make HREADY equal to PREADY.
  • ahb_trans_head is the first identification
  • ahb_trans_data is the second identification.
  • ahb_trans_data The condition for ahb_trans_data to be valid is that it occurs in the second beat of ahb_trans_head.
  • HREADY When HREADY is low and there is no ahb_trans_head, ahb_trans_data will become invalid, and all the above signals are active high.
  • HREADY When both ahb_trans_head and ahb_trans_data are invalid, it will trigger HREADY to go high. That is to say, HREADY is high by default. In other cases, HREADY is equal to PREADY.
  • This application provides a data transmission method, which is applied to the APB bridge connecting the APB bus and the AHB bus.
  • the transmission process is divided into an address phase phase and a data phase phase according to the characteristics of the AHB bus, so as to transmit address information in their respective clock cycles. , Control information and data.
  • the information or data after receiving the information or data, it will be transmitted when the conditions corresponding to the current phase phase are met, thereby reducing the cache time of address information, control information and data, and thereby reducing the occupation of storage space.
  • FIG. 9 is a data transmission device provided by this application, which is applied to an APB bridge connecting the APB bus and the AHB bus, and includes:
  • Dividing module 1 used to divide the transmission into address phase and data phase according to the characteristics of the AHB bus
  • the first transmission module 2 is used to transmit the address information and control information sent by the AHB bus to the APB bus when the AHB bus meets the address transmission conditions corresponding to the current operation in the address phase phase;
  • the second transmission module 3 is used to send the received data to the bus corresponding to the current operation when the APB bus meets the valid data transmission conditions corresponding to the current operation, and the bus is an APB bus or AHB bus.
  • this embodiment first divides the transmission process into an address phase phase and a data phase phase according to the characteristics of the AHB bus, so as to transmit address information, control information and data in their respective clock cycles.
  • the transmission is performed when the conditions corresponding to the current phase phase are met, thereby reducing the cache time of address information, control information and data, and thereby reducing the occupation of storage space.
  • the data transmission device further includes:
  • An identification setting module which is used to set the first identification corresponding to the address phase phase and the second identification corresponding to the data phase phase;
  • the phase phase judgment module is used to judge whether the current transmission is the address phase phase or the data phase phase according to whether the first identification or the second identification is valid.
  • the address transmission condition includes that the HTRANS of the AHB bus is 2'b02, and the HREADY of the AHB bus is valid.
  • the current operation includes a read operation or a write operation
  • the valid conditions for data transmission include:
  • PREADY, PENABLE and PSEL are all high level
  • the valid conditions for data transmission include:
  • the data transmission device further includes:
  • Assignment module used to assign the value of PREADY to HREADY.
  • the phase phase determination module is specifically configured to determine that the current transmission is the address phase phase when the first identifier and the second identifier are valid at the same time.
  • the first flag is valid; the next clock cycle after the first flag is valid, the second flag is determined to be valid.
  • the data transmission device further includes:
  • the trigger module is used to trigger HREADY to switch to a high level when the first identifier and the second identifier are both invalid.
  • the present application also provides an electronic device.
  • FIG. 10 shows a schematic diagram of a composition structure of an electronic device according to an embodiment of the present application.
  • the electronic device 2100 in this embodiment may include: a processor 2101 and memory 2102.
  • the electronic device may further include a communication interface 2103, an input unit 2104, a display 2105, and a communication bus 2106.
  • the processor 2101, the memory 2102, the communication interface 2103, the input unit 2104, and the display 2105 all communicate with each other through the communication bus 2106.
  • the processor 2101 may be a central processing unit (Central Processing Unit, CPU), an application-specific integrated circuit, a digital signal processor, an off-the-shelf programmable gate array, or other programmable logic devices.
  • CPU Central Processing Unit
  • the processor can call programs stored in the memory 2102. Specifically, the processor may perform operations performed on the electronic device side in the following embodiments of the data transmission method.
  • the memory 2102 is used to store one or more programs, the programs may include program codes, and the program codes include computer operation instructions.
  • the memory stores at least programs for implementing the following functions:
  • the transmission is divided into an address phase phase and a data phase phase
  • the address phase phase when the AHB bus meets the address transmission conditions corresponding to the current operation, the address information and control information sent by the AHB bus are transmitted to the APB bus;
  • the received data is sent to the bus corresponding to the current operation, and the bus is the APB bus or the AHB bus.
  • this embodiment first divides the transmission process into an address phase phase and a data phase phase according to the characteristics of the AHB bus, so as to transmit address information, control information and data in their respective clock cycles.
  • the transmission is performed when the conditions corresponding to the current phase phase are met, thereby reducing the cache time of address information, control information and data, and thereby reducing the occupation of storage space.
  • the memory 2102 may include a program storage area and a data storage area, where the program storage area may store an operating system, and an application program required for at least one function (such as a validity judgment function, etc.). ;
  • the data storage area can store the data created during the use of the computer.
  • the memory 2102 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device or other volatile solid-state storage devices.
  • the communication interface 2103 may be an interface of a communication module, such as an interface of a GSM module.
  • This application may also include a display 2104, an input unit 2105, and so on.
  • the structure of the Internet of Things device shown in FIG. 10 does not constitute a limitation on the Internet of Things device in the embodiment of the present application.
  • the electronic device may include more or less components than those shown in FIG. 10, or a combination Certain parts.

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Abstract

一种数据传输方法，应用于连接APB总线和AHB总线的APB桥，包括：根据AHB总线特征将传输分为地址相位阶段和数据相位阶段；在地址相位阶段，当AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；在数据相位阶段，当APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，总线为APB总线或AHB总线。本申请不需要对地址信息和控制信息及数据进行缓存，从而减少对存储空间的占用。本申请还公开了一种数据传输装置及电子设备，具有以上有益效果。

Description

一种数据传输方法、装置及相关组件
本申请要求于2019年12月15日提交至中国专利局、申请号为201911287932.8、发明名称为“一种数据传输方法、装置及相关组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及AMBA总线领域，特别是涉及一种数据传输方法、装置及相关组件。
背景技术
BMC(Baseboard Management Controller，基板管理控制器)芯片内部集成一个处理器，处理器通过数据总线与其外部设备进行通信。以ARM处理器为例，ARM处理器通过AMBA(Advanced Microcontroller Bus Architecture，先进微控制器总线体系结构)总线与外部设备进行通信，根据AMBA协议规范，需要将AHB(Advanced High Performance Bus，高级高性能总线)总线上的数据传输到APB(Advanced Peripheral Bus，外围总线)总线上，一般是通过Bridge实现两条总线上数据的转换和传输。
参照图1和图2所示，图1为AHB总线的传输时序图，图2为APB总线的传输时序图，可见，现有的AHB总线的传输方案中，对于当前事务，先传输地址信息和控制信息，在下一时钟周期再传输数据，且传输地址信息和控制信息仅需要一个时钟周期，而传输数据需要多个时钟周期，现有的APB总线的传输方案中，对同一事务是同时传输地址信息、控制信息及数据的，因此需要在APB桥中，需要对AHB总线发送的地址信息、控制信息进行缓存，等到所有信息和数据均接收完毕后再传输，这样会使用过多的缓存隔离，占用存储空间。
因此，如何提供一种解决上述技术问题的方案是本领域技术人员目前需要解决的问题。
发明内容
本申请的目的是提供一种数据传输方法、装置及电子设备，不需要对 地址信息和控制信息及数据进行缓存，从而减少对存储空间的占用。
为解决上述技术问题，本申请提供了一种数据传输方法，应用于连接APB总线和AHB总线的APB桥，包括：
根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段；
在所述地址相位阶段，当所述AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；
在所述数据相位阶段，当所述APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，所述总线为所述APB总线或所述AHB总线。
优选的，所述根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段之后，该数据传输方法还包括：
设置所述地址相位阶段对应的第一标识及所述数据相位阶段对应的第二标识；
根据所述第一标识或所述第二标识是否有效判断当前传输为所述地址相位阶段或所述数据相位阶段。
优选的，所述地址传输条件包括所述AHB总线的HTRANS为2’b02，且所述AHB总线的HREADY有效。
优选的，所述当前操作包括读操作或写操作；
若当前操作为所述读操作，所述数据传输有效条件包括：
PREADY、PENABLE及PSEL均为高电平；
若当前操作为所述写操作，所述数据传输有效条件包括：
所述PREADY为高电平。
优选的，所述将接收到的数据发送至与当前操作对应的总线的同时，该数据传输方法还包括：
将所述PREADY的值赋予HREADY。
优选的，该数据传输方法还包括：
当所述第一标识和所述第二标识同时有效时，判定当前传输为所述地址相位阶段。
优选的，该数据传输方法还包括：
当HREADY及HTRANS均有效时所述第一标识有效；
所述第一标识有效后的下一时钟周期，所述第二标识有效。
优选的，该数据传输方法还包括：
当所述第一标识和所述第二标识均无效时，触发HREADY转换为高电平。
为解决上述技术问题，本申请还提供了一种数据传输装置，应用于连接APB总线和AHB总线的APB桥，包括：
划分模块，用于根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段；
第一传输模块，用于在所述地址相位阶段，当所述AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；
第二传输模块，用于在所述数据相位阶段，当所述APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，所述总线为所述APB总线或所述AHB总线。
为解决上述技术问题，本申请还提供了一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现如上文任意一项所述数据传输方法的步骤。
本申请提供了一种数据传输方法，应用于连接APB总线和AHB总线的APB桥，首先将传输过程按AHB总线特征分为地址相位阶段和数据相位阶段，以便在各自对应的时钟周期传输地址信息、控制信息及数据，本申请中，收到信息或数据后，满足当前相位阶段对应的条件即进行传输，从而减少对地址信息、控制信息及数据的缓存时间，进而减少对存储空间的占用。本申请还提供了一种数据传输装置及电子设备，具有和上述数据传输方法相同的有益效果。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对现有技术和 实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请所提供的一种AHB总线的传输时序图；
图2为本申请所提供的一种APB总线的传输时序图；
图3为本申请所提供的一种数据传输系统的结构示意图；
图4为本申请所提供的一种数据传输方法的步骤流程图；
图5为本申请所提供的一种AHB总线转APB总线的读操作时序图；
图6为本申请所提供的一种AHB总线转APB总线的写操作时序图；
图7为现有技术中一种AHB总线转APB总线的多事务时序图；
图8为本申请所提供的一种AHB总线转APB总线的多事务时序图；
图9为本申请所提供的一种数据传输装置的结构示意图；
图10为本申请所提供的一种电子设备的结构示意图。
具体实施方式
本发明的核心是提供一种数据传输方法、装置及电子设备，不需要对地址信息和控制信息及数据进行缓存，从而减少对存储空间的占用。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了便于理解本申请的数据传输方法，下面对于本申请的数据传输方法所适用的系统进行介绍，参照图3，其示出了本申请实施例的一种数据传输系统的结构示意图。
如图3所示，AHB总线上挂载有高带宽内存接口High-bandwidth Memory Interface、高性能ARM处理器High-performance ARM processor、高带宽RAM芯片High-bandwidth on-chip RAM、DMA总线主控DMA bus  master，APB总线上挂载有UART(Universal Asynchronous Receiver Transmitter，通用异步收发传输器)、键盘Keypad、计时器Timer、电脑PIO(Parts In One，可自由组装成一体电脑的新型准电脑)等外设，AHB总线和APB总线通过AHB to APB Bridge桥连接，以下简称APB桥。本申请所提供的数据传输方法具体可以通过APB桥实现，APB桥可看作AHB总线的从设、看作APB总线的主设。
请参照图4，图4为本申请所提供的一种数据传输方法的步骤流程图，该数据传输方法包括：
S101：根据AHB总线特征将传输分为地址相位阶段和数据相位阶段；
S102：在地址相位阶段，当AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；
S103：在数据相位阶段，当APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，总线为APB总线或AHB总线。
具体的，根据AHB总线的特征，将传输分为两个阶段，一个为地址相位阶段，一个为数据相位阶段。本实施例中，当前操作可以包括读操作或写操作，参照图5、图6所示，图5为AHB总线转APB总线的读操作对应的时序图，图6为AHB总线转APB总线的写操作对应的时序图，在地址相位阶段，例如当HTRANS为2’b01，同时HREADY有效(高电平)的情况下，将HADDR赋值给PADDR，将HWRITE赋值给PWRITE，同时使能PENABLE，当PREADY为高电平以后，PENABLE恢复为低电平，HWRITE为AHB总线的写控制信号(即控制信息)，HWRITE为高电平时，当前操作为写操作，HWRITE为低电平时，当前操作为读操作。
具体的，若当前操作为读操作，参照图5所示，只有第一个时钟周期为地址相位阶段，在数据相位阶段，等待APB总线的PREADY信号为高电平，同时数据有效，数据有效即PSEL为高电平且PENABLE为高电平，将数据反馈到AHB总线的HRDATA上。
具体的，若当前操作为写操作，参照图6所示，地址相位阶段的操作和读操作相同，在数据相位阶段，需要等待PREADY有效后，将AHB总 线的HWDATA直接赋值给APB总线上的PWDATA，并使HREADY等于PREADY。
进一步的，在将传输分为地址相位阶段和数据相位阶段后，分别用ahb_trans_head和ahb_trans_data进行标识，其中ahb_trans_head为第一标识，ahb_trans_data为第二标识，当ahb_trans_head有效，且ahb_trans_data无效时，判定传输当前处于地址相位阶段，当ahb_trans_data有效，且ahb_trans_head无效时，判定传输当前处于数据相位阶段。ahb_trans_head有效的条件为HREADY有效，且HTRANS有效。ahb_trans_data有效的条件是发生在ahb_trans_head的第二拍，当HREADY为低电平并且没有ahb_trans_head时，ahb_trans_data就会变为无效，以上所有信号均为高电平有效。当ahb_trans_head和ahb_trans_data都无效的时候，会触发HREADY变为高电平。也就是说HREADY默认为高电平，其他情况下，HREADY等于PREADY。
可以理解的是，当AHB总线进行如图7所示的多事务传输时，当前事务的数据相位阶段，同时也是下一个事务的地址相位阶段，传输过程容易出现bug，因此，当ahb_trans_data与ahb_trans_head同时有效时，即图8中的第三周期，本申请采取地址相位阶段优先的方式，即在第3周期，将HADDR赋值给PADDR，所以在第4周期的PADDR变为地址B，从而达到区分事务的地址相位阶段和数据相位阶段的目的。
本申请提供了一种数据传输方法，应用于连接APB总线和AHB总线的APB桥，首先将传输过程按AHB总线特征分为地址相位阶段和数据相位阶段，以便在各自对应的时钟周期传输地址信息、控制信息及数据，本申请中，收到信息或数据后，满足当前相位阶段对应的条件即进行传输，从而减少对地址信息、控制信息及数据的缓存时间，进而减少对存储空间的占用。
请参照图9，图9为本申请所提供的一种数据传输装置，应用于连接APB总线和AHB总线的APB桥，包括：
划分模块1，用于根据AHB总线特征将传输分为地址相位阶段和数据 相位阶段；
第一传输模块2，用于在地址相位阶段，当AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；
第二传输模块3，用于在数据相位阶段，当APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，总线为APB总线或AHB总线。
可见，本实施例首先将传输过程按AHB总线特征分为地址相位阶段和数据相位阶段，以便在各自对应的时钟周期传输地址信息、控制信息及数据，本申请中，收到信息或数据后，满足当前相位阶段对应的条件即进行传输，从而减少对地址信息、控制信息及数据的缓存时间，进而减少对存储空间的占用。
作为一种优选的实施例，该数据传输装置还包括：
标识设置模块，用于设置地址相位阶段对应的第一标识及数据相位阶段对应的第二标识；
相位阶段判断模块，用于根据第一标识或第二标识是否有效判断当前传输为地址相位阶段或数据相位阶段。
作为一种优选的实施例，地址传输条件包括AHB总线的HTRANS为2’b02，且AHB总线的HREADY有效。
作为一种优选的实施例，当前操作包括读操作或写操作；
若当前操作为读操作，数据传输有效条件包括：
PREADY、PENABLE及PSEL均为高电平；
若当前操作为写操作，数据传输有效条件包括：
PREADY为高电平。
作为一种优选的实施例，该数据传输装置还包括：
赋值模块，用于将PREADY的值赋予HREADY。
作为一种优选的实施例，相位阶段判断模块，具体用于当第一标识和第二标识同时有效时，判定当前传输为地址相位阶段。
作为一种优选的实施例，当HREADY及HTRANS均有效时，第一标 识有效；第一标识有效后的下一时钟周期，判定第二标识有效。
作为一种优选的实施例，该数据传输装置还包括：
触发模块，用于当第一标识和第二标识均无效时，触发HREADY转换为高电平。
另一方面，本申请还提供了一种电子设备，如参见图10，其示出了本申请实施例一种电子设备的一种组成结构示意图，本实施例的电子设备2100可以包括：处理器2101和存储器2102。
可选的，该电子设备还可以包括通信接口2103、输入单元2104和显示器2105和通信总线2106。
处理器2101、存储器2102、通信接口2103、输入单元2104、显示器2105、均通过通信总线2106完成相互间的通信。
在本申请实施例中，该处理器2101，可以为中央处理器(Central Processing Unit，CPU)，特定应用集成电路，数字信号处理器，现成可编程门阵列或者其他可编程逻辑器件等。
该处理器可以调用存储器2102中存储的程序。具体的，处理器可以执行以下数据传输方法的实施例中电子设备侧所执行的操作。
存储器2102中用于存放一个或者一个以上程序，程序可以包括程序代码，程序代码包括计算机操作指令，在本申请实施例中，该存储器中至少存储有用于实现以下功能的程序：
根据AHB总线特征将传输分为地址相位阶段和数据相位阶段；
在地址相位阶段，当AHB总线满足当前操作对应的地址传输条件，将AHB总线发送的地址信息和控制信息传输到APB总线上；
在数据相位阶段，当APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，总线为APB总线或AHB总线。
可见，本实施例首先将传输过程按AHB总线特征分为地址相位阶段和数据相位阶段，以便在各自对应的时钟周期传输地址信息、控制信息及数据，本申请中，收到信息或数据后，满足当前相位阶段对应的条件即进 行传输，从而减少对地址信息、控制信息及数据的缓存时间，进而减少对存储空间的占用。
在一种可能的实现方式中，该存储器2102可包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、以及至少一个功能(比如有效性判断功能等)所需的应用程序等；存储数据区可存储根据计算机的使用过程中所创建的数据。
此外，存储器2102可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件或其他易失性固态存储器件。
该通信接口2103可以为通信模块的接口，如GSM模块的接口。
本申请还可以包括显示器2104和输入单元2105等等。
当然，图10所示的物联网设备的结构并不构成对本申请实施例中物联网设备的限定，在实际应用中电子设备可以包括比图10所示的更多或更少的部件，或者组合某些部件。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的状况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种数据传输方法，其特征在于，应用于连接APB总线和AHB总线的APB桥，包括：
    根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段；
    在所述地址相位阶段，当所述AHB总线满足当前操作对应的地址传输条件，将所述AHB总线发送的地址信息和控制信息传输到所述APB总线上；
    在所述数据相位阶段，当所述APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，所述总线为所述APB总线或所述AHB总线。
  2. 根据权利要求1所述的数据传输方法，其特征在于，所述根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段之后，该数据传输方法还包括：
    设置所述地址相位阶段对应的第一标识及所述数据相位阶段对应的第二标识；
    根据所述第一标识或所述第二标识是否有效判断当前传输为所述地址相位阶段或所述数据相位阶段。
  3. 根据权利要求1所述的数据传输方法，其特征在于，所述地址传输条件包括所述AHB总线的HTRANS为2’b02，且所述AHB总线的HREADY有效。
  4. 根据权利要求1所述的数据传输方法，其特征在于，所述当前操作包括读操作或写操作；
    若当前操作为所述读操作，所述数据传输有效条件包括：
    PREADY、PENABLE及PSEL均为高电平；
    若当前操作为所述写操作，所述数据传输有效条件包括：
    所述PREADY为高电平。
  5. 根据权利要求1所述的数据传输方法，其特征在于，所述将接收到的数据发送至与当前操作对应的总线的同时，该数据传输方法还包括：
    将PREADY的值赋予HREADY。
  6. 根据权利要求2所述的数据传输方法，其特征在于，该数据传输方法还包括：
    当所述第一标识和所述第二标识同时有效时，判定当前传输为所述地址相位阶段。
  7. 根据权利要求2所述的数据传输方法，其特征在于，该数据传输方法还包括：
    当HREADY及HTRANS均有效时所述第一标识有效；
    所述第一标识有效后的下一时钟周期，所述第二标识有效。
  8. 根据权利要求7所述的数据传输方法，其特征在于，该数据传输方法还包括：
    当所述第一标识和所述第二标识均无效时，触发HREADY转换为高电平。
  9. 一种数据传输装置，其特征在于，应用于连接APB总线和AHB总线的APB桥，包括：
    划分模块，用于根据所述AHB总线特征将传输分为地址相位阶段和数据相位阶段；
    第一传输模块，用于在所述地址相位阶段，当所述AHB总线满足当前操作对应的地址传输条件，将所述AHB总线发送的地址信息和控制信息传输到所述APB总线上；
    第二传输模块，用于在所述数据相位阶段，当所述APB总线满足当前操作对应的数据传输有效条件，将接收到的数据发送至与当前操作对应的总线，所述总线为所述APB总线或所述AHB总线。
  10. 一种电子设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1-8任意一项所述数据传输方法的步骤。
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