WO2021114384A1 - 薄膜晶体管及其制备方法、 cmos 反相器 - Google Patents

薄膜晶体管及其制备方法、 cmos 反相器 Download PDF

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WO2021114384A1
WO2021114384A1 PCT/CN2019/127484 CN2019127484W WO2021114384A1 WO 2021114384 A1 WO2021114384 A1 WO 2021114384A1 CN 2019127484 W CN2019127484 W CN 2019127484W WO 2021114384 A1 WO2021114384 A1 WO 2021114384A1
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thin film
film transistor
channel
carbon nanotubes
manufacturing
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PCT/CN2019/127484
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French (fr)
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谢华飞
陈书志
李佳育
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Tcl华星光电技术有限公司
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Priority to US16/627,352 priority Critical patent/US11289543B2/en
Publication of WO2021114384A1 publication Critical patent/WO2021114384A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/472—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present disclosure relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, and a CMOS inverter.
  • CNT carbon nanotube thin film transistor
  • CNT-TFT In CNT-TFT technology, its mobility and on-state current have obvious advantages, and the process temperature and process complexity are relatively low.
  • the preparation of CNT-TFT is to use CNT solution to prepare CNT thin film on the substrate. The adsorption of water or oxygen in the air results in the prepared CNT-TFT as a p-type transistor.
  • the threshold value of the transistor prepared in this way is poor in controllability.
  • the threshold control method for CNT-TFT is mainly to change the work function of the gate electrode, to dope the channel, or to control the thickness of the dielectric oxide layer and the interface charge. Only by changing the work function of the gate electrode, the ability to control the threshold voltage is limited, and the controllability of the channel doping is poor, and it is difficult to obtain repeatable and reliable results.
  • the present disclosure provides a thin film transistor and a manufacturing method thereof, so as to solve the problems that the existing carbon nanotube thin film transistor cannot effectively control its threshold voltage and the control reliability is poor.
  • a method for manufacturing a thin film transistor including the following steps:
  • S10 preparing a dielectric layer on the base substrate, and preparing the source electrode, the drain electrode and the gate electrode of the thin film transistor on the dielectric layer, and the thickness of the dielectric layer is 4.5 nm to 5.5 nm;
  • S11 preparing carbon nanotubes, and depositing the carbon nanotubes into the first channel of the thin film transistor, the first channel being arranged between the source electrode and the drain electrode;
  • S12 Prepare ion glue, and deposit the ion glue in the second channel of the thin film transistor, the second channel is arranged between the drain and the gate, and the ion glue is sprayed Ink printing, low-speed spin coating or drip coating processes are arranged in the second channel;
  • the thickness of the gate is 4.5 nm to 5.5 nm.
  • the carbon nanotubes are arranged in the first channel through a printing process.
  • the step S12 further includes the following steps:
  • S121 Mix the polystyrene-polymethyl methacrylate, 1-ethyl-3-methylimidazoline bis(trifluoromethylsulfonyl)imide, ethyl acetate and the dopant according to the mass ratio, and at the same time Add a stirring magnet and stir to obtain an ion gel solution.
  • the mass fraction content of the polystyrene-polymethyl methacrylate is 0.3wt%-0.7wt%, and the 1-ethyl-3-methylimidazoline bis(trifluoromethyl)
  • the mass fraction content of sulfonyl)imine is 9.3 wt% to 9.7% by weight, and the mass fraction content of the dopant is 90 wt%.
  • a thin film transistor including:
  • a dielectric layer, the dielectric layer is disposed on the base substrate;
  • a semiconductor layer, the semiconductor layer is disposed on the dielectric layer
  • the semiconductor layer further includes a source electrode, a drain electrode, and a gate electrode.
  • a first channel is arranged between the source electrode and the drain electrode, and carbon nanotubes are arranged in the first channel.
  • a second channel is arranged between the electrode and the gate, and ion glue is arranged in the second channel, and the ion glue covers the semiconductor layer at the same time.
  • the material of the dielectric layer includes hafnium oxide, and the material of the source electrode and the drain electrode includes gold.
  • the ion glue includes a front-end copolymer, ethyl acetate, and a dopant.
  • a method for manufacturing a thin film transistor including the following steps:
  • S10 preparing a dielectric layer on the base substrate, and preparing the source, drain, and gate of the thin film transistor on the dielectric layer;
  • S11 preparing carbon nanotubes, and depositing the carbon nanotubes into the first channel of the thin film transistor, the first channel being arranged between the source electrode and the drain electrode;
  • S12 preparing an ion glue, and depositing the ion glue into a second channel of the thin film transistor, the second channel being arranged between the drain and the gate;
  • the thickness of the dielectric layer is 4.5 nm to 5.5 nm
  • the thickness of the gate is 4.5 nm to 5.5 nm
  • the carbon nanotubes are arranged in the first channel through a printing process.
  • the ionic glue is disposed in the second channel by inkjet printing, low-speed spin coating or drop coating process.
  • the content of the ionomer is selected to be 30 ⁇ L-50 ⁇ L.
  • the step S12 further includes the following steps:
  • S121 Mix the polystyrene-polymethyl methacrylate, 1-ethyl-3-methylimidazoline bis(trifluoromethylsulfonyl)imide, ethyl acetate and the dopant according to the mass ratio, and at the same time Add a stirring magnet and stir to obtain an ion gel solution.
  • the mass fraction content of the polystyrene-polymethyl methacrylate is 0.3wt%-0.7wt%, and the 1-ethyl-3-methylimidazoline bis(trifluoromethyl)
  • the mass fraction content of sulfonyl)imine is 9.3 wt% to 9.7% by weight, and the mass fraction content of the dopant is 90 wt%.
  • the carbon nanotubes when they are deposited, they are prepared by an aerosol printer or a drop coating process.
  • the carbon nanotubes are dried.
  • step S10 when the source electrode, the drain electrode and the gate electrode are prepared, one-step photolithography exposure and electron beam evaporation techniques are used for preparation.
  • the present disclosure provides a thin film transistor and a preparation method thereof.
  • the gate layer of the thin film transistor is used by ion glue.
  • carbon nanotubes and gold source/drain electrodes are also arranged in the semiconductor layer, and doping is added to the ion glue.
  • the threshold voltage of carbon nanotube thin film transistors can be effectively controlled.
  • FIG. 1 is a schematic diagram of the structure of a thin film transistor according to an embodiment of the disclosure
  • FIG. 2 is a method for manufacturing a thin film transistor provided by an embodiment of the disclosure
  • FIG. 3 is a graph showing the transfer performance of a thin film transistor according to an embodiment of the disclosure.
  • FIG. 4 is a schematic plan view of a CMOS inverter composed of bipolar CNT-TFT provided by an embodiment of the disclosure
  • FIG. 5 is a performance test diagram of the thin film transistor of the inverter of the disclosed embodiment.
  • FIG. 1 is a schematic diagram of the structure of the thin film transistor of the embodiment of the disclosure.
  • the thin film transistor includes a base substrate 100, a dielectric layer 101, an ion glue 106, and a semiconductor layer.
  • the dielectric layer 101 is disposed on the base substrate 100, and the semiconductor layer further includes a metal source 102, a metal drain 103, and a metal gate 104.
  • a first channel is provided between the metal source 102 and the metal drain 103, and a second channel is provided between the metal drain 103 and the metal gate 104.
  • Carbon nanotubes 105 are arranged in the first channel, and ion glue 106 is arranged in the second channel, and the ion glue 106 covers the entire semiconductor layer at the same time.
  • the embodiment of the present disclosure is a carbon nanotube thin film transistor with a side gate structure.
  • the carbon nanotube 105 and the ionomer 106 can controllably adjust the threshold voltage and polarity of the thin film transistor.
  • the present disclosure constructs Two types of CMOS inverter circuits. Specifically, one is to construct a CMOS inverter with the aid of two carbon tube transistors CNT-TFT that exhibit bipolarity after adjusting the threshold; the other is to use traditional n-type and p-type unipolar CNTs.
  • the metal source 102, the metal drain 103, the side gate 104 and the connecting line are usually on the same plane.
  • the source 102 and the drain electrode 103 can be prepared at the same time. Electrodes and connecting wires.
  • the source electrode 102, the drain electrode 103, the side gate electrode 104, and the connection line of the CMOS inverter are prepared by one step of photolithography and electron beam evaporation on the same plane, and then a layer of semiconductor carbon nanotubes is deposited on the transistor channel region 105, and then deposit ion gel 106 with different dopant content by printing, and finally construct a CNT-TFT with a controllable threshold.
  • the ion gel 106 used as a thin film transistor with a side gate structure is used to form the insulating layer material of the transistor on the one hand; on the other hand, the ion gel 106 containing dopants can dope the underlying semiconductor carbon nanotube 105. Therefore, the final side gate transistor exhibits a typical bipolar transistor curve instead of a single p-type curve. By adjusting the dopant content, transistor devices with different turn-on voltages are obtained.
  • the material of the dielectric layer 101 in the thin film transistor in the embodiment of the present disclosure includes hafnium oxide, and the material of the metal source/drain electrode includes gold; the ionomer 106 includes front-stage copolymer, organic amine substance and dopant; carbon
  • the material of the nanotube 105 includes any one or more of polythiophene derivatives, polyfluorene derivatives, and polymetaphenylene acetylene derivatives.
  • FIG. 2 is a method for manufacturing a thin film transistor provided by an embodiment of the disclosure.
  • the preparation method includes the following steps:
  • S10 Prepare a dielectric layer on the base substrate, and prepare source/drain electrodes and gates of thin film transistors on the dielectric layer.
  • a certain thickness of hafnium oxide is deposited on the base substrate, the thickness of the hafnium oxide is 4.5nm ⁇ 5.5nm, preferably the thickness is 5nm, and a certain thickness of titanium/gold is deposited by traditional photolithography and electron beam evaporation techniques.
  • Source/drain electrodes preferably, when titanium is selected, the thickness is 5nm, when gold is selected, the thickness is 50nm, and side gate electrodes
  • the base substrate includes Si substrate, polyethylene terephthalate substrate or glass substrate .
  • S11 preparing carbon nanotubes, and depositing the carbon nanotubes in the first channel of the thin film transistor, the first channel being arranged between the source electrode and the drain electrode.
  • the carbon nanotubes are P2 single-walled carbon tubes with large diameters.
  • the polymer includes any one or more combinations of polythiophene derivatives, polyfluorene and/or polyfluorene derivatives, and polymetaphenylene acetylene derivatives, but is not limited thereto.
  • the concentration of the polymer in the carbon nanotube solution is controlled between 0.0001 wt% and 0.5 wt%.
  • S12 preparing an ion glue, and depositing the ion glue into a second channel of the thin film transistor, the second channel being arranged between the drain and the gate.
  • an ion gel solution is prepared, and the ion gel of the embodiment of the disclosure is obtained from the ion gel solution.
  • the components of the ionic glue include front-end copolymers, organic amines and dopants.
  • the preferred front-end copolymers include polystyrene-polymethyl methacrylate (PS-PMMA) with a mass fraction content of 0.3 wt.
  • organic amines are particle liquid, including 1-ethyl-3-methylimidazoline bis(trifluoromethylsulfonyl)imine, the mass fraction content of which is 9.3wt%-9.7wt% ;
  • the solvent is preferably ethyl acetate, and its mass fraction content is 90% by weight.
  • the dopant is preferably triethanolamine (TEOA).
  • TEOA triethanolamine
  • the dopant (TEOA) solution take an appropriate amount of dopant in methanol or ethanol at room temperature and heat it in a water bath at 70°C for ten minutes to prepare 1M and 4M solutions for later use. Before use, take 30 ⁇ 200 ⁇ L dopant solution into 1.5ml ion gel each time.
  • the ion glue is set in the second channel by inkjet printing, low-speed spin coating or drop coating process.
  • the source/drain electrodes and the side gate electrode are prepared at the same time through a one-step photolithography exposure and electron beam evaporation technique, or after the carbon nanotubes are deposited, the side gate electrode is deposited by inkjet printing.
  • the process of preparing the ion gel take an appropriate amount, preferably 1.5 ml of the ion gel solution as ink, and use an aerosol printer to accurately deposit the ion gel on the channel area and connect it to the gate electrode with the source/drain electrodes on the same horizontal plane. If spin-coating or drip-coating technology is used, take an appropriate amount (preferably 30-50 ⁇ L ion gel solution) for low-speed spin-coating (500 rpm), or drop-coating directly to cover all electrodes. The ionomer containing dopant is finally baked at 105°C for 3 minutes.
  • FIG. 3 is a graph showing the transfer performance of the thin film transistor according to an embodiment of the disclosure.
  • a in FIG. 3 is a pure ionic glue
  • b in FIG. 3 is added with a different content of dopants.
  • the prepared carbon nanotube transistor device with a side gate structure exhibits p-type conductivity
  • the bipolar performance in b is shown with hysteresis Smaller, higher switching ratio, adjustable threshold and conductivity characteristics.
  • the 1-5 curves represent the transfer curves of transistors prepared with different dopants.
  • the threshold voltages of the transistors are different with different dopant contents. As the concentration of the dopant increases, the threshold voltage will gradually shift to the left, which is very beneficial to the subsequent construction of a CMOS inverter circuit with excellent performance. In turn, the content of the dopant can be adjusted according to the threshold voltage requirement of the transistor for the circuit to form a transistor device with the optimal threshold voltage.
  • FIG. 4 is a plan view of a CMOS inverter composed of bipolar CNT-TFT provided by an embodiment of the disclosure.
  • the inverter in Figure 4 includes two bipolar CNT-TFTs.
  • the CMOS inverter includes: a side gate 1, an inverter output connection terminal 2, a source 3, a drain 4, and an ion glue 5.
  • the electrodes and electrode connecting wires in the figure are all prepared by photolithography and electron beam evaporation. Specifically, first, semiconductor carbon nanotubes are deposited at the source/drain electrode channels by printing, drip coating, spin coating, and immersion.
  • the CNT-TFT constitutes the CMOS inverter provided by the embodiment of the present disclosure.
  • FIG. 5 is a transistor performance test diagram of the inverter according to an embodiment of the disclosure.
  • a in Fig. 5 is the transistor transfer performance curve of the inverter
  • b in Fig. 5 is a schematic diagram of the NOT gate of a single CMOS inverter
  • c in Fig. 5 and d in Fig. 5 are inverter circuits The input-output voltage curve and gain graph. It can be seen from a in FIG. 5 that the prepared carbon nanotube transistor devices with a gold side gate structure all exhibit bipolar performance, with small hysteresis, high switching ratio, and large output current.
  • the performance of the CMOS inverter circuit provided by the embodiment of the present disclosure is excellent.
  • the embodiment of the present disclosure provides another CMOS inverter, which is different from the bipolar CNT-TFT in FIG. 4 in that: the CMOS inverter of this embodiment uses a bipolar CNT-TFT and a p -Type CNT-TFT structure.
  • the construction process and process of this inverter are the same as those of the inverter in the embodiment in FIG. 4, and will not be repeated here.
  • the ion gel composition of two different CNT-TFTs There are differences.
  • One ion glue uses ion glue that does not contain dopants. Transistors built with this ion glue usually exhibit p-type characteristics as a PMOS tube. The other ion glue uses dopants.

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  • Engineering & Computer Science (AREA)
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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制备方法、CMOS反相器，薄膜晶体管包括衬底基板（100）、介质层（101）、半导体层，半导体层的源极（102）与漏极（103）之间设置有第一沟道，第一沟道中设置有碳纳米管（105），漏极（103）与栅极（104）之间设置有第二沟道，第二沟道中设置有离子胶（106）。通过调控离子胶（106）的组成成分和掺杂剂的含量，有效的对碳纳米管薄膜晶体管的阈值电压控制。

Description

薄膜晶体管及其制备方法、CMOS反相器
本申请要求于2019年12月12日提交中国专利局、申请号为201911273124.6、发明名称为“薄膜晶体管及其制备方法、CMOS反相器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本揭示涉及显示技术领域，尤其涉及一种薄膜晶体管及其制备方法、CMOS反相器。
 背景技术
近年来，碳纳米管薄膜晶体管引起人们越来越多的关注。其原因在于相比现有的薄膜晶体管技术，单层碳纳米管（CNT）薄膜晶体管（TFT）器件在性能和制备工艺方面具有明显的优势。
CNT-TFT技术中，其迁移率、开态电流具有明显优势，且工艺温度以及工艺复杂度都较低。但是在现有CNT-TFT薄膜晶体管产品中，还存在许多问题，其中一个就是CNT-TFT的阈值控制问题，通常CNT-TFT的制备是利用CNT溶液在基底上制备出CNT薄膜，由于CNT极易吸附空气中的水或氧，导致制备出的CNT-TFT为p-型晶体管。同时，由于CNT材料制备工艺过程中存在的不理想因素，这样制备出的晶体管阈值可控性较差。并且，现有的CNT-TFT产品中，对CNT-TFT的阈值控制手段主要是改变栅电极的功函数，对沟道掺杂，或者对介电氧化层厚度及界面电荷的控制等。仅靠改变栅电极的功函数对阈值电压调控能力有限，对沟道掺杂可控性较差，难以得到重复性可靠的结果。
因此需要对现有技术中的问题提出解决方法。
 技术问题
综上所述，现有的碳纳米管薄膜晶体管产品，不能有效的对其阈值电压进行控制，并且阈值电压控制能力有限，难以获得重复性可靠的控制结果，因此，需要提出进一步的解决及完善方案。
 技术解决方案
为解决上述问题，本揭示提供一种薄膜晶体管及其制备方法，以解决现有的碳纳米管薄膜晶体管不能有效的对其阈值电压进行控制，控制可靠性差等问题。
为解决上述技术问题，本揭示实施例提供的技术方案如下：
根据本揭示实施例的第一方面，提供一种薄膜晶体管的制备方法，包括如下步骤：
S10：在衬底基板上制备介质层，并在所述介质层上制备薄膜晶体管的源极、漏极以及栅极，所述介质层的厚度为4.5nm~5.5nm；
S11：制备碳纳米管，并将所述碳纳米管沉积到所述薄膜晶体管的第一沟道中，所述第一沟道设置在所述源极与所述漏极之间；
S12：制备离子胶，并将所述离子胶沉积到所述薄膜晶体管的第二沟道中，所述第二沟道设置在所述漏极与所述栅极之间，所述离子胶通过喷墨打印、低速旋涂或滴涂工艺设置在所述第二沟道中；
S13：干燥处理所述离子胶，得到所述薄膜晶体管。
根据本揭示一实施例，所述栅极的厚度为4.5nm~5.5nm。
根据本揭示一实施例，所述碳纳米管通过印刷工艺设置在所述第一沟道中。
根据本揭示一实施例，所述步骤S12中还包括如下步骤：
S121：将聚苯乙烯-聚甲基丙烯酸甲酯、1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺、乙酸乙酯以及掺杂剂按质量比例混合，同时添加搅拌磁子，进行搅拌，获得离子胶溶液。
根据本揭示一实施例，所述聚苯乙烯-聚甲基丙烯酸甲酯的质量分数含量为0.3wt%-0.7wt％，所述1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺的质量分数含量为9.3wt%-9.7wt％，所述掺杂剂的质量分数含量为90wt％。
根据本揭示实施例的第二方面，还提供一种薄膜晶体管，包括：
衬底基板；
介质层，所述介质层设置在所述衬底基板上；以及
半导体层，所述半导体层设置在所述介质层上；
其中，所述半导体层还包括源极、漏极以及栅极，所述源极与所述漏极之间设置有第一沟道，所述第一沟道中设置有碳纳米管，所述漏极与所述栅极之间设置有第二沟道，所述第二沟道中设置有离子胶，所述离子胶同时覆盖所述半导体层。
根据本揭示一实施例，所述介质层的材料包括氧化铪，所述源极和漏极的材料包括金。
根据本揭示一实施例，所述离子胶包括前段共聚物、乙酸乙酯以及掺杂剂。
根据本揭示实施例的第三方面，还提供一种薄膜晶体管的制备方法，包括如下步骤：
S10：在衬底基板上制备介质层，并在所述介质层上制备薄膜晶体管的源极、漏极以及栅极；
S11：制备碳纳米管，并将所述碳纳米管沉积到所述薄膜晶体管的第一沟道中，所述第一沟道设置在所述源极与所述漏极之间；
S12：制备离子胶，并将所述离子胶沉积到所述薄膜晶体管的第二沟道中，所述第二沟道设置在所述漏极与所述栅极之间；
S13：干燥处理所述离子胶，得到所述薄膜晶体管。
根据本揭示一实施例，所述介质层的厚度为4.5nm~5.5nm，所述栅极的厚度为4.5nm~5.5nm。
根据本揭示一实施例，所述碳纳米管通过印刷工艺设置在所述第一沟道中。
根据本揭示一实施例，所述离子胶通过喷墨打印、低速旋涂或滴涂工艺设置在所述第二沟道中。
根据本揭示一实施例，所述低速旋涂工艺中，选取所述离子胶的含量为30μL~50μL。
根据本揭示一实施例，所述步骤S12中还包括如下步骤：
S121：将聚苯乙烯-聚甲基丙烯酸甲酯、1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺、乙酸乙酯以及掺杂剂按质量比例混合，同时添加搅拌磁子，进行搅拌，获得离子胶溶液。
根据本揭示一实施例，所述聚苯乙烯-聚甲基丙烯酸甲酯的质量分数含量为0.3wt%-0.7wt％，所述1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺的质量分数含量为9.3wt%-9.7wt％，所述掺杂剂的质量分数含量为90wt％。
根据本揭示一实施例，所述步骤S11中，对所述碳纳米管进行沉积时，通过气溶胶打印机或滴涂工艺进行制备。
根据本揭示一实施例，每次打印或滴涂完毕后，60℃烘烤2min，用甲苯洗净，并在60℃温度下烘烤2min，重复两到三次。
根据本揭示一实施例，碳纳米管沉积完成后，对所述碳纳米管进行干燥。
根据本揭示一实施例，所述步骤S10中，在制备所述源极、所述漏极和所述栅极时，采用一步光刻曝光和电子束蒸发技术进行制备。
 有益效果
综上所述，本揭示实施例的有益效果为：
本揭示提供一种薄膜晶体管及其制备方法，通过离子胶作为薄膜晶体管的栅极层，同时，在半导体层中还设置碳纳米管以及金源/漏电极，并且在离子胶中还添加掺杂剂，进一步加强半导体层中的离子流动情况，通过调控离子胶栅极层的组成成分和含量，进而有效的对碳纳米管薄膜晶体管的阈值电压进行控制。
 附图说明
图1为本揭示实施例的薄膜晶体管的结构示意图；
图2为本揭示实施例提供的薄膜晶体管的制备方法；
图3为本揭示实施例的薄膜晶体管的转移性能曲线图；
图4为本揭示实施例提供的双极性CNT-TFT构成的CMOS反相器的平面示意图；
图5为本揭示实施例的反相器的薄膜晶体管性能测试图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
在本揭示的实施例中，如图1所示，图1为本揭示实施例的薄膜晶体管的结构示意图。所述薄膜晶体管包括衬底基板100、介质层101、离子胶106以及半导体层。
具体的，介质层101设置在衬底基板100上，半导体层还包括金属源极102、金属漏极103以及金属栅极104。在金属源极102与金属漏极103之间设置有第一沟道，金属漏极103与金属栅极104之间设置有第二沟道，其中，在本揭示实施例提供的薄膜晶体管中，第一沟道中设置有碳纳米管105，第二沟道中设置有离子胶106，并且所述离子胶106同时覆盖整个半导体层。
本揭示实施例中为一侧栅结构的碳纳米管薄膜晶体管，碳纳米管105与离子胶106可对薄膜晶体管的阈值电压和极性进行可控调节，同时，本揭示在此基础上构建了两类CMOS反相器电路。具体的，一种是借助于调节阈值后呈现双极性的两个碳管晶体管CNT-TFT的器件构建CMOS反相器；另一种是采用传统的n-type和p-type单极性CNT-TFT构成的反相器，并利用阈值调节后的双极性晶体管替代n-type晶体管，两类反相器均利用CMOS反相器的连接方式，即可形成具有明显CMOS反相器性能的逻辑电路。
在薄膜晶体管结构的制备过程中，金属源极102、金属漏极103以及侧栅极104和连接线均通常在同一平面上，在制备源极102和漏电极103的同时可一并制备出所有电极和连接线。具体为首先在同一平面通过一步光刻和电子束蒸发制备源极102和漏电极103和侧栅电极104，以及CMOS反相器的连接线，然后在晶体管沟道区域沉积一层半导体碳纳米管105，再通过打印的方式沉积不同掺杂剂含量的离子胶106，最终构建了具有阈值可控的CNT-TFT。选择性地打印具有合适掺杂剂浓度的离子胶106，调控CNT-TFT具有不同的阈值，即可构成两类CMOS逻辑电路。
作为侧栅结构的薄膜晶体管的离子胶106，一方面用于组成晶体管的绝缘层材料；一方面含掺杂剂的离子胶106可对于底层的半导体碳纳米管105进行掺杂。因此，最终的侧栅晶体管表现出了典型的双极性晶体管曲线，而不是单一的p型曲线，通过调控掺杂剂含量，获得了具有不同开启电压的晶体管器件。
具体的，本揭示实施例中的薄膜晶体管中的介质层101的材料包括氧化铪，金属源/漏极的材料包括金；离子胶106包括前段共聚物、有机胺类物质以及掺杂剂；碳纳米管105的材料包括聚噻吩衍生物、聚芴衍生物、聚间苯乙炔衍生物中的任意一种或多种。
本揭示实施例还提供一种薄膜晶体管的制备方法。如图2所示，图2为本揭示实施例提供的薄膜晶体管的制备方法。其制备方法包括如下步骤：
S10：在衬底基板上制备介质层，并在所述介质层上制备薄膜晶体管的源/漏电极以及栅极。
具体的，首先，在衬底基板上沉积一定厚度氧化铪，氧化铪的厚度为4.5nm~5.5nm，优选厚度为5nm，通过传统的光刻以及电子束蒸发技术沉积一定厚度的钛/金作为源/漏电极，优选的，当选用钛时，厚度为5nm，选用金时，厚度为50 nm，以及侧栅电极，衬底基板包括Si基板、聚对苯二甲酸乙二酯基板或玻璃基板。
S11：制备碳纳米管，并将所述碳纳米管沉积到所述薄膜晶体管的第一沟道中，所述第一沟道设置在所述源极与所述漏极之间。
在制备碳纳米管时，将大管径的碳纳米管分散于含聚合物的有机溶液中，获得分散均一的碳纳米管溶液；然后，对碳纳米管溶液进行离心处理，离心速度大于10000g，离心时间在30 min-120 min之间，离心后将上层清液分离出，获得富集的大管径半导体碳纳米管，然后通过印刷工艺，重复多次印刷（3-4次），将碳纳米管设置在所述第一沟道中。
具体而言，所述碳纳米管为大管径P2单壁碳管。
作为较为优选的实施方案之一，所述聚合物包括聚噻吩衍生物、聚芴和/或聚芴衍生物、聚间苯乙炔衍生物中的任意一种或多种组合，但不限于此。
作为较为优选的实施方案之一，所述碳纳米管溶液中的聚合物的浓度控制在0.0001wt%-0.5 wt %之间。
S12：制备离子胶，并将所述离子胶沉积到所述薄膜晶体管的第二沟道中，所述第二沟道设置在所述漏极与所述栅极之间。
首先制备离子胶溶液，从离子胶溶液中得到本揭示实施例的离子胶。具体的，离子胶的成分包括前段共聚物、有机胺类物质以及掺杂剂，优选的前段共聚物包括聚苯乙烯-聚甲基丙烯酸甲酯（PS-PMMA），其质量分数含量为0.3wt%-0.7wt％；有机胺类物质为粒子液，包括1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺，其质量分数含量为9.3wt%-9.7wt％；溶剂优选为乙酸乙酯，其质量分数含量为90wt％。按质量比例准确称量配制离子胶溶液所需药品，室温下，在其中放入搅拌磁子，在中速下搅拌约四个小时即获得离子胶溶液。
同时在离子胶中添加适量掺杂剂，掺杂剂优选为三乙醇胺（TEOA）。在配制掺杂剂（TEOA）溶液时，室温下取适量掺杂剂于甲醇或乙醇中，70℃水浴加热十分钟，配制成1M和4M的溶液待用。在使用前，每次取30~200μL掺杂剂溶液于1.5 ml离子胶中。
完成后，所述离子胶通过喷墨打印、低速旋涂或滴涂工艺设置在所述第二沟道中。
S13：干燥处理所述离子胶，得到所述薄膜晶体管。
具体的，在沉积碳纳米管后，通过气溶胶打印机或滴涂，每次打印或滴涂完毕后，60℃烘烤约2min，用甲苯洗净，再60℃烘烤2min，重复两到三次，最后再120℃烘烤30min完成碳管的沉积。
在刻蚀栅电极工艺中，通过一步光刻曝光和电子束蒸发技术，同时制备源/漏电极和侧栅电极，或在沉积碳纳米管之后，通过喷墨打印沉积侧栅电极。
在制备离子胶工艺中，取适量，优选1.5ml离子胶溶液作为墨水，用气溶胶打印机精确地把离子胶沉积在沟道区域，并与源/漏电极处在同一水平面的栅电极相连。如果采用旋涂或滴涂技术，取适量（优选30~50μL离子胶溶液）进行低速旋涂（500 rpm），或直接滴涂覆盖所有电极。含有掺杂剂的离子胶最后在105℃烘烤3min。
具体的，对上述薄膜晶体管进行测试，如图3所示，图3为本揭示实施例的薄膜晶体管的转移性能曲线图。其中，图3中的a中为纯离子胶，图3中的b中添加不同含量掺杂剂。从a中可见，所制备的侧栅结构的碳纳米管晶体管器件，呈现出p型导电特性，而当离子胶中加入适当掺杂剂之后，b中均表现出双极性的性能，并且迟滞较小，开关比较高，阈值和导电特性可调节。同时，从图b中，1-5曲线分别代表不同含量的掺杂剂制备的晶体管的转移曲线，可以明显看出，掺杂剂的含量不同，晶体管的阈值电压不同。随着掺杂剂的浓度增加，阈值电压会逐渐左移，这些对后续构建出性能优异的CMOS反相器电路非常有利。依次可根据电路对晶体管的阈值电压需求而调节掺杂剂的含量，形成最优阈值电压的晶体管器件。
同时，本揭示实施例还提供一种两个双极性CNT-TFT构成的CMOS反相器。如图4所示，图4为本揭示实施例提供的双极性CNT-TFT构成的CMOS反相器的平面图。其中，图4中的反相器包括两个双极性CNT-TFT。CMOS反相器包括：侧栅极1、反相器输出连接端2、源极3、漏极4以及离子胶5。图中各电极以及电极连接线均通过光刻和电子束蒸发制备而来，具体的，首先在源/漏电极沟道处通过打印、滴涂、旋涂及浸泡的方式沉积半导体碳纳米管，而后打印含掺杂剂离子胶，连接侧栅输入电极和两处沟道区域，通过调控离子胶掺杂剂的浓度，促使CNT-TFT的阈值电压在0V附近，并形成两个相同的双极性CNT-TFT，在此基础上即构成了本揭示实施例提供的CMOS反相器。
对上述反相器的性能测试，如图5所示，图5为本揭示实施例的反相器的晶体管性能测试图。其中，图5中的a为反相器的晶体管转移性能曲线，图5中的b为单个CMOS反相器的非门原理图，图5中的c、图5中的d为反相器电路的输入-输出电压曲线和增益图。从图5中的a可见，所制备的金侧栅结构的碳纳米管晶体管器件，均表现出双极性的性能，并且迟滞较小，开关比较高，输出电流较大。对于在此晶体管的基础上构建的CMOS反相器而言，如图5中的c所示，当输入电压位于逻辑0时，输出电压位于逻辑1；当输入电压位于逻辑1时，输出电压位于逻辑0。由图5中的d可知，其反相器在Vdd=0.75V时达到最大增益为43。
由此，本揭示实施例提供的CMOS反相器电路的性能优异。
优选的，本揭示实施例提供另一种CMOS反相器，与图4中的双极性CNT-TFT区别在于：本实施例的CMOS反相器采用一个双极性的CNT-TFT和一个p-型CNT-TFT构成。此反相器的构建流程和工艺和图4中实施例中的反相器一致，在此不再赘述，需要指出的是，本揭示实施例中，两个不同的CNT-TFT的离子胶成分存在差异，一处离子胶采用的是不含掺杂剂的离子胶，用此离子胶构建的晶体管通常表现为p型特性，作为PMOS管，另一处的离子胶采用的是含掺杂剂（1M、100μl/1.5ml）离子胶，用此离子胶构建的晶体管表现为双极性。通过对所述CMOS反相器的性能进行测试，表现出双极性的性能，并且迟滞较小，开关比较高，输出电流较大，同时，CMOS反相器在不同工作电压下均表现出较低的功耗，性能优异。
以上对本揭示实施例所提供的一种薄膜晶体管及其制备方法、CMOS反相器进行了详细介绍，以上实施例的说明只是用于帮助理解本揭示的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，而这些修改或者替换，并不使相应技术方案的本质脱离本揭示各实施例的技术方案的范围。

Claims (19)

  1. 一种薄膜晶体管的制备方法，包括如下步骤：
    S10：在衬底基板上制备介质层，并在所述介质层上制备薄膜晶体管的源极、漏极以及栅极，所述介质层的厚度为4.5nm~5.5nm；
    S11：制备碳纳米管，并将所述碳纳米管沉积到所述薄膜晶体管的第一沟道中，所述第一沟道设置在所述源极与所述漏极之间；
    S12：制备离子胶，并将所述离子胶沉积到所述薄膜晶体管的第二沟道中，所述第二沟道设置在所述漏极与所述栅极之间，所述离子胶通过喷墨打印、低速旋涂或滴涂工艺设置在所述第二沟道中；
    S13：干燥处理所述离子胶，得到所述薄膜晶体管。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中所述栅极的厚度为4.5nm~5.5nm。
  3. 根据权利要求1所述的薄膜晶体管的制备方法，其中所述碳纳米管通过印刷工艺设置在所述第一沟道中。
  4. 根据权利要求1所述的薄膜晶体管的制备方法，其中所述步骤S12中还包括如下步骤：
    S121：将聚苯乙烯-聚甲基丙烯酸甲酯、1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺、乙酸乙酯以及掺杂剂按质量比例混合，同时添加搅拌磁子，进行搅拌，获得离子胶溶液。
  5. 根据权利要求4所述的薄膜晶体管的制备方法，其中所述聚苯乙烯-聚甲基丙烯酸甲酯的质量分数含量为0.3wt%-0.7wt％，所述1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺的质量分数含量为9.3wt%-9.7wt％，所述掺杂剂的质量分数含量为90wt％。
  6. 一种薄膜晶体管，包括：
    衬底基板；
    介质层，所述介质层设置在所述衬底基板上；以及
    半导体层，所述半导体层设置在所述介质层上；
    其中，所述半导体层还包括源极、漏极以及栅极，所述源极与所述漏极之间设置有第一沟道，所述第一沟道中设置有碳纳米管，所述漏极与所述栅极之间设置有第二沟道，所述第二沟道中设置有离子胶，所述离子胶同时覆盖所述半导体层。
  7. 根据权利要求6所述的薄膜晶体管，其中所述介质层的材料包括氧化铪，所述源极和漏极的材料包括金。
  8. 根据权利要求6所述的薄膜晶体管，其中所述离子胶包括前段共聚物、乙酸乙酯以及掺杂剂。
  9. 一种薄膜晶体管的制备方法，包括如下步骤：
    S10：在衬底基板上制备介质层，并在所述介质层上制备薄膜晶体管的源极、漏极以及栅极；
    S11：制备碳纳米管，并将所述碳纳米管沉积到所述薄膜晶体管的第一沟道中，所述第一沟道设置在所述源极与所述漏极之间；
    S12：制备离子胶，并将所述离子胶沉积到所述薄膜晶体管的第二沟道中，所述第二沟道设置在所述漏极与所述栅极之间；
    S13：干燥处理所述离子胶，得到所述薄膜晶体管。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述介质层的厚度为4.5nm~5.5nm，所述栅极的厚度为4.5nm~5.5nm。
  11. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述碳纳米管通过印刷工艺设置在所述第一沟道中。
  12. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述离子胶通过喷墨打印、低速旋涂或滴涂工艺设置在所述第二沟道中。
  13. 根据权利要求12所述的薄膜晶体管的制备方法，其中所述低速旋涂工艺中，选取所述离子胶的含量为30μL~50μL。
  14. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述步骤S12中还包括如下步骤：
    S121：将聚苯乙烯-聚甲基丙烯酸甲酯、1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺、乙酸乙酯以及掺杂剂按质量比例混合，同时添加搅拌磁子，进行搅拌，获得离子胶溶液。
  15. 根据权利要求14所述的薄膜晶体管的制备方法，其中所述聚苯乙烯-聚甲基丙烯酸甲酯的质量分数含量为0.3wt%-0.7wt％，所述1-乙基-3-甲基咪唑啉双(三氟甲基磺酰基)亚胺的质量分数含量为9.3wt%-9.7wt％，所述掺杂剂的质量分数含量为90wt％。
  16. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述步骤S11中，对所述碳纳米管进行沉积时，通过气溶胶打印机或滴涂工艺进行制备。
  17. 根据权利要求16所述的薄膜晶体管的制备方法，其中每次打印或滴涂完毕后，在60℃温度下对所述碳纳米管烘烤2min，用甲苯洗净，并在60℃温度下继续烘烤2min，重复两到三次。
  18. 根据权利要求16所述的薄膜晶体管的制备方法，其中所述碳纳米管沉积完成后，对所述碳纳米管进行干燥。
  19. 根据权利要求9所述的薄膜晶体管的制备方法，其中所述步骤S10中，在制备所述源极、所述漏极和所述栅极时，采用一步光刻曝光和电子束蒸发工艺进行制备。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723276A (zh) * 2012-04-06 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 全印刷柔性碳纳米管薄膜晶体管的制备方法
US20150053927A1 (en) * 2013-08-20 2015-02-26 Wisconsin Alumni Research Foundation Stretchable transistors with buckled carbon nanotube films as conducting channels
CN105789130A (zh) * 2014-12-24 2016-07-20 中国科学院苏州纳米技术与纳米仿生研究所 一种基于碳纳米管薄膜晶体管的cmos反相器的制作方法
CN108630760A (zh) * 2017-03-24 2018-10-09 中国科学院苏州纳米技术与纳米仿生研究所 N型场效应薄膜晶体管及其制作方法、cmos反相器及其制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130080309A (ko) * 2012-01-04 2013-07-12 삼성전자주식회사 파이버 상에 형성된 박막 트랜지스터 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723276A (zh) * 2012-04-06 2012-10-10 中国科学院苏州纳米技术与纳米仿生研究所 全印刷柔性碳纳米管薄膜晶体管的制备方法
US20150053927A1 (en) * 2013-08-20 2015-02-26 Wisconsin Alumni Research Foundation Stretchable transistors with buckled carbon nanotube films as conducting channels
CN105789130A (zh) * 2014-12-24 2016-07-20 中国科学院苏州纳米技术与纳米仿生研究所 一种基于碳纳米管薄膜晶体管的cmos反相器的制作方法
CN108630760A (zh) * 2017-03-24 2018-10-09 中国科学院苏州纳米技术与纳米仿生研究所 N型场效应薄膜晶体管及其制作方法、cmos反相器及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
XIAO HONGSHAN, XIE HUAFEI, ROBIN MALO, ZHAO JIANWEN, SHAO LIN, WEI MIAOMIAO, PORTILLA LUIS, PECUNIA VINCENZO, CHEN SHUJHIH, LEE CH: "Polarity tuning of carbon nanotube transistors by chemical doping for printed flexible complementary metal-oxide semiconductor (CMOS)-like inverters", CARBON, ELSEVIER OXFORD, GB, vol. 147, 1 June 2019 (2019-06-01), GB, pages 566 - 573, XP055821124, ISSN: 0008-6223, DOI: 10.1016/j.carbon.2019.03.003 *

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