WO2021109795A1 - 金属化叠层及其制造方法及包括金属化叠层的电子设备 - Google Patents

金属化叠层及其制造方法及包括金属化叠层的电子设备 Download PDF

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WO2021109795A1
WO2021109795A1 PCT/CN2020/126987 CN2020126987W WO2021109795A1 WO 2021109795 A1 WO2021109795 A1 WO 2021109795A1 CN 2020126987 W CN2020126987 W CN 2020126987W WO 2021109795 A1 WO2021109795 A1 WO 2021109795A1
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layer
metal
interconnection
interconnection line
metal layer
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PCT/CN2020/126987
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/782,928 priority Critical patent/US20230005836A1/en
Publication of WO2021109795A1 publication Critical patent/WO2021109795A1/zh
Priority to US18/300,719 priority patent/US20230253316A1/en

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Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to a metallization stack and a method of manufacturing the same, and an electronic device including such a metallization stack.
  • the purpose of the present disclosure is at least partly to provide a metallized laminate and a manufacturing method thereof, and an electronic device including the metallized laminate.
  • a metallization stack including at least one interconnection layer and at least one via layer alternately arranged on a substrate. At least a pair of adjacent interconnection line layers and via layers in the metallization stack includes interconnection lines in the interconnection line layer and vias in the via layer. The interconnect layer is closer to the substrate than the via layer. The outer peripheral sidewall of the via hole on at least a part of the interconnection line does not exceed the outer peripheral sidewall of the at least part of the interconnection line.
  • a method of manufacturing a metalized laminate includes at least one interconnection layer and at least one via layer alternately arranged.
  • the method includes forming at least a pair of adjacent interconnection line layers and via layers in a metallization stack by the following operations: forming a first metal layer on a lower layer; forming a second metal layer on the first metal layer; The first metal layer and the second metal layer are patterned into interconnection patterns; the second metal layer is patterned into separate parts to form the via.
  • an electronic device including the above-mentioned metallization stack.
  • the interconnection pattern may be formed by photolithography.
  • the line width and spacing of the interconnection line and the critical dimension (CD) and spacing of the via can be determined by the line width or CD and spacing of the photolithography, so that the line width or CD and spacing can be reduced, and thus the integration can be increased. density.
  • the problem of metal filling in conventional processes is avoided.
  • ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co) or chromium (Cr) can be used Metal material, so that it is not necessary to use a diffusion barrier layer.
  • FIG. 1 to 16 schematically show some stages in the process of manufacturing a metallized laminate according to an embodiment of the present disclosure
  • Figures 17 to 24(d) schematically show some stages in the process of manufacturing a metallized laminate according to another embodiment of the present disclosure
  • Figure 3 (a), 7, 8 (a), 9, 10 (a), 11 (a), 14 (a), 18 (a), 21, 22 (a), 23, 24 (a) It is a top view.
  • Figures 1, 2, 10(b), 11(b), 12(a), 14(b), 15(a), 15(b), 16, 17, 24(b) are along AA' Cross-sectional view of the line
  • Figure 3(b), 4(a), 5(a), 8(b), 10(c), 11(c), 12(b), 13(a), 14(c) , 18(b), 19(a), 20(a), 22(b), 24(c) are cross-sectional views along the line BB'
  • Figures 3(c), 4(b), 5(b), 8(c), 10(d), 11(d), 12(c), 13(b), 14(d), 18(c), 19(b), 20(b), 22(c), 24(d) is a cross-sectional view along the CC' line
  • FIGS. 6(a) to 6(c)
  • a layer/element when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located "under” the other layer/element when the orientation is reversed.
  • the embodiment of the present disclosure proposes a method of manufacturing a metallized laminate.
  • a method of manufacturing a metallized laminate Different from the conventional technique in which an interlayer dielectric layer is formed first, then trenches or holes are formed in the interlayer dielectric layer, and the trenches or holes are filled with a conductive material to form interconnect lines or vias, according to the embodiments of the present disclosure,
  • the metal pattern may be formed on the lower layer (for example, the substrate on which the device is formed or the next layer in the metallization stack) first, and then the gaps of the metal patterns are filled with dielectric material to form an interlayer dielectric layer.
  • the metal pattern can be formed by photolithography.
  • the line width and spacing of the interconnection line and the critical dimension (CD) and spacing of the via can be determined by the line width or CD and spacing of the photolithography, so that the line width or CD and spacing can be reduced, and thus the integration can be increased. density.
  • the problem of metal filling in conventional processes is avoided.
  • ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt (Co) or chromium (Cr) can be used Metal material, so that it is not necessary to use a diffusion barrier layer.
  • the trenches or holes formed by etching have a shape that tapers from top to bottom, so the interconnect lines or vias formed therein have a corresponding shape.
  • the interconnection line or the via hole may be directly obtained by photolithography, and thus may have a shape that is tapered from the bottom to the top.
  • a pair of interconnection layer and via layer adjacent to each other may be formed together.
  • a first metal layer for the interconnection layer and a second metal layer for the via layer may be formed on the lower layer.
  • the first metal layer and the second metal layer may be sequentially formed on the entire area where the metallization stack needs to be formed, for example, over substantially the entire surface of the lower layer.
  • the first metal layer and the second metal layer may be patterned, for example, by photolithography, into an interconnection pattern, and the interconnection pattern may correspond to or be the layout of the interconnection line in the interconnection line layer.
  • the second metal layer having the interconnection pattern can be patterned into separate parts to form via holes.
  • the interconnection line may be formed by the first metal layer (which may be cut at certain areas) having an interconnection pattern.
  • a spacer layer may be provided between the first metal layer and the second metal layer.
  • a spacer layer can be used as an etch stop layer (to optimize the manufacturing process, especially the etching process therein) and/or a diffusion barrier layer (which improves interconnect performance).
  • the spacer layer may be patterned into an interconnection pattern together with the first metal layer and the second metal layer.
  • the metallization stack may include a plurality of such interconnection line layers and via layers, and at least a part or even all of the interconnection line layers and via layers can be manufactured according to this method.
  • the interconnection pattern may include a series of metal lines. These metal lines may have the same pattern as the layout of the interconnection lines in the interconnection line layer. That is, the metal layer can be patterned according to the layout of the interconnection lines.
  • the interconnection pattern may have a pattern in which the metal lines extend according to the layout of the interconnection lines, but the metal lines corresponding to the separated interconnection lines opposite to each other may extend continuously. In this case, forming metal wires extending in the same direction is advantageous for patterning.
  • This layout is matched with metal lines extending in another direction that intersects (for example, orthogonal) to the direction in another interconnection line layer, and various interconnection routes can be realized.
  • an interconnection line layer in which the interconnection lines extend in a first direction and an interconnection line in which the interconnection lines extend in a second direction orthogonal to the first direction may be alternately arranged in the vertical direction.
  • the metal lines formed by the first metal layer can be cut at a predetermined area according to the layout of the interconnection lines, so as to realize the separation between different interconnection lines.
  • a dielectric material may be filled to form an interlayer dielectric layer. Since the gap between the metal lines or the above-mentioned gap is small, an air gap or a hole may be formed in the filled dielectric material. Such air gaps or holes can help reduce capacitance. As described below, the position of the air gap or hole can be adjusted by a deposition-etch-deposition method. In addition, the dielectric material of each filling may be the same or different.
  • the metallization stack according to the embodiment of the present disclosure can be obtained.
  • at least a part of the interconnection line and the via holes on it can be respectively passed through the same photolithography process from the first metal layer and the second metal layer (and then undergo further cutting processing to form the interconnection lines and the vias respectively). Therefore, it can be self-aligned with each other, so that the sidewall of the via hole may not exceed the sidewall of the interconnection line below.
  • the side wall of the at least a portion of the interconnection line along the longitudinal extension direction thereof is substantially coplanar with at least the lower portion of the corresponding side wall of the via hole.
  • etching selectivity is also considered. In the following description, the required etching selectivity may or may not be indicated.
  • 1 to 16 schematically show some stages in the process of manufacturing metallization according to an embodiment of the present disclosure.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • compound semiconductor substrates such as SiGe substrates, and the like.
  • the following description takes the bulk Si substrate as an example.
  • an active region may be defined by an isolation portion 1003, such as shallow trench isolation (STI).
  • the isolation part 1003 may surround each active region.
  • a semiconductor device T can be formed, such as a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a nanowire field effect transistor, and the like.
  • the semiconductor device T may have a gate stack including a gate dielectric layer 1005 and a gate electrode layer 1007, and source/drain regions S/D formed on both sides of the gate stack in the active region.
  • a gate spacer 1009 may be formed on the sidewalls of the gate stack.
  • the semiconductor device T may be a planar device such as a MOSFET or a three-dimensional device such as a FinFET.
  • the active region may be formed in the form of a fin protruding with respect to the surface of the substrate.
  • An interlayer dielectric layer 1011 such as oxide (for example, silicon oxide) may be formed on the substrate 1001 to cover each semiconductor device T formed on the substrate 1001.
  • a contact portion 1013 to each semiconductor device T may be formed.
  • FIG. 1 only the contact portion to the source/drain region S/D is shown, and the contact portion to the gate electrode layer 1007 may also be included (for example, see FIG. 3(b)).
  • an interconnection structure or metallization stack can be fabricated on the substrate 1001.
  • the interlayer dielectric layer 1011 can be formed for metalization by, for example, deposition such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.
  • the first metal layer 1015 and the second metal layer 1115 may include conductive metals such as ruthenium (Ru), molybdenum (Mo), rhodium (Rh), platinum (Pt), iridium (Ir), nickel (Ni), cobalt ( Co) or chromium (Cr), etc.
  • the first metal layer 1015 and the second metal layer 1115 may have a certain etching selectivity with respect to each other, for example, have different materials.
  • the first metal layer 1015 is a Ru layer
  • the second metal layer 1115 is a Mo layer.
  • the first metal layer 1015 may have a thickness for the first interconnect layer, for example, about 5 nm-100 nm; the second metal layer 1115 may have a thickness for the first via layer, for example, about 5 nm-100 nm.
  • the Ru source can be purified in the following manner to obtain high-purity Ru metal.
  • a gas stream including ozone (O 3 ) can be introduced into one or more reaction chambers to contact with the Ru source, thereby forming ruthenium tetroxide (RuO 4 ) that is gaseous under the reaction conditions.
  • Ruthenium tetroxide and unreacted ozone and airflow residues can be sent into the collection chamber, in which the gaseous ruthenium tetroxide can be reduced to a ruthenium dioxide (RuO 2 ) layer on the semiconductor substrate.
  • the deposited ruthenium dioxide can be reduced by using, for example, hydrogen to produce high-purity Ru metal.
  • ozone can be used as an etching gas to etch and pattern the deposited Ru metal layer.
  • the first metal layer 1015 and the second metal layer 1115 can be patterned into a series of metal lines.
  • the patterning can be performed by a photolithography process, for example, partition wall pattern transfer photolithography or extreme ultraviolet (EUV) photolithography.
  • photolithography reactive ion etching (RIE) can be used, and the RIE can be stopped at the interlayer dielectric layer 1011 (or the contact portion 1013 therein) under the first metal layer 1015.
  • RIE reactive ion etching
  • the interval between the metal lines may define the interval between the interconnection lines in the first interconnection line layer, and is, for example, about 5 nm-150 nm.
  • dummy metal lines may be formed so that the metal lines are arranged at substantially uniform intervals, for example.
  • the line width of the metal line may define the line width of the interconnection line in the first interconnection line layer, for example, about 5 nm-100 nm.
  • at least a part of the metal wire may contact and be electrically connected to the contact portion 1013 below.
  • the formed metal wire extends substantially in parallel along the first direction (the horizontal direction on the paper in FIG. 3(a)), and may be formed later along the first direction crossing (for example, perpendicular) to the first direction.
  • the metal wires extending in two directions cooperate to realize various interconnection routes.
  • the present disclosure is not limited to this.
  • different metal wires can extend in different directions, and the same metal wire can extend zigzag.
  • another interlayer dielectric layer may be formed on the interlayer dielectric layer 1011 to fill the gap between the metal lines 1015 and 1115.
  • the other interlayer dielectric layer may include dielectric materials such as silicon oxide, silicon oxycarbide, other low-k dielectric materials, and the like.
  • the other interlayer dielectric layer and the previous interlayer dielectric layer 1011 may include the same material, and thus may be shown as a whole as 1011, and the possible boundary between them is schematically shown with a dashed line. Of course, they can also include different materials.
  • the other interlayer dielectric layer can be deposited (for example, CVD or ALD) dielectric material to cover the metal lines 1015, 1115, and then etch back or planarize (for example, chemical mechanical polishing (CMP)) the deposited dielectric material and Stop at the top surface of the metal wire 1115 to be formed. Etching back can use atomic layer etching (ALE) to achieve good process control.
  • CVD or ALD chemical mechanical polishing
  • the deposited dielectric material completely fills the gap between the metal lines 1015, 1115.
  • the present disclosure is not limited to this.
  • an air gap or an air gap can be formed between the metal lines 1015.
  • Hole 1017 Such an air gap or hole 1017 helps to reduce the capacitance between the metal lines.
  • the position of the air gap or hole 1017 in the vertical direction can be adjusted.
  • a dielectric material may be deposited into the gap between the metal lines 1015 and 1115 until the dielectric material closes the top of the gap.
  • multiple films can be used.
  • the formed air gap or hole 1017a may be located approximately in the middle of the gap in the vertical direction.
  • a dielectric material can be deposited into the gap between the metal lines 1015 and 1115, but the top of the gap is not closed. Then, the deposited dielectric material can be selectively etched, such as RIE, leaving a part at the bottom of the gap, thereby increasing the opening in the dielectric material. Then, the dielectric material can be deposited continuously until the dielectric material closes the top of the gap.
  • the dielectric material deposited twice can be the same or different. Of course, this deposition-etch-deposition process can be repeated multiple times. In this case, the formed air gap or hole 1017b may be located at the lower part of the gap in the vertical direction.
  • a dielectric material may be deposited into the gap between the metal lines 1015 until the dielectric material can completely fill the gap. Then, the deposited dielectric material can be selectively etched such as RIE, leaving a part at the bottom of the gap. Then, the dielectric material can be deposited continuously until the dielectric material closes the top of the gap.
  • the dielectric material deposited twice can be the same or different. Of course, this deposition-etch-deposition process can be repeated multiple times. In this case, the formed air gap or hole 1017c may be located at the upper part of the gap in the vertical direction.
  • the positions of air gaps or holes between metal line gaps can be adjusted up and down.
  • the pattern of the second metal layer used for the first via layer is the same as the pattern of the first metal layer used for the first interconnect layer (ie, the aforementioned metal line pattern).
  • the second metal layer (currently in the form of a metal wire) used for the first via layer can be further patterned to form a via pattern.
  • a photoresist 1019 may be formed on the interlayer dielectric layer 1011 and the metal line 1115, and the photoresist 1019 may be patterned (for example, by exposure and development) to cover the area where the via is to be formed, and expose The rest of the area.
  • the width W1 of the photoresist 1019 (the width of the via hole in the first via layer defined thereby) (the dimension in the longitudinal extension direction of the metal wire, in this example, the horizontal direction on the paper in FIG. 7 The upper dimension) may be relatively large, so that the interconnection line in the second interconnection line layer formed thereon can better land on the via hole and make better contact with the via hole.
  • the photoresist 1019 can be used as an etching mask to selectively etch the metal line 1115, such as RIE, to form a via.
  • the etching of the metal wire 1115 may have an etching selectivity with respect to the metal wire 1015, so that it may stop on the top surface of the metal wire 1015.
  • endpoint detection can also be used to determine whether the etching reaches the top surface of the metal wire 1015.
  • the metal lines 1115 can be formed into some separated patterns (vias in the first via layer can be formed, see the top view of FIG. 8(a)). After that, the photoresist 1019 may be removed.
  • the minimum interval between the via holes can be defined by the minimum line interval achievable by the photolithography process (for example, equal). In general, the minimum spacing between vias formed by photolithography is greater than the minimum spacing between lines.
  • the metal line 1015 for the first interconnection line layer currently maintains a continuous extension. They can be separated into multiple parts according to the design layout.
  • a photoresist 1021 may be formed on the interlayer dielectric layer 1011 and the metal lines 1015 and 1115, and the photoresist 1021 may be patterned to cover the area where the interconnection lines exist in the pattern of the first interconnection line layer. , While exposing the region where there is no interconnection line in the pattern of the first interconnection line layer.
  • the photoresist 1021 can be used as an etching mask to selectively etch the metal line 1015, such as RIE.
  • the etching of the metal line 1015 can be stopped at the underlying interlayer dielectric layer 1011 to cut the metal line 1015. Therefore, in the first interconnection line layer, the metal lines 1015 can form some separated metal line segments to obtain corresponding interconnection lines. After that, the photoresist 1021 may be removed.
  • the vias in the first via layer are first patterned (etching of the metal line 1115), and then the interconnecting lines in the first interconnection layer (etching of the metal line 1015) are patterned. This is advantageous because the etching depth of each etching process is reduced.
  • the present disclosure is not limited to this. For example, the order of the two composition processing can be exchanged.
  • the metal line 1015 extends on the interlayer dielectric layer 1011 to form an interconnection line; the metal line 1115 is patterned into a localized pattern on the interconnection line to form a via. Since the metal lines 1015 and 1115 can be formed by the same photolithography process (and then undergo a further cutting process to form the interconnection line and the via hole respectively), the interconnection line 1015 and the via hole 1115 can be self-aligned with each other.
  • the thickness of the metal wire between them may not be reduced. That is, the widths of adjacent via holes are increased to be connected to each other as one body. In this way, the connection resistance can be reduced.
  • the via hole 1115 may be located in a local area of the interconnection line, for example The sidewalls of the via are recessed with respect to the corresponding sidewalls of the interconnection line.
  • the sidewall of the via hole 1115 and the corresponding sidewall of the interconnection line may be substantially coplanar .
  • voids are formed in the interlayer dielectric layer 1011. As shown in Figures 11(a) to 11(d), these voids can be filled with dielectric materials. This can be done by deposition and then etch back or planarization as described above.
  • the deposited dielectric material may be the same as or different from the previous interlayer dielectric layer 1011. Here, the deposited dielectric material and the previous interlayer dielectric layer are still shown integrally as 1011, and the possible boundary between them is schematically shown with a dashed line. According to other embodiments, before depositing the dielectric material, a thin layer may be formed by, for example, deposition for the purpose of diffusion barrier, protection, or etch stop.
  • air gaps or holes 1023 may be formed when the dielectric material is deposited, as shown in FIGS. 12(a) to 12(c).
  • the air gap or hole 1023 may be different according to the shape of the corresponding gap.
  • the position of the air gap or hole 1023 in the vertical direction can be adjusted by adjusting the deposition process.
  • FIGS. 13(a) and 13(b) show a case where an air gap or a hole is formed when the gap in the interlayer dielectric layer is filled twice. That is, in the example shown in FIGS. 13(a) and 13(b), the above-mentioned air gap or hole 1017 and air gap or hole 1023 are combined.
  • the first interconnection layer and the first via layer are formed.
  • the interconnection layer and the via layer in the upper layer of the metallization stack can be formed continuously.
  • the present disclosure is not limited to this.
  • a manufacturing method according to another embodiment of the present disclosure will be described. The methods described below can be used alone or in combination with the methods described above.
  • a third metal layer 1025 for the second interconnect layer in the metallization stack and a third metal layer 1025 for the metallization stack can be formed.
  • the third metal layer 1025 and the fourth metal layer 1125 may include the same or different metal material as the first metal layer 1015 and the second metal layer 1115.
  • the third metal layer 1025 may include the same material as the first metal layer 1015 such as Ru, and the fourth metal layer 1125 may include the same material as the second metal layer 1115 such as Mo.
  • the third metal layer 1025 may have a thickness for the second interconnect layer, for example, about 5 nm-100 nm; the fourth metal layer 1125 may have a thickness for the second via layer, for example, about 5 nm-100 nm.
  • the third metal layer 1025 and the fourth metal layer 1125 may be patterned into a series of metal lines.
  • the third metal layer 1025 and the fourth metal layer 1125 may be directly patterned according to the pattern of the second interconnection line layer. .
  • the third metal layer 1025 and the fourth metal layer 1125 may be patterned as a series of metal line segments. That is, here, the wire cutting process described above in conjunction with FIGS. 9 and 10(a) to 10(d) is combined to be performed together with the metal layer patterning, so that a separate cutting photolithography process is not required.
  • the metal line segment may not be limited to a straight line segment, but may include a zigzag line segment.
  • the metal line segment 1025 forms an interconnection line in the second interconnection line layer.
  • the width of the upper portion of the via hole 1115 in the first via layer can be reduced, and is approximately the same as the line width of the metal line segment 1025 formed thereon.
  • the line width W2 of the metal line segment 1025 (the scale in the horizontal direction on the paper in FIG. 14(b)) can be relatively small and smaller than the via hole in the first via layer (not Considering the upper part, its width may be reduced due to the above-mentioned over-etching) width W1 (the scale in the horizontal direction on the paper in FIG. 14(b)), so that the metal line segment 1025 (the second interconnection line layer in the second interconnection layer is subsequently formed) is the width W1
  • the interconnection line can better land on the via hole so as to make better contact with the via hole.
  • interlayer dielectric layer may be formed on the interlayer dielectric layer 1011 to fill the gap between the metal line segments 1025 and 1125.
  • the other interlayer dielectric layer may include dielectric materials such as silicon oxide, silicon oxycarbide, other low-k dielectric materials, and the like.
  • This other interlayer dielectric layer is formed as described below.
  • a dielectric material may be deposited (for example, CVD or ALD) to cover the metal line segments 1025 and 1125.
  • the deposited dielectric material and the previous interlayer dielectric layer 1011 may include the same material, and thus may be shown integrally as 1011, and the possible boundary between them is schematically shown with a dashed line. Of course, they can also include different materials.
  • an air gap or hole 1027 may be formed between the metal line segments 1025 and 1125.
  • the metal line segments have the pattern of the second interconnection line layer, the density of the metal line segments in a part of the area may be lower, or the gap between the metal line segments may be larger. In these areas, it is difficult to form air gaps or holes.
  • the dielectric material deposited by CMP can be etched back or planarized and stopped on the top surface of the metal line segment 1125.
  • ALE can be used for etch back to achieve good process control.
  • the via hole in the second via layer can be formed from the metal line segment 1125 according to the process described above in conjunction with FIGS. 7 and 8(a) to 8(c). Then, the gap in the interlayer dielectric layer 1011 can be filled with a dielectric material according to the process described above in conjunction with FIGS. 11(a) to 11(d). In this way, the second interconnect layer and the second via layer are formed.
  • FIGS. 17 to 24(d) schematically show some stages in the process of manufacturing a metallized laminate according to another embodiment of the present disclosure.
  • the differences from the embodiment described above in conjunction with FIGS. 1 to 16 will be mainly described.
  • a first metal layer 1015 for the first interconnect layer in the metallization stack and a second metal layer 1015 for the first via layer in the metallization stack may be formed on the interlayer dielectric layer 1011.
  • the metal layer 1215 is as described above with reference to FIG. 2.
  • the first metal layer 1015 and the second metal layer 1215 may include the same material such as Ru, of course, may also include different materials as in the above-mentioned embodiment.
  • the difference from the foregoing embodiment is that between the first metal layer 1015 and the second metal layer 1215, a spacer layer 1201 may be additionally provided by, for example, deposition.
  • the spacer layer 1201 may be used as a diffusion barrier layer or an etch stop layer between the first metal layer 1015 and the second metal layer 1215.
  • the spacer layer 1201 may include conductive metal silicides such as NiSi, NiPtSi, CoSi, etc., or conductive metal nitrides such as TiN, TaN, etc., or metals such as Ti, Pt, etc., with a thickness of about 1 nm-10 nm.
  • the first metal layer 1015, the spacer layer 1201, and the second metal layer 1215 can be patterned into a series of linear patterns, as described above with reference to FIGS. 3(a) to 3 (c) said.
  • another interlayer dielectric layer may be formed on the interlayer dielectric layer 1011 to fill the gaps between the linear patterns, as described above with reference to Figs. 4(a) and 4( b) said.
  • an air gap or hole 1017 may be formed, as shown in Figs. 20(a) and 20(b).
  • a photoresist 1019 can be formed, and the second metal layer 1215 can be selectively etched, such as RIE, to pattern it into via holes, as referenced above Figure 7 and Figures 8(a) to 8(c).
  • the etching may stop at the spacer layer 1201.
  • a photoresist 1021 may be formed, and the spacer layer 1201 and the first metal layer 1015 may be selectively etched, such as RIE, to form interconnections, as described above Refer to Figure 9 and Figures 10(a) to 10(d).
  • the spacer layer 1201 (for example, used as a diffusion barrier layer) may only extend on the bottom surface of the via hole 1215 or the bottom surface of the interconnection line 1015, and not extend to the over On the sidewall of the hole 1215, this is different from the diffusion barrier formed by the conventional process.
  • a spacer layer may also be combined between the third metal layer and the fourth metal layer.
  • the spacer layer it can be used as an etch stop layer when patterning the fourth metal layer, and the spacer layer itself can be patterned together with the third metal layer.
  • the other aspects may be the same as the above-mentioned embodiment.
  • the metallization stack according to the embodiment of the present disclosure can be applied to various electronic devices. Therefore, the present disclosure also provides an electronic device including the above-mentioned metallization stack.
  • the electronic device may also include components such as a display screen and a wireless transceiver.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.
  • a manufacturing method of a system on chip is also provided.
  • the method may include the method described above.
  • a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

一种金属化叠层及其制造方法及包括这种金属化叠层的电子设备，金属化叠层可以包括在衬底（1001）上交替设置的至少一个互连线层和至少一个过孔层。金属化叠层中至少一对相邻的互连线层和过孔层包括互连线层中的互连线（1015）以及过孔层中的过孔（1115）。互连线层比过孔层更靠近衬底（1001）。互连线（1015）的至少一部分上的过孔（1115）的外周侧壁不超出互连线（1015）的所述至少一部分的外周侧壁。

Description

金属化叠层及其制造方法及包括金属化叠层的电子设备
相关申请的引用
本申请要求于2019年12月6日递交的题为“金属化叠层及其制造方法及包括金属化叠层的电子设备”的中国专利申请201911254611.8的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及金属化叠层及其制造方法及包括这种金属化叠层的电子设备。
背景技术
随着半导体器件的不断小型化，越来越难以制造高密度的互连结构，因为需要极细的金属线(意味着小晶粒尺寸、过大的阻挡层厚度及因此导致的大电阻)和极小的线间隔(意味着未对准、难以填充接触孔)。另外，难以将金属线与过孔对准，这会导致集成电路(IC)中的短路或开路故障，并因此增加IC的制造成本。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种金属化叠层及其制造方法及包括这种金属化叠层的电子设备。
根据本公开的一个方面，提供了一种金属化叠层，包括在衬底上交替设置的至少一个互连线层和至少一个过孔层。金属化叠层中至少一对相邻的互连线层和过孔层包括互连线层中的互连线以及过孔层中的过孔。互连线层比过孔层更靠近衬底。互连线的至少一部分上的过孔的外周侧壁不超出互连线的所述至少一部分的外周侧壁。
根据本公开的另一方面，提供了一种制造金属化叠层的方法。金属化叠层包括交替设置的至少一个互连线层和至少一个过孔层。所述方法包括通过以下操作来形成金属化叠层中至少一对相邻的互连线层和过孔层：在下层上形成第 一金属层；在第一金属层上形成第二金属层；将第一金属层和第二金属层构图为互连图案；将第二金属层构图为分离的部分，以形成所述过孔。
根据本公开的另一方面，提供了一种电子设备，包括上述金属化叠层。
根据本公开的实施例，互连图案可以通过光刻来形成。于是，互连线的线宽和间隔以及过孔的关键尺寸(CD)和间隔可以由光刻的线宽或CD以及间隔来确定，从而可以减小线宽或CD以及间隔，并因此增加集成密度。另外，避免了常规工艺中金属填充的难题。而且，由于不使用填充工艺，可以使用钌(Ru)、钼(Mo)、铑(Rh)、铂(Pt)、铱(Ir)、镍(Ni)、钴(Co)或铬(Cr)等金属材料，从而可以不必使用扩散阻挡层。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至16示意性示出了根据本公开实施例的制造金属化叠层的流程中的一些阶段；
图17至24(d)示意性示出了根据本公开另一实施例的制造金属化叠层的流程中的一些阶段，
其中，图3(a)、7、8(a)、9、10(a)、11(a)、14(a)、18(a)、21、22(a)、23、24(a)是俯视图，图1、2、10(b)、11(b)、12(a)、14(b)、15(a)、15(b)、16、17、24(b)是沿AA′线的截面图，图3(b)、4(a)、5(a)、8(b)、10(c)、11(c)、12(b)、13(a)、14(c)、18(b)、19(a)、20(a)、22(b)、24(c)是沿BB′线的截面图，图3(c)、4(b)、5(b)、8(c)、10(d)、11(d)、12(c)、13(b)、14(d)、18(c)、19(b)、20(b)、22(c)、24(d)是沿CC′线的截面图，图6(a)至6(c)是沿BB′线或CC′线的截面中金属线附近区域的放大图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知 结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
本公开的实施例提出了一种制造金属化叠层的方法。与常规技术中先形成层间电介质层，然后在层间电介质层中形成沟槽或孔，并以导电材料填充沟槽或孔来形成互连线或过孔不同，根据本公开的实施例，可以在下层(例如，形成有器件的衬底或者金属化叠层中的下一层)上先形成金属图案，然后再向金属图案的间隙中填充电介质材料来形成层间电介质层。金属图案可以通过光刻来形成。于是，互连线的线宽和间隔以及过孔的关键尺寸(CD)和间隔可以由光刻的线宽或CD以及间隔来确定，从而可以减小线宽或CD以及间隔，并因此增加集成密度。另外，避免了常规工艺中金属填充的难题。而且，由于不使用填充工艺，可以使用钌(Ru)、钼(Mo)、铑(Rh)、铂(Pt)、铱(Ir)、镍(Ni)、钴(Co)或铬(Cr)等金属材料，从而可以不必使用扩散阻挡层。
另外，在常规工艺中，通过刻蚀形成的沟槽或孔具有从上往下渐缩的形状，于是其中形成的互连线或过孔具有相应的形状。与此不同，根据本公开的实施例，互连线或过孔可以直接通过光刻得到，于是可以具有从下往上渐缩的形状。
根据本公开的实施例，彼此相邻的一对互连线层和过孔层可以一起形成。例如，可以在下层上形成用于互连线层的第一金属层和用于过孔层的第二金属层。第一金属层和第二金属层可以依次形成在需要形成金属化叠层的整个区域上，例如遍及下层的基本上整个表面。可以将第一金属层和第二金属层构图例如光刻为互连图案，互连图案可以对应于或者是互连线层中互连线的布局。可 以将具有互连图案的第二金属层构图为分离的部分，以形成过孔。另外，可以由具有互连图案的第一金属层(可能在某些区域处切断)形成互连线。于是，互连线及之上的过孔可以彼此自对准。
在第一金属层与第二金属层之间，可以设置间隔层。例如，这种间隔层可以用作刻蚀停止层(以优化制造工艺，特别是其中的刻蚀工艺)和/或扩散阻挡层(其改善互连性能)。间隔层可以与第一金属层和第二金属层一起被构图为互连图案。
金属化叠层可以包括多个这样的互连线层和过孔层，其中至少一部分乃至全部互连线层和过孔层可以按照这种方法制造。
根据本公开的实施例，互连图案可以包括一系列金属线。这些金属线可以具有与互连线层中互连线的布局相同的图案。也即，可以按照互连线的布局，来对金属层进行构图。或者，互连图案可以具有这样的图案：其中的金属线按照互连线的布局延伸，但与彼此相对的分离互连线相对应的金属线可以连续延伸。这种情况下，形成沿同一方向延伸的金属线对于构图来说是有利的。这种布局与另一互连线层中沿与该方向相交(例如，正交)的另一方向延伸的金属线相配合，可以实现各种互连路线。例如，在金属化叠层中，可以在竖直方向上交替设置互连线沿第一方向延伸的互连线层以及互连线沿与第一方向正交的第二方向延伸的互连线层。可以在将第二金属层构图为过孔之后，再按照互连线的布局，在预定区域处切断第一金属层形成的金属线，以实现不同互连线之间的分离。
在以上制作过程中，在形成金属线之后在金属线之间，在构图过孔之后在由于第二金属层的去除而导致的空隙中，可以填充电介质材料以形成层间电介质层。由于金属线之间的间隙或者上述空隙较小，填充的电介质材料中可以形成气隙或孔洞。这种气隙或孔洞可以有助于降低电容。如下所述，可以通过淀积-刻蚀-淀积的方法，来调整气隙或孔洞的位置。另外，各次填充的电介质材料可以相同，也可以不同。
根据上述方法，可以得到根据本公开实施例的金属化叠层。如上所述，互连线的至少一部分及之上的过孔可以分别由第一金属层和第二金属层通过相同的光刻工艺(之后再分别经历进一步的切断处理以形成互连线和过孔)而得 到，因此可以彼此自对准，从而过孔的侧壁可以不超过之下的互连线的侧壁。例如，互连线的所述至少一部分沿其纵向延伸方向的侧壁与过孔的相应侧壁的至少下部实质上共面。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成互连线和过孔)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至16示意性示出了根据本公开实施例的制造金属化叠层(metallization)的流程中的一些阶段。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。以下以体Si衬底为例进行描述。
在衬底1001中，可以通过隔离部1003例如浅沟槽隔离(STI)，来限定有源区。例如，隔离部1003可以围绕各有源区。在各有源区上，可以形成半导体器件T，例如金属氧化物半导体场效应晶体管(MOSFET)、鳍式场效应晶体管(FinFET)、纳米线场效应晶体管等。半导体器件T可以具有包括栅介质层1005和栅电极层1007在内的栅堆叠以及在有源区中栅堆叠两侧形成的源/漏区S/D。在栅堆叠的侧壁上，可以形成有栅隔墙(spacer)1009。半导体器件T可以是平面型器件如MOSFET或者立体器件如FinFET。在FinFET的情况下，有源区可以形成为相对于衬底表面突出的鳍片形式。
在衬底1001上可以形成层间电介质层1011如氧化物(例如，氧化硅)，以覆盖衬底1001上形成的各半导体器件T。另外，在层间电介质层1011中，可形成到各半导体器件T的接触部1013。在图1中，仅示出了到源/漏区S/D的接触部，也可以包括到栅电极层1007的接触部(例如，参见图3(b))。
之后，可以在衬底1001上制作互连结构或者说金属化叠层。
如图2所示，可以在层间电介质层1011上，通过例如淀积如物理气相淀积(PVD)、化学气相淀积(CVD)、原子层淀积(ALD)等，形成用于金属化叠层中第一互连线层的第一金属层1015和用于金属化叠层中第一过孔层的第二金属层1115。例如，第一金属层1015和第二金属层1115可以包括导电金属如钌(Ru)、钼(Mo)、铑(Rh)、铂(Pt)、铱(Ir)、镍(Ni)、钴(Co)或铬(Cr)等。根据实施例，第一金属层1015和第二金属层1115相对于彼此可以具有一定的刻蚀选择性，例如具有不同的材料。在一个示例中，第一金属层1015是Ru层，而第二金属层1115是Mo层。第一金属层1015可以具有针对第一互连线层的厚度，例如为约5nm-100nm；第二金属层1115可以具有针对第一过孔层的厚度，例如为约5nm-100nm。
根据本公开的实施例，可以通过如下方式来纯化Ru源，以获得高纯度Ru金属。可以将包括臭氧(O 3)的气流引入一个或多个反应室中与Ru源相接触，从而形成在反应条件下为气态的四氧化钌(RuO 4)。可以将四氧化钌以及未反应的臭氧和气流的残余物送入收集室，在收集室中，可以将气态的四氧化钌还原成半导体衬底上的二氧化钌(RuO 2)层。然后，可以利用例如氢，将淀积的二氧化钌还原，以产生高纯度的Ru金属。另外，可以使用臭氧作为刻蚀气体，来对淀积的Ru金属层进行刻蚀和构图。
如图3(a)至图3(c)所示，可以将第一金属层1015和第二金属层1115构图为一系列金属线。构图可以通过光刻工艺进行，例如，隔墙图形转移光刻或者极紫外(EUV)光刻等。在光刻中，可以采用反应离子刻蚀(RIE)，RIE可以停止于第一金属层1015下方的层间电介质层1011(或其中的接触部1013)。金属线之间的间隔可以限定第一互连线层中的互连线之间的间隔，例如为约5nm-150nm。另外，为了避免同一层中图案的密度在不同区域之间波动过大，可以形成虚设金属线，从而金属线例如以大致均匀的间隔布置。金属线的线宽可以限定第一互连线层中的互连线的线宽，例如为约5nm-100nm。另外，至少一部分金属线可以接触并电连接到下方的接触部1013。
在该示例中，所形成的金属线沿第一方向(图3(a)中纸面上的水平方向)大致平行延伸，可以与之后形成的沿与第一方向交叉(例如，垂直)的第二方向延伸的金属线相配合，以实现各种互连路线。但是，本公开不限于此。例如， 不同金属线可以沿不同方向延伸，且同一金属线可以曲折延伸。
如图4(a)和4(b)所示，可以在层间电介质层1011上形成另一层间电介质层，以填充金属线1015、1115之间的间隙。另一层间电介质层可以包括电介质材料如氧化硅、碳氧化硅、其他低k电介质材料等。在此，该另一层间电介质层与之前的层间电介质层1011可以包括相同的材料，并因此可以一体示出为1011，并以虚线示意性示出了它们之间可能存在的边界。当然，它们也可以包括不同的材料。
该另一层间电介质层可以通过淀积(例如，CVD或ALD)电介质材料以覆盖金属线1015、1115，然后回蚀或平坦化(例如，化学机械抛光(CMP))淀积的电介质材料并停止于金属线1115的顶面来形成。回蚀可以采用原子层刻蚀(ALE)，以实现良好的工艺控制。
在图4(a)和4(b)所示的示例中，淀积的电介质材料完全填充了金属线1015、1115之间的间隙。但是，本公开不限于此。如图5(a)和5(b)所示，由于金属线1015之间的间隙较小，在淀积电介质材料时，例如在采用CVD工艺时，可以在金属线1015之间形成气隙或孔洞1017。这种气隙或孔洞1017有助于降低金属线之间的电容。
根据本公开的实施例，通过调整淀积工艺，可以调节气隙或孔洞1017在竖直方向上的位置。
例如，如图6(a)所示，可以向金属线1015、1115之间的间隙中淀积电介质材料，直至电介质材料使间隙的顶部闭合。在淀积过程中，可以使用多层(相同或不同材料的)膜。这种情况下，所形成的气隙或孔洞1017a可以位于间隙在竖直方向上的大致中部。
或者，如图6(b)所示，可以向金属线1015、1115之间的间隙中淀积电介质材料，但不使间隙的顶部闭合。然后，可以对淀积的电介质材料进行选择性刻蚀如RIE，留下一部分在间隙的底部，从而使得电介质材料中的开口增大。接着，可以继续淀积电介质材料，直至电介质材料使间隙的顶部闭合。两次淀积的电介质材料可以相同或不同。当然，可以多次重复这种淀积-刻蚀-淀积的过程。这种情况下，所形成的气隙或孔洞1017b可以位于间隙在竖直方向上的下部。
或者，如图6(c)所示，可以向金属线1015之间的间隙中淀积电介质材料，直至电介质材料可以完全填充间隙。然后，可以对淀积的电介质材料进行选择性刻蚀如RIE，留下一部分在间隙的底部。接着，可以继续淀积电介质材料，直至电介质材料使间隙的顶部闭合。两次淀积的电介质材料可以相同或不同。当然，可以多次重复这种淀积-刻蚀-淀积的过程。这种情况下，所形成的气隙或孔洞1017c可以位于间隙在竖直方向上的上部。
如上所述，通过交替执行淀积和刻蚀，可以上下调节金属线间隙之间的气隙或孔洞的位置。
当前，用于第一过孔层的第二金属层的图案与用于第一互连线层的第一金属层的图案(即，上述的金属线图案)相同。可以对用于第一过孔层的第二金属层(当前为金属线的形式)进一步构图，以形成过孔图案。
如图7所示，可以在层间电介质层1011和金属线1115上形成光刻胶1019，并将光刻胶1019构图(例如，通过曝光和显影)为覆盖将要形成过孔的区域，而露出其余区域。
在此，光刻胶1019的宽度W1(由此限定的第一过孔层中过孔的宽度)(在金属线纵向延伸方向上的尺度，在该示例中，图7中纸面内水平方向上的尺度)可以相对较大，以便之后在其上方形成的第二互连线层中的互连线可以更好地着落在过孔上从而与过孔更好地接触。
如图8(a)至8(c)所示，可以利用光刻胶1019作为刻蚀掩模，对金属线1115进行选择性刻蚀如RIE，以形成过孔。根据实施例，对金属线1115的刻蚀可以相对于金属线1015具有刻蚀选择性，从而可以停止于金属线1015的顶面。当然，本公开不限于此，也可以使用终点检测来确定刻蚀是否到达金属线1015的顶面。这样，金属线1115可以形成为一些分离图案(可以形成第一过孔层中的过孔，参见图8(a)的俯视图)。之后，可以去除光刻胶1019。
由于过孔从光刻形成的线来获得，因此过孔之间的最小间隔可以由光刻工艺所能实现的最小线间隔来限定(例如，相等)。而通常情况下，光刻形成的过孔之间的最小间隔大于线之间的最小间隔。
另外，用于第一互连线层的金属线1015当前保持连续延伸。可以根据设计布局，将它们分离为多个部分。
如图9所示，可以在层间电介质层1011和金属线1015、1115上形成光刻胶1021，并将光刻胶1021构图为覆盖第一互连线层的图案中存在互连线的区域，而露出第一互连线层的图案中不存在互连线的区域。
如图10(a)至10(d)所示，可以利用光刻胶1021作为刻蚀掩模，对金属线1015进行选择性刻蚀如RIE。在此，对金属线1015的刻蚀可以停止于下方的层间电介质层1011，以将金属线1015切断。于是，在第一互连线层中，金属线1015可以形成一些分离的金属线段，得到相应的互连线。之后，可以去除光刻胶1021。
在以上示例中，先构图第一过孔层中的过孔(对金属线1115的刻蚀)，然后构图第一互连线层中的互连线(对金属线1015的刻蚀)。这是有利的，因为每一刻蚀处理的刻蚀深度减小。但是，本公开不限于此。例如，这两个构图处理的顺序可以交换。
如图10(b)所示，金属线1015在层间电介质层1011上延伸，形成互连线；金属线1115被构图为互连线上的局域化图案，形成过孔。由于金属线1015、1115可以通过相同的光刻工艺形成(之后再分别经历进一步的切断处理以形成互连线和过孔)，因此互连线1015和过孔1115可以彼此自对准。
另外，如图10(b)中最右侧的过孔1115中的虚线所示，对于同一互连线上的相邻过孔，在不会造成上层互连线之间不正确电连接的情况下，它们之间的金属线厚度可以不减小。也即，相邻过孔的宽度增大从而彼此连接成一体。这样，可以减小连接电阻。
另外，如图10(b)所示，在互连线1015的纵向延伸方向(图10(b)中纸面内的水平方向)上，过孔1115可以位于互连线的局部区域内，例如过孔的侧壁相对于互连线的相应侧壁缩进。另外，如图10(c)和10(d)所示，在垂直于互连线1015的纵向延伸方向的截面中，过孔1115的侧壁与互连线的相应侧壁可以实质上共面。
由于以上对金属线1015、1115的刻蚀，层间电介质层1011中形成了空隙。如图11(a)至11(d)所示，可以利用电介质材料将这些空隙填满。这可以通过如上所述的淀积然后回蚀或平坦化的方式来进行。淀积的电介质材料可以与之前的层间电介质层1011相同或不同。在此，仍将淀积的电介质材料和之前的层 间电介质层一体示出为1011，并以虚线示意性示出了它们之间可能存在的边界。根据其他实施例，可以在淀积电介质材料之前，先通过例如淀积形成一薄层，以用于扩散阻挡、保护或刻蚀停止等目的。
类似地，如上所述，由于要填充的间隙较小，在淀积电介质材料时，可能形成气隙或孔洞1023，如图12(a)至12(c)所示。气隙或孔洞1023可以根据相应间隙的形状而不同。另外，如上所述，可以通过调整淀积工艺，可以调节气隙或孔洞1023在竖直方向上的位置。
另外，图13(a)和13(b)示出了在两次填充层间电介质层中的间隙时均形成气隙或孔洞的情况。也即，在图13(a)和13(b)所示的示例中，结合了上述的气隙或孔洞1017以及气隙或孔洞1023。
通过上述工艺，形成了第一互连线层和第一过孔层。接下来，可以按照同样的方式，继续形成金属化叠层中上层的各互连线层和过孔层。
但是，本公开不限于此。以下，结合第二互连线层和第二过孔层，说明根据本公开另一实施例的制造方法。如下说明的方法可以单独使用，或者可以与以上说明的方法结合使用。
如图14(a)至14(d)所示，如以上结合图2所述，可以形成用于金属化叠层中第二互连线层的第三金属层1025和用于金属化叠层中第二过孔层的第四金属层1125。第三金属层1025和第四金属层1125可以包括与第一金属层1015和第二金属层1115相同或不同的金属材料。例如，第三金属层1025可以包括与第一金属层1015相同的材料如Ru，第四金属层1125可以包括与第二金属层1115相同的材料如Mo。类似地，第三金属层1025可以具有针对第二互连线层的厚度，例如为约5nm-100nm；第四金属层1125可以具有针对第二过孔层的厚度，例如为约5nm-100nm。
然后，如以上结合图3(a)至图3(c)所述，可以将第三金属层1025和第四金属层1125构图为一系列金属线。在该示例中，代替将第三金属层1025和第四金属层1125构图为连续延伸的金属线，可以直接按照第二互连线层的图案来构图第三金属层1025和第四金属层1125。于是，第三金属层1025和第四金属层1125可以被构图为一系列金属线段。也即，在此，将以上结合图9和图10(a)至10(d)所述的金属线切断处理结合到与金属层构图一起进行，从而不 需要单独的切断光刻工艺。另外，由于这种构图方式，金属线段可以不限于直线段，而是可以包括曲折线段。于是，金属线段1025形成第二互连线层中的互连线。
另外，在对第三金属层1025和第四金属层1125刻蚀时，可以发生对下方的过孔1115的过刻蚀。于是，如图14(b)所示，第一过孔层中过孔1115的上部的宽度可以减小，且与之上形成的金属线段1025的线宽大致相同。另外，如图14(b)所示，金属线段1025的线宽W2(图14(b)中纸面内水平方向上的尺度)可以相对较小，小于第一过孔层中过孔(不考虑其上部，其宽度由于上述过刻蚀而可能缩减)的宽度W1(图14(b)中纸面内水平方向上的尺度)，从而金属线段1025(随后形成第二互连线层中的互连线)可以更好地着落在过孔上从而与过孔更好地接触。
可以在层间电介质层1011上形成另一层间电介质层，以填充金属线段1025、1125之间的间隙。另一层间电介质层可以包括电介质材料如氧化硅、碳氧化硅、其他低k电介质材料等。
该另一层间电介质层如下所述形成。
如图15(a)所示，可以通过淀积(例如，CVD或ALD)电介质材料以覆盖金属线段1025、1125。在此，淀积的电介质材料与之前的层间电介质层1011可以包括相同的材料，并因此可以一体示出为1011，并以虚线示意性示出了它们之间可能存在的边界。当然，它们也可以包括不同的材料。
或者，如上所述，如图15(b)所示，在淀积电介质材料时，可以在金属线段1025、1125之间形成气隙或孔洞1027。在该示例中，由于金属线段具有第二互连线层的图案，因此部分区域中金属线段的密度可以较低，或者说金属线段之间的间隙可能较大。在这些区域中，难以形成气隙或孔洞。
然后，如图16所示，可以回蚀或平坦化如CMP淀积的电介质材料并停止于金属线段1125的顶面。回蚀可以采用ALE，以实现良好的工艺控制。
之后，可以按照以上结合图7和8(a)至8(c)描述的工艺，由金属线段1125形成第二过孔层中的过孔。然后，可以按照以上结合图11(a)至11(d)描述的工艺，利用电介质材料填充层间电介质层1011中的空隙。这样，形成了第二互连线层和第二过孔层。
图17至24(d)示意性示出了根据本公开另一实施例的制造金属化叠层的流程中的一些阶段。以下，将主要描述与以上结合图1至16描述的实施例之间的不同之处。
如图17所示，可以在层间电介质层1011上形成用于金属化叠层中第一互连线层的第一金属层1015和用于金属化叠层中第一过孔层的第二金属层1215，如以上参考图2所述。第一金属层1015和第二金属层1215可以包括相同的材料如Ru，当然也可以如上述实施例中那样包括不同的材料。与上述实施例的不同之处在于，在第一金属层1015与第二金属层1215之间，可以通过例如淀积，另外设置间隔层1201。例如，间隔层1201可以用作第一金属层1015与第二金属层1215之间的扩散阻挡层或者刻蚀停止层。例如，间隔层1201可以包括导电的金属硅化物如NiSi、NiPtSi、CoSi等，或者导电的金属氮化物如TiN、TaN等，或者金属如Ti、Pt等，厚度为约1nm-10nm。
如图18(a)至图18(c)所示，可以将第一金属层1015、间隔层1201和第二金属层1215构图为一系列线形图案，如以上参考图3(a)至图3(c)所述。
如图19(a)和19(b)所示，可以在层间电介质层1011上形成另一层间电介质层，以填充线形图案之间的间隙，如以上参考图4(a)和4(b)所述。同样地，可能形成气隙或孔洞1017，如图20(a)和20(b)所示。
如图21以及图22(a)至22(c)所示，可以形成光刻胶1019，并对第二金属层1215进行选择性刻蚀如RIE，以将其构图为过孔，如以上参考图7以及图8(a)至8(c)所述。在此，刻蚀可以停止于间隔层1201。
如图23以及图24(a)至24(d)所示，可以形成光刻胶1021，对间隔层1201和第一金属层1015进行选择性刻蚀如RIE，以形成互连线，如以上参考图9以及图10(a)至10(d)所述。如图24(a)至24(d)所示，间隔层1201(例如，用作扩散阻挡层)可以仅在过孔1215的底面上或者互连线1015的底面上延伸，而没有延伸到过孔1215的侧壁上，这与常规工艺形成的扩散阻挡层不同。
另外，在以上参考图14(a)至图16描述的工艺中，在第三金属层与第四金属层之间，也可以结合间隔层。关于间隔层，在对第四金属层构图时可以用作刻蚀停止层，另外间隔层本身可以与第三金属层一起构图。其他方面可以与上述实施例相同。
根据本公开实施例的金属化叠层可以应用于各种电子设备。因此，本公开还提供了一种包括上述金属化叠层的电子设备。电子设备还可以包括显示屏幕以及无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (40)

  1. 一种金属化叠层，包括在衬底上交替设置的至少一个互连线层和至少一个过孔层，其中所述金属化叠层中至少一对相邻的互连线层和过孔层包括：
    所述互连线层中的互连线；以及
    所述过孔层中的过孔，
    其中，所述互连线层比所述过孔层更靠近衬底，
    其中，所述互连线的至少一部分上的过孔的外周侧壁不超出所述互连线的所述至少一部分的外周侧壁。
  2. 根据权利要求1所述的金属化叠层，其中，所述互连线的所述至少一部分沿其纵向延伸方向的侧壁与所述过孔的相应侧壁的至少下部实质上共面。
  3. 根据权利要求1或2所述的金属化叠层，其中，所述互连线和所述过孔包括金属，且与周围的电介质层直接接触。
  4. 根据权利要求3所述的金属化叠层，其中，所述金属包括钌Ru、钼Mo、铑Rh、铂Pt、铱Ir、镍Ni、钴Co或铬Cr。
  5. 根据权利要求1或2所述的金属化叠层，其中，所述互连线和所述过孔包括彼此不同的材料。
  6. 根据权利要求1或2所述的金属化叠层，还包括：设于所述互连线和所述过孔之间的间隔层。
  7. 根据权利要求6所述的金属化叠层，其中，所述互连线和所述过孔包括彼此相同的材料。
  8. 根据权利要求6所述的金属化叠层，其中，所述间隔层在所述互连线与所述过孔之间延伸，而没有延伸到所述过孔的侧壁上。
  9. 根据权利要求6所述的金属化叠层，其中，所述间隔层用作扩散阻挡层和/或刻蚀停止层。
  10. 根据权利要求9所述的金属化叠层，其中，所述间隔层包括导电的金属硅化物、导电的金属氮化物或金属。
  11. 根据权利要求1或2所述的金属化叠层，还包括：围绕所述互连线和所述过孔的电介质层，其中，所述电介质层中在所述互连线之间和/或所述过 孔之间包括孔洞或气隙。
  12. 根据权利要求1或2所述的金属化叠层，其中，所述互连线层中的各条互连线沿同一方向延伸。
  13. 根据权利要求12所述的金属化叠层，其中，至少一对上下相邻的互连线层中的互连线沿彼此正交的方向延伸。
  14. 根据权利要求1或2或13所述的金属化叠层，其中，所述过孔的宽度大于该过孔上的互连线的宽度。
  15. 根据权利要求14所述的金属化叠层，其中，所述过孔的上部与该过孔上的互连线的宽度基本相同，而所述过孔的下部的宽度大于该过孔上的互连线的宽度。
  16. 根据权利要求1或2所述的金属化叠层，其中，在与所述互连线的纵向延伸方向垂直的截面中，所述过孔和所述互连线呈从下往上渐缩的形状。
  17. 根据权利要求1或2所述的金属化叠层，其中，过孔之间的最小间隔由光刻工艺能够实现的最小线间隔限定。
  18. 一种制造金属化叠层的方法，所述金属化叠层包括交替设置的至少一个互连线层和至少一个过孔层，所述方法包括通过以下操作来形成所述金属化叠层中至少一对相邻的互连线层和过孔层：
    在下层上形成第一金属层；
    在第一金属层上形成第二金属层；
    将第一金属层和第二金属层构图为互连图案；
    将第二金属层构图为分离的部分，以形成所述过孔层中的过孔，
    其中，由第一金属层形成所述互连线层中的互连线。
  19. 根据权利要求18所述的方法，还包括：
    在第一金属层与第二金属层之间设置间隔层，
    其中，将第一金属层和第二金属层构图为互连图案包括将间隔层与第一金属层和第二金属层一起构图为互连图案。
  20. 根据权利要求19所述的方法，其中，对第二金属层的构图停止于间隔层。
  21. 根据权利要求18或19所述的方法，其中，所述金属化叠层中各对相 邻的互连线层和过孔层均通过所述操作来形成。
  22. 根据权利要求18或19所述的方法，其中，所述第一金属层和所述第二金属层各自包括钌Ru、钼Mo、铑Rh、铂Pt、铱Ir、镍Ni、钴Co或铬Cr。
  23. 根据权利要求18或19所述的方法，其中，形成的第一金属层遍及所述下层的基本上整个表面，形成的第二金属层遍及第一金属层的基本上整个表面。
  24. 根据权利要求18或19所述的方法，其中，所述构图包括光刻。
  25. 根据权利要求24所述的方法，其中，光刻包括隔墙图形转移或极紫外光刻。
  26. 根据权利要求18或19所述的方法，其中，
    将第一金属层和第二金属层构图为互连图案包括：将第一金属层和第二金属层构图为一系列金属线，
    该方法还包括：在所述金属线之间填充第一电介质层。
  27. 根据权利要求26所述的方法，还包括：
    在所述金属线之间的所述第一电介质层中形成孔洞或气隙。
  28. 根据权利要求27所述的方法，其中，形成孔洞或气隙包括：
    通过向所述金属线之间的空间中淀积电介质材料，使所述空间的顶部封闭，来填充所述第一电介质层，
    其中，所述孔洞或气隙形成在所述空间的基本上中部。
  29. 根据权利要求28所述的方法，其中，淀积电介质材料包括：淀积多层相同或不同的电介质材料。
  30. 根据权利要求27所述的方法，其中，形成孔洞或气隙包括通过以下操作来填充所述第一电介质层：
    向所述金属线之间的空间中淀积第一电介质材料，使淀积的第一电介质材料在所述空间的顶部具有开口；
    对所淀积的第一电介质材料进行选择性刻蚀，使其开口增大；以及
    向所述金属线之间的空间中进一步淀积第二电介质材料，使所述空间的顶部封闭，
    其中，所述孔洞或气隙形成在所述空间的下部，
    其中，第一电介质材料与第二电介质材料相同或不同。
  31. 根据权利要求27所述的方法，其中，形成孔洞或气隙包括通过以下操作来填充所述第一电介质层：
    向所述金属线之间的空间中淀积第一电介质材料，以完全填充所述空间；
    对所淀积的第一电介质材料进行选择性刻蚀，使其留于所述空间的底部；以及
    向所述金属线之间的空间中进一步淀积第二电介质材料，使所述空间的顶部封闭，
    其中，所述孔洞或气隙形成在所述空间的上部，
    其中，第一电介质材料与第二电介质材料相同或不同。
  32. 根据权利要求26所述的方法，其中，
    所述一系列金属线沿同一方向连续延伸，
    所述方法还包括：
    在预定区域处切断所述一系列金属线中至少一条由第一金属层形成的金属线，以形成互连线；以及
    在所述金属线之间由于所述构图和所述切断而形成的空间中，填充第二电介质层，
    其中，第一电介质层和第二电介质层包括相同或不同的材料。
  33. 根据权利要求32所述的方法，还包括：
    在所述金属线之间的所述第二电介质层中形成孔洞或气隙。
  34. 根据权利要求26所述的方法，其中，
    所述一系列金属线的图案对应于相应互连线层中互连线的布局。
  35. 根据权利要求21所述的方法，其中，对于相邻的两对互连线层和过孔层，在形成上方的一对互连线层和过孔层的操作中，所述构图包括过刻蚀。
  36. 根据权利要求18或19所述的方法，其中，将第二金属层构图为分离的部分包括：
    对于金属化叠层的设计布局中同一互连线上相邻的两个过孔，不将之分离，从而形成针对这两个过孔的共享过孔。
  37. 根据权利要求18或19所述的方法，其中，在所述互连图案与围绕所 述互连图案的电介质层之间，不形成扩散阻挡层。
  38. 根据权利要求18或19所述的方法，其中，过孔的宽度大于该过孔上的互连线的宽度。
  39. 一种电子设备，包括如权利要求1至18中任一项所述的金属化叠层。
  40. 根据权利要求39所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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