WO2021107409A1 - Method for filling via hole of circuit board and circuit board manufactured using same - Google Patents

Abstract

The present invention provides a method for filling a via hole of a circuit board with a conductive material, comprising the steps of: forming a via hole in a board; forming an electroless plating layer with a predetermined thickness on the inner surface of the via hole by means of electroless plating; performing bridge plating such that a bridge is formed in a partial area inside the via hole by means of electroplating that applies a pulse waveform to the electroless plating layer; and performing via hole fill plating in the via hole on which the bridge plating has been formed by electroplating, wherein the bridge plating and the via hole fill plating are performed using the same plating solution as each other.

Description

Method for filling through-holes in circuit boards and circuit boards manufactured using the same

The present invention relates to a method for filling a through-hole of a circuit board and a circuit board manufactured thereby, and more particularly, to a method for filling a conductive material in a through-hole in order to electrically connect circuits formed on different surfaces of the substrate; Thereby, it relates to a circuit board manufactured.

A circuit board in which a predetermined circuit is integrated is widely used in electronic devices such as mobile terminals and display devices. A circuit board is a board in which a wiring pattern is formed on an insulating board by using a printing technique, a plating technique, an etching technique, or the like. Circuit boards are divided into single-sided printed circuit boards, double-sided printed circuit boards, multilayer printed circuit boards, and the like according to the formation structure of the wiring pattern. In a double-sided printed circuit board and a multi-layer printed circuit board, a through-hole or a via hole processed by a CNC drill or a laser drill is formed in order to connect the wiring patterns of different layers. Various methods have been used to form a conductive material on a resin of an inner wall of a through hole or a via hole.

Recently, due to the miniaturization of electronic devices, the diameter of a through hole or a via hole applied to a circuit board is also decreasing, and accordingly, an aspect ratio, which means a ratio of a diameter to a depth of the hole, is also increasing. In the process of filling the conductive material inside the through hole having a high aspect ratio, it is important that pores are not formed therein. When pores are formed inside the through-hole, a defect in which electrical connection is not made occurs or electrical resistance is partially increased, which causes the circuit not to operate normally or to generate a lot of heat.

One of the methods for filling the through-holes of the circuit board with a conductive material is to form an electroless plating layer on the inner surface of the through-hole by electroless plating, and then apply an electric current to the electroless plating layer to perform electroplating. Korean Patent Registration No. 1418034 is a prior document on a technique for filling a conductive material in a through hole of a circuit board. The prior literature discloses A) a step of preparing a multilayer printed circuit board in which a plurality of conductors and insulators are cross-stacked and having through holes formed therein, and B) an anionic oxide film by oxidizing the surface of the conductor exposed through the through holes in the substrate. Forming a layer, C) coating the entire substrate including the through hole with conductive anionic carbon, and D) using a micro-etching solution to coat the conductive anion carbon on the entire conductor surface of the substrate including the through hole Disclosed is a technique for a method of manufacturing a multilayer printed circuit board, comprising the steps of removing and E) electroplating the substrate to electrically connect the plurality of conductors. However, the technique disclosed in the prior art has a disadvantage in that the process cost is high because the pretreatment step before the electroplating step is complicated, and does not include a technical feature for suppressing the generation of pores in the through-hole in the electroplating step.

Therefore, there is a great need to develop a new technology capable of suppressing the generation of pores inside the through-hole by controlling the process conditions in the electroplating process while simplifying the configuration of the pre-filling step of the through-hole and reducing the process cost.

The first problem to be solved by the present invention is to reduce the process cost in the plating process for filling the conductive material inside the through hole of the circuit board, and to achieve complete filling so that pores are not formed inside the through hole. To provide a hole filling method.

A second problem to be solved by the present invention is to provide a circuit board manufactured by using the method for filling the through-holes of the circuit board.

In order to achieve the first object, the present invention is a method of filling a through hole of a circuit board with a conductive material, the method comprising: forming a through hole in the substrate; and electroless plating on the inner surface of the through hole to a predetermined thickness forming an electroless plating layer by using a method, performing bridge plating on the electroless plating layer to form a bridge in a partial region of the through hole by electroplating the through hole through electroplating in the through hole on which the bridge plating is made and performing fill plating, wherein the bridge plating and the through-hole fill plating are performed using the same plating solution.

According to one embodiment of the present invention, a reverse pulse waveform may be applied to the bridge plating.

According to another embodiment of the present invention, the reverse pulse waveform may be applied to the upper and lower portions of the circuit board under different conditions.

According to another embodiment of the present invention, a reverse pulse waveform may be applied to the through-hole filling plating.

In order to achieve the second object of the present invention, there is provided a circuit board manufactured by the method for filling the through-holes of the circuit board.

The method for filling the through-holes of the circuit board of the present invention has the following effects.

Since bridge plating and through-hole filling plating are performed using one type of plating solution, the process can be simplified and an increase in process cost due to replacement of the plating solution can be suppressed.

In the bridge plating process, reverse pulse waveforms of different timings are applied to the upper and lower surfaces of the substrate to generate a bridge in the inner central portion of the through hole.

By applying a predetermined reverse pulse waveform during the through-hole filling plating process, it is possible to suppress the formation of pores inside the through-hole during the through-hole filling process.

In the overcoat plating, a plating film having a predetermined thickness may be formed in the through-hole and the peripheral portion after filling the through-hole by applying a predetermined reverse pulse waveform.

1 is a sequential view of a through-hole filling process of a circuit board.

FIG. 2 illustrates a process in which the inside of the through-hole is filled with a conductive material by the through-hole filling process shown in FIG. 1 .

3 is a sequential view of the circuit board through-hole filling process of the present invention.

FIG. 4 illustrates a process in which the inside of the through-hole is filled with a conductive material by the through-hole filling process shown in FIG. 3 .

5 and 6 show current waveforms applied in the bridge plating step of the circuit board through-hole filling method of the present invention.

7 shows the current waveform applied in the through-hole filling plating step of the circuit board through-hole filling method of the present invention.

8 is a view showing a current waveform applied in the overcoat plating step of the circuit board through-hole filling method of the present invention.

9 is a cross-sectional photograph after filling the circuit board through-holes by plating.

The present invention provides a method for filling a conductive material inside a through hole of a circuit board, comprising the steps of: forming a through hole in a substrate; forming an electroless plating layer to a predetermined thickness on an inner surface of the through hole by electroless plating; , performing bridge plating on the electroless plating layer so that a bridge is generated in a partial region inside the through hole by electroplating, and performing through-hole filling plating by electrolytic plating on the through hole on which the bridge plating is made, , The bridge plating and the through-hole filling plating are performed using the same plating solution.

A circuit board is an electronic device in which a predetermined circuit pattern is implemented on a board. Although the circuit pattern of the circuit board is composed of a single layer, it is also composed of multiple layers to improve the degree of integration, and in this case, a means for electrically connecting the circuit patterns formed on different layers is required. A method of connecting the circuit patterns of different layers is to form a through hole in a substrate by a method such as laser drilling, and to fill the inside of the through hole with a conductor. At this time, since the surface of the through-hole formed in the substrate is made of an insulator, a thin electroless plating layer is formed on the surface using electroless plating, and an electric current is applied to the electroless plating layer to perform electroplating. In the process of filling the conductive material inside the through-hole using the plating method, if the growth rate of the plating film on the upper or lower part of the through-hole is fast, it becomes difficult to fill the conductive material in the middle area of the through-hole. Therefore, a special technique is required for the plating method for through-hole filling. need.

FIG. 1 shows a through-hole filling process of a circuit board sequentially, and FIG. 2 shows a process in which the inside of the through-hole is filled with a conductive material by the through-hole filling process shown in FIG. 1 . 1 and 2 , first, a through hole 102 having a predetermined diameter is formed by drilling a substrate 101 . Then, electroless plating is performed to form the electroless plating layer 103 on the inner surface of the through hole 102 . At this time, the electroless plating layer 103 is formed not only on the inside of the through hole, but also on the upper and lower surfaces of the substrate. Next, bridge plating is performed using the first plating solution. In the bridge plating process, a current is applied to the electroless plating layer 103 , and a plating film is grown in an intermediate depth region inside the through hole 102 to form the bridge plating portion 104a. Next, the through-hole filling part 104 is formed by filling the inside of the through-hole by electroplating using the second plating solution. In this case, it is common that the second plating solution has a different component and composition from the first plating solution. As described above, in the existing through-hole filling method, two types of plating solution divided into a plating solution for the bridge forming step and a plating solution for filling are used, which causes inconvenience in plating solution management and process. However, in the present invention, unlike the case of using two types of plating solution (two-component solution), one type of plating solution (one-component solution) is used. have.

The method for filling through-holes in a circuit board of the present invention is characterized in that the electrolytic plating process after electroless plating consists of bridge plating and through-hole filling plating, and a plating solution having the same component and composition is used in the bridge plating and through-hole filling plating process. do. The plating solution includes copper sulfate, sulfuric acid, chlorine, a brightener, a carrier and a leveler. In the conventional plating technique for filling through-holes, the bridge plating solution does not include a leveler, but in the through-hole filling plating of the present invention, a leveler is included in both the bridge plating solution and the through-hole filling plating solution, and the composition ratio of the leveler is low. As described above, since the leveler is included in both the bridge plating solution and the through-hole filling plating solution, two-step plating can be performed in one plating bath, thereby reducing process costs. A preferred composition of the bridge plating solution and the through-hole filling plating solution is 200 to 300 parts by weight of copper sulfate, 0.5 to 4 parts by weight of a brightener, 70 to 130 parts by weight of a carrier, and 2 to 8 parts by weight of a leveler based on 100 parts by weight of sulfuric acid. 50 to 100 ppm of chlorine relative to the total plating solution may be included in the plating solution. In addition, in the through-hole filling method of the present invention, reverse pulse waveforms with different timings are applied to the front and back surfaces of the substrate in the bridge plating process, and predetermined reverse pulse waveforms are applied in the through-hole filling plating process and the overcoat plating process.

FIG. 3 sequentially shows the circuit board through-hole filling process of the present invention, and FIG. 4 shows a process in which the inside of the through-hole is filled with a conductive material by the through-hole filling process shown in FIG. 3 .

3 and 4 , first, a through hole 202 is formed in the substrate 201 .

Next, an electroless plating layer 203 is formed on the through hole 202 and the surface of the substrate 201 . The electroless plating layer 203 may be made of copper. As the electroless plating solution, a plating solution having a known component and composition may be used. The electroless plating solution contains a copper ion source, a copper ion complexing agent, a copper ion reducing agent and a pH adjusting agent, and further contains an additive for the purpose of improving the mechanical properties of the plating film(s) or the stability of the plating solution. The main required technology of such electroless plating is to ensure uniformity of the entire surface of the inner wall of the through hole. In a portion such as inside a through hole where convection of the used plating solution is not sufficiently performed, the concentrations of copper ions (complex), reducing agents and hydroxides, which are the main components of the plating reaction, decrease, and the uniform precipitation property is greatly reduced. In order to solve this problem, in the present invention, in addition to the copper ion source (copper salt), copper ion complexing agent, copper ion reducing agent, and pH adjusting agent of the electroless plating solution, the uniform precipitation property is improved by using one or more additives, It is possible to ensure a constant plating thickness of the inner wall of the hole. Copper sulfate may be used as the copper ion source, and EDTA may be used as a complexing agent for stabilization in an alkali plating solution. Although the redox potential of the reducing agent is lower than the copper redox potential and the reaction occurs, it does not actually create a decomposition reaction in the plating solution and does not form an insoluble precipitate by combining with other compositions, and there is a condition that the reaction rate as a catalyst must be fast. As such a reducing agent, formalin or sodium borohydride may be used. The pH adjusting agent is used for the purpose of supplying OH required for the oxidation reaction of formalin, and sodium hydroxide, potassium hydroxide, etc. may be used. As the additive, ethylenediaminetetraacetic acid, hydroxyethylethylenetriacetic acid, cyclohexanediaminetetraacetic acid, diethylenetriaminepentaacetic acid, tetrakis(2-hydroxypropyl)ethyldiamine, and the like may be used. The plating operation conditions are a temperature of 20 to 60° C., a pH of 11 to 14, and it is preferable to work at a pH as high as possible in terms of plating speed. The plating rate is 10 μm/Hr, and copper ions can easily precipitate under conditions where the plating rate is too fast, and thus solution stability tends to be poor.

Next, bridge plating is performed to bridge the copper plating film in the through hole 202 (the electroless plating layer 203 ). In this case, the bridge plating may be performed by an electrolytic plating method, and a pulse and/or a reverse pulse waveform may be applied during the electrolytic plating process. The application of the reverse pulse waveform is to keep the thickness of the plating film constant, and in particular, it reduces the dog bone effect that may occur at the edges of the upper and lower regions of the through hole 202 , ) can prevent the bridge from rising first. The plating solution used for the bridge plating may include sulfuric acid, copper sulfate, chlorine, a brightener, a carrier, and a leveler. The composition ratio of the plating solution is 200 to 300 parts by weight of copper sulfate based on 100 parts by weight of sulfuric acid, 50 to 150 parts by weight of a carrier (specifically 70 to 130 parts by weight), 0.5 to 5 parts by weight of a brightener (specifically 0.5 to 4 parts by weight), Leveler may be 1 to 10 parts by weight (specifically 2 to 8 parts by weight), and chlorine is preferably 30 to 120 ppm (specifically 50 to 100 ppm) based on the total weight of the plating solution. In this case, the chlorine refers to chlorine ions generated by adding diluted hydrochloric acid to the plating solution.

The brightener is (O-ethyldithiocarbonato)-S-(3-sulfopropyl)-ester, 3-[(amino-iminomethyl)-thiol]-1-propane sulfonic acid, 3-(benzothiazole- 2-Mercapto)-propyl sulfonic acid, sodium bis-(sulfopropyl)-disulfide, N,N-dimethyl dithiocarbamile propyl sulfonic acid, 3,3-thiobis(1-propane sulfonic acid), 2-hydroxy-3 -[tris(hydroxymethyl)methylamino]-1-propane sulfonic acid, sodium 2,3-dimercaptopropane sulfonic acid, 3-mercapto-1-propane sulfonic acid, 5,5'-dithiobis(2-nitrobenzoic acid) ), DL-cysteine, 4-mercapto-benzene sulfonic acid and 5-mercapto-1H-tetrazole-1-methane sulfonic acid.

The carrier comprises polyoxyalkylene glycol, carboxymethylcellulose, octanediol bis glycol ether, oleic acid polyglycol ester, polyethylene glycol, polyethylene glycol dimethyl ether, polyethylene glycol-block-polypropylene glycol-block-polyethylene glycol, polypropylene glycol, Polyvinyl alcohol, stearyl alcohol polyglycol ether, stearic acid polyglycol ester, 3-methyl-1-butyn-3-ol, 3-methyl-penten-3-ol, L-ethynylcyclohexanol, phenyl propynol , 3-phenyl-1-butyn-3-ol, propargyl alcohol, methyl butynol-ethylene oxide, 2-methyl-4-chloro-3-butain-2-ol, dimethyl hexaindiol, dimethylocta and at least one of the group consisting of indiol, phenylbutinol and 1,4-butanediol diglycidyl ether.

The leveler is a saturated heterocyclic compound containing one or two of nitrogen, oxygen, sulfur, and phosphorus, aziridine, oxirane, thiirane, diaziridine, oxaziridine, dioxirane, azetidine, ox Cetane, thietane, diazetidine, dioxetane, dithiethane, pyrrolidine, thiolane, phosphorane, imidazolidine, pyrazolidine, oxazolidine, isoxazolidine, thiazolidine, isothiazolidine , dioxolane, dithiolane, piperidine, oxane, thiane, phosphinan, piperazine, morpholine, thiomorpholine, dioxane, dithiane, azepane, homopyrerazine, azocan, oxocan, thiocane, It may be an organic compound comprising at least one of the group of substances consisting of azonane, oxonane and thionane.

5 and 6 show an example of the reverse pulse waveform applied in the bridge plating step of the circuit board through-hole filling method of the present invention. FIG. 5 is a waveform applied to the upper portion (front) of the substrate 201, and FIG. 6 illustrates a waveform applied to the lower portion (rear) of the substrate 201 with a predetermined timing difference from the upper portion (front). 5 and 6 , the reverse pulse waveform applied during the bridge plating process _{maintains the positive current I 1} for a time t ₁ , and then maintains the positive current I ₂ for a time t ₂ , followed by the positive current I ₁ . hold for time t ₃ , then hold positive current I ₂ for time t ₄ , then hold positive current I ₁ for time t ₅ , and then hold negative current I ₃ for time t6 , wherein the waveform is It is applied periodically for a predetermined period of time. In this case, I ₁ is preferably in the range of 1.5 to 2.5 ASD, and I ₂ is preferably in the range of 0.5 to 1.5 ASD. More preferably, I ₁ is in the range of 1.7 to 2.3 ASD, and I ₂ is preferably in the range of 0.7 to 1.3 ASD. Within the above range, I ₁ is preferably 1.5 to 2.5 times that of I ₂ , and more preferably 1.7 to 2.3 times that of I 2 . t ₁ , t _{2 ,} t ₃ , t ₄ and t ₅ are preferably 5 to 20 ms, more preferably 7 to 13 ms, respectively, and t ₁ , t _{2 ,} t ₃ , t ₄ and t ₅ may be the same time. I ₃ is preferably in the range of 3 to 5 ASD, more preferably 3.5 to 4.5 ASD. t ₆ is preferably 0.5 to 1.5 ms, more preferably 0.7 to 1.3 ms. The reverse pulse waveform has a period of 't ₁ +t ₂ +t ₃ +t ₄ +t ₅ +t ₆ ', specifically, the duty cycle = ton / (ton + toff) of the waveform. It can be in the range of 0.6-1.2. In the bridge plating process, the reverse pulse waveform may be continuously applied for 1 to 3 hours. The voltage can be selected in the range of 5 to 6 V. Bridge plating process, the circuit on the upper (front) and lower (back) of the substrate there with each other to apply a reverse pulse waveform of the different timings, of the substrate at the time of t ₁ is the start of the waveform corresponding to the upper (front) of the substrate The same waveform may be applied to the rear side with _{a difference in timing at which t 4 starts.} The reason for applying current waveforms at different timings to the upper (front) and lower (rear) of the substrate in the bridge plating process is to further improve the bridging and filling effect of the through hole. While the bridge is being formed, an advantageous filling effect can be obtained without voids as the inner through-hole is peeled off in reverse. Conversely, when the upper and lower current waveforms are the same, a large void may be formed in the inner center due to excessive growth of the inner through-hole during bridging and filling. In the conventional technology, pulse reversal plating was performed to form a plating layer inside the through-hole. When the through-hole thickness was 0.4 t or less, pulse reversal plating of the same waveform was performed on the upper and lower portions of the substrate, but the through-hole thickness was 0.4 t. As the above, internal voids were formed in the method through pulse/reverse plating of the same waveform. The reason is that if current is supplied to the upper and lower parts in the same waveform, plating and dissolution of the plating layer occur simultaneously, and voids may occur inside. The main cause of the formation of voids inside the through-hole is that metal ions are rapidly consumed in the limited space inside the through-hole, and an overvoltage is formed during plating, which increases the generation of hydrogen, and the increased generation of hydrogen interferes with the normal plating layer growth process in the plating film. As a result, voids are formed inside. Therefore, if a certain copper metal ion can be sufficiently supplied into the thick through-hole, hydrogen generation due to overvoltage can be suppressed, and a normal plating layer growth process can be helped. There is also a method of externally stirring as such a constant copper ion supply method, but it is difficult to stir and supply a sufficient amount to the micropores. Therefore, if the upper part is plated with copper ions in the forward direction by different current waveforms on the upper part and the lower part, the lower part is dissolved in the plating film in reverse to release copper ions. Copper ions emitted from the lower part are consumed for upper plating, and sufficient metal ions are supplied thereto, so that plating filling can be formed without voids in the through hole.

A preferred composition of the bridge plating solution includes 200 to 300 parts by weight of copper sulfate, 0.5 to 5 parts by weight of a brightener, 50 to 150 parts by weight of a carrier, and 1 to 10 parts by weight of a leveler based on 100 parts by weight of sulfuric acid, and 30 to 120 ppm of chlorine compared to the total plating solution It may contain ions. The reason why the leveler is included in the plating solution used in the bridge plating process of the through-hole filling method of the present invention as described above is that the bridge delay effect caused by the leveler can be suppressed due to the application of the waveform having the special configuration. Specifically, during the filling of the through-hole, the leveler suppresses the growth of the entrance of the through-hole, and can preferentially help the growth in the interior where the current distribution is not sufficiently supplied. That is, a certain amount of the leveler serves to help the plating growth on the inner wall of the through-hole where the current distribution is not sufficient, so that void-free filling plating can be performed.

Next, the through-hole filling part 204 is formed by performing through-hole filling plating. In the through-hole filling plating, since a plating solution having the same components and composition as the plating solution used in the bridge plating process is used, the bridge plating and the through-hole filling plating can be performed in a continuous process without replacing the plating bath. In through-hole filling plating, the same pulse and/or reverse pulse waveform may be applied to upper and lower portions (front and back surfaces) of the substrate at the same timing. 7 shows an example of the reverse pulse waveform applied to the through-hole filling plating. Referring to FIG. 7 , the reverse pulse waveform applied to the through-hole filling plating is a waveform in which the positive current I ₄ is maintained for a time t ₇ , and then the negative current I ₅ is maintained for a time t _{8 .} I ₄ is preferably in the range of 1.5 to 2.5 ASD, more preferably 1.7 to 2.3 ASD. t ₇ is preferably in the range of 30 to 60 ms, more preferably 40 to 50 ms. I ₅ is preferably in the range of 3 to 4 ASD, more preferably 3.2 to 3.8. t ₈ is preferably in the range of 1 to 3 ms, more preferably 1.7 to 2.3 ms.

Next, the overcoat plating is performed to form the overcoat in the upper and lower regions of the through hole. In the overcoat plating, the same pulse and/or reverse pulse waveform may be applied to upper and lower portions (front and back surfaces) of the substrate. 8 shows an example of the reverse pulse waveform applied to the overcoat plating. Referring to FIG. 8 , the waveform applied to the overcoat plating is a waveform in which a positive current I ₆ is maintained for a time t ₉ , and then a negative current I ₇ is maintained for a time t _{10 .} I ₆ is preferably in the range of 1.6 to 2.8 ASD, and t ₉ is preferably in the range of 70 to 130 ms. I ₇ is preferably in the range of 1.5 to 2.5 ASD, and t ₁₀ is preferably in the range of 1 to 3 ms.

The present invention will be described in more detail below using examples.

[Example 1]

A through hole with a diameter of 170 microns was processed with a laser in an epoxy resin substrate of 200 microns in thickness.

Plating was performed as a method for filling the through-holes, and the plating steps were as follows. First, electroless plating was performed, and then electrolytic plating was performed. At this time, the electrolytic plating step is divided into a bridge plating step, a through-hole filling plating step for filling copper inside the through-holes of the upper and lower sides of the bridge, and a covering film plating step to secure the plating thickness after finally filling the through-holes. was carried out. The same electrolytic plating solution was used for the bridge plating, the through-hole filling plating, and the overcoat plating.

Specifically, an electroless copper plating film was formed on the surface of the substrate and inside the through hole by using the electroless plating method. As the electroless plating solution, 30 parts by weight of copper sulfate, 85 parts by weight of ethylenediaminetetraacetic acid (EDTA) as a complexing agent, and 22 parts by weight of formalin as a reducing agent, together with OH required for the oxidation reaction of the ethylenediaminetetraacetic acid and formalin. A plating solution containing a trace amount of caustic soda was used. The acidity of the plating operation condition was pH 12, and the bath temperature was 65 °C.

Subsequently, copper electroplating, which is a bridge plating process, was performed after the degreasing process and the pickling process. As the electrolytic plating solution, 100 parts by weight of sulfuric acid, 200 parts by weight of copper sulfate, 0.5 parts by weight of a brightener, 70 parts by weight of a carrier, 2 parts by weight of a leveler, and a plating solution containing 50 ppm of chlorine ions compared to the total plating solution were used. The temperature of the plating solution was 27°C, and the plating time was 4.5 hours. In this case, (O-ethyldithiocarbonato)-S-(3-sulfopropyl)-ester was used as a brightener, polyoxyalkylene glycol was used as a carrier, and aziridine was used as a leveler. The current waveform of the bridge plating is in FIG. 5, I ₁ is 2 ASD, I ₂ is 1 ASD, I ₃ is 4 ASD, t ₁ , t ₂ , t ₃ , t ₄ , t ₅ was 10 ms, t ₆ was 1 ms. The voltage was selected in the range of 5-6 V. At this time, current waveforms were applied at different timings to the upper (front) and lower (rear) surfaces of the substrate, and there was a difference in timing as shown in FIG. 6 .

Then, through-hole filling plating was performed with an electrolytic plating solution. The through-hole filling plating conditions were a forward current density of 2 ASD (I _{4 in} FIG. 7 ), a reverse current density of 3.5 ASD (I _{5 in} FIG. 7 ), and the forward current application time was 50 ms (t _{7 in} FIG. 7 ), and the The time for applying the verse current was 2 ms (t _{8 in} FIG. 7 ). The voltage was selected in the range of 5 to 6 V, and the plating time was set to 1 hour. At this time, the same waveform was applied to the upper (front) and lower (rear) surfaces of the substrate at the same timing.

Then, the overcoat plating was performed with an electrolytic plating solution. The overcoat plating conditions were a forward current density of 2.2 ASD (I _{6 in} FIG. 8 ), a time of 100 ms ( t _{9 in} FIG. 8 ), a reverse current density of 2 ASD (I _{7 in} FIG. 8 ), and a time of 2 ms ( _{t 10 in} FIG. 8 ). The voltage was selected in the range of 5 to 6 V, and the plating time was set to 1 hour. At this time, the same waveform was applied to the upper (front) and lower (rear) surfaces of the substrate at the same timing.

[Example 2]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 8 ms.}

[Example 3]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 12 ms.}

[Example 4]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 6 ms.}

[Example 5]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 18 ms.}

[Example 6]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 0.8 ms.}

[Example 7]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 1.2 ms.}

[Example 8]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 0.6 ms.}

[Example 9]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 1.4 ms.}

[Example 10]

In the through-hole filling plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 8 was set to 1.8 ms.}

[Example 11]

In the through-hole filling plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 8 was set to 2.2 ms.}

[Comparative Example 1]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 3 ms.}

[Comparative Example 2]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 1} , t ₂ , t ₃ , t ₄ , and t _{5 were set to 23 ms.}

[Comparative Example 3]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 0.4 ms.}

[Comparative Example 4]

In the bridge plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 6 was set to 1.7 ms.}

[Comparative Example 5]

In the through-hole filling plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 8 was set to 0.8 ms.}

[Comparative Example 6]

In the through-hole filling plating step, through-hole filling plating was performed in the same manner as in Example 1, except that _{t 8 was set to 3.5 ms.}

[Comparative Example 7]

The through-hole filling plating was performed in the same manner as in Example 1, except that an electrolytic plating solution without a leveler was used.

[Evaluation Example 1]

The cross-section of the circuit board on which the through-hole filling plating was performed according to Examples 1 to 11 and Comparative Examples 1 to 7 was cut and the inside of the through-hole was observed with an optical microscope. In Examples 1, 2, 3, 4, 6, 7, 10, and 11, voids were not observed in the through-holes, and in Examples 4, 5, 8, and 9, voids with a diameter of 10 microns or less were observed in the through-holes. In Comparative Examples 1 to 6, voids with a diameter of 20 microns or more were observed, and in Comparative Example 7, through-hole filling was not performed. The results are summarized in Table 1 below. From these results, it can be seen that the control of the waveform during the plating process is very important, and from this, the adsorption and desorption of metal ions are induced according to the current waveform, and the leveler in the plating solution is adsorbed to the outside of the through hole to control the plating. It can be seen that it plays a role that can preferentially do internal plating. In addition, it can be seen that the existence and type of the leveler also plays an important role in filling the through hole.

9 (a) is a cross-sectional photograph of a through-hole on which the through-hole filling plating was performed according to Example 1, and it can be seen that plating was performed well without voids formed inside the through-hole. On the other hand, FIG. 9(b) is a cross-sectional photograph of a through-hole on which the through-hole filling plating was performed according to Comparative Example 7, and it can be seen that the through-hole filling was incompletely performed.

division	Whether voids are formed	void diameter	void location
Example 1	none	-	-
Example 2	none	-	-
Example 3	none	-	-
Example 4	has exist	less than 10 microns	center
Example 5	has exist	less than 10 microns	center
Example 6	none	-	-
Example 7	none	-	-
Example 8	has exist	less than 10 microns	center
Example 9	has exist	less than 10 microns	center
Example 10	none	-	-
Example 11	none	-	-
Comparative Example 1	has exist	20 microns or more	from the surface to the center
Comparative Example 2	has exist	20 microns or more	from the surface to the center
Comparative Example 3	has exist	20 microns or more	from the surface to the center
Comparative Example 4	has exist	20 microns or more	from the surface to the center
Comparative Example 5	has exist	over 20 microns in length	from the surface to the center
Comparative Example 6	has exist	over 20 microns in length	from the surface to the center
Comparative Example 7	unfilled	unfilled	unfilled

Claims (11)

1. forming a through hole in the substrate;

   forming an electroless plating layer to a predetermined thickness on the inner surface of the through hole by electroless plating;

   performing bridge plating on the electroless plating layer to form a bridge in a partial region inside the through hole by electroplating; and

   Comprising the step of performing a through-hole filling plating by electrolytic plating on the through-hole on which the bridge plating is made,

   The through-hole filling method of the circuit board, wherein the bridge plating and the through-hole filling plating are performed using the same plating solution.
2. The method according to claim 1,

   A through-hole filling method of a circuit board in which a reverse pulse waveform is applied to the bridge plating.
3. 3. The method according to claim 2,

   The through-hole filling method of the circuit board, wherein the reverse pulse waveform is applied under different conditions from the upper part and the lower part of the circuit board.
4. 3. The method according to claim 2,

   The reverse pulse waveform has a period of t ₁ +t ₂ +t ₃ +t ₄ +t ₅ +t ₆ ,

   In the period, t ₁ , t ₂ , t ₃ , t ₄ and t ₅ are each a time for which a positive current is applied, and t ₆ is a time for which a negative current is applied.
5. 5. The method according to claim 4,

   The time for which the positive current is applied is 5 to 20 ms,

   The time for which the negative current is applied is 0.5 to 1.5 ms.
6. 5. The method according to claim 4,

   The _{current I 1} applied at each of _{t 1} , t ₃ and t ₅ is 1.5 to 2.5 ASD,

   The _{current I 2} applied at each of _{t 2} and t ₄ is 0.5 to 1.5 ASD,

   The current I _{3 applied at t 6} is 3 to 5 ASD of the through-hole filling method of the circuit board.
7. The method according to claim 1,

   A through-hole filling method of a circuit board in which a reverse pulse waveform is applied to the through-hole filling plating.
8. The method according to claim 1,

   The bridge plating and the through-hole filling plating are performed in the same plating bath.
9. The method according to claim 1,

   The plating solution includes a leveler,

   The leveler is a through-hole filling method of a circuit board that is a saturated heterocyclic compound containing at least one element selected from the group consisting of nitrogen, oxygen, sulfur and phosphorus.
10. The method according to claim 1,

    The method of filling the through-holes of the circuit board further comprising the step of performing a cover film plating by electroplating on the through-holes on which the through-hole filling plating has been made.
11. A circuit board manufactured by the through-hole filling method of the circuit board of claim 1.

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