US20050121314A1 - Electrolytic plating method and device for a wiring board - Google Patents

Electrolytic plating method and device for a wiring board Download PDF

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Publication number
US20050121314A1
US20050121314A1 US10/896,488 US89648804A US2005121314A1 US 20050121314 A1 US20050121314 A1 US 20050121314A1 US 89648804 A US89648804 A US 89648804A US 2005121314 A1 US2005121314 A1 US 2005121314A1
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United States
Prior art keywords
plating
copper
wiring board
plating solution
solution
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Abandoned
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US10/896,488
Inventor
Toshiki Inoue
Kyoko Kumagai
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Toyota Industries Corp
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Toyoda Jidoshokki Seisakusho KK
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Priority to US10/896,488 priority Critical patent/US20050121314A1/en
Publication of US20050121314A1 publication Critical patent/US20050121314A1/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/12Process control or regulation
    • C25D21/14Controlled addition of electrolyte components
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18Electroplating using modulated, pulsed or reversing current
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60Electroplating characterised by the structure or texture of the layers
    • C25D5/605Surface topography of the layers, e.g. rough, dendritic or nodular layers
    • C25D5/611Smooth layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1492Periodical treatments, e.g. pulse plating of through-holes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S204/00Chemistry: electrical and wave energy
    • Y10S204/09Wave forms

Definitions

  • the present invention relates to an electrolytic plating method and device filling up a microvia hole formed on a wiring board with metal plating.
  • a buildup board on which a wiring layer and an insulation layer are sequentially formed a printed-circuit board of an all-layer microvia type to which wiring boards on which microvias are formed are attached with heat and pressure, etc. are proposed.
  • micro holes are formed on an insulation layer, and the inner side and the bottom of the holes are metal-plated, so that wiring layers above and below the insulation layer are electrically connected.
  • Japanese Laid-open Patent Publication No. 8469 discloses the technique filling up microvia holes by performing electric metal plating with PR electrolysis after an electroless metal film is formed.
  • plating must be performed for a long time (for example, two hours or longer) to fill up microvia holes. Therefore, the manufacturing cost of a printed-circuit board increases, and it is difficult to use a printed-circuit board on a mass-production level. Additionally, attempts are made to improve the density of an electric current in order to shorten a plating time. However, problems such that a void occurs during plating, or a plated surface becomes rough occur.
  • Japanese Laid-open Patent Publication No. 507106 discloses a metal plating method using an insoluble anode and a plating solution to which an oxidization-reduction compound is added.
  • the above described invention assumes electrolytic plating using a direct current power source, and does not present a plating method for filling up microvia holes on a printed-circuit board for a short time.
  • An object of the present invention aims at filling up microvia holes on a printed-circuit board for a short time.
  • a printed-circuit board is used as one pole and an insoluble electrode is used as the other, and electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, so that microvia holes formed on a printed-circuit board are filled up with metal plating.
  • electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, whereby microvia holes can be filled up for a time shorter than a conventional method, and a metal film having a smooth surface characteristic can be formed.
  • microvias which electrically connect wiring layers above and below an insulation layer can be formed for a short time, thereby significantly reducing the manufacturing cost of a multi-layer printed-circuit board.
  • an electrolytic plating method for example, a pulse reverse electrolytic method applying a forward/reverse pulsed current is available.
  • a plating solution may be stirred to flow in parallel with the surface to be plated of a printed-circuit board. At this time, the flow quantity of the plating solution may be controlled depending on the diameter or the depth of a microvia hole.
  • the deposit speed of metal plating on the surface of a printed-circuit board and that of metal plating within a microvia hole can be suitably controlled. Consequently, a deep microvia hole with a short diameter can be filled up without causing a void, etc. within the hole.
  • FIG. 1 explains the manufacturing process of a multi-layer printed-circuit board
  • FIG. 2 explains an electrolytic plating method according to a preferred embodiment
  • FIG. 3 shows the flow of a plating solution
  • FIG. 4 shows the waveform of a plating current
  • FIG. 5 shows the plating conditions of Samples
  • FIG. 6 shows the results of measuring the degree of roughness of surfaces in Samples
  • FIGS. 7A and 7B show the cross-sectional view of a microvia according to the preferred embodiment.
  • FIG. 8 shows the cross-sectional view of a microvia when being plated with a plating solution that does not include iron ions.
  • a wiring pattern (wiring layer) 11 ′ is formed by etching a copper foil (conductor layer) stacked onto a core resin 12 such as glass epoxy, etc. (process steps ( 1 ) and ( 2 ) in FIG. 1 ).
  • an insulation layer 13 is formed on the wiring pattern (process step ( 3 ) in FIG. 1 ). Holes are drilled in the insulation layer 13 with laser, etc., so that microvia holes 14 are formed (process step ( 4 ) in FIG. 1 ).
  • a copper plated layer 15 is formed with electrolytic plating, etc. to fill up the microvia holes (process step ( 5 ) in FIG. 1 ). In the plating process step ( 5 ) in FIG.
  • the microvia holes 14 are filled up with pulse reverse electrolytic plating to form the copper plated layer 15 .
  • a wiring pattern 15 ′ is formed by etching the copper plated layer 15 (process step ( 6 ) in FIG. 1 ). As a result, the wiring patterns 11 ′ and 15 ′ above and below the insulation layer 13 can be electrically connected.
  • a plating bath 21 is composed of insoluble anodes 22 , a cathode 23 being a printed-circuit board, a power source 24 for applying a forward/reverse current between the electrodes, and a copper plating solution including iron ions.
  • a multi-aperture electrode such as an expanded metal, etc. is used as each of the insoluble anodes 22 .
  • copper dissolved baths 25 are arranged to supply copper ions to the plating bath 21 , and a solution within the copper dissolved baths 25 and the plating solution within the plating bath 21 are circulated by a circulation pump 26 .
  • an iron ion “Fe 2+ ” is added to the plating solution, so that “Fe 3+ +e” is generated from “Fe 2+ ” in the proximity of the insoluble anodes 22 as shown in FIG. 2 .
  • Cu is deposited from “Cu 2+ ” which is carried from the copper dissolved baths 25 , so that a copper plated layer is formed on the printed-circuit board.
  • Fe 2+ is produced from “Fe 3+ +e” which is generated by the insoluble anodes 22 .
  • FIG. 3 schematically shows the flow of the plating solution within the plating bath 21 according to this preferred embodiment.
  • the cathode (printed-circuit board) 23 is arranged in the middle of the plating bath 21 , and the two insoluble anodes 22 in a meshed state are arranged as opposed to the printed-circuit board 23 .
  • the plating solution is circulated by the circulation pump 26 in the right direction of FIG. 3 . That is, the plating solution is circulated to flow in parallel to the surface to be plated by a predetermined flow quantity.
  • pulse reverse electrolytic plating is performed by applying a forward/reverse pulsed current to the electrodes.
  • the plating current applied to both of the electrodes is a forward/reverse pulsed current having a forward current duration T 1 that is 40 ms, and a reverse current duration T 2 that is 2 ms, as shown in FIG. 4 .
  • the average current density of the cathode is set to 3A/dm 2 .
  • FIG. 5 shows the plating conditions of Samples 1 through 3 of a printed-circuit board for which pulse reverse electrolytic plating is performed, namely, the amount of iron ions included in the plating solution, the average current density, a plating time, and the thickness of a plated layer.
  • Sample 1 indicates the plating performed for 33.3 minutes with the average current density 3 ⁇ /dm 2 in a plating solution that does not include iron ions.
  • Sample 2 indicates the plating performed for 33.3 minutes with the average current density 3 ⁇ /dm 2 in a plating solution that includes iron ions by 15 g/L.
  • Sample 3 indicates the plating performed for 33.3 minutes with the average current density 3 ⁇ /dm 2 in a plating solution that includes iron ions by 0.1 g/L.
  • FIG. 6 shows the results of the measurement of the degrees of roughness of the plated surfaces of Samples 1 through 3 by using a roughness meter of a touch needle type.
  • the average value of the degree of roughness of the plated surface of Sample 1 for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that does not include iron ions, is 3.496 ⁇ m
  • the average value of the degree of roughness of the plated surface of Sample 3 for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that includes iron ions by 0.1 g/L, is 2.830 ⁇ m. Namely, it can be verified that a smoother plated surface can be obtained by Sample 3 for which the plating is performed with the plating solution including iron ions.
  • the average value of the degree of roughness of the plated surface of Sample 2 for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that includes iron ions by 15 g/L is 1.821 ⁇ m, and a further smoother plated surface than that with the plating solution which includes iron ions by 0.1 g/L can be obtained.
  • FIG. 7A shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed with the plating solution which includes iron ions by 15 g/L under the above described conditions.
  • FIG. 7B shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed by using the plating solution which includes iron ions by 0.1 g/L.
  • FIG. 8 shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed with the plating solution which does not include iron ions.
  • a microvia hole tapers, the diameter of the aperture of the hole is 40 ⁇ m, the diameter of the bottom of the hole is 25 ⁇ m, and the depth is 50 ⁇ m.
  • the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution which includes iron ions by 15 g/L, the microvia hole is completely filled up, and the copper plated surface is smooth as shown in FIG. 7A . Since a cavity in the middle of the microvia is smaller in comparison with its depth (50 ⁇ m), it does not matter practically.
  • the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution which includes iron ions by 0.1 g/L, the microvia hole is completely filled up a shown in FIG. 7B .
  • the copper plated surface is slightly rougher than that in FIG. 7A , it is a level which does not matter practically.
  • FIG. 8 shows the cross-sectional view of a microvia hole when the pulse reverse electrolytic plating is performed with the plating solution which does not include iron ions under the above described conditions for comparison.
  • the microvia is filled up, but the copper plated surface becomes rougher in comparison with the case where the plating is performed with the plating solution which includes iron ions by 0.1 g/L in FIG. 7B . If a plated surface is rough, a pattern on the lower surface of a resist is scraped when the resist is formed to etch the pattern, leading to an unevenness of the width of the pattern. Therefore, it can be verified that a wiring pattern of higher quality can be obtained with the plating solution which includes iron ions in FIG. 7A or 7 B.
  • microvias can be filled up for a time (approximately 33.3 minutes) shorter than a conventional method by adding iron ions to a plating solution by 0.1 g/L or more, and by performing pulse reverse electrolytic plating, and at the same time, a plated surface can be formed to be smooth. Furthermore, judging from the result in the case where the plating is performed with the plating solution which does not include iron ions under the same conditions, it can be verified that an effect of smoothing a plated surface by adding iron ions is high.
  • iron ions are added to a copper dissolved solution and pulse reverse electrolytic plating is performed, whereby microvia holes can be filed up for a short time, and its surface can be almost smoothed.
  • a plating solution is made to flow in parallel to the surface to be plated (the surface on which microvia holes are formed) of a printed-circuit board being a cathode, thereby further improving the plating characteristic. Furthermore, by controlling the flow quantity of a plating solution to be a suitable value, the deposit speed of the surface of the cathode 23 and that of copper within a microvia hole my be set to a desired value.
  • “Fe 2+ ”, is added to a copper plating solution.
  • the present invention is not limited to “Fe 2+ ”, and other oxidization-reduction compounds may be added.
  • the present invention may also be applied to metal plating other than copper.
  • the application time of a forward/reverse plating current, the current density of an electrode, the composition of a plating solution, a plating time, etc. are not limited to those implemented in the above described preferred embodiment. For example, any composition can be used if it is available to electrolytic plating of copper, and other metals.
  • the direction in which a plating solution is made to flow upward or downward not limited to the right and the left.
  • the essentiality is to make a plating solution flow in parallel to the surface desired to be plated of a printed-circuit board.
  • the present invention may be applied to a multi-layer substrate on which a semiconductor device is mounted, etc., not limited to a multi-layer printed circuit board.
  • microvia holes are filled up for a short time, and a metal film having a smooth surface characteristic can be formed. Namely, microvias which electrically connect wiring layers above and below an insulation layer can be formed for a short time, thereby significantly reducing the manufacturing cost of a multi-layer wiring board.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Automation & Control Theory (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A plating bath which accommodates an insoluble node and a printed-circuit board, and a copper dissolved bath which supplies copper ions are arranged. The insoluble anode Is arranged as opposed to the printed-circuit board being a cathode, and a forward/reverse current is applied between both of the electrodes. Iron ions are added to a plating solution.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an electrolytic plating method and device filling up a microvia hole formed on a wiring board with metal plating.
  • 2. Description of the Related Art
  • For electric appliances such as a cellular phone, a video camera, a notebook computer, etc., it is demanded to mount high-density components. As an implementation of high-density mounting, a buildup board on which a wiring layer and an insulation layer are sequentially formed, a printed-circuit board of an all-layer microvia type to which wiring boards on which microvias are formed are attached with heat and pressure, etc. are proposed.
  • For a conventional buildup board, micro holes (microvia holes) are formed on an insulation layer, and the inner side and the bottom of the holes are metal-plated, so that wiring layers above and below the insulation layer are electrically connected.
  • With this method, however, it is difficult to further form one microvia hole on another, and to securely connect the holes in an electric manner. Therefore, a land cannot be arranged on a microvia hole after microvia holes are stacked. Due to such a restriction on a pattern design, the whole of a pattern design cannot be made with an automatic wiring tool, and part of the design must be made manually. As a result, the time period required to design a printed-circuit board becomes long.
  • To overcome such a problem, a technique filling up microvia holes with electrolytic plating is proposed. For example, Japanese Laid-open Patent Publication No. 8469 discloses the technique filling up microvia holes by performing electric metal plating with PR electrolysis after an electroless metal film is formed.
  • However, with the plating method using PR electrolysis disclosed by the above described publication, plating must be performed for a long time (for example, two hours or longer) to fill up microvia holes. Therefore, the manufacturing cost of a printed-circuit board increases, and it is difficult to use a printed-circuit board on a mass-production level. Additionally, attempts are made to improve the density of an electric current in order to shorten a plating time. However, problems such that a void occurs during plating, or a plated surface becomes rough occur.
  • Furthermore, to solve the problems occurring when a soluble anode is used, for example, Japanese Laid-open Patent Publication No. 507106 discloses a metal plating method using an insoluble anode and a plating solution to which an oxidization-reduction compound is added.
  • The above described invention assumes electrolytic plating using a direct current power source, and does not present a plating method for filling up microvia holes on a printed-circuit board for a short time.
  • SUMMARY OF THE INVENTION
  • An object of the present invention aims at filling up microvia holes on a printed-circuit board for a short time.
  • According to the present invention, a printed-circuit board is used as one pole and an insoluble electrode is used as the other, and electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, so that microvia holes formed on a printed-circuit board are filled up with metal plating.
  • According to the present invention, electrolytic plating is performed by applying a forward/reverse current with the use of a metal plating solution including iron ions by 0.1 gram/liter or more, whereby microvia holes can be filled up for a time shorter than a conventional method, and a metal film having a smooth surface characteristic can be formed. As a result, microvias which electrically connect wiring layers above and below an insulation layer can be formed for a short time, thereby significantly reducing the manufacturing cost of a multi-layer printed-circuit board.
  • As an electrolytic plating method, for example, a pulse reverse electrolytic method applying a forward/reverse pulsed current is available.
  • Additionally, a plating solution may be stirred to flow in parallel with the surface to be plated of a printed-circuit board. At this time, the flow quantity of the plating solution may be controlled depending on the diameter or the depth of a microvia hole.
  • With the above described configuration, the deposit speed of metal plating on the surface of a printed-circuit board and that of metal plating within a microvia hole can be suitably controlled. Consequently, a deep microvia hole with a short diameter can be filled up without causing a void, etc. within the hole.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 explains the manufacturing process of a multi-layer printed-circuit board;
  • FIG. 2 explains an electrolytic plating method according to a preferred embodiment;
  • FIG. 3 shows the flow of a plating solution;
  • FIG. 4 shows the waveform of a plating current;
  • FIG. 5 shows the plating conditions of Samples;
  • FIG. 6 shows the results of measuring the degree of roughness of surfaces in Samples;
  • FIGS. 7A and 7B show the cross-sectional view of a microvia according to the preferred embodiment; and
  • FIG. 8 shows the cross-sectional view of a microvia when being plated with a plating solution that does not include iron ions.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Hereinafter, a preferred embodiment according to the present invention will be described by referencing drawings. First of all, the manufacturing process of a multi-layer printed-circuit board is explained by referencing FIG. 1.
  • A wiring pattern (wiring layer) 11′ is formed by etching a copper foil (conductor layer) stacked onto a core resin 12 such as glass epoxy, etc. (process steps (1) and (2) in FIG. 1). Next, an insulation layer 13 is formed on the wiring pattern (process step (3) in FIG. 1). Holes are drilled in the insulation layer 13 with laser, etc., so that microvia holes 14 are formed (process step (4) in FIG. 1). Next, a copper plated layer 15 is formed with electrolytic plating, etc. to fill up the microvia holes (process step (5) in FIG. 1). In the plating process step (5) in FIG. 1, after a thin conductor layer is formed with chemical plating, etc. on the wiring pattern 11′ at the bottom of the insulation layer 13 and the microvia holes 14, the microvia holes 14 are filled up with pulse reverse electrolytic plating to form the copper plated layer 15. Then, a wiring pattern 15′ is formed by etching the copper plated layer 15 (process step (6) in FIG. 1). As a result, the wiring patterns 11′ and 15′ above and below the insulation layer 13 can be electrically connected.
  • The technique filling up microvia holes with pulse reverse electrolytic plating is recited, for example, in “Gist of the 100th Lecture (held on Oct. 6 and 7, 1999) by Surface Finishing Society of Japan.
  • Next, an electrolytic plating method for a printed-circuit board according to this preferred embodiment will be explained by referencing FIG. 2.
  • A plating bath 21 is composed of insoluble anodes 22, a cathode 23 being a printed-circuit board, a power source 24 for applying a forward/reverse current between the electrodes, and a copper plating solution including iron ions. To widen the surface areas of the electrodes, a multi-aperture electrode such as an expanded metal, etc. is used as each of the insoluble anodes 22.
  • Besides, copper dissolved baths 25 are arranged to supply copper ions to the plating bath 21, and a solution within the copper dissolved baths 25 and the plating solution within the plating bath 21 are circulated by a circulation pump 26.
  • According to this preferred embodiment, an iron ion “Fe2+” is added to the plating solution, so that “Fe3++e” is generated from “Fe2+” in the proximity of the insoluble anodes 22 as shown in FIG. 2.
  • In the copper dissolved baths 25, “Cu2+” and “Fe2+” are generated by the dissolution reaction between the copper material within the copper dissolved baths 25 and “Fe3+” which is generated by each of the insoluble anodes 22 and carried to the copper dissolved baths 25.
  • At the cathode 23, Cu is deposited from “Cu2+” which is carried from the copper dissolved baths 25, so that a copper plated layer is formed on the printed-circuit board. At the same time, “Fe2+” is produced from “Fe3++e” which is generated by the insoluble anodes 22.
  • Namely, “Fe3+” is generated from the iron ion “Fe2+” included in the plating solution as a result of the electrolytic reaction of the insoluble anodes 22, and “Cu2+” and “Fe2+” are generated by “Fe3+” and the copper material within the copper dissolved baths 25. Therefore, the copper ion “Cu2+” and the iron ion “Fe2+”, which is added to the plating solution and consumed by the reaction of the insoluble anodes 22 continue to be supplied from the copper dissolved baths 25.
  • FIG. 3 schematically shows the flow of the plating solution within the plating bath 21 according to this preferred embodiment.
  • The cathode (printed-circuit board) 23 is arranged in the middle of the plating bath 21, and the two insoluble anodes 22 in a meshed state are arranged as opposed to the printed-circuit board 23. The plating solution is circulated by the circulation pump 26 in the right direction of FIG. 3. That is, the plating solution is circulated to flow in parallel to the surface to be plated by a predetermined flow quantity. By making the plating solution flow in parallel to the surface to be plated of the printed-circuit board 23, microvia holes are completely filled up, and a plated layer having a suitable film thickness can be formed. This can be considered to be implemented, because the deposit speed of copper on the surface of the printed-circuit board 23 and that of copper within the microvia holes can be adjusted by making the plating solution flow, for example, in parallel to the surface of the printed-circuit board 23 to control the amount of “Fe3+” existing on the surface of the printed-circuit board 23.
  • Described next are plating conditions and evaluation results of plating when a microvia hole having a depth of 50 μm, which is formed on an insulation layer, is filled up with the plating method according to this preferred embodiment.
  • The fundamental composition of the plating solution used in this preferred embodiment is as follows:
      • copper sulfate·5 hydrates: 235.7 g/liter (L)
      • sulfuric acid: 60 g/L
      • organic additive (surface active agent such as Impulse Leveler provided by Atotec Co., Ltd.)
      • organic additive (brightener such as Impulse Brightener provided by Atotec Co., Ltd.)
      • chloric ion: 40 mg/L
      • iron ion: 15 g/L (or 0.1 g/L)
  • In this preferred embodiment, pulse reverse electrolytic plating is performed by applying a forward/reverse pulsed current to the electrodes. The plating current applied to both of the electrodes is a forward/reverse pulsed current having a forward current duration T1 that is 40 ms, and a reverse current duration T2 that is 2 ms, as shown in FIG. 4. Furthermore, the average current density of the cathode is set to 3A/dm2.
  • FIG. 5 shows the plating conditions of Samples 1 through 3 of a printed-circuit board for which pulse reverse electrolytic plating is performed, namely, the amount of iron ions included in the plating solution, the average current density, a plating time, and the thickness of a plated layer.
  • Sample 1 indicates the plating performed for 33.3 minutes with the average current density 3 Å/dm2 in a plating solution that does not include iron ions.
  • Sample 2 indicates the plating performed for 33.3 minutes with the average current density 3 Å/dm2 in a plating solution that includes iron ions by 15 g/L.
  • Sample 3 indicates the plating performed for 33.3 minutes with the average current density 3 Å/dm2 in a plating solution that includes iron ions by 0.1 g/L.
  • FIG. 6 shows the results of the measurement of the degrees of roughness of the plated surfaces of Samples 1 through 3 by using a roughness meter of a touch needle type.
  • In this figure, the average value of the degree of roughness of the plated surface of Sample 1, for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that does not include iron ions, is 3.496 μm, whereas the average value of the degree of roughness of the plated surface of Sample 3, for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that includes iron ions by 0.1 g/L, is 2.830 μm. Namely, it can be verified that a smoother plated surface can be obtained by Sample 3 for which the plating is performed with the plating solution including iron ions.
  • Additionally, the average value of the degree of roughness of the plated surface of Sample 2, for which the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution that includes iron ions by 15 g/L is 1.821 μm, and a further smoother plated surface than that with the plating solution which includes iron ions by 0.1 g/L can be obtained.
  • FIG. 7A shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed with the plating solution which includes iron ions by 15 g/L under the above described conditions. In the meantime, FIG. 7B shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed by using the plating solution which includes iron ions by 0.1 g/L.
  • Furthermore, FIG. 8 shows the cross-sectional view of a microvia when the pulse reverse electrolytic plating is performed with the plating solution which does not include iron ions.
  • Note that a microvia hole tapers, the diameter of the aperture of the hole is 40 μm, the diameter of the bottom of the hole is 25 μm, and the depth is 50 μm.
  • If the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution which includes iron ions by 15 g/L, the microvia hole is completely filled up, and the copper plated surface is smooth as shown in FIG. 7A. Since a cavity in the middle of the microvia is smaller in comparison with its depth (50 μm), it does not matter practically.
  • If the pulse reverse electrolytic plating is performed for 33.3 minutes with the plating solution which includes iron ions by 0.1 g/L, the microvia hole is completely filled up a shown in FIG. 7B. Although the copper plated surface is slightly rougher than that in FIG. 7A, it is a level which does not matter practically.
  • FIG. 8 shows the cross-sectional view of a microvia hole when the pulse reverse electrolytic plating is performed with the plating solution which does not include iron ions under the above described conditions for comparison. In this case, the microvia is filled up, but the copper plated surface becomes rougher in comparison with the case where the plating is performed with the plating solution which includes iron ions by 0.1 g/L in FIG. 7B. If a plated surface is rough, a pattern on the lower surface of a resist is scraped when the resist is formed to etch the pattern, leading to an unevenness of the width of the pattern. Therefore, it can be verified that a wiring pattern of higher quality can be obtained with the plating solution which includes iron ions in FIG. 7A or 7B.
  • It can be verified from the results of the comparisons between the degrees of roughness of the plated surface and the cross-sectional views of the microvias in FIGS. 7A, 7B, and 8 that microvias can be filled up for a time (approximately 33.3 minutes) shorter than a conventional method by adding iron ions to a plating solution by 0.1 g/L or more, and by performing pulse reverse electrolytic plating, and at the same time, a plated surface can be formed to be smooth. Furthermore, judging from the result in the case where the plating is performed with the plating solution which does not include iron ions under the same conditions, it can be verified that an effect of smoothing a plated surface by adding iron ions is high.
  • According to the above described preferred embodiment, iron ions are added to a copper dissolved solution and pulse reverse electrolytic plating is performed, whereby microvia holes can be filed up for a short time, and its surface can be almost smoothed.
  • Additionally, a plating solution is made to flow in parallel to the surface to be plated (the surface on which microvia holes are formed) of a printed-circuit board being a cathode, thereby further improving the plating characteristic. Furthermore, by controlling the flow quantity of a plating solution to be a suitable value, the deposit speed of the surface of the cathode 23 and that of copper within a microvia hole my be set to a desired value.
  • In the above described preferred embodiment, “Fe2+”, is added to a copper plating solution. However, the present invention is not limited to “Fe2+”, and other oxidization-reduction compounds may be added. The present invention may also be applied to metal plating other than copper. Furthermore, the application time of a forward/reverse plating current, the current density of an electrode, the composition of a plating solution, a plating time, etc. are not limited to those implemented in the above described preferred embodiment. For example, any composition can be used if it is available to electrolytic plating of copper, and other metals.
  • Still further, the direction in which a plating solution is made to flow upward or downward, not limited to the right and the left. The essentiality is to make a plating solution flow in parallel to the surface desired to be plated of a printed-circuit board. The present invention may be applied to a multi-layer substrate on which a semiconductor device is mounted, etc., not limited to a multi-layer printed circuit board.
  • According to the present invention, microvia holes are filled up for a short time, and a metal film having a smooth surface characteristic can be formed. Namely, microvias which electrically connect wiring layers above and below an insulation layer can be formed for a short time, thereby significantly reducing the manufacturing cost of a multi-layer wiring board.

Claims (6)

1-6. (canceled)
7. An electrolytic plating device, comprising;
a wiring board with microvia holes, each having a bottom made of copper foil provided on a surface of the wiring board as an electrode;
an insoluble electrode, which is an electrode opposed to the wiring board;
a metal plating solution containing iron ions of at least 0.1 gram/liter;
a power source for performing electrolytic plating by applying a forward/reverse current between the wiring board and said insoluble electrode; and
a stirring unit stirring said metal plating solution to make the solution flow in parallel to the surface to be plated of said wiring board so that the microvia holes having the copper foil at the bottom, which are formed on the surface of said wiring board, may be filled up with said metal plating.
8. The electrolytic plating device according to claim 7, wherein:
the metal plating solution is comprised of copper plating solution; and
the stirring unit adjusts a flow rate of the copper plating solution to a level at which copper deposition speeds both on the surface and inside microvia holes of the wiring board are optimum.
9. The electrolytic plating device according to claim 8, wherein
the string unit adjusts the flow rate of the copper plating solution to bring the iron ion amount present near to wiring board surface to a level at which all the microvia holes are almost fully filled and the plating layer thickness on the wiring board surface becomes optimum.
10. The electrolytic plating device according to claim 9, further comprising:
a plating bath accommodating the insoluble electrode and the wiring board; and
a copper dissolved bath supplying copper ions to said plating bath, wherein
said stirring unit circulates a solution within the copper dissolved bath and the plating solution within the plating bath.
11. The electrolytic plating device according to claim 7, wherein:
said insoluble electrode is implemented by a multi-aperture electrode; and
said plating solution is implemented by a copper plating solution.
US10/896,488 2000-03-22 2004-07-22 Electrolytic plating method and device for a wiring board Abandoned US20050121314A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090236230A1 (en) * 2004-09-20 2009-09-24 Bert Reents Galvanic process for filling through-holes with metals, in particular of printed circuit boards with copper
WO2011151328A1 (en) * 2010-06-02 2011-12-08 Atotech Deutschland Gmbh Method for etching of copper and copper alloys
CN103388172A (en) * 2013-07-22 2013-11-13 苏州昕皓新材料科技有限公司 Rapid determining method for performances of an electroplating additive

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6458696B1 (en) * 2001-04-11 2002-10-01 Agere Systems Guardian Corp Plated through hole interconnections
DE10259362A1 (en) * 2002-12-18 2004-07-08 Siemens Ag Process for depositing an alloy on a substrate
DE10325101A1 (en) * 2003-06-03 2004-12-30 Atotech Deutschland Gmbh Method for filling µ-blind vias (µ-BVs)
US7296398B2 (en) * 2004-10-29 2007-11-20 General Electric Company Counter-rotating turbine engine and method of assembling same
FI20041525A (en) * 2004-11-26 2006-03-17 Imbera Electronics Oy Electronics module and manufacturing process
SE0403047D0 (en) * 2004-12-14 2004-12-14 Polymer Kompositer I Goeteborg Pulse-plating method and apparatus
US7494920B2 (en) * 2005-10-14 2009-02-24 Honeywell International Inc. Method of fabricating a vertically mountable IC package
JP2007169700A (en) * 2005-12-21 2007-07-05 Victor Co Of Japan Ltd Copper electroplating method using insoluble anode
KR100728754B1 (en) * 2006-04-11 2007-06-19 삼성전기주식회사 Printed circuit board using bump and method for manufacturing thereof
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EP2416635A1 (en) * 2007-02-20 2012-02-08 Dynamic Details, Inc. Multilayer printed wiring boards with copper filled through-holes
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US20100132371A1 (en) * 2008-11-28 2010-06-03 Pratt & Whitney Canada Corp. Mid turbine frame system for gas turbine engine
US20100206737A1 (en) * 2009-02-17 2010-08-19 Preisser Robert F Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4292144A (en) * 1979-06-29 1981-09-29 Office National D'etudes Et De Recherches Aerospatiales Process and device for coating small-sized elements with a metal deposit
US5683564A (en) * 1996-10-15 1997-11-04 Reynolds Tech Fabricators Inc. Plating cell and plating method with fluid wiper
US5976341A (en) * 1993-12-24 1999-11-02 Schumacher; Rolf Process and apparatus for electrolytic deposition of metal layers
US6099711A (en) * 1995-11-21 2000-08-08 Atotech Deutschland Gmbh Process for the electrolytic deposition of metal layers
US6129830A (en) * 1996-12-13 2000-10-10 Atotech Deutschland Gmbh Process for the electrolytic deposition of copper layers
US6537439B2 (en) * 1998-07-27 2003-03-25 Noram Engineering & Constructors Ltd. Method and apparatus for recovering a reaction product produced at a surface

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118469A (en) 1997-06-16 1999-01-12 Hideo Honma Via-filling method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4292144A (en) * 1979-06-29 1981-09-29 Office National D'etudes Et De Recherches Aerospatiales Process and device for coating small-sized elements with a metal deposit
US5976341A (en) * 1993-12-24 1999-11-02 Schumacher; Rolf Process and apparatus for electrolytic deposition of metal layers
US6099711A (en) * 1995-11-21 2000-08-08 Atotech Deutschland Gmbh Process for the electrolytic deposition of metal layers
US5683564A (en) * 1996-10-15 1997-11-04 Reynolds Tech Fabricators Inc. Plating cell and plating method with fluid wiper
US6129830A (en) * 1996-12-13 2000-10-10 Atotech Deutschland Gmbh Process for the electrolytic deposition of copper layers
US6537439B2 (en) * 1998-07-27 2003-03-25 Noram Engineering & Constructors Ltd. Method and apparatus for recovering a reaction product produced at a surface

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090236230A1 (en) * 2004-09-20 2009-09-24 Bert Reents Galvanic process for filling through-holes with metals, in particular of printed circuit boards with copper
US9445510B2 (en) 2004-09-20 2016-09-13 Atotech Deutschland Gmbh Galvanic process for filling through-holes with metals, in particular of printed circuit boards with copper
US9526183B2 (en) 2004-09-20 2016-12-20 Atotech Deutschland Gmbh Galvanic process for filling through-holes with metals, in particular of printed circuit boards with copper
WO2011151328A1 (en) * 2010-06-02 2011-12-08 Atotech Deutschland Gmbh Method for etching of copper and copper alloys
CN103003473A (en) * 2010-06-02 2013-03-27 安美特德国有限公司 Method for etching of copper and copper alloys
CN103388172A (en) * 2013-07-22 2013-11-13 苏州昕皓新材料科技有限公司 Rapid determining method for performances of an electroplating additive

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