WO2021104382A1 - 基线漂移消除装置及接收机 - Google Patents

基线漂移消除装置及接收机 Download PDF

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WO2021104382A1
WO2021104382A1 PCT/CN2020/131828 CN2020131828W WO2021104382A1 WO 2021104382 A1 WO2021104382 A1 WO 2021104382A1 CN 2020131828 W CN2020131828 W CN 2020131828W WO 2021104382 A1 WO2021104382 A1 WO 2021104382A1
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module
analog
compensation
digital
input terminal
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PCT/CN2020/131828
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English (en)
French (fr)
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卢天基
陆小凡
张玉龙
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深圳市中兴微电子技术有限公司
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Priority to EP20893071.9A priority Critical patent/EP4068637A4/en
Publication of WO2021104382A1 publication Critical patent/WO2021104382A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/12—Neutralising, balancing, or compensation arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H04L25/0296—Arrangements to ensure DC-balance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices

Definitions

  • This application relates to the field of circuit technology, and in particular to a baseline drift elimination device and a receiver.
  • isolation transformers or AC couplers are usually used to connect signals, which can enhance the signal, isolate interference, and isolate and protect it. It also makes it easier to adjust the working status of circuits at all levels.
  • the isolation transformer and the AC coupler are physically equivalent to a high-pass filter.
  • the DC component and low-frequency components in the signal are suppressed, leading to the phenomenon of "baseline drift": the signal appears to drift upwards for a while, then go down again after a while Roam.
  • baseline drift the signal appears to drift upwards for a while, then go down again after a while Roam.
  • transmission symbols with a very narrow pulse width and multi-level adjustment methods are often used in communication systems. In these working scenarios, the baseline drift will more seriously affect the accuracy of the symbol decision, resulting in an increase in the bit error rate, which in turn restricts the increase in the transmission rate. Therefore, it is necessary to eliminate the baseline drift as much as possible.
  • the baseline drift error is usually calculated in the digital domain and then compensated in the digital domain or the analog domain.
  • the baseline drift is introduced at the front end of the receiving circuit.
  • the baseline drift also affects the analog circuits placed in front, such as amplifiers, equalizers, and variable gain adjustment modules. , It will cause the nonlinear distortion of the analog circuit, and the compensation in the digital domain is powerless at this point; on the other hand, when the compensation in the analog domain is selected, the compensation value needs to be looped back to the analog circuit through the digital-to-analog converter. Then there is usually a large loop delay, the compensation amount calculation will not be timely and accurate, and due to the inherent characteristics of the analog circuit, it is impossible to achieve the accuracy of the digital circuit.
  • This application provides a baseline drift elimination device and a receiver to solve the current technical problems that cannot take into account the accuracy of baseline drift compensation, compensation speed, and alleviation of the nonlinear distortion of analog circuits.
  • the embodiment of the present application provides a baseline drift elimination device, including:
  • Analog processing module analog-to-digital conversion module, decision module, error estimation module, digital compensation acquisition module, digital compensation module, analog compensation acquisition module, analog compensation module, and digital-to-analog conversion module;
  • the output terminal of the front-end module is connected to the first input terminal of the analog compensation module, the output terminal of the digital-to-analog conversion module is connected to the second input terminal of the analog compensation module, and the output terminal of the analog compensation module Connected with the input terminal of the analog processing module;
  • the output terminal of the analog processing module is connected to the input terminal of the analog-to-digital conversion module
  • the output terminal of the analog-to-digital conversion module is connected to the first input terminal of the digital compensation module, the output terminal of the digital compensation acquisition module is connected to the second input terminal of the digital compensation module, and the The output terminal is connected with the input terminal of the judgment module;
  • the output terminal of the decision module is connected with the input terminal of the error estimation module, the output terminal of the error estimation module is connected with the input terminal of the digital compensation acquisition module, and the output terminal of the error estimation module is also connected with the The input terminal connection of the analog compensation acquisition module;
  • the output terminal of the analog compensation acquisition module is connected to the input terminal of the digital-to-analog conversion module;
  • the error estimation module is configured to output a baseline drift error according to the decision error output by the decision module
  • the digital compensation acquisition module is configured to output a high-frequency error component in the baseline drift error according to the baseline drift error.
  • the analog compensation acquisition module is configured to output the low-frequency error component in the baseline drift error according to the baseline drift error
  • the analog compensation module is configured to compensate the analog processing module according to the low-frequency error component after digital-to-analog conversion, so
  • the digital compensation module is configured to compensate the decision module according to the high-frequency error component.
  • An embodiment of the present application provides a receiver including a front-end module and any baseline drift elimination device in the embodiments of the present application.
  • FIG. 1 is a schematic structural diagram of a baseline drift elimination device provided by an embodiment
  • FIG. 2 is a schematic structural diagram of another baseline drift elimination device provided by an embodiment
  • FIG. 3 is a schematic structural diagram of yet another baseline drift elimination device provided by an embodiment
  • FIG. 4 is a schematic structural diagram of still another baseline drift elimination device provided by an embodiment
  • FIG. 5 is a schematic structural diagram of another baseline drift elimination device provided by an embodiment
  • FIG. 6 is a schematic structural diagram of another baseline drift elimination device provided by an embodiment
  • Figure 7 is a schematic diagram of the structure of the lead compensation circuit
  • FIG. 8 is a schematic diagram of the structure of the first integrating circuit.
  • isolation transformers or AC couplers are usually used to connect signals.
  • These devices can be equivalent to a resistance-capacitance (Resistor-Capacitance, RC) circuit, and the transfer function is expressed as: Based on the transfer function, it can be seen that these devices are equivalent to a high-pass filter, which will cause the loss of DC and low-frequency components, causing the received signal to continuously go upstream and downstream, that is, the phenomenon of baseline drift occurs, which affects the correct reception of the signal.
  • RC resistance-capacitance
  • This embodiment provides a baseline drift elimination device, which can be installed in a receiver to eliminate baseline drift caused by a front-end module in the receiver, such as an isolation transformer or an AC coupler.
  • the device can simultaneously Compensation for baseline wander phenomenon in the digital domain and analog domain, taking into account the accuracy of baseline wander compensation, compensation speed and reducing the influence of baseline wander on the nonlinear distortion of the analog circuit, thereby ensuring the accuracy of the received signal.
  • Fig. 1 is a schematic structural diagram of a baseline drift elimination device provided by an embodiment.
  • the baseline drift elimination device provided by this embodiment includes the following modules: analog processing module 13, analog-to-digital conversion module 14, decision module 16, error estimation module 17, digital compensation acquisition module 18, digital compensation module 15, The analog compensation acquisition module 19, the analog compensation module 12, and the digital-to-analog conversion module 20.
  • the output terminal of the front-end module 11 is connected to the first input terminal of the analog compensation module 12.
  • the output terminal of the digital-to-analog conversion module 20 is connected to the second input terminal of the analog compensation module 12.
  • the output terminal of the analog compensation module 12 is connected to the input terminal of the analog processing module 13.
  • the output terminal of the analog processing module 13 is connected to the input terminal of the analog-to-digital conversion module 14.
  • the output terminal of the analog-to-digital conversion module 14 is connected to the first input terminal of the digital compensation module 15.
  • the output terminal of the digital compensation acquisition module 18 is connected to the second input terminal of the digital compensation module 15.
  • the output terminal of the digital compensation module 15 is connected to the input terminal of the decision module 16.
  • the output terminal of the decision module 16 is connected to the input terminal of the error estimation module 17.
  • the output terminal of the error estimation module 17 is connected to the input terminal of the digital compensation acquisition module 18.
  • the output terminal of the error estimation module 17 is also connected to the input terminal of the analog compensation acquisition module 19.
  • the output terminal of the analog compensation acquisition module 19 is connected to the input terminal of the digital-to-analog conversion module 20.
  • the error estimation module 17 is configured to output a baseline drift error according to the decision error output by the decision module 16.
  • the digital compensation acquisition module 18 is configured to output high-frequency error components in the baseline drift error according to the baseline drift error.
  • the analog compensation acquisition module 19 is configured to output the low-frequency error component in the baseline drift error according to the baseline drift error.
  • the analog compensation module 12 is configured to compensate the analog processing module 13 according to the low-frequency error component after digital-to-analog conversion.
  • the digital compensation module 15 is configured to compensate the decision module 16 according to the high-frequency error component.
  • the front-end module 11 may be an isolation transformer or an AC coupler.
  • the analog processing module 13 may include an analog amplifier circuit, a channel compensation circuit, and a variable-gain amplifier (Variable-Gain Amplifier, VGA) and other circuits for processing analog signals.
  • VGA Variable-Gain Amplifier
  • the judgment module 16 judges which level signal the received digital signal belongs to based on the received digital signal and the standard signal level, so as to recover the transmitted information bits.
  • the decision module 16 can output a decision error according to the error between the received digital signal and the standard signal level.
  • the error estimation module 17 outputs the baseline drift error according to the decision error.
  • the baseline drift error here includes the direction and magnitude of the baseline drift. After that, loop the baseline drift error back to the input end of the signal and subtract it from the input signal to eliminate the baseline drift. To better eliminate the baseline drift, the baseline drift elimination device needs to have a good steady-state compensation accuracy, and it also needs a faster response speed to keep up with the sudden drift.
  • the baseline drift error is output as a whole.
  • a digital compensation acquisition module 18 and an analog compensation acquisition module 19 are provided to identify the components of the baseline drift error that are suitable for compensation in the analog domain, that is, the components that the analog processing module 13 compensates, and to identify that the baseline drift error is suitable for Component of digital domain compensation.
  • This embodiment includes two compensation loops, where the digital compensation acquisition module 18 and the digital compensation module 15 form an inner digital compensation loop.
  • the analog compensation acquisition module 19, the digital-to-analog conversion module 20, and the analog compensation module 12 constitute an analog compensation outer loop.
  • the loop delay is much smaller than the analog compensation outer loop.
  • the delay of the analog compensation outer loop may be 200 nanoseconds.
  • the baseline drift error is described from the perspective of response speed, including two parts: rapid change and slow change; from the perspective of compensation accuracy, it includes two parts: coarse compensation and fine compensation.
  • the analog compensation acquisition module 19 can be used to identify the low-frequency error component in the baseline drift error, that is, the slow-changing component, and convert it Compensation is performed at the analog processing module 13 to reduce the nonlinear distortion of the analog processing circuit. Since the loop delay of the digital compensation inner loop is small, the response speed is fast, and the compensation accuracy is high, the digital compensation acquisition module 18 can be used to identify the high-frequency error component in the baseline drift error, that is, the abrupt component. The compensation is in the digital circuit, namely the decision module 16, to increase the compensation speed. In an exemplary embodiment, since the analog compensated signal is also input into the digital circuit, the digital compensation inner loop can further correct the residual error after the analog processing module 13 is compensated to improve the compensation accuracy.
  • baseline drift is relatively slow and stable, and only a few times there will be sudden changes. Therefore, in the device provided by this embodiment, the DC and low-frequency gains of the analog compensation outer loop are very high, and the slow changes of the baseline drift are accumulated and eliminated. Most of the time, the analog compensation outer loop plays a major role. Reduce the non-linear distortion of the analog processing module. Only when the baseline drift is severe, the digital compensation inner loop will intervene to eliminate the sudden change, so that the decision module will not be affected by the baseline drift. In addition, the remaining errors in the analog compensation outer loop will be further processed in the digital compensation inner loop to improve the compensation accuracy.
  • the working process of the baseline drift elimination device is as follows.
  • the front-end module 11 outputs the received analog signal to the analog compensation module 12.
  • the analog compensation module 12 outputs the analog signal after analog compensation to the analog processing module 13 according to the low-frequency error component after digital-to-analog conversion and the analog signal output by the front-end module 11.
  • the analog compensation module 12 compensates the analog processing module 13 based on the low-frequency error component after digital-to-analog conversion.
  • the analog processing module 13 processes the analog signal after the analog compensation, and after the analog-to-digital conversion module 14, converts it into a digital signal after the analog compensation.
  • the digital compensation module 15 outputs the digital signal after digital compensation to the decision module 16 according to the digital signal after analog compensation and the high-frequency error component.
  • the digital compensation module 15 compensates the decision module 16 based on the high-frequency error component.
  • the decision module 16 makes a decision based on the digital signal after digital compensation, and outputs a decision error.
  • the error estimation module 17 outputs the baseline drift error according to the decision error.
  • the digital compensation acquisition module 18 is configured to output high-frequency error components in the baseline drift error to the digital compensation module 15 according to the baseline drift error.
  • the analog compensation acquisition module 19 is configured to output the low-frequency error component in the baseline drift error to the digital-to-analog conversion module 20 according to the baseline drift error.
  • the digital-to-analog conversion module 20 performs digital-to-analog conversion on the low-frequency error component to form a low-frequency error component after the digital-to-analog conversion, which is output to the analog compensation module 12.
  • the digital compensation module is a third adder (to distinguish it from the adder below, "third" does not indicate a sequence), which is set to output the output of the analog-to-digital conversion module and the high-frequency error component. Difference.
  • the analog compensation module is a fourth adder, which is set to output the difference between the output of the front-end module and the low-frequency error component after digital-to-analog conversion.
  • the device further includes an equalization module.
  • the input end of the equalization module is connected to the output end of the analog-to-digital conversion module, and the output end of the equalization module is connected to the first input end of the third adder.
  • Fig. 2 is a schematic structural diagram of another baseline drift elimination device provided by an embodiment.
  • the difference between the baseline drift elimination device and the device shown in FIG. 1 is that the digital compensation module 15 in FIG. 1 is the third adder 151 in FIG. 2, and the analog compensation module 12 in FIG. It is the fourth adder 121 in FIG. 2.
  • an equalization module 21 is provided between the analog-to-digital conversion module 14 and the third adder 151. The input end of the equalization module 21 is connected to the output end of the analog-to-digital conversion module 14, and the output end of the equalization module 21 is connected to the first input end of the third adder 151.
  • the front-end module 11 is connected to the first input end of the fourth adder 121, and the output end of the digital-to-analog conversion module 20 is connected to the second input end of the fourth adder 121.
  • the output terminal of the fourth adder 121 is connected to the input terminal of the analog processing module 13.
  • the fourth adder 121 is configured to output the difference between the output of the front-end module 11 and the low-frequency error component after digital-to-analog conversion, so as to achieve compensation for the analog processing module 13.
  • the equalization module 21 is connected to the first input terminal of the third adder 151, and the output terminal of the digital compensation acquisition module 18 is connected to the second input terminal of the third adder 151.
  • the output terminal of the third adder 151 is connected to the input terminal of the decision module 16.
  • the third adder 151 is configured to output the difference between the output of the equalization module and the high-frequency error component, so as to achieve compensation for the decision module 16.
  • the equalization module 21 is configured to eliminate inter-symbol interference caused by imperfect channels.
  • the decision module 16 further includes a decoding circuit to correct some errors of the decision module 16.
  • the error estimation module 17 may also include a filtering module to eliminate the influence of noise and misjudgment.
  • the digital compensation acquisition module can be implemented in the following two ways. According to the principle of the feedback loop, a proportional amplifier circuit or a leading compensation circuit can be used to improve the response speed of the loop feedback.
  • the digital compensation acquisition module includes a first proportional amplifying circuit whose gain is a first preset parameter.
  • the input terminal of the first proportional amplifier circuit is connected with the output terminal of the error estimation module, and the output terminal of the first proportional amplifier circuit is connected with the second input terminal of the digital compensation module (or the third adder).
  • the digital compensation acquisition module includes: a lead compensation circuit whose gain is a second preset parameter.
  • the input terminal of the lead compensation circuit is connected with the output terminal of the error estimation module, and the output terminal of the lead compensation circuit is connected with the second input terminal of the digital compensation module (or the third adder).
  • the system function of the lead compensation circuit may be Among them, ⁇ and T D are preset parameters, and ⁇ 1. The value of is close to the loop bandwidth of the lead compensation circuit, and then the value of ⁇ is adjusted so that the lead compensation circuit can balance the lead phase and high frequency gain, taking into account the system response speed and compensation accuracy.
  • the analog compensation acquisition module may also have the following two implementation modes. According to the principle of the feedback loop, an integral circuit or a proportional integral circuit can be used to reduce the steady-state error of the loop feedback system.
  • the analog compensation acquisition module includes a first integration circuit whose gain is a third preset parameter.
  • the input terminal of the first integration circuit is connected with the output terminal of the error estimation module, and the output terminal of the first integration circuit is connected with the input terminal of the digital-to-analog conversion module.
  • the analog compensation acquisition module includes: a second integrating circuit whose gain is a fourth preset parameter, a second proportional amplifying circuit whose gain is a fifth preset parameter, and a second adder.
  • the input terminal of the second integration circuit is connected with the output terminal of the error estimation module, the output terminal of the error estimation module is also connected with the input terminal of the second proportional amplifier circuit, and the output terminal of the second integration circuit is connected with the first input of the second adder.
  • the output terminal of the second proportional amplifier circuit is connected with the second input terminal of the second adder, and the output terminal of the second adder is connected with the input terminal of the digital-to-analog conversion module.
  • the digital compensation acquisition module Based on the two implementations of the digital compensation acquisition module and the two implementations of the analog compensation acquisition module, four types of baseline drift elimination devices can be obtained. Taking the digital compensation module as the third adder, the analog compensation module as the fourth adder, and the baseline drift elimination device including the equalization module as an example, the specific structures of the four baseline drift elimination devices will be described below.
  • FIG. 3 is a schematic structural diagram of yet another baseline drift elimination device provided by an embodiment.
  • the digital compensation acquisition module includes a first proportional amplifying circuit 181 whose gain is a first preset parameter.
  • the analog compensation acquisition module includes a first integrating circuit 193 whose gain is a third preset parameter.
  • the output terminal of the error estimation module 17 is connected to the input terminal of the first proportional amplifying circuit 181.
  • the output terminal of the first proportional amplifier circuit 181 is connected to the second input terminal of the third adder 151, and the output terminal of the equalization module 21 is connected to the first input terminal of the third adder 151.
  • the output terminal of the third adder 151 is connected to the input terminal of the decision module 16.
  • the output terminal of the error estimation module 17 is connected to the input terminal of the first integrating circuit 193.
  • the output terminal of the first integrating circuit 193 is connected to the input terminal of the digital-to-analog conversion module 20.
  • the other connection modes are the same as those in FIG. 1 and FIG. 2 and will not be repeated here.
  • FIG. 4 is a schematic structural diagram of still another baseline drift elimination device provided by an embodiment.
  • the digital compensation acquisition module includes a first proportional amplifying circuit 181 whose gain is a first preset parameter.
  • the analog compensation acquisition module includes: a second integrating circuit 191 whose gain is a fourth preset parameter, a second proportional amplifying circuit 192 whose gain is a fifth preset parameter, and a second adder 194.
  • connection mode of the first proportional amplifying circuit 181 is the same as that in FIG. 3, and will not be repeated here.
  • the input terminal of the second integration circuit 191 is connected to the output terminal of the error estimation module 17.
  • the output terminal of the error estimation module 17 is also connected to the input terminal of the second proportional amplifying circuit 192.
  • the output terminal of the second integrating circuit 191 is connected to the first input terminal of the second adder 194.
  • the output terminal of the second proportional amplifier circuit 192 is connected to the second input terminal of the second adder 194.
  • the output terminal of the second adder 194 is connected to the input terminal of the digital-to-analog conversion module 20.
  • the other connection modes are the same as those in FIG. 1 and FIG. 2 and will not be repeated here.
  • FIG. 5 is a schematic structural diagram of another device for removing baseline drift provided by an embodiment.
  • the digital compensation acquisition module includes the gain as the second preset parameter, and the system function as The lead compensation circuit 182.
  • the analog compensation acquisition module includes a first integrating circuit 193 whose gain is a third preset parameter.
  • the input terminal of the lead compensation circuit 182 is connected with the output terminal of the error estimation module 17, and the output terminal of the lead compensation circuit 182 is connected with the second input terminal of the third adder 151.
  • the output terminal of the equalization module 21 is connected to the first input terminal of the third adder 151.
  • the output terminal of the third adder 151 is connected to the input terminal of the decision module 16.
  • connection mode of the first integrating circuit 193 is the same as that in FIG. 3, and will not be repeated here.
  • Fig. 6 is a schematic structural diagram of another baseline drift elimination device provided by an embodiment.
  • the digital compensation acquisition module includes a gain as a second preset parameter, and a system function as The lead compensation circuit 182.
  • the analog compensation acquisition module includes: a second integrating circuit 191 whose gain is a fourth preset parameter, a second proportional amplifying circuit 192 whose gain is a fifth preset parameter, and a second adder 194.
  • connection mode of the lead compensation circuit 182 is the same as that in FIG. 5, and will not be repeated here.
  • the connection modes of the second integrating circuit 191, the second proportional amplifying circuit 192, and the second adder 194 are the same as those in FIG.
  • the integration circuit of the analog compensation acquisition module may include an adder and a delay module.
  • the digital domain system function of the first integrator circuit is: Among them, T is the sampling period.
  • Corresponding to the time domain, its implementation is: It can be simplified, and the time domain is realized as: y(n) K i x(n)+y(n-1), where K i is the gain of the first integrating circuit, that is, the third preset parameter .
  • FIG. 8 is a schematic diagram of the structure of the first integrating circuit.
  • the first integrating circuit includes: a first adder 1931 and a first delay module 1932.
  • the output terminal of the error estimation module is connected to the input terminal of the gain module (not shown in FIG. 8) whose gain is the third preset parameter (ie K i ), and the output terminal of the gain module is connected to the first input of the first adder 1931 ⁇ End connection.
  • the output terminal of the first adder 1931 is connected with the input terminal of the first delay module 1932, and the first output terminal of the first delay module 1932 is connected with the second input terminal of the first adder 1931.
  • the second output terminal of the first delay module 1932 is connected to the input terminal of the digital-to-analog conversion module.
  • Figure 7 is a schematic diagram of the structure of the lead compensation circuit. As shown in FIG. 7, the lead compensation circuit includes a fifth adder 1821, a sixth adder 1822 and a second delay module 1823. The output terminal of the error estimation module is connected to the first input terminal of the fifth adder 1821.
  • the output terminal of the fifth adder 1821 is connected to the input terminal of the second delay module 1823 and the gain module with the gain b1 is connected to the first input terminal of the sixth adder 1822.
  • the output terminal of the sixth adder 1822 is connected to the second input terminal of the digital compensation module or the second input terminal of the third adder through a gain module whose gain is the second preset parameter (ie, KL).
  • the output terminal of the second delay module 1823 is connected to the second input terminal of the fifth adder 1821 through a gain module with a gain of a.
  • the output terminal of the second delay module 1823 is also connected to the second input terminal of the sixth adder 1822 through a gain module with a gain of b2.
  • the functions of the first delay module and the second delay module in this embodiment are both to delay the storage of data by one beat, so as to use the data of the previous beat stored by the delay module in this beat.
  • the baseline drift elimination device includes: an analog processing module, an analog-to-digital conversion module, a decision module, an error estimation module, a digital compensation acquisition module, a digital compensation module, an analog compensation acquisition module, an analog compensation module, and a digital-to-analog conversion module ,
  • the analog compensation acquisition module is configured to output the low-frequency error component in the baseline drift error according to the baseline drift error output by the error estimation module
  • the digital compensation acquisition module is configured to output the baseline drift error in the baseline drift error according to the baseline drift error.
  • the high-frequency error component realizes that when the baseline drift is eliminated, on the one hand, the baseline drift compensation can be realized quickly and accurately, and on the other hand, it reduces the influence of the baseline drift on the nonlinear distortion of the analog circuit, thereby improving the received signal Accuracy.
  • This embodiment also provides a receiver including a front-end module and the baseline wander elimination device provided in any of the foregoing embodiments and optional implementation manners. It has the technical effect of the baseline drift elimination device, and will not be repeated here.
  • the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the present application is not limited thereto.
  • the block diagram of any logic flow in the drawings of the present application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions.
  • the computer program can be stored on the memory.
  • the memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function optical discs) DVD or CD) etc.
  • Computer-readable media may include non-transitory storage media.
  • the data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (FGPA) And processors based on multi-core processor architecture.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FGPA programmable logic devices

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Abstract

本申请提出一种基线漂移消除装置及接收机，一种基线漂移消除装置包括：模拟处理模块、模数转换模块、判决模块、误差估计模块、数字补偿获取模块、数字补偿模块、模拟补偿获取模块、模拟补偿模块以及数模转换模块，模拟补偿获取模块设置为根据误差估计模块输出的基线漂移误差输出其中包含的低频误差分量，数字补偿获取模块设置为根据基线漂移误差输出其中包含的高频误差分量，实现了在消除基线漂移时，一方面，可以实现快速、准确地进行基线漂移补偿，另一方面，减轻了基线漂移对模拟电路非线性失真的影响，进而，提高了接收信号的准确性。

Description

基线漂移消除装置及接收机 技术领域
本申请涉及电路技术领域，具体涉及一种基线漂移消除装置及接收机。
背景技术
以太网和高速串行通信接收机的标准中，通常利用隔离变压器或交流耦合器来连接信号，起到增强信号、隔离干扰、隔离防护的作用，也使得各级电路的工作状态更易于调节。隔离变压器和交流耦合器，在物理上等效为一个高通滤波器，信号中直流分量和低频成分被抑制，导致了“基线漂移”现象：信号看起来，一会儿往上漂移，过一会儿又往下游走。并且，由于对通信速率要求越来越高，所以在通信系统中往往采用脉宽很窄的传输符号，以及多电平的调整方式。在这些工作场景下，基线漂移会更加严重的影响符号的判决准确性，导致误码率升高，反过来制约了传输速率的提升。因此，要尽可能地消除基线漂移现象。
在现有技术中，通常在数字域计算出基线漂移误差，然后选择在数字域或模拟域做补偿。当选择在数字域做补偿，虽然数字电路快速、准确，但是基线漂移是在接收电路前端引入的，基线漂移对放置在前面的模拟电路，如放大器、均衡器、可变增益调整模块也存在影响，它会导致模拟电路的非线性失真，而数字域的补偿在这点上就无能为力；另一方面，当选择在模拟域做补偿，需要把补偿值经过数模转换器环回到模拟电路，那么通常存在较大的环路延时，补偿量计算就不会及时、准确，以及由于模拟电路的固有特性，不可能做到数字电路这么精确。
因此，目前在消除基线漂移时，无法兼顾基线漂移补偿的准确性、补偿速度以及减轻模拟电路非线性失真的问题。
发明内容
本申请提供一种基线漂移消除装置及接收机，以解决目前无法兼顾基 线漂移补偿的准确性、补偿速度以及减轻模拟电路非线性失真的技术问题。
本申请实施例提供一种基线漂移消除装置，包括：
模拟处理模块、模数转换模块、判决模块、误差估计模块、数字补偿获取模块、数字补偿模块、模拟补偿获取模块、模拟补偿模块以及数模转换模块；
其中，前端模块的输出端与所述模拟补偿模块的第一输入端连接，所述数模转换模块的输出端与所述模拟补偿模块的第二输入端连接，所述模拟补偿模块的输出端与所述模拟处理模块的输入端连接；
所述模拟处理模块的输出端与所述模数转换模块的输入端连接；
所述模数转换模块的输出端与所述数字补偿模块的第一输入端连接，所述数字补偿获取模块的输出端与所述数字补偿模块的第二输入端连接，所述数字补偿模块的输出端与所述判决模块的输入端连接；
所述判决模块的输出端与所述误差估计模块的输入端连接，所述误差估计模块的输出端与所述数字补偿获取模块的输入端连接，所述误差估计模块的输出端还与所述模拟补偿获取模块的输入端连接；
所述模拟补偿获取模块的输出端与所述数模转换模块的输入端连接；
所述误差估计模块设置为根据所述判决模块输出的判决误差输出基线漂移误差，所述数字补偿获取模块设置为根据所述基线漂移误差输出所述基线漂移误差中的高频误差分量，所述模拟补偿获取模块设置为根据所述基线漂移误差输出所述基线漂移误差中的低频误差分量，所述模拟补偿模块设置为根据数模转换后的低频误差分量对所述模拟处理模块进行补偿，所述数字补偿模块设置为根据所述高频误差分量对所述判决模块进行补偿。
本申请实施例提供一种接收机，包括前端模块以及本申请实施例中的任意一种基线漂移消除装置。
关于本申请的以上实施例和其他方面以及其实现方式，在附图说明、 具体实施方式和权利要求中提供更多说明。
附图说明
图1为一实施例提供的一种基线漂移消除装置的结构示意图；
图2为一实施例提供的另一种基线漂移消除装置的结构示意图；
图3为一实施例提供的又一种基线漂移消除装置的结构示意图；
图4为一实施例提供的再一种基线漂移消除装置的结构示意图；
图5为一实施例提供的另一种基线漂移消除装置的结构示意图；
图6为一实施例提供的另一种基线漂移消除装置的结构示意图；
图7为超前补偿电路的结构示意图；
图8为第一积分电路的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明白，下文中将结合附图对本申请的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
以太网和高速串行通信接收机中，通常使用隔离变压器或者交流耦合器来连接信号。这些器件可以等效为电阻-电容(Resistor-Capacitance，RC)电路，传输函数表示为：
Figure PCTCN2020131828-appb-000001
基于传输函数，可以看出这些器件相当于一个高通滤波器，会导致直流和低频分量的损失，使接收到的信号不停地上下游走，即，出现基线漂移现象，影响信号的正确接收。
本实施例提供一种基线漂移消除装置，该装置可以设置于接收机中，以对接收机中的前端模块，例如，隔离变压器或者交流耦合器，造成的基线漂移现象进行消除，该装置可以同时在数字域和模拟域对基线漂移现象进行补偿，兼顾了基线漂移补偿的准确性、补偿速度以及减轻基线漂移对模拟电路非线性失真的影响，从而，保证了接收到的信号的准确性。
图1为一实施例提供的一种基线漂移消除装置的结构示意图。如图1所示，本实施例提供的基线漂移消除装置包括如下模块：模拟处理模块13、模数转换模块14、判决模块16、误差估计模块17、数字补偿获取模块18、数字补偿模块15、模拟补偿获取模块19、模拟补偿模块12以及数模转换模块20。
其中，前端模块11的输出端与模拟补偿模块12的第一输入端连接。数模转换模块20的输出端与模拟补偿模块12的第二输入端连接。模拟补偿模块12的输出端与模拟处理模块13的输入端连接。
模拟处理模块13的输出端与模数转换模块14的输入端连接。
模数转换模块14的输出端与数字补偿模块15的第一输入端连接。数字补偿获取模块18的输出端与数字补偿模块15的第二输入端连接。数字补偿模块15的输出端与判决模块16的输入端连接。
判决模块16的输出端与误差估计模块17的输入端连接。误差估计模块17的输出端与数字补偿获取模块18的输入端连接。误差估计模块17的输出端还与模拟补偿获取模块19的输入端连接。
模拟补偿获取模块19的输出端与数模转换模块20的输入端连接。
误差估计模块17设置为根据判决模块16输出的判决误差输出基线漂移误差。数字补偿获取模块18设置为根据基线漂移误差输出基线漂移误差中的高频误差分量。模拟补偿获取模块19设置为根据基线漂移误差输出基线漂移误差中的低频误差分量。模拟补偿模块12设置为根据数模转换后的低频误差分量对模拟处理模块13进行补偿。数字补偿模块15设置为根据高频误差分量对判决模块16进行补偿。
一实施例中，前端模块11可以为隔离变压器或者交流耦合器。
一实施例中，模拟处理模块13可以包括模拟放大电路、信道补偿电路以及可变增益放大器(Variable-Gain Amplifier，VGA)等处理模拟信号的电路。
一实施例中，判决模块16根据接收到的数字信号以及标准信号电平，判断接收到的数字信号属于哪一个电平信号，以恢复出传输的信息比特。判决模块16可以根据接收到的数字信号与标准信号电平之间的误差，输出判决误差。误差估计模块17根据该判决误差输出基线漂移误差。这里的基线漂移误差包括基线漂移的方向和大小。之后，将基线漂移误差环回到信号的输入端，与输入信号相减，即可以消除基线漂移。要较好地消除基线漂移，既需要基线漂移消除装置有很好的稳态补偿精度，也需要较快的响应速度来跟上突变的漂移。
误差估计模块17中，基线漂移误差是作为一个整体输出的。本实施例中，设置了数字补偿获取模块18以及模拟补偿获取模块19，以识别出基线漂移误差中适合在模拟域，即模拟处理模块13补偿的分量，以及，识别出基线漂移误差中适合在数字域补偿的分量。
本实施例中包括两个补偿环路，其中，数字补偿获取模块18以及数字补偿模块15构成数字补偿内环。模拟补偿获取模块19、数模转换模块20以及模拟补偿模块12构成模拟补偿外环。
数字补偿内环由于没有经过模拟处理模块13、模数转换模块14等，环路延时比模拟补偿外环小的多。示例性地，假设数字补偿内环的延时为30纳秒，则模拟补偿外环的延时有可能为200纳秒。
基线漂移误差，从响应速度角度描述，包括快变和缓变两部分；从补偿精度角度描述，包括粗补偿和精补偿两部分。
由于模拟补偿外环的环路延时较大、响应速度慢、补偿精度低，因此，可以采用模拟补偿获取模块19识别出基线漂移误差中的低频误差分量，即，缓变的分量，将其补偿在模拟处理模块13处，以减轻模拟处理电路的非线性失真。由于数字补偿内环的环路延时较小、响应速度快、补偿精度高，因此，可以采用数字补偿获取模块18识别出基线漂移误差中的高频误差分量，即，突变的分量，将其补偿在数字电路，即判决模块16中，以提高补偿速度。在一示例性实施例中，由于模拟补偿后的信号还会输入 到数字电路中，因此，数字补偿内环还可以进一步修正对模拟处理模块13补偿后残留的误差，提高补偿精度。
根据基线漂移的特性，绝大多数时候基线漂移都是比较缓慢平稳的，只有少数时间内会存在突然的变化。因此，本实施例提供的装置中，模拟补偿外环的直流和低频增益很高，把基线漂移的缓慢变化部分累积下来，并加以消除，大部分时间内模拟补偿外环起到主要作用，这减少了模拟处理模块的非线性失真。只有在基线漂移比较厉害的时候，数字补偿内环会介入把突变部分消除，使判决模块不受到基线漂移的影响。另外，模拟补偿外环中残留下来的误差，在数字补偿内环中会被进一步处理，提高补偿精度。
本实施例提供的基线漂移消除装置的工作过程如下。前端模块11将接收到的模拟信号输出给模拟补偿模块12。模拟补偿模块12根据数模转换后的低频误差分量以及前端模块11输出的模拟信号输出模拟补偿后的模拟信号至模拟处理模块13中。在这个过程中，模拟补偿模块12基于数模转换后的低频误差分量对模拟处理模块13进行了补偿。模拟处理模块13对模拟补偿后的模拟信号进行处理，再经过模数转换模块14后，转换为模拟补偿后的数字信号。数字补偿模块15根据模拟补偿后的数字信号以及高频误差分量，输出数字补偿后的数字信号至判决模块16中。在这个过程中，数字补偿模块15基于高频误差分量对判决模块16进行了补偿。判决模块16根据数字补偿后的数字信号，进行判决，输出判决误差。误差估计模块17根据判决误差输出基线漂移误差。数字补偿获取模块18设置为根据基线漂移误差输出基线漂移误差中的高频误差分量至数字补偿模块15中。模拟补偿获取模块19设置为根据基线漂移误差输出基线漂移误差中的低频误差分量至数模转换模块20中。数模转换模块20对低频误差分量进行数模转换，形成数模转换后的低频误差分量，输出至模拟补偿模块12中。
一实施例中，数字补偿模块为第三加法器(为与后文的加法器进行区 分，“第三”并不表示顺序)，设置为输出模数转换模块的输出量与高频误差分量的差值。
一实施例中，模拟补偿模块为第四加法器，设置为输出前端模块的输出量与数模转换后的低频误差分量的差值。
一实施例中，装置还包括均衡模块。均衡模块的输入端与模数转换模块的输出端连接，均衡模块的输出端与第三加法器的第一输入端连接。
图2为一实施例提供的另一种基线漂移消除装置的结构示意图。如图2所示，该基线漂移消除装置与图1所示装置的不同之处在于，图1中的数字补偿模块15为图2中的第三加法器151，图1中的模拟补偿模块12为图2中的第四加法器121。并且，图2中在模数转换模块14与第三加法器151之间设置了均衡模块21。均衡模块21的输入端与模数转换模块14的输出端连接，均衡模块21的输出端与第三加法器151的第一输入端连接。
前端模块11与第四加法器121的第一输入端连接，数模转换模块20的输出端与第四加法器121的第二输入端连接。第四加法器121的输出端与模拟处理模块13的输入端连接。第四加法器121设置为输出前端模块11的输出量与数模转换后的低频误差分量的差值，以实现对模拟处理模块13的补偿。
均衡模块21与第三加法器151的第一输入端连接，数字补偿获取模块18的输出端与第三加法器151的第二输入端连接。第三加法器151的输出端与判决模块16的输入端连接。第三加法器151设置为输出均衡模块的输出量与高频误差分量的差值，以实现对判决模块16的补偿。
一实施例中，均衡模块21设置为消除信道不理想导致的符号间干扰。
一实施例中，判决模块16之后还包括译码电路，以纠正判决模块16的部分错误。
一实施例中，误差估计模块17还可以包括滤波模块，以消除噪声和 误判决的影响。
本实施例提供的基线漂移消除装置中，数字补偿获取模块可以有以下两种实现方式。根据反馈环路的原理，可以使用比例放大电路或者超前补偿电路，来提高环路反馈的响应速度。
第一种实现方式中，数字补偿获取模块包括增益为第一预设参数的第一比例放大电路。第一比例放大电路的输入端与误差估计模块的输出端连接，第一比例放大电路的输出端与数字补偿模块(或者第三加法器)的第二输入端连接。
第二种实现方式中，数字补偿获取模块包括：增益为第二预设参数的超前补偿电路。超前补偿电路的输入端与误差估计模块的输出端连接，超前补偿电路的输出端与数字补偿模块(或者第三加法器)的第二输入端连接。
一实施例中，该超前补偿电路的系统函数可以为
Figure PCTCN2020131828-appb-000002
其中，α、T D均为预设参数，且α<1。
Figure PCTCN2020131828-appb-000003
的值接近于超前补偿电路的环路带宽，接着调整α的值，使得超前补偿电路可以在超前相位和高频增益之间平衡，兼顾系统响应速度和补偿精度。
本实施例提供的基线漂移消除装置中，模拟补偿获取模块也可以有以下两种实现方式。根据反馈环路的原理，可以使用积分电路或者比例积分电路，来降低环路反馈系统的稳态误差。
第一种实现方式中，模拟补偿获取模块包括增益为第三预设参数的第一积分电路。第一积分电路的输入端与误差估计模块的输出端连接，第一积分电路的输出端与数模转换模块的输入端连接。
第二种实现方式中，模拟补偿获取模块包括：增益为第四预设参数的第二积分电路、增益为第五预设参数的第二比例放大电路以及第二加法器。 第二积分电路的输入端与误差估计模块的输出端连接，误差估计模块的输出端还与第二比例放大电路的输入端连接，第二积分电路的输出端与第二加法器的第一输入端连接，第二比例放大电路的输出端与第二加法器的第二输入端连接，第二加法器的输出端与数模转换模块的输入端连接。
基于数字补偿获取模块的两种实现方式以及模拟补偿获取模块的两种实现方式，可以得到四种基线漂移消除装置。以下以数字补偿模块为第三加法器、模拟补偿模块为第四加法器、且基线漂移消除装置包括均衡模块为例，对这四种基线漂移消除装置的具体结构进行说明。
图3为一实施例提供的又一种基线漂移消除装置的结构示意图。如图3所示，该基线漂移消除装置中，数字补偿获取模块包括增益为第一预设参数的第一比例放大电路181。模拟补偿获取模块包括增益为第三预设参数的第一积分电路193。
其中，误差估计模块17的输出端与第一比例放大电路181的输入端连接。第一比例放大电路181的输出端与第三加法器151的第二输入端连接，均衡模块21的输出端与第三加法器151的第一输入端连接。第三加法器151的输出端与判决模块16的输入端连接。
误差估计模块17的输出端与第一积分电路193的输入端连接。第一积分电路193的输出端与数模转换模块20的输入端连接。其他连接方式与图1和图2中的连接方式相同，此处不再赘述。
图4为一实施例提供的再一种基线漂移消除装置的结构示意图。如图4所示，该基线漂移消除装置中，数字补偿获取模块包括增益为第一预设参数的第一比例放大电路181。模拟补偿获取模块包括：增益为第四预设参数的第二积分电路191、增益为第五预设参数的第二比例放大电路192以及第二加法器194。
第一比例放大电路181的连接方式与图3中相同，此处不再赘述。
第二积分电路191的输入端与误差估计模块17的输出端连接。误差 估计模块17的输出端还与第二比例放大电路192的输入端连接。第二积分电路191的输出端与第二加法器194的第一输入端连接。第二比例放大电路192的输出端与第二加法器194的第二输入端连接。第二加法器194的输出端与数模转换模块20的输入端连接。其他连接方式与图1和图2中的连接方式相同，此处不再赘述。
图5为一实施例提供的另一种基线漂移消除装置的结构示意图。如图5所示，该基线漂移消除装置中，数字补偿获取模块包括增益为第二预设参数、系统函数为
Figure PCTCN2020131828-appb-000004
的超前补偿电路182。模拟补偿获取模块包括增益为第三预设参数的第一积分电路193。
超前补偿电路182的输入端与误差估计模块17的输出端连接，超前补偿电路182的输出端与第三加法器151的第二输入端连接。均衡模块21的输出端与第三加法器151的第一输入端连接。第三加法器151的输出端与判决模块16的输入端连接。
第一积分电路193的连接方式与图3中相同，此处不再赘述。
图6为一实施例提供的另一种基线漂移消除装置的结构示意图。如图6所示，该基线漂移消除装置中，数字补偿获取模块包括增益为第二预设参数、系统函数为
Figure PCTCN2020131828-appb-000005
的超前补偿电路182。模拟补偿获取模块包括：增益为第四预设参数的第二积分电路191、增益为第五预设参数的第二比例放大电路192以及第二加法器194。
超前补偿电路182的连接方式与图5中相同，此处不再赘述。第二积分电路191、第二比例放大电路192以及第二加法器194的连接方式与图4中相同，此处不再赘述。
一实施例中，模拟补偿获取模块的积分电路可以包括加法器和延时模块。以下以第一积分电路为例，对模拟补偿获取模块的积分电路的实现方 式作一详细说明。第一积分电路的数字域系统函数为：
Figure PCTCN2020131828-appb-000006
其中，T为采样周期。对应到时域上，它的实现为：
Figure PCTCN2020131828-appb-000007
可以对其进行简化，得到时域实现为：y(n)＝K ix(n)+y(n-1)，其中，K i为第一积分电路的增益，即，第三预设参数。
图8为第一积分电路的结构示意图。如图8所示，第一积分电路包括：第一加法器1931和第一延时模块1932。误差估计模块的输出端与增益为第三预设参数(即K i)的增益模块(图8中未示出)的输入端连接，增益模块的输出端与第一加法器1931的第一输入端连接。第一加法器1931的输出端与第一延时模块1932的输入端连接，第一延时模块1932的第一输出端与第一加法器1931的第二输入端连接。第一延时模块1932的第二输出端与数模转换模块的输入端连接。
一实施例中，基于超前补偿电路的系统函数为
Figure PCTCN2020131828-appb-000008
采用双线性变化法、导数逼近法或者冲激不变法，把系统函数变换到数字域实现，可以得到时域表达式为：y(n)＝b 1*x(n)+b 2*x(n-1)+a*y(n-1)。图7为超前补偿电路的结构示意图。如图7所示，超前补偿电路包括第五加法器1821、第六加法器1822以及第二延时模块1823。误差估计模块的输出端与第五加法器1821的第一输入端连接。第五加法器1821的输出端与第二延时模块1823的输入端以及经过增益为b1的增益模块与第六加法器1822的第一输入端连接。第六加法器1822的输出端通过增益为第二预设参数(即KL)的增益模块与数字补偿模块的第二输入端或者第三加法器的第二输入端连接。第二延时模块1823的输出端经过增益为a的增益模块与第五加法器1821的第二输入端连接。第二延时模块1823的输出端还经过增益为b2的增益模块与第六加法器1822的第二输入端连接。
本实施例中的第一延时模块与第二延时模块的作用均为延时一个节拍存储数据，以在本节拍使用到延时模块存储的上一节拍的数据。
本实施例提供的基线漂移消除装置，包括：模拟处理模块、模数转换模块、判决模块、误差估计模块、数字补偿获取模块、数字补偿模块、模拟补偿获取模块、模拟补偿模块以及数模转换模块，模拟补偿获取模块设置为根据误差估计模块输出的基线漂移误差输出所述基线漂移误差中的低频误差分量，所述数字补偿获取模块设置为根据所述基线漂移误差输出所述基线漂移误差中的高频误差分量，实现了在消除基线漂移时，一方面，可以实现快速、准确地进行基线漂移补偿，另一方面，减轻了基线漂移对模拟电路非线性失真的影响，进而，提高了接收信号的准确性。
本实施例还提供一种接收机，包括前端模块以及上述任意实施例以及可选的实现方式提供的基线漂移消除装置。其具备基线漂移消除装置所具备的技术效果，此处不再赘述。
以上所述，仅为本申请的示例性实施例而已，并非用于限定本申请的保护范围。
一般来说，本申请的多种实施例可以在硬件或专用电路、软件、逻辑或其任何组合中实现。例如，一些方面可以被实现在硬件中，而其它方面可以被实现在可以被控制器、微处理器或其它计算装置执行的固件或软件中，尽管本申请不限于此。
本申请附图中的任何逻辑流程的框图可以表示程序步骤，或者可以表示相互连接的逻辑电路、模块和功能，或者可以表示程序步骤与逻辑电路、模块和功能的组合。计算机程序可以存储在存储器上。存储器可以具有任何适合于本地技术环境的类型并且可以使用任何适合的数据存储技术实现，例如但不限于只读存储器(ROM)、随机访问存储器(RAM)、光存储器装置和系统(数码多功能光碟DVD或CD光盘)等。计算机可读介质可以包括非瞬时性存储介质。数据处理器可以是任何适合于本地技术环境的类型，例如但不限于通用计算机、专用计算机、微处理器、数字信号 处理器(DSP)、专用集成电路(ASIC)、可编程逻辑器件(FGPA)以及基于多核处理器架构的处理器。
通过示范性和非限制性的示例，上文已提供了对本申请的示范实施例的详细描述。但结合附图和权利要求来考虑，对以上实施例的多种修改和调整对本领域技术人员来说是显而易见的，但不偏离本申请的范围。因此，本申请的恰当范围将根据权利要求确定。

Claims (10)

  1. 一种基线漂移消除装置，包括：
    模拟处理模块、模数转换模块、判决模块、误差估计模块、数字补偿获取模块、数字补偿模块、模拟补偿获取模块、模拟补偿模块以及数模转换模块；
    其中，前端模块的输出端与所述模拟补偿模块的第一输入端连接，所述数模转换模块的输出端与所述模拟补偿模块的第二输入端连接，所述模拟补偿模块的输出端与所述模拟处理模块的输入端连接；
    所述模拟处理模块的输出端与所述模数转换模块的输入端连接；
    所述模数转换模块的输出端与所述数字补偿模块的第一输入端连接，所述数字补偿获取模块的输出端与所述数字补偿模块的第二输入端连接，所述数字补偿模块的输出端与所述判决模块的输入端连接；
    所述判决模块的输出端与所述误差估计模块的输入端连接，所述误差估计模块的输出端与所述数字补偿获取模块的输入端连接，所述误差估计模块的输出端还与所述模拟补偿获取模块的输入端连接；
    所述模拟补偿获取模块的输出端与所述数模转换模块的输入端连接；
    所述误差估计模块设置为根据所述判决模块输出的判决误差输出基线漂移误差，所述数字补偿获取模块设置为根据所述基线漂移误差输出所述基线漂移误差中的高频误差分量，所述模拟补偿获取模块设置为根据所述基线漂移误差输出所述基线漂移误差中的低频误差分量，所述模拟补偿模块设置为根据数模转换后的低频误差分量对所述模拟处理模块进行补偿，所述数字补偿模块设置为根据所述高频误差分量对所述判决模块进行补偿。
  2. 根据权利要求1所述的装置，其中，所述数字补偿获取模块包括增益为第一预设参数的第一比例放大电路；
    所述第一比例放大电路的输入端与所述误差估计模块的输出端连 接，所述第一比例放大电路的输出端与所述数字补偿模块的第二输入端连接。
  3. 根据权利要求1所述的装置，其中，所述数字补偿获取模块包括：增益为第二预设参数的超前补偿电路；
    所述超前补偿电路的输入端与所述误差估计模块的输出端连接，所述超前补偿电路的输出端与所述数字补偿模块的第二输入端连接。
  4. 根据权利要求3所述的装置，其中，所述超前补偿电路的系统函数为
    Figure PCTCN2020131828-appb-100001
    其中，α、T D均为预设参数，且α<1。
  5. 根据权利要求1所述的装置，其中，所述模拟补偿获取模块包括增益为第三预设参数的第一积分电路；
    所述第一积分电路的输入端与所述误差估计模块的输出端连接，所述第一积分电路的输出端与所述数模转换模块的输入端连接。
  6. 根据权利要求5所述的装置，其中，所述第一积分电路包括：第一加法器和第一延时模块；
    所述误差估计模块的输出端与增益为所述第三预设参数的增益模块的输入端连接，所述增益模块的输出端与所述第一加法器的第一输入端连接，所述第一加法器的输出端与所述第一延时模块的输入端连接，所述第一延时模块的第一输出端与所述第一加法器的第二输入端连接，所述第一延时模块的第二输出端与所述数模转换模块的输入端连接。
  7. 根据权利要求1所述的装置，其中，所述模拟补偿获取模块包括：增益为第四预设参数的第二积分电路、增益为第五预设参数的第二比例放大电路以及第二加法器；
    所述第二积分电路的输入端与所述误差估计模块的输出端连接，所述误差估计模块的输出端还与所述第二比例放大电路的输入端连接， 所述第二积分电路的输出端与所述第二加法器的第一输入端连接，所述第二比例放大电路的输出端与所述第二加法器的第二输入端连接，所述第二加法器的输出端与所述数模转换模块的输入端连接。
  8. 根据权利要求1-7任一项所述的装置，其中，所述数字补偿模块为第三加法器，设置为输出所述模数转换模块的输出量与所述高频误差分量的差值；
    所述模拟补偿模块为第四加法器，设置为输出所述前端模块的输出量与所述数模转换后的低频误差分量的差值。
  9. 根据权利要求8所述的装置，其中，所述装置还包括均衡模块，所述均衡模块的输入端与所述模数转换模块的输出端连接，所述均衡模块的输出端与所述第三加法器的第一输入端连接。
  10. 一种接收机，包括前端模块以及如权利要求1-9任一项所述的基线漂移消除装置。
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