WO2021103601A1 - 一种图像传感器结构和形成方法 - Google Patents

一种图像传感器结构和形成方法 Download PDF

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WO2021103601A1
WO2021103601A1 PCT/CN2020/103756 CN2020103756W WO2021103601A1 WO 2021103601 A1 WO2021103601 A1 WO 2021103601A1 CN 2020103756 W CN2020103756 W CN 2020103756W WO 2021103601 A1 WO2021103601 A1 WO 2021103601A1
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pixel unit
ring
unit array
metal ring
hollow metal
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PCT/CN2020/103756
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English (en)
French (fr)
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顾学强
卢珂
赵一瑞
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上海集成电路研发中心有限公司
成都微光集电科技有限公司
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Priority to US17/775,600 priority Critical patent/US20220415951A1/en
Publication of WO2021103601A1 publication Critical patent/WO2021103601A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

Definitions

  • the present invention relates to the technical field of image sensors, and in particular to an image sensor structure and a forming method that can prevent the influence of the light-emitting and heat generation of a circuit on the photosensitive of a pixel unit.
  • Image sensor refers to a device that converts light signals into electrical signals.
  • large-scale commercial image sensor chips include charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) image sensor chips.
  • CCD charge coupled devices
  • CMOS image sensor Compared with the traditional CCD sensor, CMOS image sensor has the characteristics of low power consumption, low cost and compatibility with CMOS process, so it is more and more widely used.
  • CMOS image sensors are not only used in consumer electronics fields such as micro digital cameras (DSC), cell phone cameras, camcorders and digital single-lens reflex (DSLR), but also in automotive electronics, surveillance, biotechnology, and medicine.
  • DSC micro digital cameras
  • DSLR digital single-lens reflex
  • FIG. 1 is a schematic layout diagram of a conventional CMOS image sensor chip
  • FIG. 2 is a schematic cross-sectional structure diagram along the position A-B in FIG. 1.
  • the center of the chip is a densely arranged pixel unit array, which is responsible for converting optical signals into electrical signals; around the pixel unit array are various peripheral control and readout circuits, including column-level readout circuits and Peripheral circuits such as row selection control circuit.
  • peripheral control and readout circuits including column-level readout circuits and Peripheral circuits such as row selection control circuit.
  • the recombination of electron and hole pairs may occur.
  • the recombination process is accompanied by the generation of photons, that is, the phenomenon of circuit light emission.
  • the heating phenomenon is due to the release of a part of the heat when the current passes through the conductor or semiconductor in the circuit, causing the temperature of the chip to rise.
  • the luminescence and heat generation of these peripheral circuits will directly affect the performance of the image sensor. Among them, the heat generated by the circuit will be transferred to the pixel unit array, causing the dark current of the pixel unit to increase; the light emission of the circuit will cause an abnormal increase in the edge output signal of the pixel unit array, causing image distortion.
  • the silicon substrate 10 is a good conductor of heat and the dielectric layer 12 is a poor conductor of heat, there is an order of magnitude difference in thermal resistance between the two. Therefore, the heat generated by the circuit heating mainly propagates in the silicon substrate 10, and finally reaches the photodiode 11 area for realizing photoelectric conversion in the pixel unit area, causing the dark current of the pixel unit to rise and performance degradation;
  • the dielectric layer 12 can transmit light, so the photons generated by the circuit's light emission travel through the silicon substrate 10 and the dielectric layer 12 at the same time, and finally reach the photodiode 11 area, which causes the output value of the photodiode at the edge of the pixel unit array area to increase abnormally and image distortion.
  • the purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide an image sensor structure and forming method to prevent the deterioration and distortion of the image quality caused by the light emission and heat generation of the peripheral circuit of the image sensor.
  • the present invention provides an image sensor structure including: a pixel unit array, a peripheral circuit located at the periphery of the pixel unit array, between the pixel unit array and the peripheral circuit and surrounding the pixel unit array
  • the composite shielding structure includes a light shielding structure and a heat shielding structure; wherein, the light shielding structure is provided with a metal isolation structure surrounding the pixel unit array, which is used to protect the light emitted from the peripheral circuit.
  • the thermal shielding structure includes a cavity provided inside the metal isolation structure, and the cavity is filled with a thermal isolation medium to prevent heat from being transferred to the pixel unit array.
  • the pixel unit array and the peripheral circuit are arranged on a device silicon chip
  • the device silicon chip includes a silicon substrate and a back dielectric layer arranged on the front surface of the silicon substrate;
  • the metal isolation structure includes Connected hollow metal ring and solid metal ring, the hollow metal ring is arranged in the silicon substrate, and the hollow interior forms the cavity, and the solid metal ring is arranged on the back dielectric layer in.
  • a shallow groove isolation surrounding the pixel unit array is provided between the pixel unit array and the peripheral circuit, and the hollow metal ring includes a first hollow metal ring and a second hollow metal ring that are connected.
  • the cavity includes a first cavity provided in the hollow interior of the first hollow metal ring and a second cavity provided in the hollow interior of the second hollow metal ring, and the first hollow metal ring penetrates the Shallow trench isolation.
  • a first trench is provided in the shallow trench isolation, the first hollow metal ring is provided in the first trench, and the silicon substrate is provided with a first trench connected to the first trench.
  • the second groove, the second hollow metal ring is arranged in the second groove.
  • the solid metal ring includes a ring-shaped contact hole and a ring-shaped one-to-multi-layer metal interconnection layer metal arranged around the pixel unit array.
  • the metal of the ring-shaped multilayer metal interconnection layer is connected through ring-shaped through holes.
  • the thermal isolation medium includes air, nitrogen or helium.
  • the pixel unit array includes: a photodiode and a control transistor provided on the front surface of the silicon substrate, a pixel unit metal interconnection layer provided in the back dielectric layer;
  • the peripheral circuit includes: a device The peripheral circuit transistor on the front surface of the silicon substrate is arranged on the peripheral circuit metal interconnection layer in the back dielectric layer.
  • the peripheral circuit includes a column-level readout circuit and a row selection control circuit.
  • the present invention provides a method for forming an image sensor structure, which includes the following steps:
  • a device silicon wafer with a silicon substrate is provided, a photodiode for light-sensing in a pixel unit array, a control transistor are formed on the front surface of the silicon substrate, a peripheral circuit transistor in the peripheral circuit is formed on the outside of the pixel unit array, and A shallow groove isolation surrounding the pixel unit array is formed between the pixel unit array and the peripheral circuit;
  • the first hollow metal ring metal is deposited on the sidewall of the first trench, so that the first hollow metal ring metal is preferentially closed at the openings at the upper and lower ends of the first trench, thereby forming a second hollow metal ring inside the first trench.
  • a back dielectric layer is formed on the front surface of the silicon substrate, and a conventional contact hole and one or more conventional metal interconnection layers are formed in the back dielectric layer; wherein, the conventional contact hole and the conventional metal interconnection layer are formed At the same time, through layout design, a ring-shaped contact hole surrounding the pixel unit array and one or more layers of ring-shaped metal interconnection layer metals are formed between the pixel unit array and the peripheral circuit to form a solid metal ring;
  • the second hollow metal ring metal is deposited on the sidewall of the second trench, so that the second hollow metal ring metal is preferentially closed at the openings at the upper and lower ends of the second trench, thereby forming a second hollow metal ring inside the second trench.
  • Two hollow metal rings and a second cavity located inside the second hollow metal ring form the second hollow metal ring and its inner second cavity, the first hollow metal ring and its inner first cavity, which are sequentially connected
  • the cavity and the solid metal ring constitute a composite shielding structure against light and heat.
  • the advantage of the present invention is that the present invention can effectively shield the light emission and heat generation of peripheral circuits from propagating to the pixel unit array by forming a composite shielding structure penetrating from top to bottom in the silicon substrate and the back dielectric layer.
  • the hollow metal ring located in the silicon substrate and the shallow groove isolation, and the solid metal ring located in the back dielectric layer can effectively shield the propagation of the circuit light; and the hollow metal ring has the cavity and the shallow groove isolation.
  • the composite structure composed of the dielectric layer material can effectively block the propagation of the circuit heat, thereby effectively preventing the circuit's light emission and heat from affecting the pixel unit area.
  • Figure 1 is a schematic diagram of the layout of a conventional CMOS image sensor chip.
  • Fig. 2 is a schematic cross-sectional structure view taken along position A-B in Fig. 1.
  • FIG. 3 is a schematic diagram of the layout of an image sensor chip according to a preferred embodiment of the present invention.
  • Fig. 4 is a schematic cross-sectional structure view taken along the position C-D in Fig. 3.
  • 5 to 13 are schematic diagrams of process steps in a method for forming an image sensor structure according to a preferred embodiment of the present invention.
  • Figure 3 is a schematic diagram of the layout of an image sensor chip according to a preferred embodiment of the present invention
  • Figure 4 is a cross-sectional structure along the CD position in Figure 3 Schematic.
  • an image sensor structure of the present invention can be built on a device silicon chip and a carrier that are bonded up and down.
  • the image sensor chip structure includes a pixel unit area and a peripheral circuit area surrounding the pixel unit area.
  • the pixel unit area is provided with a pixel unit array
  • the peripheral circuit area is provided with peripheral circuits such as a column-level readout circuit and a row selection control circuit.
  • the pixel unit array and the peripheral circuit are arranged on the device silicon chip;
  • the device silicon chip includes a silicon substrate 20 and a back dielectric layer 33 arranged on the front surface of the silicon substrate 20.
  • the carrier sheet is bonded to the surface of the back dielectric layer 33.
  • the pixel unit area (pixel unit array) and the peripheral circuit area (peripheral circuit) are isolated by a shallow trench isolation 30 structure.
  • the shallow trench isolation 30 is provided on the silicon substrate 20 and forms a ring shape around the pixel unit array.
  • the pixel unit array may include a photodiode 21 and a control transistor 35 arranged on the front surface of the silicon substrate 20.
  • the peripheral circuit may include a peripheral circuit transistor 32 provided on the front surface of the silicon substrate 20.
  • a metal interconnection layer 34 is provided in the back dielectric layer 33, which includes a pixel unit metal interconnection layer and a peripheral circuit metal interconnection layer.
  • the outer side of the pixel unit array is surrounded by a ring-shaped composite shielding structure; the outer side of the composite shielding structure is surrounded by a peripheral circuit.
  • the composite shielding structure includes a light shielding structure 27 and a heat shielding structure 31.
  • the light shielding structure 27 is provided with metal isolation structures 22 to 26 surrounding the pixel unit array; the metal isolation structures 22 to 26 are used to isolate light emitted by peripheral circuits.
  • the metal isolation structures 22 to 26 may be continuous or discontinuous in the form of a plane ring around the pixel unit array.
  • the heat shielding structure 31 includes cavities 28 and 29 arranged inside the metal isolation structures 22 to 26; the cavities 28 and 29 are filled with a thermal isolation medium to prevent heat from being transferred to the pixel unit array.
  • the thermal isolation medium can include poor heat conductors such as air, nitrogen, or helium; other suitable gas or solid media can also be used.
  • the metal isolation structures 22 to 26 include hollow metal rings 25 to 26 and solid metal rings 22 to 24 connected to each other.
  • the hollow metal rings 25 to 26 are arranged in the silicon substrate 20, and the hollow metal rings 25 to 26 are hollow inside to form the cavities 28 and 29 of the heat shielding structure 31.
  • the hollow metal rings 25 to 26 may include a first hollow metal ring 25 and a second hollow metal ring 26 that are connected.
  • the cavities 28 and 29 also include a first cavity 29 arranged inside the hollow of the first hollow metal ring 25 and a second cavity 28 arranged inside the hollow of the second hollow metal ring 26.
  • the first hollow metal ring 25 penetrates through the dielectric layer of the shallow groove isolation 30.
  • the solid metal rings 22 to 24 are arranged in the back dielectric layer 33.
  • the solid metal rings 22 to 24 can be formed by using related metals for making the metal interconnection layer 34.
  • the solid metal rings 22 to 24 can include ring-shaped contact holes 24 arranged around the pixel unit array (which can be used in the production of conventional contact holes 37).
  • Simultaneously formed) and ring-shaped one-to-multi-layer metal interconnection layer metal 23, such as the illustrated two-layer ring-shaped metal interconnection layer metal 23 can be formed at the same time as the conventional metal interconnection layer 34), and used to connect two The ring-shaped through hole 22 of the layer of ring-shaped metal interconnection layer metal 23 (can be formed at the same time as the conventional through hole 38 is made).
  • the first trench 36 may be provided in the dielectric layer of the shallow trench isolation 30 of the silicon substrate 20, and the first hollow metal ring 25 may be provided in the first trench 36.
  • a second trench 39 connected to the first trench 36 is provided in the silicon substrate 20, and the second hollow metal ring 26 is provided in the second trench 39 and connected to the first hollow metal ring 25.
  • the first hollow metal ring 25 is then connected to the annular contact hole 24 in the back dielectric layer 33.
  • the light shielding structure 27 is constituted by the second hollow metal ring 26, the first hollow metal ring 25, and the solid metal rings 22 to 24 that are connected in sequence, and the second cavity 28 and the first hollow metal ring 26 inside the second hollow metal ring 26
  • the first cavity 29 and the shallow groove isolation 30 inside the metal ring 25 constitute a heat shielding structure 31, thereby forming a composite shielding structure that penetrates the silicon substrate 20 and the back dielectric layer 33 up and down.
  • FIG. 5 to FIG. 13 are schematic diagrams of process steps of a method for forming an image sensor structure according to a preferred embodiment of the present invention.
  • an image sensor chip structure forming method of the present invention can be used to fabricate the above-mentioned image sensor chip structure such as Figs. 3 to 4, and may include the following steps:
  • a conventional CMOS image sensor manufacturing process can be used to form a photodiode 21 for light-sensing in a pixel unit array, a control transistor 35, and a pixel unit array on the front surface of the silicon substrate 20 of the device silicon chip.
  • a peripheral circuit transistor 32 in the peripheral circuit is formed on the outside, and a shallow trench isolation 30 surrounding the pixel unit array is formed between the pixel unit array and the peripheral circuit. The shallow trench isolation 30 is used to isolate the pixel unit array and the peripheral circuit.
  • the dielectric layer in the shallow trench isolation 30 is subjected to isotropic dry etching or wet etching, and finally a ring-shaped second with an arc section is formed in the dielectric layer of the shallow trench isolation 30.
  • a groove 36 wherein, by isotropic dry etching or wet etching, the inner opening H of the first trench 36 formed is larger than the opening h at the upper and lower ends of the first trench 36 (similar to a beer barrel-shaped cross-section).
  • metal filling is performed in the first trench 36, that is, the metal of the first hollow metal ring 25 is uniformly deposited on the sidewall of the first trench 36. Since the opening h at the top of the arc-shaped first groove 36 is smaller than the opening H inside the first groove 36, the metal of the first hollow metal ring 25 will be preferentially closed at the opening h at the upper and lower ends of the first groove 36, and in the interior A gap is formed at the opening H, thereby forming a first hollow metal ring 25 inside the first trench 36.
  • the void formed inside the first hollow metal ring 25 constitutes a first cavity 29 for heat shielding.
  • the first cavity 29 is filled with air, which is a poor conductor of heat, which can prevent the propagation of circuit heat from the silicon substrate 20 to the pixel unit array.
  • the metal material of the first hollow metal ring 25 filled in the first trench 36 such as metal tungsten, copper, or aluminum, is opaque, so that the influence of the circuit light emission on the pixel unit can be shielded.
  • the dielectric layer filled in the conventional shallow trench isolation 30 is not a good conductor of heat, since the width of the shallow trench isolation 30 is small, thermal energy can still propagate to the pixel unit array.
  • the thermal resistance of the air is much greater than that of the medium, the influence of the heating of the circuit can be better shielded.
  • a back dielectric layer 33 is formed on the front surface of the silicon substrate 20; using contact hole photolithography, etching and filling processes, and through layout design, a conventional contact hole is formed in the back dielectric layer 33 37 and a ring-shaped contact hole 24 surrounding the pixel unit array.
  • the filling material in the conventional contact hole 37 and the annular contact hole 24 may be metal materials such as metal tungsten.
  • the position of the ring-shaped contact hole 24 is directly opposite to the upper end opening of the first groove 36 below, so the etching process of the ring-shaped contact hole 24 can be stopped on the first hollow metal ring 25 in the first groove 36 to prevent over-engraving. eclipse.
  • the back-channel dielectric layer 33 for example, the two-layer conventional metal interconnection layer 34, conventional through holes 38, and surrounding pixels are formed in the back-channel dielectric layer 33.
  • solid metal rings 22 to 24 are formed by the connected ring-shaped contact holes 24, the ring-shaped metal interconnection layer metal 23, and the ring-shaped through holes 22. Since the back dielectric layer 33 fully covers the silicon substrate 20, its lateral dimension is much larger than the shallow trench isolation 30, so the heat energy cannot be effectively transmitted from the peripheral circuit area to the pixel unit.
  • the purpose of shielding in the back dielectric layer 33 is mainly Prevent the spread of light.
  • the device silicon wafer is turned upside down and then bonded to the carrier wafer.
  • a conventional back-illumination process is used to thin the back surface of the silicon substrate 20.
  • isotropic dry etching or wet etching is performed on the back surface of the thinned silicon substrate 20 to form the first part of the shallow trench isolation 30 in the silicon substrate 20.
  • the inner opening of the second groove 39 formed is larger than the opening at the upper and lower ends.
  • the metal filling of the second hollow metal ring 26 is performed in the second trench 39, that is, the metal of the second hollow metal ring 26 is uniformly deposited on the sidewall of the second trench 39. Since the opening at the top of the arc-shaped second groove 39 is smaller than the opening inside the second groove 39, the second hollow metal ring 26 will preferentially close at the openings at the upper and lower ends of the second groove 39, and form at the inner opening. Therefore, the second hollow metal ring 26 is formed inside the second groove 39.
  • the void formed inside the second hollow metal ring 26 constitutes a second cavity 28 for heat shielding.
  • the second cavity 28 and the first cavity 29 and the shallow groove isolation 30 constitute a heat shielding structure 31; the second hollow metal ring 26, the first hollow metal ring 25, the ring-shaped contact hole 24 and the ring are connected in sequence.
  • the metal interconnection layer metal 23 (including the ring-shaped through hole 22) constitutes the light shielding structure 27; thereby forming a composite shielding structure for light and heat that penetrates the silicon substrate 20 and the back dielectric layer 33 from top to bottom.

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Abstract

本发明公开了一种图像传感器结构和形成方法，图像传感器结构包括：像素单元阵列，位于所述像素单元阵列外围的外围电路，位于所述像素单元阵列与外围电路之间且围绕所述像素单元阵列设置的复合屏蔽结构，所述复合屏蔽结构包括光屏蔽结构和热屏蔽结构；其中，所述光屏蔽结构设有围绕所述像素单元阵列的金属隔离结构，用于对所述外围电路发出的光进行隔离，所述热屏蔽结构包括设于所述金属隔离结构内部的空腔，所述空腔内填充有热隔离介质，用于防止热量向所述像素单元阵列传递。本发明能避免因图像传感器外围电路的发光和发热造成的成像质量劣化和失真问题。

Description

一种图像传感器结构和形成方法
交叉引用
本申请要求2019年11月29日提交的申请号为CN 201911197479.1的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及图像传感器技术领域，特别是涉及一种可防止因电路发光发热对像素单元感光造成影响的图像传感器结构和形成方法。
技术背景
图像传感器是指将光信号转换为电信号的装置，其中大规模商用的图像传感器芯片包括电荷耦合器件(CCD)和互补金属氧化物半导体(CMOS)图像传感器芯片两大类。CMOS图像传感器和传统的CCD传感器相比具有低功耗，低成本和与CMOS工艺兼容等特点，因此得到越来越广泛的应用。现在CMOS图像传感器不仅用于微型数码相机(DSC)，手机摄像头，摄像机和数码单反(DSLR)等消费电子领域，而且在汽车电子，监控，生物技术和医学等领域也得到了广泛的应用。
请参考图1-图2，图1是一种常规CMOS图像传感器芯片的布局示意图，图2是沿图1中A-B位置的截面结构示意图。如图1所示，芯片中央是密集排布的像素单元阵列，像素单元阵列负责将光信号转换为电信号；像素单元阵列四周是各种外围控制和读出电路，包括列级读出电路和行选控制电路等外围电路。在这些外围电路的工作过程中，其可能发生电子和空穴对的复合， 复合过程伴随着光子的产生，也就是电路发光的现象。而发热现象是由于电流通过电路中的导体或半导体时，就会释放一部分的热量，造成芯片温度的升高。这些外围电路的发光和发热的现象会直接影响图像传感器的性能。其中，电路发热的热量会传递到像素单元阵列，造成像素单元暗电流上升；电路的发光会造成像素单元阵列的边缘输出信号的异常增大，造成图像的失真。
如图2所示，由于硅衬底10是热的良导体，而介质层12是热的不良导体，两者之间的热阻有数量级的差距。所以，电路发热产生的热量主要在硅衬底10中传播，最终到达像素单元区域用于实现光电转换的光电二极管11区域，造成像素单元的暗电流上升和性能劣化；而由于硅衬底10和介质层12都可以透光，因此电路发光产生的光子同时通过硅衬底10和介质层12进行传播，最终到达光电二极管11区域，从而造成像素单元阵列区域边缘的光电二极管输出值异常变大和图像失真。
因此，需要提供一种能够防止外围电路发光和发热对像素单元阵列感光造成影响的新技术。
发明概要
本发明的目的在于克服现有技术存在的上述缺陷，提供一种图像传感器结构和形成方法，以防止因图像传感器外围电路的发光和发热造成的成像质量的劣化和失真问题。
为达成上述目的，本发明提供了一种图像传感器结构，包括：像素单元阵列，位于所述像素单元阵列外围的外围电路，位于所述像素单元阵列与外围电路之间且围绕所述像素单元阵列设置的复合屏蔽结构，所述复合屏蔽结 构包括光屏蔽结构和热屏蔽结构；其中，所述光屏蔽结构设有围绕所述像素单元阵列的金属隔离结构，用于对所述外围电路发出的光进行隔离，所述热屏蔽结构包括设于所述金属隔离结构内部的空腔，所述空腔内填充有热隔离介质，用于防止热量向所述像素单元阵列传递。
进一步地，所述像素单元阵列和外围电路设于器件硅片上，所述器件硅片包括硅衬底和设于所述硅衬底正面表面上的后道介质层；所述金属隔离结构包括相连接的空心金属环和实心金属环，所述空心金属环设于所述硅衬底中，且以其空心的内部形成所述空腔，所述实心金属环设于所述后道介质层中。
进一步地，所述像素单元阵列与外围电路之间设有围绕所述像素单元阵列的浅槽隔离，所述空心金属环包括相连接的第一空心金属环和第二空心金属环，所述空腔包括设于所述第一空心金属环的空心内部的第一空腔和设于所述第二空心金属环的空心内部的第二空腔，所述第一空心金属环穿设于所述浅槽隔离中。
进一步地，所述浅槽隔离中设有第一沟槽，所述第一空心金属环设于所述第一沟槽中，所述硅衬底中设有与所述第一沟槽相连的第二沟槽，所述第二空心金属环设于所述第二沟槽中。
进一步地，所述实心金属环包括围绕所述像素单元阵列设置的环状接触孔和环状一至多层金属互连层金属。
进一步地，环状所述多层金属互连层金属之间通过环状通孔相连接。
进一步地，所述热隔离介质包括空气、氮气或氦气。
进一步地，所述像素单元阵列包括：设于所述硅衬底正面上的光电二极管和控制晶体管，设于所述后道介质层中的像素单元金属互连层；所述外围电路包括：设于所述硅衬底正面上的外围电路晶体管，设于所述后道介质层中的外围电路金属互连层。
进一步地，所述外围电路包括列级读出电路和行选控制电路。
为达成上述目的，本发明提供了一种图像传感器结构形成方法，包括以下步骤：
提供一具有硅衬底的器件硅片，在所述硅衬底正面上形成像素单元阵列中用于感光的光电二极管，控制晶体管，在像素单元阵列外侧形成外围电路中的外围电路晶体管，以及在像素单元阵列与外围电路之间形成围绕所述像素单元阵列的浅槽隔离；
对浅槽隔离中的介质层进行各向同性的干法刻蚀或湿法腐蚀，在浅槽隔离的介质层中形成具有弧形截面的环状第一沟槽；其中，形成的第一沟槽的内部开口大于其上下两端的开口；
在第一沟槽的侧壁上进行第一空心金属环金属的淀积，使第一空心金属环金属在第一沟槽上下两端的开口处优先合拢，从而在第一沟槽的内部形成第一空心金属环及位于第一空心金属环内部的第一空腔；
在所述硅衬底正面上形成后道介质层，在所述后道介质层中形成常规接触孔和一至多层常规金属互连层；其中，在形成常规接触孔和常规金属互连层的同时，通过版图设计，在像素单元阵列和外围电路之间形成围绕像素单元阵列的环状接触孔和一至多层环状金属互连层金属，形成实心金属环；
提供一载片，将器件硅片倒置后与所述载片进行键合；
对所述硅衬底的背面进行减薄；
在减薄后的所述硅衬底背面上进行各向同性的干法刻蚀或湿法腐蚀，在所述硅衬底中形成与环状第一空心金属环相连的具有弧形截面的环状第二沟槽；其中，形成的第二沟槽的内部开口大于其上下两端的开口；
在第二沟槽的侧壁上进行第二空心金属环金属的淀积，使第二空心金属环金属在第二沟槽上下两端的开口处优先合拢，从而在第二沟槽的内部形成第二空心金属环及位于第二空心金属环内部的第二空腔，形成由依次相连的所述第二空心金属环及其内部第二空腔、所述第一空心金属环及其内部第一空腔、所述实心金属环构成的针对光和热量的复合屏蔽结构。
本发明的优点在于，本发明通过在硅衬底和后道介质层中形成从上至下贯通的复合屏蔽结构，可以有效屏蔽外围电路的发光和发热向像素单元阵列的传播。其中，位于硅衬底和浅槽隔离中的空心金属环，以及位于后道介质层中的实心金属环，可以有效屏蔽电路发光的传播；而利用空心金属环具有的空腔以及浅槽隔离中的介质层材料所组成的复合结构，可以有效阻挡电路发热的传播，从而能够有效防止电路发光和发热对像素单元区域的影响。
附图说明
图1是一种常规CMOS图像传感器芯片的布局示意图。
图2是沿图1中A-B位置的截面结构示意图。
图3是本发明一较佳实施例的一种图像传感器芯片的布局示意图。
图4是沿图3中C-D位置的截面结构示意图。
图5-图13是本发明一较佳实施例的一种图像传感器结构形成方法工艺步骤示意图。
发明内容
以下将结合说明书附图对本发明的内容作进一步的详细描述。应理解的是本发明能够在不同的示例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上当作说明之用，而非用以限制本发明。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。
在以下本发明的具体实施方式中，请参考图3-图4，图3是本发明一较佳实施例的一种图像传感器芯片的布局示意图，图4是沿图3中C-D位置的 截面结构示意图。如图3-图4所示，本发明的一种图像传感器结构，可建立在上下键合的器件硅片和载片上。图像传感器芯片结构包括像素单元区域和围绕在像素单元区域四周的外围电路区域。其中，像素单元区域设有像素单元阵列，外围电路区域设有列级读出电路和行选控制电路等外围电路。
请参考图4。像素单元阵列和外围电路设于器件硅片上；器件硅片包括硅衬底20和设于硅衬底20正面表面上的后道介质层33。载片与后道介质层33表面进行键合。
像素单元区域(像素单元阵列)与外围电路区域(外围电路)之间通过浅槽隔离30结构进行隔离。浅槽隔离30设于硅衬底20上，并围绕像素单元阵列形成环状。
像素单元阵列可包括设于硅衬底20正面上的光电二极管21和控制晶体管35。外围电路可包括设于硅衬底20正面上的外围电路晶体管32。后道介质层33中设有金属互连层34，其包括像素单元金属互连层和外围电路金属互连层。
请参考图3-图4。像素单元阵列的外侧围绕设有环状的复合屏蔽结构；复合屏蔽结构的外侧围绕设有外围电路。
复合屏蔽结构包括光屏蔽结构27和热屏蔽结构31。其中，光屏蔽结构27设有围绕像素单元阵列的金属隔离结构22至26；金属隔离结构22至26用于对外围电路发出的光进行隔离。
根据设计特点及屏蔽需求，金属隔离结构22至26可以采用连续或不连续的平面环状形式围绕在像素单元阵列的四周。
热屏蔽结构31包括设于金属隔离结构22至26内部的空腔28、29；空腔28、29内填充有热隔离介质，用于防止热量向像素单元阵列传递。
热隔离介质可包括空气、氮气或氦气等热的不良导体；也可以采用其他适用的气体或固体介质。
请参考图4。金属隔离结构22至26包括相连接的空心金属环25至26和实心金属环22至24。其中，空心金属环25至26设于硅衬底20中，且以 空心金属环25至26空心的内部来形成热屏蔽结构31的空腔28、29。
进一步地，空心金属环25至26可包括相连接的第一空心金属环25和第二空心金属环26。相应地，空腔28、29也包括设于第一空心金属环25的空心内部的第一空腔29和设于第二空心金属环26的空心内部的第二空腔28。其中，第一空心金属环25穿设于浅槽隔离30的介质层中。
实心金属环22至24设于后道介质层33中。实心金属环22至24可利用制作金属互连层34的相关金属来形成，例如，实心金属环22至24可包括围绕像素单元阵列设置的环状接触孔24(可在制作常规接触孔37的同时形成)和环状一至多层金属互连层金属23，例如图示的两层环状金属互连层金属23(可在制作常规金属互连层34的同时形成)，以及用于连接两层环状金属互连层金属23的环状通孔22(可在制作常规通孔38的同时形成)。
请参考图4。作为一可选的实施方式，可在硅衬底20的浅槽隔离30的介质层中设置第一沟槽36，将第一空心金属环25设于第一沟槽36中。同时，在硅衬底20中设置与第一沟槽36相连的第二沟槽39，将第二空心金属环26设于第二沟槽39中，并与第一空心金属环25相连接。第一空心金属环25再与后道介质层33中的环状接触孔24相连接。
这样，由依次连接的第二空心金属环26、第一空心金属环25和实心金属环22至24构成光屏蔽结构27，由第二空心金属环26内部的第二空腔28、第一空心金属环25内部的第一空腔29和浅槽隔离30构成热屏蔽结构31，从而形成上下贯通硅衬底20和后道介质层33的复合屏蔽结构。
下面通过具体实施方式并结合附图，对本发明的一种图像传感器结构形成方法进行详细说明。
请参考图5-图13，图5-图13是本发明一较佳实施例的一种图像传感器结构形成方法工艺步骤示意图。如图5-图13所示，本发明的一种图像传感器芯片结构形成方法，可用于制作上述例如图3-图4的图像传感器芯片结构，并可包括以下步骤：
首先，如图5所示，可使用常规的CMOS图像传感器制造工艺，在器件硅片的硅衬底20正面上形成像素单元阵列中用于感光的光电二极管21，控制晶体管35，在像素单元阵列外侧形成外围电路中的外围电路晶体管32，并在像素单元阵列与外围电路之间形成围绕像素单元阵列的浅槽隔离30，浅槽隔离30用于隔离像素单元阵列和外围电路。
接着，如图6所示，对浅槽隔离30中的介质层进行各向同性的干法刻蚀或湿法腐蚀，最终在浅槽隔离30的介质层中形成具有弧形截面的环状第一沟槽36。其中，通过各向同性的干法刻蚀或湿法腐蚀，使形成的第一沟槽36的内部开口H大于第一沟槽36上下两端的开口h(类似啤酒桶形截面)。
随后，如图7所示，在第一沟槽36内进行金属填充，即在第一沟槽36的侧壁上进行第一空心金属环25金属的均匀淀积。由于弧形第一沟槽36顶部的开口h小于第一沟槽36内部的开口H，因而第一空心金属环25金属会在第一沟槽36上下两端的开口h处优先合拢，而在内部开口H处形成空隙，从而在第一沟槽36的内部形成第一空心金属环25。由第一空心金属环25内部形成的空隙，构成用于热屏蔽的第一空腔29。此时，第一空腔29中填充的是空气，空气是热的不良导体，可以防止电路发热从硅衬底20向像素单元阵列的传播。同时，第一沟槽36内填充的第一空心金属环25金属材料，例如金属钨、铜或铝等是不透光的，因此可以屏蔽电路发光对像素单元的影响。虽然常规浅槽隔离30中填充的介质层并非热的良导体，但由于浅槽隔离30的宽度较小，热能还是能够向像素单元阵列传播。通过在浅槽隔离30中形成空腔隔离结构，由于空气的热阻远大于介质，可以更好地屏蔽电路发热的影响。
接着，如图8所示，在硅衬底20正面上形成后道介质层33；使用接触孔光刻、刻蚀和填充工艺，并通过版图设计，在后道介质层33中形成常规接触孔37和围绕像素单元阵列的环状接触孔24。常规接触孔37和环状接触孔24中的填充材料可采用金属钨等金属材料。其中环状接触孔24位置正对着下方第一沟槽36的上端开口，因此环状接触孔24刻蚀过程可以停止在第 一沟槽36中的第一空心金属环25上，防止过刻蚀。
再次，如图9所示，使用后道金属互连工艺，并通过版图设计，在后道介质层33中形成例如图示的二层常规金属互连层34、常规通孔38，和围绕像素单元阵列的环状通孔22和二层环状金属互连层金属23。其中，由相连接的环状接触孔24、环状金属互连层金属23及环状通孔22形成实心金属环22至24。后道介质层33由于是全面覆盖硅衬底20，其横向尺寸远大于浅槽隔离30，因此热能无法有效从外围电路区域传播到像素单元，在后道介质层33中进行屏蔽的目的主要是防止光的传播。
随后，如图10所示，将器件硅片倒置后与载片进行键合。
然后，如图11所示，使用常规的背照工艺，对硅衬底20的背面进行减薄。
再次，如图12所示，在减薄后的硅衬底20背面上进行各向同性的干法刻蚀或湿法腐蚀，以在硅衬底20中形成与浅槽隔离30中的第一沟槽36上下对准的环状第二沟槽39。同样地，形成的第二沟槽39的内部开口大于其上下两端的开口。
随后，如图13所示，在第二沟槽39内进行第二空心金属环26金属填充，即在第二沟槽39的侧壁上进行第二空心金属环26金属的均匀淀积。由于弧形第二沟槽39顶部的开口小于第二沟槽39内部的开口，因而第二空心金属环26金属会在第二沟槽39上下两端的开口处优先合拢，而在内部开口处形成空隙，从而在第二沟槽39的内部形成第二空心金属环26。由第二空心金属环26内部形成的空隙，构成用于热屏蔽的第二空腔28。
这样，由第二空腔28和第一空腔29及浅槽隔离30构成热屏蔽结构31；由依次相连的第二空心金属环26、第一空心金属环25、环状接触孔24和环状金属互连层金属23(包括环状通孔22)构成光屏蔽结构27；从而形成从上至下贯通硅衬底20和后道介质层33中的针对光和热量的复合屏蔽结构。
以上所述的仅为本发明的实施例，所述实施例并非用以限制本发明专利 保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

  1. 一种图像传感器结构，其特征在于，包括：像素单元阵列，位于所述像素单元阵列外围的外围电路，位于所述像素单元阵列与外围电路之间且围绕所述像素单元阵列设置的复合屏蔽结构，所述复合屏蔽结构包括光屏蔽结构和热屏蔽结构；其中，所述光屏蔽结构设有围绕所述像素单元阵列的金属隔离结构，用于对所述外围电路发出的光进行隔离，所述热屏蔽结构包括设于所述金属隔离结构内部的空腔，所述空腔内填充有热隔离介质，用于防止热量向所述像素单元阵列传递。
  2. 根据权利要求1所述的图像传感器结构，其特征在于，所述像素单元阵列和外围电路设于器件硅片上，所述器件硅片包括硅衬底和设于所述硅衬底正面表面上的后道介质层；所述金属隔离结构包括相连接的空心金属环和实心金属环，所述空心金属环设于所述硅衬底中，且以其空心的内部形成所述空腔，所述实心金属环设于所述后道介质层中。
  3. 根据权利要求2所述的图像传感器结构，其特征在于，所述像素单元阵列与外围电路之间设有围绕所述像素单元阵列的浅槽隔离，所述空心金属环包括相连接的第一空心金属环和第二空心金属环，所述空腔包括设于所述第一空心金属环的空心内部的第一空腔和设于所述第二空心金属环的空心内部的第二空腔，所述第一空心金属环穿设于所述浅槽隔离中。
  4. 根据权利要求3所述的图像传感器结构，其特征在于，所述浅槽隔离中设有第一沟槽，所述第一空心金属环设于所述第一沟槽中，所述硅衬底中设有与所述第一沟槽相连的第二沟槽，所述第二空心金属环设于所述第二沟槽中。
  5. 根据权利要求2所述的图像传感器结构，其特征在于，所述实心金属环包括围绕所述像素单元阵列设置的环状接触孔和环状一至多层金属互连层金属。
  6. 根据权利要求5所述的图像传感器结构，其特征在于，环状所述多层金属互连层金属之间通过环状通孔相连接。
  7. 根据权利要求1所述的图像传感器结构，其特征在于，所述热隔离介质包括空气、氮气或氦气。
  8. 根据权利要求2所述的图像传感器结构，其特征在于，所述像素单元阵列包括：设于所述硅衬底正面上的光电二极管和控制晶体管，设于所述后道介质层中的像素单元金属互连层；所述外围电路包括：设于所述硅衬底正面上的外围电路晶体管，设于所述后道介质层中的外围电路金属互连层。
  9. 根据权利要求1所述的图像传感器结构，其特征在于，所述外围电路包括列级读出电路和行选控制电路。
  10. 一种图像传感器结构形成方法，其特征在于，包括以下步骤：
    提供一具有硅衬底的器件硅片，在所述硅衬底正面上形成像素单元阵列中用于感光的光电二极管，控制晶体管，在像素单元阵列外侧形成外围电路中的外围电路晶体管，以及在像素单元阵列与外围电路之间形成围绕所述像素单元阵列的浅槽隔离；
    对浅槽隔离中的介质层进行各向同性的干法刻蚀或湿法腐蚀，在浅槽隔离的介质层中形成具有弧形截面的环状第一沟槽；其中，形成的第一沟槽的内部开口大于其上下两端的开口；
    在第一沟槽的侧壁上进行第一空心金属环金属的淀积，使第一空心金属环金属在第一沟槽上下两端的开口处优先合拢，从而在第一沟槽的内部形成第一空心金属环及位于第一空心金属环内部的第一空腔；
    在所述硅衬底正面上形成后道介质层，在所述后道介质层中形成常规接触孔和一至多层常规金属互连层；其中，在形成常规接触孔和常规金属互连层的同时，通过版图设计，在像素单元阵列和外围电路之间形成围绕像素单元阵列的环状接触孔和一至多层环状金属互连层金属，形成实心金属环；
    提供一载片，将器件硅片倒置后与所述载片进行键合；
    对所述硅衬底的背面进行减薄；
    在减薄后的所述硅衬底背面上进行各向同性的干法刻蚀或湿法腐蚀，在所述硅衬底中形成与环状第一空心金属环相连的具有弧形截面的环状第二沟槽；其中，形成的第二沟槽的内部开口大于其上下两端的开口；
    在第二沟槽的侧壁上进行第二空心金属环金属的淀积，使第二空心金属环金属在第二沟槽上下两端的开口处优先合拢，从而在第二沟槽的内部形成第二空心金属环及位于第二空心金属环内部的第二空腔，形成由依次相连的所述第二空心金属环及其内部第二空腔、所述第一空心金属环及其内部第一空腔、所述实心金属环构成的针对光和热量的复合屏蔽结构。
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