WO2021103012A1 - 阵列基板及其制备方法、像素驱动方法、显示面板 - Google Patents

阵列基板及其制备方法、像素驱动方法、显示面板 Download PDF

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Publication number
WO2021103012A1
WO2021103012A1 PCT/CN2019/122203 CN2019122203W WO2021103012A1 WO 2021103012 A1 WO2021103012 A1 WO 2021103012A1 CN 2019122203 W CN2019122203 W CN 2019122203W WO 2021103012 A1 WO2021103012 A1 WO 2021103012A1
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WIPO (PCT)
Prior art keywords
shift register
array substrate
register circuits
register circuit
scan signal
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PCT/CN2019/122203
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English (en)
French (fr)
Inventor
刘冬妮
玄明花
曲峰
齐琪
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980002734.4A priority Critical patent/CN113196371A/zh
Priority to PCT/CN2019/122203 priority patent/WO2021103012A1/zh
Priority to US16/976,530 priority patent/US11876100B2/en
Publication of WO2021103012A1 publication Critical patent/WO2021103012A1/zh
Priority to US18/525,835 priority patent/US20240105736A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/38—Digital stores in which the information is moved stepwise, e.g. shift registers two-dimensional, e.g. horizontal and vertical shift registers

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method, a pixel driving method, and a display panel.
  • the display screens are required to have a narrower frame and better display brightness uniformity.
  • an array substrate including: a base substrate, a plurality of scan signal lines arranged on the first surface, and at least two sets of shift register circuits arranged in the display area of the first surface.
  • the base substrate includes a first surface, and the first surface has a display area; each of the plurality of scanning signal lines extends along a first direction; the at least two sets of shift register circuits
  • Each group of shift register circuits in includes a plurality of shift register circuits arranged along the second direction, and each shift register circuit in the plurality of shift register circuits is coupled to one of the scanning signal lines; wherein, The first direction intersects the second direction; wherein at least one set of shift register circuits are arranged in the non-edge area of the display area; the shift register circuits arranged in the non-edge area of the display area are It is configured to transmit the scanning signal to the scanning signal lines on both sides of the scanning signal line along the first direction.
  • the spacing between each adjacent two sets of shift register circuits is equal.
  • the at least two sets of shift register circuits are all arranged at non-edge positions of the display area.
  • the two sets of shift register circuits located on the outermost side along the first direction The distance from the edge of the display area closest to it is half of the distance between each adjacent two sets of shift register circuits.
  • the number of groups of the shift register circuit is 3 to 5 groups.
  • the array substrate includes a plurality of sub-pixels arranged in a matrix, and each group of shift register circuits is disposed in a gap area between two adjacent columns of sub-pixels.
  • the scan signal line includes a gate scan signal line
  • the shift register circuit includes a gate shift register circuit
  • the gate shift register circuit is coupled to the gate scan signal line
  • the scan signal line includes a light-emitting scan signal line
  • the shift register circuit includes a light-emitting shift register circuit
  • the light-emitting shift register circuit is coupled to the light-emitting scan signal line.
  • the gate shift register circuit is configured to transmit a gate scan signal to the gate scan signal line
  • the light-emitting shift register circuit is configured to transmit a light-emitting scan signal to the light-emitting scan signal line.
  • the base substrate further includes a second surface opposite to the first surface.
  • the array substrate further includes: at least one fan-out structure disposed on the second surface.
  • Each fan-out structure in the at least one fan-out structure includes a plurality of signal connection lines, and each signal connection line of the plurality of signal connection lines extends from the edge of the second surface to the second surface The non-edge area extends; the signal connection line is coupled to the shift register circuit.
  • the array substrate further includes a plurality of control signal lines arranged on the first surface and extending along the second direction.
  • Each shift register circuit in each group of shift register circuits is coupled to at least one control signal line of the plurality of control signal lines.
  • One end of the signal connection line close to the edge of the second surface is coupled to one of the at least one control signal line.
  • the control signal line is configured to transmit a control signal to the shift register circuit, so that the shift register circuit outputs the scan signal under the control of the control signal.
  • the array substrate further includes: at least one side structure disposed on the side surface of the base substrate between the first surface and the second surface.
  • the at least one side structure corresponds to the at least one fan-out structure in a one-to-one correspondence.
  • Each side structure of the at least one side structure includes a plurality of side connections, one end of each side connection of the plurality of side connections is coupled to the signal connection line, and the other One end is coupled with the control signal line.
  • the number of the fan-out structure and the side structure is 1 to 4.
  • a display panel including: the array substrate according to any one of the above-mentioned embodiments; and a control chip coupled with the array substrate.
  • the control chip is configured to transmit a control signal to a shift register circuit of the array substrate, so that the shift register circuit outputs a scanning signal under the control of the control signal.
  • control chip is disposed on the second surface of the base substrate of the array substrate; the second surface is opposite to the first surface of the base substrate.
  • the control chip includes a control chip main body and a plurality of first pins; wherein the control chip main body is configured to transmit the control signal to the plurality of first pins.
  • the plurality of first pins are bound to a plurality of signal connection lines of the at least one fan-out structure.
  • the display panel further includes a plurality of second pins disposed on the second surface of the base substrate of the array substrate; the second surface is connected to the first surface of the base substrate relatively.
  • the plurality of second pins are coupled to the control chip.
  • the plurality of second pins are bound to a plurality of signal connection lines of the at least one fan-out structure.
  • a pixel driving method is provided, which is applied to the display panel according to any one of the above-mentioned embodiments.
  • the pixel driving method includes: the control chip of the display panel sends a control signal to each group of shift register circuits in at least two groups of shift register circuits of the array substrate of the display panel; each group of shift register circuits Each of the shift register circuits in receives the control signal, and transmits a scan signal to the scan signal line to which it is coupled along the first direction.
  • a method for preparing an array substrate including: providing a base substrate; the base substrate includes a first surface, and the first surface has a display area. A plurality of scanning signal lines are formed on the first surface; each of the plurality of scanning signal lines extends along the first direction. At least two sets of shift register circuits are formed in the display area of the first surface; each set of shift register circuits in the at least two sets of shift register circuits includes a plurality of shift register circuits arranged along the second direction, Each of the plurality of shift registers is coupled to one of the scanning signal lines. Wherein, the first direction crosses the second direction.
  • At least one set of the shift register circuit is arranged in the non-edge area of the display area; the shift register circuit arranged in the non-edge area of the display area is configured to be along the first direction, The scanning signal is transmitted to the scanning signal lines on both sides thereof.
  • the base substrate further includes a second surface opposite to the first surface.
  • the preparation method further includes: forming at least one fan-out structure on the second surface.
  • Each fan-out structure in the at least one fan-out structure includes a plurality of signal connection lines, and each signal connection line of the plurality of signal connection lines extends from the edge of the second surface to the second surface The non-edge area extends; the signal connection line is coupled to the shift register circuit.
  • the preparation method further includes: forming at least one side structure on the side surface of the base substrate located between the first surface and the second surface.
  • the at least one side structure corresponds to the at least one fan-out structure one-to-one; each side structure in the at least one side structure includes a plurality of side connecting lines, and among the plurality of side connecting lines One end of each of the side wires is coupled to the signal connection line, and the other end is coupled to the shift register circuit.
  • FIG. 1 is a top view of an array substrate provided according to the related art
  • FIG. 2 is a timing diagram of scan signals of a shift register circuit in an array substrate provided according to the related art
  • FIG. 3 is a top view of a first surface of an array substrate according to some embodiments of the present disclosure
  • FIG. 4 is a top view of the first surface of another array substrate according to some embodiments of the present disclosure.
  • FIG. 5 is a top view of the first surface of another array substrate according to some embodiments of the present disclosure.
  • Fig. 6 is a top view of a second surface of an array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is a top view of the second surface of another array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a partial cross-sectional view of the array substrate in FIG. 3 at QQ;
  • FIG. 9 is another partial cross-sectional view of the array substrate in FIG. 3 at QQ;
  • Fig. 10a is a top view of a first surface of a display panel in some embodiments of the present disclosure
  • Fig. 10b is a top view of a second surface of a display panel in some embodiments of the present disclosure.
  • FIG. 11 is a top view of the second surface of another display panel in some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • up, down, “left”, “right”, etc. are only used to indicate the corresponding positional relationship. When the absolute position of the object being described changes, the relative positional relationship also changes accordingly.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • the array substrate 1' includes a base substrate 10', the base substrate 10' includes a first surface S1', and the first surface S1' has a display area AA' and a non-display area BB. '.
  • the display area AA' a plurality of scanning signal lines G'are provided, and each of the plurality of scanning signal lines G'extends along the first direction.
  • the non-display area BB' located on the left or right side of the array substrate 1'along the first direction (the left side is taken as a schematic diagram in FIG.
  • a set of shift register circuits is provided, and the set of shift registers
  • the circuit includes a plurality of shift register circuits SR' arranged along the second direction, and each shift register circuit SR' of the plurality of shift register circuits SR' is coupled to a scanning signal line G'.
  • each shift register circuit SR' is configured to transmit a scan signal to the scan signal line G'on one side of the shift register circuit SR' along the first direction.
  • the first direction crosses the second direction.
  • the first direction F1 is the row direction in which the plurality of sub-pixels are arranged
  • the second direction F2 is the column direction in which the plurality of sub-pixels are arranged
  • the first direction and the second direction Perpendicular to each other.
  • the shift register SR' inputs the scan signal to the scan signal line G', the data signal on the data signal line D'along the second direction is written into the driving circuit of the sub-pixel of the corresponding row, and the threshold voltage is compensated.
  • the shift register circuit SR' includes a gate shift register circuit.
  • the shift The scan signal transmitted by the register circuit SR′ includes a gate scan signal (Gate), where the gate scan signal (Gate) is used to scan the gate scan signal line row by row to turn on the sub-pixels in the corresponding row.
  • the shift register circuit SR' includes a light-emitting shift register circuit, that is, the scan transmitted by the shift register circuit SR'
  • the signal includes a luminescence scan signal (EM), where the luminescence scan signal (EM) is used to scan the luminescence signal line row by row, so that the sub-pixels in the corresponding row emit light.
  • EM luminescence scan signal
  • the scan signal at the end of the scan signal line G'(that is, the end of the scan signal line G'far away from the shift register circuit) will be The scan signal is weaker than the start end of the scan signal line G'(that is, the end of the scan signal line G'close to the shift register circuit), and due to the existence of RC loading on the scan signal line G', the scan on the scan signal line G'
  • the signal has a delay phenomenon, resulting in insufficient charging time in the sub-pixels connected to the end of the scanning signal line G'on the array substrate 1'far from the shift register circuit SR', and the writing time of the data signal (Date) is equal to The compensation time of the threshold voltage (Vth) is insufficient, resulting in uneven display.
  • the RC loading at the end of the scan signal line G' is the largest, that is, the RC loading of the scan signal line G'
  • the RC loading at the end can be denoted as RC loading max, where the value of RC loading max is a'.
  • Figures 1 and 2 where Figure 2 uses two gate scanning signals Gate (Gate(0) and Gate(1)) and two luminous scanning signals EM (EM(0) and EM( 1)) Take an example for illustration.
  • a set of shift register circuits are arranged on the array substrate 1', and the RC loading max on each scanning signal line G'is a'.
  • the RC loading on each scanning signal line is larger, that is, the RC loading max on each scanning signal line G'is larger, so that the rise time and fall time of the scanning signal on the scanning signal line G'increase.
  • the rise time of the scan signal includes the rise time of the gate scan signal (tr-G) and the rise time of the light-emitting scan signal (tr-E), and the fall time of the scan signal includes the fall time of the gate scan signal (tf-G) and the light-emitting scan signal Rise time (tf-E).
  • the gate scan signal is configured to turn on a row of sub-pixels electrically connected to the scan signal line G', so that the data signal line D'writes a data signal (Date) to the corresponding sub-pixel.
  • 1H is the time when the data signal (Date) is written into a row of sub-pixels
  • the array substrate 1 includes: a base substrate 10, a plurality of scanning signal lines G arranged on the first surface S1, and At least two sets of shift register circuits in the display area AA of S1.
  • the base substrate 10 includes a first surface S1, the first surface S1 has a display area AA; each scan signal line G of the plurality of scan signal lines G extends along a first direction;
  • Each group of shift register circuits includes a plurality of shift register circuits SR arranged along the second direction, and each shift register circuit SR of the plurality of shift register circuits SR is coupled to a scanning signal line G.
  • FIG. 3 only uses three groups of shift register circuits for illustration. Some embodiments of the present disclosure do not limit the number of groups of shift register circuits, and the number of groups of shift register circuits is limited to at least two groups.
  • the number of shift register circuits in each group of shift register circuits in at least two groups of shift register circuits is the same.
  • the number of shift registers SR to which each of the plurality of scan signal lines G is coupled is the same as the number of groups of shift register circuits SR in the display area AA.
  • the same scan signal line G is coupled to at least two shift register circuits SR, wherein the at least two shift register circuits SR are from different groups of at least two groups of shift register circuits.
  • the first direction intersects the second direction.
  • the first direction F1 is the row direction or the horizontal direction in which the plurality of sub-pixels are arranged
  • the second direction F2 is the column direction or the column direction in which the plurality of sub-pixels are arranged.
  • the first direction and the second direction are perpendicular to each other.
  • At least one set of shift register circuits is disposed in the non-edge area of the display area AA.
  • the display area AA of the array substrate 1 has two sets of shift register circuits, one of which is set in the non-edge area of the display area AA, and the other set is located in the edge area of the display area AA.
  • the display area AA of the array substrate 1 has three sets of shift register circuits, one of which is arranged in the non-edge area of the display area AA, and the other two are arranged in the edge area of the display area AA; or, two of them are arranged In the non-edge area of the display area AA, another group is set in the edge area of the display area AA.
  • Some embodiments of the present disclosure do not limit the number of groups of at least two sets of shift register circuits arranged in the non-edge area of the display area AA, and is limited to having at least one set of shift register circuits arranged in the non-edge area of the display area AA.
  • the shift register circuit SR provided in the non-edge area of the display area AA is configured to transmit the scan signal to the scan signal lines G on both sides of the shift register circuit along the first direction.
  • the non-edge area of the display area AA is an area within the display area AA, and the non-edge area of the display area AA is opposite to the edge area of the display area AA.
  • the shift register circuit arranged in the edge area of the display area AA can only transmit the scanning signal to the scanning signal line G on one side of the shift register circuit along the first direction.
  • the shift register circuit arranged in the non-edge area of the display area AA can transmit scanning signals to the scanning signal lines G on both sides of the shift register circuit along the first direction; alternatively, it can also selectively transmit scanning signals to the scanning signal lines on one side of the shift register circuit. G transmits the scan signal.
  • the array substrate 1 may be applied to a liquid crystal display panel (Liquid Crystal Display, LCD), an organic light emitting diode (Organic Light-Emitting Diode, OLED) display panel, and a micro light emitting diode (Micro Light-Emitting Diode, Micro-LED) display panel. Or Mini Light Emitting Diode (Mini-LED) display panel, etc.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • Micro-LED micro light emitting diode
  • Mini-LED Mini Light Emitting Diode
  • the scan signal line G includes a gate scan signal line G1
  • the shift register circuit SR includes a gate shift register circuit SR1.
  • the gate shift register circuit SR1 is coupled to the gate scan signal line G1, wherein the gate shift register circuit SR1 is configured to transmit a gate scan signal (Gate) to the gate scan signal line G1.
  • the scan signal line G includes a light-emitting scan signal line G2
  • the shift register circuit SR includes a light-emitting shift register circuit SR2.
  • the light-emitting shift register circuit SR2 is coupled to the light-emitting scan signal line G2, wherein the light-emitting shift register circuit SR2 is configured to transmit a light-emitting scan signal (EM) to the light-emitting scan signal line G2.
  • EM light-emitting scan signal
  • the scan signal line G includes a gate scan signal line G1 and a light-emitting scan signal line G2, and the shift register circuit includes a gate shift register circuit SR1 and a light-emitting shift register circuit SR2.
  • the gate shift register circuit SR1 is coupled to the gate scanning signal line G1, and the light-emitting shift register circuit SR2 is coupled to the light-emitting scanning signal line G2.
  • the gate shift register circuit SR1 is configured to transmit a gate scan signal (Gate) to the gate scan signal line G1
  • the light-emitting shift register circuit SR2 is configured to transmit a light-emitting scan signal (EM) to the light-emitting scan signal line G2.
  • the gate shift register circuit SR1 and the light-emitting shift register circuit SR2 are separately arranged at intervals; another example is shown in Figure 5 ( Take three sets of shift register circuits for illustration), the gate shift register circuit SR1 and the light-emitting shift register circuit SR2 are integrated in the same shift register circuit SR, that is, the shift register circuit and the gate scanning signal line G1 is coupled to the light-emitting scan signal line G2, and the shift register circuit SR is configured to transmit a gate scan signal (Gate) to the gate scan signal line G1 and transmit a light-emitting scan signal (EM) to the light-emitting scan signal line G2.
  • Gate gate scan signal
  • EM light-emitting scan signal
  • the spacing s between each adjacent two sets of shift register circuits is equal. In this way, the RC loading distribution on each scan signal line G can be made more uniform.
  • the spacing between each adjacent two sets of shift register circuits may also be unequal. Some embodiments of the present disclosure determine whether the spacing between each adjacent two sets of shift register circuits is equal. It is not limited, and it is limited to provide at least two sets of shift register circuits in the display area AA.
  • At least two sets of shift register circuits are all disposed at non-edge positions of the display area AA.
  • the at least two sets of shift register circuits are all arranged at non-edge positions of the display area AA, and the spacing between each adjacent two sets of shift register circuits is equal.
  • the at least two groups of shift register circuits are all arranged at non-edge positions of the display area AA, and the spacing between each adjacent two groups of shift register circuits is not equal.
  • the two sets of shift register circuits located on the outermost side are at the edge of the display area AA closest to it.
  • the distance m is half of the distance s between each adjacent two sets of shift register circuits.
  • the width of the display area of the array substrate 1 in the first direction is w, and n sets of shift register circuits are provided on the array substrate 1, where n ⁇ 2.
  • the distance between the two sets of shift register circuits located on the outermost side and the edge of the display area AA closest to it is m, where,
  • the value of RC loading max on each scanning signal line G in the plurality of scanning signal lines G is a, where, when the size and resolution of the array substrate 1 and the array substrate 1'are the same,
  • the RC loading max on each scan signal line G is effectively reduced, that is, the RC loading on each scan signal line G is effectively reduced, and the rise time of the scan signal (tr-G and tr-E) and fall time (tf-G and tf-E), it is also possible to avoid reducing the writing time of the data signal (Date) and the threshold voltage (Vth) compensation time, thereby ensuring the uniformity of display brightness.
  • the rise time of the scan signal includes the rise time of the gate scan signal (tr-G) and the rise time of the light-emitting scan signal (tr-E), and the fall time of the scan signal includes the fall time of the gate scan signal ( tf-G) and the rising time of the luminous scanning signal (tf-E).
  • the description is given by taking the number of groups of the shift register circuit as three groups as an example.
  • the value of RC loading max on the scan signal line on the array substrate 1 is one-sixth of the value of RC loading max on the scan signal line on the array substrate 1'.
  • the RC loading on each scan signal line G is effectively reduced, thereby reducing the rise time (tr-G and tr-E) and fall time (tf-G and tf-E) of the scan signal, so that you can Avoid reducing the writing time of the data signal (Date) and the threshold voltage (Vth) compensation time, thereby ensuring the uniformity of the display brightness.
  • the number of groups of shift register circuits SR provided on the array substrate 1 is related to the size of the array substrate 1 and the display resolution. For example, the larger the size of the array substrate or the higher the display resolution, the more groups of shift register circuits are provided, so as to ensure that the RC loading on each scan signal line G is small, thereby ensuring the uniformity of display brightness.
  • the number of groups of shift register circuits can be set to 3 to 5 groups.
  • the pixel current of the LCD or OLED display panel is tens of nA
  • the pixel current of the Micro-LED display panel or Mini-LED display panel is tens of uA
  • the Micro-LED display panel or Mini-LED display The pixel current required by the panel is about 1000 times the pixel current required by the LCD or OLED display panel.
  • the array substrate 1 in some of the above embodiments can effectively reduce the RC loading on each scan signal line G, it can avoid the increase in RC loading and the scan signal caused by increasing the width-to-length ratio (W/L) of the thin film transistor.
  • the rise time (tr-G and tr-E) and fall time (tf-G and tf-E) increase, which can avoid reducing the writing time of the data signal (Date) and the threshold voltage (Vth) compensation time, so It can better ensure the uniformity of the display brightness of the Micro-LED display panel or Mini-LED display panel.
  • the array substrate 1 includes a plurality of sub-pixels arranged in a matrix, and each group of shift register circuits is disposed in a gap area between two adjacent columns of sub-pixels. In this way, the shift register circuit SR does not occupy an area other than the display area AA, which is beneficial to the array substrate 1 to realize a narrow border display or a borderless display.
  • the base substrate 10 further includes a second surface S2 opposite to the first surface S1.
  • the array substrate 1 further includes at least one fan-out structure 12 disposed on the second surface S2.
  • each fan-out structure 12 in the at least one fan-out structure 12 includes a plurality of signal connection lines L, and each signal connection line L of the plurality of signal connection lines L extends from the edge of the second surface S2 to the second surface S2.
  • the non-edge area of ?? extends; the signal connection line L is coupled to the shift register circuit SR.
  • the number of fan-out structures 12 is 1 to 4.
  • the number of fan-out structures 12 is one; for another example, as shown in FIG. 7, the number of fan-out structures 12 is Two; for another example, the number of fan-out structures 12 can also be three or four.
  • the wiring length of the signal connection line L on the second surface S2 can be effectively shortened, thereby reducing the complexity of wiring and simplifying the manufacturing process.
  • a set of shift register circuits and a fan-out structure 12' are all located in the non-display area BB' of the first surface S1' of the array substrate 1', and each shift register circuit Due to its own circuit structure, it occupies a certain volume and area in the array substrate 1'.
  • the shift register circuit SR' and the fan-out structure 12' occupy a relatively large area of the first surface S1', so that the display panel with the array substrate 1'cannot meet the requirement of a narrow frame or no frame.
  • the shift register circuit SR is disposed in the display area AA of the first surface S1 of the array substrate 1, and the fan-out structure 12 is disposed on the second surface S2 of the array substrate 1, thereby facilitating the array substrate 1. 1 Realize narrow border display or no border display.
  • the array substrate 1 further includes: a plurality of control signal lines C arranged on the first surface S1 and extending in the second direction, and each shift register in each group of shift register circuits
  • the circuit SR is coupled to at least one control signal line C among the plurality of control signal lines C. It should be pointed out that FIG. 3 only uses three control signal lines C for illustration.
  • one end of the signal connection line L close to the edge of the second surface S2 is coupled to one of the at least one control signal line C.
  • the control signal line C is configured to transmit a control signal to the shift register circuit SR, so that the shift register circuit SR outputs a scanning signal under the control of the control signal.
  • the control signal includes at least one of a clock signal, a constant voltage signal (such as a high-level VGH or a low-level VGL), or an on signal (such as an STV signal).
  • the clock signals are one or more groups, each group of clock signals includes a complementary CLK signal and a CLKB signal, and each group of clock signals corresponds to a group of shift register circuits.
  • the array substrate 1 further includes: at least one side structure 13 disposed on the side surface of the base substrate 10 between the first surface S1 and the second surface S2 , At least one side structure 13 corresponds to at least one fan-out structure 12 one-to-one.
  • each side structure in at least one side structure includes a plurality of side connections, one end of each side connection of the plurality of side connections is coupled to the signal connection line L, and the other end is connected to the control The signal line C is coupled.
  • the coupling of the signal connection line L and the shift register circuit SR is realized through the side connection.
  • the number of side structures is 1 to 4. As shown in FIGS. 6 and 7, the number of side structures 13 is the same as the number of fan-out structures 12, and the side structures 13 and the fan-out structures 12 correspond one-to-one.
  • the material of the side structure 13 is metal or conductive silver glue, where the metal includes at least one of silver and copper.
  • the side structure can have good conductivity.
  • the orthographic projection of the side structure 13 on the base substrate 10 and the orthographic projection of the fan-out structure 12 on the base substrate 10 are different. overlapping.
  • the orthographic projection of the side structure 13 on the base substrate 10 overlaps with the orthographic projection of the fan-out structure 12 on the base substrate 10,
  • the array substrate 1 further includes a conductive layer 14 disposed between the fan-out structure 12 and the side structure 13.
  • the orthographic projection of the conductive layer 14 on the base substrate 10 is within the range of the orthographic projection of the fan-out structure 12 on the base substrate 10.
  • the arrangement of the conductive layer 14 ensures an effective connection between the fan-out structure 12 and the side structure 13.
  • the material of the conductive layer 14 is a metal with good conductivity or indium tin oxide (ITO).
  • ITO indium tin oxide
  • the display panel 100 includes: an array substrate 1 as disclosed in some of the above embodiments, and a control chip coupled to the array substrate 1 The control chip is configured to transmit a control signal to the shift register circuit of the array substrate 1, so that the shift register circuit outputs a scan signal under the control of the control signal.
  • control chip is directly disposed on the array substrate 1; or, the control chip is not directly disposed on the array substrate 1, but is coupled to the array substrate 1 through electronic connectors (such as pins, connecting wires, etc.).
  • electronic connectors such as pins, connecting wires, etc.
  • the control chip 2 is directly disposed on the array substrate 1.
  • the base substrate 10 includes a second surface S2 opposite to the first surface S1, and the control chip 2 is disposed on the second surface S2 of the base substrate 10 of the array substrate 1.
  • the control chip 2 includes a control chip main body 21 and a plurality of first pins 22. Wherein, the control chip main body 21 is configured to transmit control signals to the plurality of first pins 22.
  • a plurality of first pins 22 are bound to a plurality of signal connection lines L of at least one fan-out structure 12.
  • control chip 2 is disposed on the second surface S2 of the base substrate 10, which can prevent the control chip from occupying the space on the first surface S1 of the base substrate 10, which is beneficial to realize the narrow frame or frameless display of the display panel 100.
  • each first pin 22 of the plurality of first pins 22 and one signal connection line of the plurality of signal connection lines may be bound by an anisotropic conductive film (ACF), Some embodiments of the present disclosure do not limit the binding manner of the signal connection line of the first pin 22.
  • ACF anisotropic conductive film
  • the control chip is not directly disposed on the array substrate 1.
  • the base substrate 10 includes a second surface S2 opposite to the first surface S1
  • the display panel 100 further includes a plurality of second leads disposed on the second surface S2 of the base substrate 10 of the array substrate 1.
  • Pin 3 wherein a plurality of second pins 3 are coupled to the control chip.
  • multiple second pins 3 are bound to multiple signal connection lines of at least one fan-out structure 12.
  • control chip is not disposed on the first surface S1 of the base substrate 10, and a plurality of second pins 3 coupled to the control chip are disposed on the second surface S2 of the base substrate 10, and the upper control chip 2 and None of the second pins 3 occupy the space on the first surface S1 of the base substrate 10, thereby facilitating the realization of a narrow frame or frameless display of the display panel 100.
  • each second pin 3 of the plurality of second pins 3 and one of the plurality of signal connection lines may also be bound by an anisotropic conductive film (ACF)
  • ACF anisotropic conductive film
  • the binding manner of the signal connection line of the second pin 3 is not limited.
  • the display panel 100 is a liquid crystal display (LCD), an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel, a micro light-emitting diode (Micro Light-Emitting Diode, Micro-LED) display panel, or a mini Mini-Light Emitting Diode (Mini-LED) display panel.
  • LCD liquid crystal display
  • OLED Organic Light-Emitting Diode
  • Micro-LED Micro Light-Emitting Diode
  • Mini-LED Mini-Light Emitting Diode
  • the beneficial effects of the display panel in some embodiments of the present disclosure are the same as the beneficial effects of the array substrate described in some of the above embodiments, and will not be repeated here.
  • Some embodiments of the present disclosure also provide a pixel driving method, which is applied to the display panel as described in any of the above-mentioned embodiments, and the pixel driving method includes: S11 to S12.
  • the control chip 2 of the display panel 100 sends a control signal to each of the at least two sets of shift register circuits of the array substrate 1 of the display panel 100.
  • Each shift register circuit in each group of shift register circuits receives the control signal, and transmits the scan signal to the scan signal line coupled thereto along the first direction.
  • At least one set of shift register circuits is disposed in the non-edge area of the display area AA of the first surface S1 of the array substrate 1, that is, there is one set of or Two sets of shift register circuits are arranged in the edge area of the display area AA.
  • each shift register circuit in each group of shift register circuits arranged in the non-edge area receives the control signal sent by the control chip, according to the control signal, it moves along the first direction to each other.
  • the scan signal lines on both sides of the shift register circuit are coupled to transmit the scan signal; after each shift register circuit in each group of shift register circuits arranged in the edge area receives the control signal sent by the control chip, according to the control signal , Along the first direction, the scanning signal is transmitted to the scanning signal line on the side coupled with each shift register circuit.
  • At least two sets of shift register circuits are both disposed in the non-edge area of the display area AA on the first surface S1 of the array substrate 1.
  • each shift register circuit in each group of shift register circuits in at least two groups of shift register circuits receives the control signal sent by the control chip, according to the control signal, it shifts to and from each in the first direction.
  • the scan signal lines on both sides of the bit register circuit are coupled to transmit scan signals.
  • Some embodiments of the present disclosure also provide a method for preparing an array substrate, including:
  • a base substrate 10 is provided, wherein the base substrate 10 includes a first surface S1, and the first surface S1 has a display area AA.
  • a plurality of scan signal lines G are formed on the first surface S1, wherein each scan signal line G of the plurality of scan signal lines G extends along the first direction.
  • At least two groups of shift register circuits are formed in the display area AA of the first surface S1; each group of shift register circuits in the at least two groups of shift register circuits includes a plurality of shift register circuits SR arranged along the second direction, and Each shift register circuit SR in the two shift register circuits SR is coupled to one of the scanning signal lines G; wherein, the first direction crosses the second direction.
  • At least one set of shift register circuits are arranged in the non-edge area of the display area AA; the shift register circuits SR arranged in the non-edge area of the display area are configured to scan signal lines along the first direction toward both sides of the shift register circuit. G transmits the scan signal.
  • the shift register circuit includes a plurality of thin film transistors, and the thin film transistors are formed by stacking a gate electrode layer, a gate insulating layer, an active layer, and a source and drain electrode layer.
  • the preparation of the scan signal line G can be compatible with the preparation process of one or some film layers of the thin film transistor.
  • the scan signal line G is a gate scan signal line G1.
  • the gate scan signal line G1 can be formed in the same layer as the gate of the thin film transistor.
  • the base substrate 10 further includes a second surface S2 opposite to the first surface S1.
  • the preparation method also includes:
  • At least one fan-out structure 12 is formed on the second surface S2; each fan-out structure 12 in the at least one fan-out structure 12 includes a plurality of signal connection lines L, and each signal connection line L of the plurality of signal connection lines L It extends from the edge of the second surface S2 to the non-edge area of the second surface S2; the signal connection line L is coupled to the shift register circuit SR.
  • a plurality of scanning signal lines G and at least two sets of shift register circuits may be formed on the first surface S1 of the base substrate 10, and then on the substrate At least one fan-out structure 12 is formed on the second surface S2 of the substrate 10; alternatively, at least one fan-out structure 12 may be formed on the second surface S2 of the base substrate 10 first, and then formed on the first surface S1 of the base substrate 10
  • Multiple scanning signal lines G and at least two sets of shift register circuits are to say, some embodiments of the present disclosure do not limit the sequence of preparing the structures on the first surface S1 and preparing the structures on the second surface S2.
  • the protective film process can be used to treat the structures on the first surface S1.
  • the prepared structures are protected, and then the structures on the second surface S2 are prepared.
  • the structures on the second surface S2 are prepared first, and then the structures on the first surface S1 are prepared, the same is true, which will not be repeated here. Therefore, it can be ensured that during the preparation process, the first side S1 and the second side S2 may not interfere with each other, and avoid damaging the previously prepared side that has been prepared when the side prepared later is prepared.
  • the preparation method further includes: forming at least one side structure 13 on the side surface of the base substrate located between the first surface S1 and the second surface S2.
  • at least one side structure 13 corresponds to at least one fan-out structure 12; each side structure 13 in the at least one side structure 13 includes a plurality of side connections, and each of the plurality of side connections One end of the side line is coupled to the signal connection line L, and the other end is coupled to the shift register circuit SR.
  • the preparation method of the side structure includes one of 3D printing, photocopying, sputtering or etching.

Abstract

一种阵列基板，包括：衬底基板，衬底基板包括第一面，第一面具有显示区；设置于第一面的多条扫描信号线，多条扫描信号线中的每条扫描信号线沿第一方向延伸；设置于第一面的显示区内的至少两组移位寄存器电路，至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路，多个移位寄存器电路中的每个移位寄存器电路与一条扫描信号线耦接；其中，第一方向与第二方向相交叉。其中，至少有一组移位寄存器电路设置于显示区的非边缘区域；设置于显示区的非边缘区域的移位寄存器电路被配置为，沿第一方向，向其两侧的扫描信号线传输扫描信号。

Description

阵列基板及其制备方法、像素驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及制备方法、像素驱动方法、显示面板。
背景技术
随着显示技术的发展，人们对显示屏在边框宽度、显示亮度和画质等方面的性能要求越来越高，例如需要显示屏具有较窄的边框与较好的显示亮度均一性。
发明内容
一方面，提供一种阵列基板，包括：衬底基板、设置于所述第一面的多条扫描信号线以及设置于所述第一面的显示区内的至少两组移位寄存器电路。其中，所述衬底基板包括第一面，所述第一面具有显示区；所述多条扫描信号线中的每条扫描信号线沿第一方向延伸；所述至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路，所述多个移位寄存器电路中的每个移位寄存器电路与一条所述扫描信号线耦接；其中，所述第一方向与所述第二方向相交叉；其中，至少有一组移位寄存器电路设置于所述显示区的非边缘区域；设置于所述显示区的非边缘区域的移位寄存器电路被配置为，沿所述第一方向，向其两侧的扫描信号线传输扫描信号。
在一些实施例中，沿所述第一方向，每相邻两组所述移位寄存器电路之间的间距相等。
在一些实施例中，所述至少两组移位寄存器电路均设置于所述显示区的非边缘位置。
在一些实施例中，在沿所述第一方向每相邻两组所述移位寄存器电路之间的间距相等的情况下，沿所述第一方向，位于最外侧的两组移位寄存器电路与距其最近的所述显示区的边缘的距离为每相邻两组移位寄存器电路之间的距离的一半。
在一些实施例中，所述移位寄存器电路的组数为3～5组。
在一些实施例中，所述阵列基板包括矩阵式布置的多个子像素，所述每组移位寄存器电路设置于相邻两列子像素之间的间隙区域。
在一些实施例中，所述扫描信号线包括栅扫描信号线，所述移位寄存器电路包括栅移位寄存器电路；所述栅移位寄存器电路与所述栅扫描信号线耦 接；和/或，所述扫描信号线包括发光扫描信号线，所述移位寄存器电路包括发光移位寄存器电路；所述发光移位寄存器电路与所述发光扫描信号线耦接。其中，所述栅移位寄存器电路被配置为，向所述栅扫描信号线传输栅扫描信号；所述发光移位寄存器电路被配置为，向所述发光扫描信号线传输发光扫描信号。
在一些实施例中，所述衬底基板还包括与所述第一面相对的第二面。所述阵列基板还包括：设置于所述第二面的至少一个扇出结构。所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线中的每条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸；所述信号连接线与所述移位寄存器电路耦接。
在一些实施例中，所述阵列基板还包括：设置于所述第一面的沿所述第二方向延伸的多条控制信号线。所述每组移位寄存器电路中的各移位寄存器电路与所述多条控制信号线中的至少一条控制信号线耦接。所述信号连接线的靠近所述第二面的边缘的一端与所述至少一条控制信号线中的一条控制信号线耦接。所述控制信号线被配置为向所述移位寄存器电路传输控制信号，以使所述移位寄存器电路在所述控制信号的控制下输出所述扫描信号。
在一些实施例中，所述阵列基板还包括：设置于所述衬底基板的位于所述第一面和所述第二面之间的侧面上的至少一个侧边结构。所述至少一个侧边结构与所述至少一个扇出结构一一对应。所述至少一个侧边结构中的每个侧边结构包括多条侧边连线，所述多条侧边连线中的每条侧边连线的一端与所述信号连接线耦接，另一端与所述控制信号线耦接。
在一些实施例中，所述扇出结构和所述侧边结构的数量均为1～4个。
另一方面，提供一种显示面板，包括：如上述一些实施例中任一项所述的阵列基板；以及与所述阵列基板耦接的控制芯片。所述控制芯片被配置为向所述阵列基板的移位寄存器电路传输控制信号，以使所述移位寄存器电路在所述控制信号的控制下输出扫描信号。
在一些实施例中，所述控制芯片设置于所述阵列基板的衬底基板的第二面上；所述第二面与所述衬底基板的第一面相对。所述控制芯片包括控制芯片主体和多个第一引脚；其中，所述控制芯片主体被配置为，向所述多个第一引脚传输所述控制信号。在所述阵列基板包括至少一个扇出结构的情况下，所述多个第一引脚与所述至少一个扇出结构的多条信号连接线绑定。
在一些实施例中，所述显示面板还包括设置于所述阵列基板的衬底基板的第二面上的多个第二引脚；所述第二面与所述衬底基板的第一面相对。所 述多个第二引脚与所述控制芯片耦接。在所述阵列基板包括至少一个扇出结构的情况下，所述多个第二引脚与所述至少一个扇出结构的多条信号连接线绑定。
又一方面，提供一种像素驱动方法，应用于如上述一些实施例中任一项所述的显示面板。所述像素驱动方法包括：所述显示面板的控制芯片向所述显示面板的阵列基板的至少两组移位寄存器电路中的每组移位寄存器电路发送控制信号；所述每组移位寄存器电路中的各所述移位寄存器电路接收所述控制信号，并沿第一方向向其耦接的扫描信号线传输扫描信号。
再一方面，提供一种阵列基板的制备方法，包括：提供衬底基板；所述衬底基板包括第一面，所述第一面具有显示区。在所述第一面形成多条扫描信号线；所述多条扫描信号线中的每条扫描信号线沿第一方向延伸。在所述第一面的显示区内形成至少两组移位寄存器电路；所述至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路，所述多个移位寄存器中的每个移位寄存器与一条所述扫描信号线耦接。其中，所述第一方向与所述第二方向相交叉。其中，至少有一组所述移位寄存器电路设置于所述显示区的非边缘区域；设置于所述显示区的非边缘区域的所述移位寄存器电路被配置为，沿所述第一方向，向其两侧的所述扫描信号线传输扫描信号。
在一些实施例中，所述衬底基板还包括与所述第一面相对的第二面。所述制备方法还包括：在所述第二面上形成至少一个扇出结构。所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线中的每条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸；所述信号连接线与所述移位寄存器电路耦接。
在一些实施例中，所述制备方法还包括：在所述衬底基板的位于所述第一面和所述第二面之间的侧面上形成至少一个侧边结构。所述至少一个侧边结构与所述至少一个扇出结构一一对应；所述至少一个侧边结构中的每个侧边结构包括多条侧边连线，所述多条侧边连线中的每条侧边连线的一端与所述信号连接线耦接，另一端与所述移位寄存器电路耦接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作 示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术提供的一种阵列基板的俯视图；
图2为根据相关技术提供的阵列基板中的移位寄存器电路的扫描信号的时序图；
图3为根据本公开一些实施例中的一种阵列基板的第一面的俯视图；
图4为根据本公开一些实施例中的另一种阵列基板的第一面的俯视图；
图5为根据本公开一些实施例中的又一种阵列基板的第一面的俯视图；
图6为根据本公开一些实施例中的一种阵列基板的第二面的俯视图；
图7为根据本公开一些实施例中的另一种阵列基板的第二面的俯视图；
图8为图3中的阵列基板在QQ处的一种局部剖视图；
图9为图3中的阵列基板在QQ处的另一种局部剖视图；
图10a为根据本公开一些实施例中的一种显示面板的第一面的俯视图；
图10b为根据本公开一些实施例中的一种显示面板的第二面的俯视图；
图11为根据本公开一些实施例中的另一种显示面板的第二面的俯视图。
具体实施方式
下面将结合本公开一些实施例中的附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的一些实施例，本领域普通技术人员所能获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第 一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。术语“上”、“下”、“左”、“右”等仅是用于表示相应的位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触，。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在一些相关技术中，如图1所示，阵列基板1’包括衬底基板10’，衬底基板10’包括第一面S1’，第一面S1’具有显示区AA’和非显示区BB’。在显示区AA’内，设置有多条扫描信号线G’，多条扫描信号线G’中的每条扫描信号线G’沿第一方向延伸。在位于阵列基板1’的沿第一方向的左侧或右侧(图1中以左侧作为示意)的非显示区BB’内，设置有一组移位寄存器电路，所述一组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路SR’，所述多个移位寄存器电路SR’中的每个移位寄存器电路SR’与一条扫描信号线G’耦接。其中，每个移位寄存器电路SR’被配置为，沿第一方向，向其一侧的扫描信号线G’传输扫描信号。
此处，第一方向与第二方向相交叉。例如，在阵列基板包括阵列式布置的多个子像素的情况下，第一方向F1为多个子像素排列的行方向，第二方向F2为多个子像素排列的列方向，第一方向和第二方向相互垂直。
当移位寄存器SR’向扫描信号线G’输入扫描信号，沿第二方向的数据信号线D’上的数据信号写入相应行的子像素的驱动电路中，并且进行阈值电压的补偿。
示例性的，在阵列基板为被动发光显示器(例如LCD等)或者主动发光显示器(例如OLED、mini-LED等)，移位寄存器电路SR’包括栅移位寄存器电路，在此情况下，移位寄存器电路SR’传输的所述扫描信号包括栅扫描信号(Gate)，其中，栅扫描信号(Gate)用于对栅扫描信号线逐行扫描，以开启相应行的子像素。
或者，在阵列基板为主动发光显示器(例如OLED、mini-LED等)的阵列基板的情况下，移位寄存器电路SR’包括发光移位寄存器电路，也即，移 位寄存器电路SR’传输的扫描信号包括发光扫描信号(EM)，其中，发光扫描信号(EM)用于对发光描信号线逐行扫描，以使相应行的子像素发光。
基于此，在每条扫描信号线G’上，由于RC loading(电阻电容负载)的存在，扫描信号线G’的末端(即扫描信号线G’远离移位寄存器电路的一端)的扫描信号会比扫描信号线G’的起始端(即扫描信号线G’靠近移位寄存器电路的一端)的扫描信号弱，并且由于扫描信号线G’上RC loading的存在，扫描信号线G’上的扫描信号具有延迟现象，造成阵列基板1’上的扫描信号线G’的远离移位寄存器电路SR’的一端所连接的子像素中，充电时间不足，并且，数据信号(Date)的写入时间和阈值电压(Vth)的补偿时间不足，从而造成显示不均一。
示例性的，如图1所示，多条扫描信号线G’中的每条扫描信号线G’上，扫描信号线G’的末端处的RC loading最大，也即，扫描信号线G’的末端处的的RC loading可以记作RC loading max，其中，RC loading max的值为a’。
示例性的，如图1和图2所示，其中，图2以两个栅扫描信号Gate(Gate(0)与Gate(1))、两个发光扫描信号EM(EM(0)与EM(1))为例进行示意。阵列基板1’上设置有一组移位寄存器电路，每条扫描信号线G’上的RC loading max为a’。每条扫描信号线上的RC loading较大，也即每条扫描信号线G’上的RC loading max较大，这样使得扫描信号线G’上的扫描信号的上升时间及下降时间增加。其中，扫描信号的上升时间包括栅扫描信号上升时间(tr-G)与发光扫描信号上升时间(tr-E)，扫描信号的下降时间包括栅扫描信号下降时间(tf-G)与发光扫描信号上升时间(tf-E)。
此处，栅扫描信号被配置为开启与扫描信号线G’电连接的一行子像素，以使数据信号线D’对相应的子像素写入数据信号(Date)。如图2所示，1H为数据信号(Date)写入一行子像素的时间，充电时间T(Charge time)等于数据信号(Date)写入一行子像素的时间减去扫描信号的上升时间及下降时间，也即，T＝1H-(tr-G+tf-G)-(tr-E+tf-E)。
由此，扫描信号线G’上的扫描信号的上升时间及下降时间增加，使得数据信号(Date)的写入时间以及对阈值电压(Vth)的补偿时间减小，从而影响显示均一性。
基于此，本公开一些实施例提供一种阵列基板1，如图3所示，阵列基板1包括：衬底基板10、设置于第一面S1的多条扫描信号线G以及设置于第一面S1的显示区AA内的至少两组移位寄存器电路。其中，衬底基板10包括 第一面S1，第一面S1具有显示区AA；多条扫描信号线G中的每条扫描信号线G沿第一方向延伸；至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路SR，多个移位寄存器电路SR中的每个移位寄存器电路SR与一条扫描信号线G耦接。需要说明的是，图3仅以3组移位寄存器电路进行示意，本公开一些实施例对移位寄存器电路的组数不作限定，以移位寄存器电路的组数为至少两组为限。
在一些示例中，如图3所示，至少两组移位寄存器电路中的每组移位寄存器电路中的移位寄存器电路的数量相同。并且，多条扫描信号线G中的每条扫描信号线G所耦接的移位寄存器SR的数量与显示区AA内的移位寄存器电路SR的组数相同。由此，同一条扫描信号线G耦接至少两个移位寄存器电路SR，其中，至少两个移位寄存器电路SR分别来自至少两组移位寄存器电路中的不同组。
在一些示例中，第一方向与所述第二方向相交叉。如图3所示，在阵列基板包括阵列式布置的多个子像素的情况下，第一方向F1为多个子像素排列的行方向或水平方向，第二方向F2为多个子像素排列的列方向或垂直方向，第一方向和第二方向相互垂直。
在一些实施例中，在至少两组移位寄存器电路中，至少有一组移位寄存器电路设置于显示区AA的非边缘区域。例如，阵列基板1的显示区AA内具有两组移位寄存器电路，其中一组设置于显示区AA的非边缘区域，另一组设置于显示区AA的边缘区域。又如，阵列基板1的显示区AA内具有三组移位寄存器电路，其中一组设置于显示区AA的非边缘区域，另外两组设置于显示区AA的边缘区域；或者，其中两组设置于显示区AA的非边缘区域，另外一组设置于显示区AA的边缘区域。本公开一些实施例对于至少两组移位寄存器电路设置在显示区AA的非边缘区域的组数不作限定，以具有至少有一组移位寄存器电路设置于显示区AA的非边缘区域为限。其中，设置于显示区AA的非边缘区域的移位寄存器电路SR被配置为，沿第一方向，向其两侧的扫描信号线G传输扫描信号。
示例性的，显示区AA的非边缘区域为显示区AA内的区域，显示区AA的非边缘区域与显示区AA的边缘区域相对。设置于显示区AA的边缘区域的移位寄存器电路，沿第一方向，只能向其一侧的扫描信号线G传输扫描信号。设置于显示区AA的非边缘区域的移位寄存器电路，沿第一方向，可以向其两侧的扫描信号线G传输扫描信号；或者，也可以有选择性的向其一侧的扫描信号线G传输扫描信号。
示例性的，阵列基板1可以应用于液晶显示面板(Liquid Crystal Display，LCD)、有机发光二极管(OrganicLight-Emitting Diode，OLED)显示面板、微型发光二极管(Micro Light Emitting Diode，Micro-LED)显示面板或者迷你发光二极管(Mini Light Emitting Diode，Mini-LED)显示面板等。
在一些示例中，扫描信号线G包括栅扫描信号线G1，移位寄存器电路SR包括栅移位寄存器电路SR1。栅移位寄存器电路SR1与栅扫描信号线G1耦接，其中，栅移位寄存器电路SR1被配置为，向栅扫描信号线G1传输栅扫描信号(Gate)。
在另一些示例中，扫描信号线G包括发光扫描信号线G2，移位寄存器电路SR包括发光移位寄存器电路SR2。发光移位寄存器电路SR2与发光扫描信号线G2耦接，其中，发光移位寄存器电路SR2被配置为，向发光扫描信号线G2传输发光扫描信号(EM)。
在又一些示例中，扫描信号线G包括栅扫描信号线G1和发光扫描信号线G2，移位寄存器电路包括栅移位寄存器电路SR1和发光移位寄存器电路SR2。栅移位寄存器电路SR1与栅扫描信号线G1耦接，发光移位寄存器SR2电路与发光扫描信号线G2耦接。其中，栅移位寄存器电路SR1被配置为向栅扫描信号线G1传输栅扫描信号(Gate)，发光移位寄存器电路SR2被配置为向发光扫描信号线G2传输发光扫描信号(EM)。
例如，如图4所示(以4组移位寄存器电路进行示意)，沿第一方向，栅移位寄存器电路SR1和发光移位寄存器电路SR2单独间隔设置；又如，如图5所示(以3组移位寄存器电路进行示意)，将栅移位寄存器电路SR1和发光移位寄存器电路SR2集成设置于同一移位寄存器电路SR中，也即，所述移位寄存器电路与栅扫描信号线G1、发光扫描信号线G2耦接，所述移位寄存器电路SR被配置为，向栅扫描信号线G1传输栅扫描信号(Gate)，并向发光扫描信号线G2传输发光扫描信号(EM)。
在一些示例中，如图3所示，沿第一方向，每相邻两组移位寄存器电路之间的间距s相等。这样可以使得每条扫描信号线G上各处的RC loading分布较为均匀。
在另一些示例中，沿第一方向，每相邻两组移位寄存器电路之间的间距也可以不相等，本公开一些实施例对每相邻两组移位寄存器电路之间的间距是否相等不作限定，以在显示区AA内设置至少两组移位寄存器电路为限。
在一些实施例中，如图3所示，至少两组移位寄存器电路均设置于显示区AA的非边缘位置。例如，所述至少两组移位寄存器电路均设置于显示区 AA的非边缘位置，且每相邻两组移位寄存器电路之间的间距相等。又如，所述至少两组移位寄存器电路均设置于显示区AA的非边缘位置，且每相邻两组移位寄存器电路之间的间距不相等。
在一些实施例中，在每相邻两组移位寄存器电路之间的间距相等的情况下，沿第一方向，位于最外侧的两组移位寄存器电路与距其最近的显示区AA的边缘的距离m为每相邻两组移位寄存器电路之间的距离s的一半。
在一些示例中，阵列基板1的显示区在第一方向上的宽度为w，在阵列基板1上设置n组移位寄存器电路，其中n≥2。由此，沿第一方向，位于最外侧的两组移位寄存器电路与距其最近的显示区AA的边缘的距离为m，其中，
Figure PCTCN2019122203-appb-000001
并且，每相邻两组移位寄存器电路之间的间距为s，其中，s＝2m。
基于此，多条扫描信号线G中的每条扫描信号线G上的RC loading max的值为a，其中，在阵列基板1与阵列基板1’的尺寸及分辨率等条件相同的情况下，
Figure PCTCN2019122203-appb-000002
这样，有效减小了每条扫描信号线G上的RC loading max，也即，有效减小了每条扫描信号线G上的RC loading，并且减小了扫描信号的上升时间(tr-G与tr-E)及下降时间(tf-G与tf-E)，也就可以避免减小数据信号(Date)的写入时间以及阈值电压(Vth)补偿时间，从而确保了显示亮度均一性。
其中，如图2所示，所述扫描信号的上升时间包括栅扫描信号上升时间(tr-G)与发光扫描信号上升时间(tr-E)，扫描信号的下降时间包括栅扫描信号下降时间(tf-G)与发光扫描信号上升时间(tf-E)。
如图3所示，以移位寄存器电路的组数为3组为例进行说明。阵列基板1在第一方向上的宽度为w，由此，沿第一方向，位于最外侧的两组移位寄存器电路与距其最近的显示区AA的边缘的距离为m，其中，
Figure PCTCN2019122203-appb-000003
n＝3。由此，位于最外侧的两组移位寄存器电路与距其最近的显示区AA的边缘的距离
Figure PCTCN2019122203-appb-000004
在3组移位寄存器电路中，每相邻两组移位寄存器电路之间的间距为s，其中，s＝2m，
Figure PCTCN2019122203-appb-000005
因此，每相邻两组移位寄存器电路之间的间距
Figure PCTCN2019122203-appb-000006
基于此，多条扫描信号线中的每条扫描信号线上的RC loading max的值为a，其中，
Figure PCTCN2019122203-appb-000007
n＝3。由此可知，每条扫描信号线上的RC loading max 的值
Figure PCTCN2019122203-appb-000008
由此可见，阵列基板1上的扫描信号线上的RC loading max的值，为阵列基板1’上的扫描信号线上的RC loading max的值的六分之一。这样，有效减小了每条扫描信号线G上的RC loading，进而减小了扫描信号的上升时间(tr-G与tr-E)及下降时间(tf-G与tf-E)，这样可以避免减小数据信号(Date)的写入时间以及阈值电压(Vth)补偿时间，从而确保了显示亮度均一性。
在一些实施例中，在阵列基板1上设置的移位寄存器电路SR的组数与阵列基板1的尺寸以及显示分辨率有关。例如，阵列基板的尺寸越大或者显示分辨率越高，设置的移位寄存器电路的组数越多，从而可以确保每条扫描信号线G上的RC loading较小，进而确保显示亮度均一性。
示例性的，阵列基板1的尺寸为10.1寸～12.1寸(例如11寸或者12寸)或者显示分辨率为480*270的情况下，移位寄存器电路的组数可以设置为3～5组。
此外，在一些示例中，LCD或者OLED显示面板的像素电流为几十nA，而Micro-LED显示面板或者Mini-LED显示面板的像素电流为几十uA，Micro-LED显示面板或者Mini-LED显示面板所需的像素电流约为LCD或者OLED显示面板所需的像素电流的1000倍。
在此情况下，为确保Micro-LED显示面板或者Mini-LED显示面板的像素电流的驱动能力，需要增加Micro-LED显示面板或者Mini-LED显示面板的像素电流的通路上的薄膜晶体管(Thin Film Transistor，TFT)的宽长比(W/L)。然而，薄膜晶体管的宽长比(W/L)增加，导致阵列基板上的每条扫描信号线G上的RC loading增加，这样，也会增加扫描信号的上升时间(tr-G与tr-E)及下降时间(tf-G与tf-E)。从而导致数据信号(Date)的写入时间以及对阈值电压(Vth)的补偿时间减小，影响显示亮度均一性。
由于上述一些实施例中的阵列基板1可以有效减小每条扫描信号线G上的RC loading，从而可以避免由增加薄膜晶体管的宽长比(W/L)导致的RC loading增加、以及扫描信号的上升时间(tr-G与tr-E)和下降时间(tf-G与tf-E)增加，进而可以避免减小数据信号(Date)的写入时间以及阈值电压(Vth)补偿时间，这样就可以更好的确保Micro-LED显示面板或者Mini-LED显示面板的显示亮度均一性。
在一些实施例中，阵列基板1包括矩阵式布置的多个子像素，每组移位寄存器电路设置于相邻两列子像素之间的间隙区域。这样使得移位寄存器电 路SR不占用显示区AA以外的区域，从而有利于阵列基板1实现窄边框显示或者无边框显示。
在一些实施例中，如图3和图6所示，衬底基板10还包括与第一面S1相对的第二面S2。阵列基板1还包括设置于第二面S2的至少一个扇出结构12。其中，至少一个扇出结构12中的每个扇出结构12包括多条信号连接线L，多条信号连接线L中的每条信号连接线L由第二面S2的边缘向第二面S2的非边缘区域延伸；信号连接线L与移位寄存器电路SR耦接。
在一些示例中，扇出结构12的数量为1～4个，例如，如图6所示，扇出结构12的数量为一个；又如，如图7所示，扇出结构12的数量为两个；再如，扇出结构12的数量也可以为三个或者四个。其中，在扇出结构的数量为一个的情况下，可以有效缩短信号连接线L在第二面S2上的走线长度，从而降低布线的复杂性，并且简化制作工艺。
此外，示例性的，如图1所示，一组移位寄存器电路和扇出结构12’均位于阵列基板1’的第一面S1’的非显示区BB’，并且每个移位寄存器电路由于其自身的电路结构在阵列基板1’中占用的一定体积和面积。移位寄存器电路SR’和扇出结构12’占用第一面S1’的较大面积，从而无法满足具有阵列基板1’的显示面板对窄边框或无边框的需求。
而在公开的一些实施例中，移位寄存器电路SR设置于阵列基板1的第一面S1的显示区AA内，扇出结构12设置于阵列基板1的第二面S2，从而有利于阵列基板1实现窄边框显示或者无边框显示。
在一些实施例中，如图3所示，阵列基板1还包括：设置于第一面S1的沿第二方向延伸的多条控制信号线C，每组移位寄存器电路中的各移位寄存器电路SR与多条控制信号线C中的至少一条控制信号线C耦接。需要指出的是，图3仅以三条控制信号线C进行示意。
并且，信号连接线L的靠近第二面S2的边缘的一端与至少一条控制信号线C中的一条控制信号线C耦接。其中，控制信号线C被配置为向移位寄存器电路SR传输控制信号，以使移位寄存器电路SR在控制信号的控制下输出扫描信号。
示例性的，控制信号包括时钟信号、恒压信号(例如高电平VGH或者低电平VGL)或者开启信号(例如STV信号)中的至少一者。其中，时钟信号为一组或多组，每组时钟信号包括互补的CLK信号和CLKB信号，每组时钟信号对应一组移位寄存器电路。
在一些实施例中，如图3和图6所示，阵列基板1还包括：设置于衬底 基板10的位于第一面S1和第二面S2之间的侧面上的至少一个侧边结构13，至少一个侧边结构13与至少一个扇出结构12一一对应。其中，至少一个侧边结构中的每个侧边结构包括多条侧边连线，多条侧边连线中的每条侧边连线的一端与信号连接线L耦接，另一端与控制信号线C耦接。从而通过侧边连线实现了信号连接线L与移位寄存器电路SR的耦接。
在一些实施例中，侧边结构的数量为1～4个。如图6和图7所示，侧边结构13的数量与扇出结构12的数量相同，并且，侧边结构13与扇出结构12一一对应。
示例性的，侧边结构13的材料为金属或者导电银胶，其中，金属包括银、铜等中的至少一种。从而可以使得侧边结构具有良好的导电性。
在一些示例中，如图8所示，在衬底基板10的垂直方向上，侧边结构13在衬底基板10的上的正投影与扇出结构12在衬底基板10上的正投影无重叠。
在另一些示例中，如图9所示，在衬底基板10的垂直方向上，侧边结构13在衬底基板10的上的正投影与扇出结构12在衬底基板10上的正投影有重叠。
在一些实施例中，在衬底基板10的垂直方向上，侧边结构13在衬底基板10的上的正投影与扇出结构12在衬底基板10上的正投影有重叠的情况下，如图9所示，阵列基板1还包括设置于扇出结构12和侧边结构13之间的导电层14。导电层14在衬底基板10上的正投影位于扇出结构12在衬底基板10上的正投影的范围内。导电层14的设置确保了扇出结构12和侧边结构13之间的有效连接。
示例性的，导电层14的材料为导电性良好的金属或者氧化铟锡(ITO)。
本公开一些实施例还提供了一种显示面板100，如图10a和图10b所示，显示面板100包括：如上述一些实施例中公开的阵列基板1，以及与阵列基板1耦接的控制芯片，控制芯片被配置为向阵列基板1的移位寄存器电路传输控制信号，以使移位寄存器电路在控制信号的控制下输出扫描信号。
示例性的，控制芯片直接设置于阵列基板1上；或者，控制芯片不直接设置于阵列基板1上，而通过电子连接件(例如引脚、连接线等)与阵列基板1耦接。本公开一些实施例对此不作限定，以控制芯片能够实现向阵列基板1的移位寄存器电路传输控制信号，以使移位寄存器电路在控制信号的控制下输出扫描信号为限。
在一些实施例中，如图10b所示，控制芯片2直接设置于阵列基板1上。衬底基板10包括与第一面S1相对的第二面S2，控制芯片2设置于阵列基板 1的衬底基板10的第二面S2上。控制芯片2包括控制芯片主体21和多个第一引脚22。其中，控制芯片主体21被配置为，向多个第一引脚22传输控制信号。并且，多个第一引脚22与至少一个扇出结构12的多条信号连接线L绑定。
这样，控制芯片2设置于衬底基板10的第二面S2上，可以避免控制芯片占用衬底基板10的第一面S1上的空间，有利于实现显示面板100的窄边框或者无边框显示。
示例性的，多个第一引脚22中的每个第一引脚22与多条信号连接线中的一条信号连接线可以通过异方性导电薄膜(Anisotropic Conductive Film，ACF)进行绑定，本公开一些实施例对第一引脚22信号连接线的绑定方式不作限定。
在一些实施例中，控制芯片不直接设置于阵列基板1上。如图11所示，衬底基板10包括与第一面S1相对的第二面S2，显示面板100还包括设置于阵列基板1的衬底基板10的第二面S2上的多个第二引脚3，其中，多个第二引脚3与控制芯片耦接。并且，多个第二引脚3与至少一个扇出结构12的多条信号连接线绑定。
这样，控制芯片不设置于衬底基板10的第一面S1上，并且，与控制芯片耦接的多个第二引脚3设置于衬底基板10的第二面S2，上控制芯片2与第二引脚3均不占用衬底基板10的第一面S1上的空间，从而有利于实现显示面板100的窄边框或者无边框显示。
示例性的，多个第二引脚3中的每个第二引脚3与多条信号连接线中的一条信号连接线也可以通过异方性导电薄膜(Anisotropic Conductive Film，ACF)进行绑定，本公开一些实施例对第二引脚3信号连接线的绑定方式不作限定。
示例性的，显示面板100为液晶显示面板(Liquid Crystal Display，LCD)、有机发光二极管(OrganicLight-Emitting Diode，OLED)显示面板、微型发光二极管(Micro Light Emitting Diode，Micro-LED)显示面板或者迷你发光二极管(Mini Light Emitting Diode，Mini-LED)显示面板。
本公开一些实施例中的显示面板的有益效果和上述一些实施例所述的阵列基板的有益效果相同，此处不再赘述。
本公开一些实施例还提供了一种像素驱动方法，应用于如上述一些实施例中任一所述的显示面板，像素驱动方法包括：S11～S12。
S11：显示面板100的控制芯片2向显示面板100的阵列基板1的至少两 组移位寄存器电路中的每组移位寄存器电路发送控制信号。
S12：每组移位寄存器电路中的各移位寄存器电路接收控制信号，并沿第一方向向其耦接的扫描信号线传输扫描信号。
这样，有效减小了每条扫描信号线G上的RC loading，进而减小了扫描信号的上升时间(tr-G与tr-E)及下降时间(tf-G与tf-E)，这样可以避免减小数据信号(Date)的写入时间以及阈值电压(Vth)补偿时间，从而确保了显示均一性。
在一些示例中，在至少两组移位寄存器电路中，有至少一组移位寄存器电路设置于阵列基板1的第一面S1的显示区AA的非边缘区域，也就是说，存在一组或者两组移位寄存器电路设置于所述显示区AA的边缘区域。在此情况下，设置于所述非边缘区域的每组移位寄存器电路中的各移位寄存器电路接收控制芯片所发送的控制信号后，根据所述控制信号，沿第一方向，向与各移位寄存器电路耦接的两侧的扫描信号线传输扫描信号；设置于所述边缘区域的每组移位寄存器电路中的各移位寄存器电路接收控制芯片所发送的控制信号后，根据控制信号，沿第一方向，向与各移位寄存器电路耦接的一侧的扫描信号线传输扫描信号。
在另一些示例中，至少两组移位寄存器电路均设置于阵列基板1的第一面S1的显示区AA的非边缘区域。在此情况下，至少两组移位寄存器电路中的每组移位寄存器电路中的各移位寄存器电路接收控制芯片所发送的控制信号后，根据控制信号，沿第一方向，向与各移位寄存器电路耦接的两侧的扫描信号线传输扫描信号。
本公开一些实施例还提供了一种阵列基板的制备方法，包括：
提供衬底基板10，其中，衬底基板10包括第一面S1，第一面S1具有显示区AA。
在第一面S1形成多条扫描信号线G，其中，多条扫描信号线G中的每条扫描信号线G沿第一方向延伸。
在第一面S1的显示区AA内形成至少两组移位寄存器电路；至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路SR，多个移位寄存器电路SR中的每个移位寄存器电路SR与一条所述扫描信号线G耦接；其中，第一方向与第二方向相交叉。
其中，至少有一组移位寄存器电路设置于显示区AA的非边缘区域；设置于显示区的非边缘区域的移位寄存器电路SR被配置为，沿第一方向，向其两侧的扫描信号线G传输扫描信号。
需要说明的是，移位寄存器电路包括多个薄膜晶体管，薄膜晶体管由栅电极层、栅极绝缘层、有源层、源漏电极层等膜层堆叠形成。在一些实施例中，扫描信号线G的制备可以兼容于薄膜晶体管的某一或某些膜层的制备工艺中。例如，扫描信号线G为栅扫描信号线G1，这种情况下，该栅扫描信号线G1可与薄膜晶体管的栅极同层形成。
在一些实施例中，衬底基板10还包括与所述第一面S1相对的第二面S2。制备方法还包括：
在第二面S2上形成至少一个扇出结构12；至少一个扇出结构12中的每个扇出结构12包括多条信号连接线L，多条信号连接线L中的每条信号连接线L由第二面S2的边缘向第二面S2的非边缘区域延伸；信号连接线L与移位寄存器电路SR耦接。
在一些示例中，在制备上述一些实施例中公开的阵列基板时，可以先在衬底基板10的第一面S1形成多条扫描信号线G及至少两组移位寄存器电路，再在衬底基板10的第二面S2形成至少一个扇出结构12；或者，也可以先在衬底基板10的第二面S2形成至少一个扇出结构12，再在衬底基板10的第一面S1形成多条扫描信号线G及至少两组移位寄存器电路。这也就是说，本公开一些实施例对于制备第一面S1上的各结构与制备第二面S2上的各结构的先后顺序不作限定。
示例性的，若先制备第一面S1上的各结构再制备第二面S2上的各结构，可以在制备完第一面S1的各结构之后，采用保护膜工艺对第一面S1上已经制备完成的各结构进行保护，再制备第二面S2上的各结构。同样地，若先制备第二面S2上的各结构再制备第一面S1上的各结构也是如此，此处不再赘述。从而可以确保在制备过程中，第一面S1和第二面S2之间可以不互相影响，避免在制备在后制备的一面时，对已经制备完成的在先制备的一面造成损坏。
在一些实施例中，制备方法还包括：在衬底基板的位于第一面S1和第二面S2之间的侧面上形成至少一个侧边结构13。其中，至少一个侧边结构13与至少一个扇出结构12一一对应；至少一个侧边结构13中的每个侧边结构13包括多条侧边连线，多条侧边连线中的每条侧边连线的一端与信号连接线L耦接，另一端与移位寄存器电路SR耦接。
示例性的，侧边结构的制备方法包括3D打印、影印、溅镀(Sputter)或者刻蚀等方法中的一种。
上述阵列基板的制备方法的有益效果与上述一些实施例所述的阵列基板 的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种阵列基板，包括：
    衬底基板，所述衬底基板包括第一面，所述第一面具有显示区；
    设置于所述第一面的多条扫描信号线，所述多条扫描信号线中的每条扫描信号线沿第一方向延伸；
    设置于所述第一面的显示区内的至少两组移位寄存器电路，所述至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路，所述多个移位寄存器电路中的每个移位寄存器电路与一条所述扫描信号线耦接；其中，所述第一方向与所述第二方向相交叉；
    其中，至少有一组移位寄存器电路设置于所述显示区的非边缘区域；设置于所述显示区的非边缘区域的移位寄存器电路被配置为，沿所述第一方向，向其两侧的扫描信号线传输扫描信号。
  2. 根据权利要求1所述的阵列基板，其中，沿所述第一方向，每相邻两组所述移位寄存器电路之间的间距相等。
  3. 根据权利要求1或2所述的阵列基板，其中，所述至少两组移位寄存器电路均设置于所述显示区的非边缘位置。
  4. 根据权利要求3所述的阵列基板，其中，在沿所述第一方向每相邻两组所述移位寄存器电路之间的间距相等的情况下，
    沿所述第一方向，位于最外侧的两组移位寄存器电路与距其最近的所述显示区的边缘的距离为每相邻两组移位寄存器电路之间的距离的一半。
  5. 根据权利要求1～4中任一项所述的阵列基板，其中，所述移位寄存器电路的组数为3～5组。
  6. 根据权利要求1～5中任一项所述的阵列基板，所述阵列基板包括矩阵式布置的多个子像素，所述每组移位寄存器电路设置于相邻两列子像素之间的间隙区域。
  7. 根据权利要求1～6中任一项所述的阵列基板，其中，
    所述扫描信号线包括栅扫描信号线，所述移位寄存器电路包括栅移位寄存器电路；所述栅移位寄存器电路与所述栅扫描信号线耦接；和/或，
    所述扫描信号线包括发光扫描信号线，所述移位寄存器电路包括发光移位寄存器电路；所述发光移位寄存器电路与所述发光扫描信号线耦接；
    其中，所述栅移位寄存器电路被配置为，向所述栅扫描信号线传输栅扫描信号；所述发光移位寄存器电路被配置为，向所述发光扫描信号线传输发光扫描信号。
  8. 根据权利要求1～7中任一项所述的阵列基板，其中，所述衬底基板还 包括与所述第一面相对的第二面；
    所述阵列基板还包括：设置于所述第二面的至少一个扇出结构，所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线中的每条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸；
    所述信号连接线与所述移位寄存器电路耦接。
  9. 根据权利要求8所述的阵列基板，所述阵列基板还包括：设置于所述第一面的沿所述第二方向延伸的多条控制信号线，所述每组移位寄存器电路中的各移位寄存器电路与所述多条控制信号线中的至少一条控制信号线耦接；
    所述信号连接线的靠近所述第二面的边缘的一端与所述至少一条控制信号线中的一条控制信号线耦接；
    所述控制信号线被配置为向所述移位寄存器电路传输控制信号，以使所述移位寄存器电路在所述控制信号的控制下输出所述扫描信号。
  10. 根据权利要求9所述的阵列基板，所述阵列基板还包括：
    设置于所述衬底基板的位于所述第一面和所述第二面之间的侧面上的至少一个侧边结构，所述至少一个侧边结构与所述至少一个扇出结构一一对应；
    所述至少一个侧边结构中的每个侧边结构包括多条侧边连线，所述多条侧边连线中的每条侧边连线的一端与所述信号连接线耦接，另一端与所述控制信号线耦接。
  11. 根据权利要求10所述的阵列基板，其中，所述扇出结构和所述侧边结构的数量均为1～4个。
  12. 一种显示面板，包括：
    如权利要求1～11中任一项所述的阵列基板；以及
    与所述阵列基板耦接的控制芯片，所述控制芯片被配置为向所述阵列基板的移位寄存器电路传输控制信号，以使所述移位寄存器电路在所述控制信号的控制下输出扫描信号。
  13. 根据权利要求12所述的显示面板，其中，所述控制芯片设置于所述阵列基板的衬底基板的第二面上；所述第二面与所述衬底基板的第一面相对；
    所述控制芯片包括控制芯片主体和多个第一引脚；其中，
    所述控制芯片主体被配置为，向所述多个第一引脚传输所述控制信号；
    在所述阵列基板包括至少一个扇出结构的情况下，所述多个第一引脚与所述至少一个扇出结构的多条信号连接线绑定。
  14. 根据权利要求12所述的显示面板，所述显示面板还包括设置于所述阵列基板的衬底基板的第二面上的多个第二引脚；所述第二面与所述衬底基板的第一面相对；
    所述多个第二引脚与所述控制芯片耦接；
    在所述阵列基板包括至少一个扇出结构的情况下，所述多个第二引脚与所述至少一个扇出结构的多条信号连接线绑定。
  15. 一种像素驱动方法，应用于如权利要求12～14中任一项所述的显示面板，所述像素驱动方法包括：
    所述显示面板的控制芯片向所述显示面板的阵列基板的至少两组移位寄存器电路中的每组移位寄存器电路发送控制信号；
    所述每组移位寄存器电路中的各所述移位寄存器电路接收所述控制信号，并沿第一方向向其耦接的扫描信号线传输扫描信号。
  16. 一种阵列基板的制备方法，包括：
    提供衬底基板；所述衬底基板包括第一面，所述第一面具有显示区；
    在所述第一面形成多条扫描信号线；所述多条扫描信号线中的每条扫描信号线沿第一方向延伸；
    在所述第一面的显示区内形成至少两组移位寄存器电路；所述至少两组移位寄存器电路中的每组移位寄存器电路包括沿第二方向设置的多个移位寄存器电路，所述多个移位寄存器电路中的每个移位寄存器电路与一条所述扫描信号线耦接；其中，所述第一方向与所述第二方向相交叉；
    其中，至少有一组所述移位寄存器电路设置于所述显示区的非边缘区域；设置于所述显示区的非边缘区域的所述移位寄存器电路被配置为，沿所述第一方向，向其两侧的所述扫描信号线传输扫描信号。
  17. 根据权利要求16所述的制备方法，其中，所述衬底基板还包括与所述第一面相对的第二面；
    所述制备方法还包括：
    在所述第二面上形成至少一个扇出结构；所述至少一个扇出结构中的每个扇出结构包括多条信号连接线，所述多条信号连接线中的每条信号连接线由所述第二面的边缘向所述第二面的非边缘区域延伸；所述信号连接线与所述移位寄存器电路耦接。
  18. 根据权利要求17所述的制备方法，所述制备方法还包括：
    在所述衬底基板的位于所述第一面和所述第二面之间的侧面上形成至少一个侧边结构；
    所述至少一个侧边结构与所述至少一个扇出结构一一对应；所述至少一个侧边结构中的每个侧边结构包括多条侧边连线，所述多条侧边连线中的每条侧边连线的一端与所述信号连接线耦接，另一端与所述移位寄存器电路耦接。
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