WO2021100199A1 - 半導体装置およびその製造方法ならびに電力変換装置 - Google Patents

半導体装置およびその製造方法ならびに電力変換装置 Download PDF

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Publication number
WO2021100199A1
WO2021100199A1 PCT/JP2019/045818 JP2019045818W WO2021100199A1 WO 2021100199 A1 WO2021100199 A1 WO 2021100199A1 JP 2019045818 W JP2019045818 W JP 2019045818W WO 2021100199 A1 WO2021100199 A1 WO 2021100199A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit pattern
conductive circuit
joint
semiconductor device
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/045818
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
哲 根岸
晃久 福本
仁 上村
吉典 横山
悠策 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2021558142A priority Critical patent/JP7237192B2/ja
Priority to PCT/JP2019/045818 priority patent/WO2021100199A1/ja
Publication of WO2021100199A1 publication Critical patent/WO2021100199A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device.
  • the terminal includes an external output terminal for outputting the controlled power to the outside.
  • an external output terminal for outputting the controlled power to the outside.
  • Patent Document 1 proposes an external output terminal provided with a protrusion mounted on an insulating substrate. By making the external output terminal self-supporting by the protrusions, the jig that was conventionally required is eliminated, and the joining process is simplified and the yield is improved.
  • One or more supports are connected to the joint and are located in a region other than the region where the joint is joined in the conductive circuit pattern in such a manner that they are in contact with the conductive circuit pattern, and the joint layer is interposed. Maintain the distance between the junction surface of the body and the conductive circuit pattern.
  • the terminal includes a joint including the joint surface and one or more supports that maintain a distance between the joint surface and the conductive circuit pattern, whereby the joint layer is provided.
  • the distance between the joint body and the conductive circuit pattern corresponding to the thickness of the joint layer is maintained, and the thickness of the joint layer becomes a desired thickness.
  • the reliability of the joint portion between the terminal and the conductive circuit pattern can be ensured, which contributes to the extension of the life of the semiconductor device. it can.
  • FIG. It is a top view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a front view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a side view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is a perspective view which shows an example of the terminal applied to the semiconductor device in the same embodiment. It is sectional drawing which shows one step of the manufacturing method of the semiconductor device in the same embodiment. It is sectional drawing which shows the process performed after the process shown in FIG. 6 in the same embodiment. It is sectional drawing which shows the process performed after the process shown in FIG. 7 in the same embodiment.
  • the insulating substrate 5 includes an insulating substrate main body 7, conductive circuit patterns 9a, 9b, 9c, and a heat radiating material 11.
  • the insulating substrate 5 has a first main surface and a second main surface that face each other.
  • the conductive circuit pattern 9a, the conductive circuit pattern 9b, and the conductive circuit pattern 9c are arranged on the side of the first main surface of the substrate main body 7 at intervals.
  • the heat radiating material 11 is arranged on the side of the second main surface of the substrate body 7.
  • the conductive circuit patterns 9a, 9b, 9c may be formed of a conductive material, and for example, a metal material such as copper (Cu) or aluminum (Al) is preferable.
  • the conductive material does not have to be a single conductive material and may be formed from, for example, an alloy. Further, the conductive circuit patterns 9a, 9b, 9c may have a multi-layer structure.
  • the heat radiating material 11 is joined to the base plate 3 by, for example, solder.
  • the heat radiating material 11 and the base plate 3 may be integrally formed of, for example, the same member.
  • heat radiating material 11 and the base plate 3 are formed of a single member, heat is dissipated without passing through the joint portion between the heat radiating material 11 and the base plate 3, as compared with the case where the heat radiating material 11 and the base plate 3 are formed of different members. Will be done. Therefore, the heat radiating material 11 and the base plate 3 formed of a single member are more preferable because the thermal resistance from the semiconductor element 15 to the back surface of the base plate 3 can be reduced.
  • the bonding layer 17 may be a conductive material, and a metal material such as solder, sintered silver (Ag), or sintered copper (Cu) is preferable.
  • the conductive material does not have to be a single conductive material and may be formed from, for example, an alloy. Further, the bonding layer 17 may have a multilayer structure.
  • the bonding layer 17 is, for example, solder
  • the bonding layer 17 solder
  • the thickness of the bonding layer 17 corresponds to the distance between the bonding surface 23a of the bonding body 23 and the conductive circuit pattern 9c. This thickness (distance) is preferably constant over the entire joint surface 23a.
  • the support 25 is arranged so as to be in contact with the conductive circuit pattern 9c.
  • the distance L (see FIG. 10) between the joint surface 23a and the conductive circuit pattern 9c is maintained in a state where the support 25 is in contact with the conductive circuit pattern 9c. That is, the support 25 has a function of holding a distance corresponding to the thickness of the bonding layer 17 at a constant distance.
  • a film may be appropriately formed on the surface of the conductive circuit pattern 9b by plating or the like, depending on the material to be the bonding material 13.
  • a silver (Ag) sintered body or a copper (Cu) sintered body is used as the material of the bonding material 13 13
  • appropriate pressure is applied to the surface of the semiconductor element 15 at the time of bonding to assist the bonding. You may try to do it.
  • the semiconductor element 15 and the conductive circuit pattern 9a are electrically connected by the conductive wire 19a using a wire bonding device (not shown).
  • the semiconductor element 15 and the conductive circuit pattern 9c are electrically connected by the conductive wire 19b.
  • the conductive wire 19a is joined to, for example, the gate electrode or sense (neither shown) of the semiconductor element 15.
  • the conductive wire 19b is joined to an electrode (not shown) from which the current of the semiconductor element 15 is output.
  • a frame may be bonded to the electrode to which the current is output.
  • the insulating substrate 5 on which the semiconductor element 15 is mounted is joined to the base plate 3.
  • a bonding material such as solder is placed on the base plate 3.
  • the insulating substrate 5 is placed on the bonding material using, for example, a jig (not shown).
  • the base plate 3 is put into a high-temperature furnace such as a reflow furnace, and the solder is melted in the high-temperature furnace. By solidifying the molten solder, the insulating substrate 5 is joined to the base plate 3.
  • each of the conductive circuit patterns 9a, 9b, and 9c is electrically connected to the outside.
  • a connection mode a direct coupling may be used in which the terminals and the conductive circuit pattern are bonded by a bonding layer using terminals.
  • indirect joining may be used in which the terminal and the conductive circuit pattern are joined via a wire.
  • the case 31 is filled with the insulating sealing material 33 for insulating sealing.
  • an insulating sealing material 33 such as gel or epoxy resin is filled so that no bubbles remain.
  • a high temperature treatment is appropriately performed to cure the insulating sealing material 33.
  • a lid (not shown) that covers the insulating sealing material 33 may be attached.
  • a lid such as PPS may be adhered to the case 31 using a silicone resin.
  • the shape of the external connection body 27 of the terminal 21 may be changed by bending the external connection body 27 of the terminal 21 according to the connection specifications with the outside, for example. In this way, the semiconductor device 1 shown in FIG. 1 is completed.
  • the support 25 also functions as a heat dissipation path. As shown in FIG. 14, the heat generated in the joint layer 17 is dissipated through three paths including the first heat dissipation path P1 and the second heat dissipation path P2 plus the third heat dissipation path P3.
  • the third heat dissipation path P3 flows from the joint layer 17 through the joint 23, then through the support 25, and from the support 25 through the portion of the conductive circuit pattern 9c located directly below the support 25, and flows through the base. This is a heat dissipation path that flows to the plate 3.
  • the support 25 becomes a part of the third heat dissipation path P3 and can contribute to the heat dissipation of the bonding layer 17.
  • the temperature of the bonding layer 17 can be effectively lowered.
  • the thermal stress generated in the bonding layer 17 and the like can be alleviated, and the deformation of the peripheral portion of the bonding layer 17 can be suppressed. As a result, it is possible to contribute to extending the life of the semiconductor device 1.
  • the number of supports 25 is not limited to one, and terminals 21 having a plurality of supports 25 may be applied. As shown in FIGS. 18, 19 and 20, for example, a terminal provided with three supports 25, a support 25a and 25b as the first part of the support and a support 25c as the second part of the support. 21 may be applied.
  • Embodiment 2 The semiconductor device according to the second embodiment will be described. As shown in FIG. 21, in the semiconductor device 1, the bonding layer 17 is formed so as to surround the support 25 from a region where the bonding 23 is bonded to the conductive circuit pattern 9c to a region where the support 25 is located. There is. Since the other configurations are the same as those of the semiconductor device 1 shown in FIG. 1 and the like, the same members are designated by the same reference numerals, and the description thereof will not be repeated unless necessary.
  • the power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 28, the power conversion device 200 has a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And have.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2019/045818 2019-11-22 2019-11-22 半導体装置およびその製造方法ならびに電力変換装置 Ceased WO2021100199A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021558142A JP7237192B2 (ja) 2019-11-22 2019-11-22 半導体装置およびその製造方法ならびに電力変換装置
PCT/JP2019/045818 WO2021100199A1 (ja) 2019-11-22 2019-11-22 半導体装置およびその製造方法ならびに電力変換装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/045818 WO2021100199A1 (ja) 2019-11-22 2019-11-22 半導体装置およびその製造方法ならびに電力変換装置

Publications (1)

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WO2021100199A1 true WO2021100199A1 (ja) 2021-05-27

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WO (1) WO2021100199A1 (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017188528A (ja) * 2016-04-04 2017-10-12 三菱電機株式会社 半導体装置
JP2018160618A (ja) * 2017-03-23 2018-10-11 株式会社三社電機製作所 外部導出用自立端子及び半導体モジュールの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7238277B2 (ja) 2018-06-14 2023-03-14 富士電機株式会社 半導体装置、リードフレーム及び半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017188528A (ja) * 2016-04-04 2017-10-12 三菱電機株式会社 半導体装置
JP2018160618A (ja) * 2017-03-23 2018-10-11 株式会社三社電機製作所 外部導出用自立端子及び半導体モジュールの製造方法

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