WO2021098077A1 - 一种真随机数发生器和真随机数发生方法 - Google Patents

一种真随机数发生器和真随机数发生方法 Download PDF

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WO2021098077A1
WO2021098077A1 PCT/CN2020/077067 CN2020077067W WO2021098077A1 WO 2021098077 A1 WO2021098077 A1 WO 2021098077A1 CN 2020077067 W CN2020077067 W CN 2020077067W WO 2021098077 A1 WO2021098077 A1 WO 2021098077A1
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random number
circuit
ring oscillator
multiplexer
sampling
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PCT/CN2020/077067
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English (en)
French (fr)
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鹿益铭
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深圳市纽创信安科技开发有限公司
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Publication of WO2021098077A1 publication Critical patent/WO2021098077A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes

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  • the invention relates to the technical field of information security, in particular to a true random number generator and a true random number generation method.
  • True random numbers are commonly used in cryptographic operation scenarios. To generate a true random number, a true random number generator is required. Unlike the pseudo-random number generator, the true random number generator needs to use a physical noise source. One of the most commonly used sources of physical noise at present is to use a ring oscillator to sample the output of the ring oscillator with a sampling clock. Affected by external noise, the waveform generated by the ring oscillator has jitter, and a true random number can be generated after digital processing. Since the output entropy of a single-channel ring oscillator is relatively low, multiple ring oscillators are usually used for sampling to increase the entropy of the output.
  • Ring oscillators are usually built using inverters.
  • the multiple ring oscillators will use the same number of inverters, that is, the cycles of the multiple ring oscillators are relatively close.
  • the frequency of some ring oscillators may be interlocked, resulting in a stable phase difference of the interlocked ring oscillators, and the output results will not produce random effects after XOR processing.
  • the general way to deal with this problem is to manually disperse the ring oscillators in various parts of the chip during placement and routing, but this increases the difficulty of back-end placement and routing.
  • the embodiment of the present invention provides a true random number generator and a true random number generation method, which can automatically adjust the configuration of the true random number generator and generate a high-quality random number sequence without increasing the difficulty of back-end layout and wiring. high.
  • an embodiment of the present invention provides a true random number generator, including: a configuration selection circuit, a ring oscillator circuit array, a clock sampling array, an exclusive OR circuit, and a random number statistical analysis circuit connected in sequence; the random number statistical analysis circuit; The feedback output terminal of the analysis circuit is connected with the input terminal of the configuration selection circuit; wherein, the ring oscillator circuit array includes a plurality of ring oscillator circuits; the clock sampling array includes a circuit with the plurality of ring oscillators A plurality of flip-flops corresponding to the circuit; the plurality of flip-flops are used to respectively sample the signals of the plurality of ring oscillator circuits according to the sampling clock; the sampling clock is controlled by the configuration selection circuit; the exclusive OR circuit , Used to perform an exclusive OR operation on the sampling results of the clock sampling array, and send the random number sequence generated by the operation to the random number statistical analysis circuit; the random number statistical analysis circuit is used to analyze the random number sequence and The analysis conclusion is fed back to the configuration selection circuit;
  • the analysis conclusion includes random number sequence quality information; the random number statistical analysis circuit is further configured to output the random number sequence if the random number sequence quality information meets a preset requirement.
  • the ring oscillator circuit includes: an inverter link and a multiplexer; the inverter link includes an odd number of inverters connected in series; the control of the multiplexer Terminal is connected to the configuration selection circuit to receive control information of the configuration selection circuit; multiple selection terminals of the multiplexer are respectively connected to different positions of the inverter link; the output of the multiplexer The terminal is connected to the end of the inverter link; the enable closing terminal of the multiplexer is left empty; thereby forming a loop of the ring oscillator circuit with the inverter link.
  • the configuration selection circuit sends control information to adjust the configuration of the true random number generator, including at least one of the following ways: sending quantity control information To the multiplexer in the ring oscillator circuit array to control the number of turn-on of the multiple ring oscillator circuits; send length control information to the multiplexer in the ring oscillator circuit array to control The length of the multiple ring oscillator circuits; sending clock control information to the clock sampling array to adjust the sampling clock.
  • the true random number generator further includes a post-processing circuit for post-processing the output random number sequence.
  • the embodiment of the present invention provides a true random number generation method, which is applied to a true random number generator, and the true random number generator includes a configuration selection circuit, a ring oscillator circuit array, a clock sampling array, An exclusive OR circuit and a random number statistical analysis circuit; the feedback output terminal of the random number statistical analysis circuit is connected to the input terminal of the configuration selection circuit; the method includes: sampling, using a clock sampling array, and respectively performing a loop operation according to the sampling clock In the oscillator circuit array, the signals of at least two ring oscillator circuits are sampled; the exclusive OR operation is performed by the exclusive OR circuit to perform the exclusive OR operation on the sampling results to generate a random number sequence; the statistical analysis is performed by the random number statistical analysis circuit.
  • the analysis conclusion includes random number sequence quality information; if it meets, the random number sequence is output; if it does not meet, then Send control information through the configuration selection circuit to adjust the configuration of the true random number generator, and repeat the steps of sampling, exclusive-or operation, and statistical analysis until the random number sequence meets the preset requirements;
  • the adjustment methods include the following At least one: adjusting the number of turn-on of the plurality of ring oscillator circuits; adjusting the length of the plurality of ring oscillator circuits; and adjusting the sampling clock.
  • the ring oscillator circuit includes: a loop of a ring oscillator circuit composed of an inverter link and a multiplexer; wherein, the inverter link is composed of an odd number of inverter links connected in series.
  • the multiplexer consists of an enable/close end that is left blank, a control end for receiving control information, and multiple selection ends connected to different positions of the inverter link.
  • the adjusting the number of openings of the multiple ring oscillator circuits is specifically: sending number control information to the control end of the multiplexer to control the multiplexer selection enable and close end , Thereby disconnecting the ring oscillator circuit; or, controlling the multiplexer to select any selection terminal to maintain the ring oscillator circuit on.
  • the adjusting the lengths of the multiple ring oscillator circuits is specifically: sending length control information to the control end of the multiplexer to control the multiplexer to select one of the multiple selection ends One is to connect the corresponding positions of the inverter link to adjust the length of the multiple ring oscillator circuits.
  • the clock sampling array includes a plurality of flip-flops corresponding to the plurality of ring oscillator circuits; the plurality of flip-flops are used to sample the signals of the plurality of ring oscillator circuits respectively according to the sampling clock ; Adjusting the sampling clock is specifically: sending a new clock signal to the clock input of the flip-flop to replace the original sampling clock.
  • the method for generating a true random number further includes: post-processing, performing post-processing on the output random number sequence in a preset manner; the preset manner includes: parity check, von Neumann correction, One or more of XOR chain, hash function, Fourier transform, and shift register.
  • a plurality of ring oscillator circuits are arranged in an array, and the random number sequence can be analyzed by the random number statistical analysis circuit and the analysis conclusion is fed back to the configuration selection circuit; the configuration selection circuit is based on the analysis conclusion of the random number statistical analysis circuit , Send control information to adjust the configuration of the true random number generator.
  • the configuration of the true random number generator can be automatically adjusted without increasing the difficulty of back-end layout and wiring, and high-quality random number sequences can be generated with high efficiency.
  • FIG. 1 is a schematic diagram of an embodiment of a true random number generator provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the ring oscillator circuit array in the embodiment corresponding to FIG. 1;
  • Fig. 3 is a schematic diagram of an embodiment of a method for generating a true random number disclosed in an embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an embodiment of a true random number generator according to an embodiment of the present invention.
  • the true random number generator includes a configuration selection circuit 11, a ring oscillator circuit array 12, a clock sampling array 13, an exclusive OR circuit 14, and a random number statistical analysis circuit 15 which are connected in sequence;
  • the feedback output terminal of the circuit 15 is connected to the input terminal of the configuration selection circuit 11 to form a feedback loop 16.
  • the circuit at the connection between the configuration selection circuit 11 and the ring oscillator array 12 is added with "/" to indicate that there can be more than one connection line here, because there can be multiple rings in the corresponding ring oscillator array 12.
  • the ring oscillator array 12 schematically shows three ring oscillator circuits, but the embodiment of the present invention does not limit the number of ring oscillator circuits. Therefore, it is expressed by a vertical ellipsis, and there can be more ring oscillators.
  • the device circuit can also be less.
  • the ring oscillator circuit array 12, the clock sampling array 13, and the exclusive OR circuit 14 are surrounded by a dashed frame to facilitate the description of their respective functions, and it is understandable that they are not necessarily individually packaged modules.
  • each ring oscillator circuit in the ring oscillator array 12 includes an inverter and a data selector.
  • the "" or "" between the inverters means that the embodiment is not limited.
  • the 0 end of the data selector indicates that it is enabled and closed.
  • the ring oscillator circuit itself in the ring oscillator circuit array 12 will be further described in subsequent embodiments.
  • the clock sampling array 13 includes a plurality of flip-flops 1301 corresponding to the plurality of ring oscillator circuits; the plurality of flip-flops 1301 are used to respectively sample the signals of the plurality of ring oscillator circuits according to the sampling clock Fs input to the CLK terminal D is the signal input terminal, Q is the sampling output terminal; the sampling clock Fs is controlled by the configuration selection circuit 11; there is also a vertical ellipsis in the clock sampling array 13 to indicate that the number of flip-flops 1301 is not limited , The number corresponds to the number of ring oscillator circuits in the ring oscillator array 12.
  • the flip-flop 1301 is a D flip-flop.
  • the exclusive OR circuit 14 is used to perform an exclusive OR operation on the sampling results of the clock sampling array 13 and send the random number sequence generated by the operation to the random number statistical analysis circuit 15; of course, as shown in FIG. 1, the exclusive OR operation As a result, a corresponding trigger is also sampled, and then sent to the random number statistical analysis circuit 15.
  • the random number statistical analysis circuit 15 is used to analyze the random number sequence it receives and feed back the analysis conclusion to the configuration selection circuit 11 through the feedback loop 16; the analysis conclusion contains random number quality information, which can reflect the entropy of the true random number generator.
  • the configuration selection circuit 11 sends control information to adjust the configuration of the true random number generator according to the analysis conclusion of the random number statistical analysis circuit 15.
  • the control information may include control of the sampling clock Fs and control of the number or length of ring oscillators in the ring oscillator array, so as to achieve adaptive adjustment of entropy, and then adjust the quality of the random number sequence.
  • the random number statistical analysis circuit 15 analyzes that the received random number sequence quality information meets the preset requirements, the random number sequence is output. In this case, the configuration selection circuit 11 no longer adjusts the configuration, and the entire true random number generator can work according to the current state.
  • FIG. 2 is a schematic diagram of the ring oscillator array in the embodiment corresponding to FIG. 1 to further explain the ring oscillator circuit array 12.
  • the ring oscillator circuit array 12 includes a plurality of ring oscillator circuits, and each ring oscillator circuit includes an inverter link formed by a plurality of inverters 1201 connected in series and The multiplexer 1202; the control terminal EN of the multiplexer 1202 is connected to the configuration selection circuit 11 shown in FIG. 1 to receive the control information of the configuration selection circuit 11; the multiplexer 1202 multiple choices Terminals 1, 2, and 3 are respectively connected to different positions of the inverter link; different positions can be set according to actual needs. In some embodiments, any two of the different positions are adjacent to each other. Between, the number of inverters is equal.
  • the multiplexer in Figure 1 and Figure 2 has three selection terminals, but in practical applications, the number of selection terminals can be more or less. In some specific implementations, 8 out of 1 can be used. Road selector.
  • the output terminal OUT of the multiplexer 1202 is connected to the end of the inverter link; the enable close terminal 0 of the multiplexer 1202 is left blank; the end of the inverter link is connected To clock sampling array 13.
  • the loop of each ring oscillator circuit is constituted by a plurality of inverters 1201 and multiplexers 1202.
  • the multiplexer 1202 can control the connection according to the length control information sent by the configuration selection circuit 11. Pass a certain selection terminal, and then control the length of multiple ring oscillator circuits. Also, because the enable closing terminal 0 of the multiplexer 1202 is empty, that is, when the multiplexer selects the enable closing terminal 0, the corresponding ring oscillator circuit is disconnected, so that the number sent by the circuit 11 can be selected according to the configuration Control information to adjust the number of openings of multiple ring oscillator circuits.
  • the end of the inverter link formed by the series connection of a plurality of inverters 1201 is connected to the clock sampling array 13.
  • the configuration selection circuit 11 can send clock control information to adjust the sampling clock Fs.
  • the flip-flop corresponding to each ring oscillator circuit performs sampling according to the sampling clock Fs.
  • the true random number generator further includes a post-processing circuit for post-processing the output random number sequence.
  • Post-processing methods include: one or more of parity check, von Neumann correction, XOR chain, hash function, Fourier transform, shift register
  • a plurality of ring oscillator circuits are arranged in an array, and the random number sequence can be analyzed by the random number statistical analysis circuit 15 and the analysis conclusion can be fed back to the configuration selection circuit 11; the configuration selection circuit 11 performs statistical analysis based on the random number
  • the analysis conclusion of circuit 15 is to send control information to adjust the configuration of the true random number generator; and the control information can include at least one of clock control information, length control information, and quantity control information to achieve control of the sampling clock Fs and control of the ring
  • the number or length of the ring oscillators in the oscillator array is controlled so as to achieve adaptive adjustment of entropy, and then automatically adjust the quality of the random number sequence to generate a high-quality random number sequence with high efficiency; and since the length of the ring oscillator can be automatically adjusted
  • the adaptation adjustment control also avoids the occurrence of some ring oscillators interlocking, and it is not necessary to disperse the ring oscillators, and does not increase the difficulty of back-end layout and wiring.
  • FIG. 3 is a schematic diagram of an embodiment of a method for generating a true random number disclosed in an embodiment of the present invention.
  • the true random number generation method is applied to the true random number generator described in the foregoing embodiment. It includes the steps: S301, sampling, sampling the signals of at least two ring oscillator circuits in the ring oscillator circuit array according to the sampling clocks by using the clock sampling array; S302, exclusive OR operation, sampling the samples through the exclusive OR circuit As a result, an exclusive OR operation is performed to generate a random number sequence; S303, statistical analysis, through the random number statistical analysis circuit, statistically analyze whether the random number sequence meets the preset requirements, and feed back the analysis conclusion to the configuration selection circuit; the analysis conclusion includes Random number sequence quality information; if it matches, execute step S304 to output the random number sequence; if not, execute step S305 to send control information through the configuration selection circuit to adjust the configuration of the true random number generator; and The steps S301, S302, and S303 are repeated until the random number sequence meets the preset requirements and is output.
  • the adjustment method includes at least one of the following: adjusting the number of turn-on of the plurality of ring oscillator circuits; adjusting the length of the plurality of ring oscillator circuits; and adjusting the sampling clock.
  • the selection circuit 11 by configuring the selection circuit 11 to send control information to adjust the number of turn-on of the multiple ring oscillator circuits, specifically: sending the number control information to the control end EN of the multiplexer 1202 to control the multiplexer.
  • the selector 1202 selects the enable terminal 0 to disconnect the ring oscillator circuit; or, controls the multiplexer to select any one of the selected terminals to maintain the ring oscillator circuit on.
  • the configuration selection circuit 11 sends control information to adjust the length of the multiple ring oscillator circuits, specifically: sending length control information to the control end EN of the multiplexer 1202 to control the multiplexer to select multiple One of the selection terminals 1, 2, and 3 is connected to the corresponding position of the inverter link, thereby adjusting the length of the multiple ring oscillator circuits.
  • the configuration selection circuit 11 sends control information to adjust the sampling clock Fs, specifically: sending a new clock signal to the clock input terminal CLK of the flip-flop to replace the original sampling clock.
  • the embodiment further includes a post-processing step of performing post-processing on the output random number sequence in a preset manner; the preset manner includes: parity, von Neumann correction, XOR One or more of chain, hash function, Fourier transform, shift register.
  • the concept of entropy level is introduced, and the statistical analysis result of the random number statistical analysis circuit 15 fails, that is, the random number sequence does not meet the preset requirements, and the selection circuit 11 is configured to increase an entropy level.
  • the entropy level is divided into three categories: sampling clock frequency, the number of ring oscillator circuits turned on, and the length configuration of the ring oscillator circuit. Among them, the higher the frequency division multiple of the clock frequency, the higher the entropy level; the more the ring oscillator circuit is turned on, the higher the entropy level; the longer the length of the ring oscillator circuit, the higher the entropy level.
  • the configuration selection circuit 11 in some embodiments, in the initial stage, it can be configured to a lower entropy level. According to the statistical analysis result of the random number statistical analysis circuit 15, if the statistical analysis result passes, the current configuration is maintained; , Then increase the entropy level one by one.
  • the statistical analysis method uses two types of tests: frequency test and poker test, and 256 WORD is used as a sample size.
  • frequency test if the number of 1 is between 4014 and 4018 in the 256WORD sample, it is a single pass; in the poker test, 4bit is a hexadecimal number.
  • 256WORD sample each If the arrangement occurs between 96 and 160 times, it is a single pass; in the same statistical analysis test, if any one of the frequency test and the poker test fails, the statistical analysis test fails.
  • the configuration selection circuit 11 Under the same configuration of the configuration selection circuit 11, perform three statistical analysis tests. If the failure of the three times is more than 1 time, that is, the quality of the random number sequence does not meet the preset standard and cannot meet the preset requirements, and the analysis conclusion is fed back to the configuration selection circuit 11. To increase the entropy level.
  • the selection circuit 11 is configured to increase two entropy levels at a time.
  • a plurality of ring oscillator circuits are arranged in an array, and the random number sequence can be analyzed by the random number statistical analysis circuit 15 and the analysis conclusion can be fed back to the configuration selection circuit 11; the configuration selection circuit 11 performs statistical analysis based on the random number
  • the analysis conclusion of circuit 15 is to send control information to adjust the configuration of the true random number generator; and the control information can include at least one of clock control information, length control information, and quantity control information to achieve control of the sampling clock Fs and control of the ring
  • the number or length of the ring oscillators in the oscillator array is controlled to achieve adaptive adjustment of the entropy level, and then automatically adjust the quality of the random number sequence to generate a high-quality random number sequence with high efficiency; and because the length of the ring oscillator can be realized
  • the self-adaptive adjustment control also avoids the occurrence of some ring oscillators interlocking. It is not necessary to disperse the ring oscillators, and does not increase the difficulty of back-end layout and wiring
  • the current configuration is maintained without increasing the entropy level. While the quality of the random number sequence is guaranteed, the power consumption of the true random number generator is minimized.

Abstract

一种真随机数发生器和真随机数发生方法。多个环形振荡器电路（12）以阵列方式排布，且能够通过随机数统计分析电路（15）分析随机数序列并反馈（16）分析结论至配置选择电路（11），配置选择电路（11）根据随机数统计分析电路（15）的分析结论，发送控制信息调整真随机数发生器的配置。通过该真随机数发生器和真随机数发生方法，在不增加后端布局布线难度的情况下，能够自动调节真随机数发生器配置，生成高质量的随机数序列，效率高。

Description

一种真随机数发生器和真随机数发生方法 技术领域
本发明涉及信息安全技术领域，尤其涉及一种真随机数发生器和真随机数发生方法。
背景技术
真随机数普遍应用于密码运算场景。产生真随机数需要使用真随机数发生器。和伪随机数发生器不同的是，真随机数发生器需要使用物理噪声源。目前最常用的物理噪声源之一是使用环形振荡器环形振荡器，用采样时钟采样环形振荡器的输出。受到外界噪声的影响，环形振荡器产生的波形存在抖动，数字化处理后即可产生真随机数。由于单路环形振荡器输出的熵比较低，通常会使用多路环形振荡器采样，以增加输出的熵。
环形振荡器通常使用反相器进行搭建。在使用设计中，为了方便后端布局布线，多路环形振荡器会采用相同反相器数量，即多路环形振荡器的周期较为接近。当周期比较接近的不同环形振荡器环进行震荡时，可能会出现部分环形振荡器频率互锁的情况，导致互锁的环形振荡器相位差稳定，输出结果异或处理后不产生随机效果。一般处理这个问题的方法是，在布局布线时手动将环形振荡器分散在芯片的各个部分，但这增加了后端布局布线的难度。
此外，现有设计中，若产生的随机数序列无法达到要求，则需设计人员重新规划设计，以增强熵，改善随机数序列的质量，效率低下，缺乏自动调节的手段。
发明内容
本发明实施例提供一种真随机数发生器和真随机数发生方法，在不增加后端布局布线难度的情况下，能够自动调节真随机数发生器配置，生成高质量的随机数序列，效率高。
一方面，本发明实施例提供一种真随机数发生器，包括：依次连接的配置选择电路，环形振荡器电路阵列，时钟采样阵列，异或电路，随机数统计分析电路；所述随机数统计分析电路的反馈输出端与所述配置选择电路的输入端连接；其中，所述环形振荡器电路阵列，包括多个环形振荡器电路；所述时钟采样阵列，包括与所述多个环形振荡器电路所对应的多个触发器；所述多个触发器用于以根据采样时钟分别对多个环形振荡器电路的信号进行采样；所述采样时钟受所述配置选择电路控制；所述异或电路，用于将所述时钟采样阵列的采样结果进行异或运算，并将运算产生的随机数序列发送至随机数统计分析电路；所述随机数统计分析电路，用于分析所述随机数序列并反馈分析结论至配置选择电路；所述配置选择电路，用于根据所述随机数统计分析电路的分析结论，发送控制信息调整所述真随机数发生器的配置。
可选的，所述分析结论，包含随机数序列质量信息；所述随机数统计分析电路还用于，若所述随机数序列质量信息符合预设要求，则输出所述随机数序列。
可选的，所述环形振荡器电路，包括：反相器链路和多路选择器；所述反相器链路，包括串联连接的奇数个反相器；所述多路选择器的控制端连接所述配置选择电路以接收所述配置选择电路的控制信息；所述多路选择器多个选择端分别连接至所述反相器链路的不同位置；所述多路选择器的输出端连接至所述反相器链路的末尾；所述多路选择器的使能关闭端置空；从而与所述反相器链路构成环形振荡器电路的回路。
可选的，所述配置选择电路，根据所述随机数统计分析电路的分析结论，发送控制信息调整所述真随机数发生器的配置，包括通过以下方式中的至少一种：发送数量控制信息至所述环形振荡器电路阵列中的多路选择器，以控制所述多个环形振荡器电路的开启数量；发送长度控制信息至所述环形振荡器电路阵列中的多路选择器，以控制所述多个环形振荡器电路的长度；发送时钟控制信息至所述时钟采样阵列，以调整采样时钟。
可选的，真随机数发生器还包括后处理电路，用于对输出的所述随机数序列进行后处理。
另一方面，本发明实施例提供一种真随机数发生方法，应用于真随机数发生器，所述真随机数发生器包括依次连接的配置选择电路、环形振荡器电 路阵列、时钟采样阵列、异或电路以及随机数统计分析电路；所述随机数统计分析电路的反馈输出端与所述配置选择电路的输入端连接；所述方法包括：采样，通过时钟采样阵列，根据采样时钟分别对环形振荡器电路阵列中，至少两个环形振荡器电路的信号进行采样；异或运算，通过异或电路将所述采样结果进行异或运算产生随机数序列；统计分析，通过随机数统计分析电路统计分析所述随机数序列是否符合预设要求，并反馈分析结论至所述配置选择电路；所述分析结论包含随机数序列质量信息；若符合，则输出所述随机数序列；若不符合，则通过配置选择电路发送控制信息以调整所述真随机数发生器的配置，并重复所述采样、异或运算和统计分析的步骤，直至所述随机数序列符合预设要求；调整的方式包括以下至少一种：调整所述多个环形振荡器电路的开启数量；调整所述多个环形振荡器电路的长度；以及，调整所述采样时钟。
可选的，所述环形振荡器电路，包括：由反相器链路和多路选择器所构成的环形振荡器电路的回路；其中，所述反相器链路由串联的奇数个反相器组成；所述多路选择器包括置空的使能关闭端，用于接收控制信息的控制端，和连接到所述反相器链路不同位置的多个选择端。
可选的，所述调整所述多个环形振荡器电路的开启数量，具体为：发送数量控制信息至所述多路选择器的控制端，以控制所述多路选择器选择使能关闭端，从而断开环形振荡器电路；或，控制所述多路选择器选择任一选择 端而维持环形振荡器电路的开启。
可选的，所述调整所述多个环形振荡器电路的长度，具体为：发送长度控制信息至所述多路选择器的控制端，以控制所述多路选择器选择多个选择端的其中一个，连通所述反相器链路的相应位置，从而调整所述多个环形振荡器电路的长度。
可选的，所述时钟采样阵列，包括与所述多个环形振荡器电路所对应的多个触发器；所述多个触发器用于根据采样时钟分别对多个环形振荡器电路的信号进行采样；调整所述采样时钟，具体为：发送新的时钟信号至所述触发器的时钟输入端，替代原有的采样时钟。
可选的，真随机数发生方法，还包括：后处理，对输出的所述随机数序列以预设方式进行后处理；所述预设方式包括：奇偶校验、冯-诺伊曼矫正、异或链、哈希函数、傅里叶变换、移位寄存器中的一种或多种。
本发明实施例，多个环形振荡器电路以阵列方式排布，且能够通过随机数统计分析电路分析随机数序列并反馈分析结论至配置选择电路；配置选择电路根据随机数统计分析电路的分析结论，发送控制信息调整真随机数发生器的配置。通过实施本发明实施例，在不增加后端布局布线难度的情况下，能够自动调节真随机数发生器配置，生成高质量的随机数序列，效率高。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种真随机数发生器的实施例示意图；
图2为图1对应实施例中环形振荡器电路阵列的示意图；
图3为本发明实施例公开的一种真随机数发生方法的实施例示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参照图1，图1为本发明实施例提供的一种真随机数发生器的实施例示意图。
在本实施例中，真随机数发生器包括依次连接的配置选择电路11，环形振荡器电路阵列12，时钟采样阵列13，异或电路14，随机数统计分析电路 15；所述随机数统计分析电路15的反馈输出端与所述配置选择电路11的输入端连接，从而形成反馈回路16。
其中，如图1所示，配置选择电路11与环形振荡器阵列12连接处的电路加“/”是为示意此处连接线可以不止一条，因为对应环形振荡器阵列12中可以有多个环形振荡器电路。环形振荡器阵列12中示意性的展现出了3个环形振荡器电路，但本发明实施例并不限制环形振荡器电路的个数，因此以纵向的省略号表述，还可以有更多的环形振荡器电路，也可以更少。环形振荡器电路阵列12，时钟采样阵列13，异或电路14采用虚线框围起是为了方便说明它们各自的功能，且可以理解的是，它们并非必须是各自封装的模块。
先在此处说明，环形振荡器阵列12中的每个环形振荡器电路包括反相器和数据选择器，其中反相器之间的“……”或“…”表示本实施例并不限制环形振荡器电路的长度。数据选择器的0端表示其使能关闭端。关于环形振荡器电路阵列12中的环形振荡器电路本身，会在后续实施例中进行进一步描述。
时钟采样阵列13，包括与多个环形振荡器电路所对应的多个触发器1301；多个触发器1301用于以根据输入至CLK端的采样时钟Fs分别对多个环形振荡器电路的信号进行采样；D为信号输入端，Q为采样输出端；所述采样时钟Fs受所述配置选择电路11控制；时钟采样阵列13中亦有纵向的省略号，用 来表述对触发器1301的数量不加限制，其数量对应环形振荡器阵列12中的环形振荡器电路的数量。可选的，触发器1301为D触发器。
异或电路14，用于将所述时钟采样阵列13的采样结果进行异或运算，并将运算产生的随机数序列发送至随机数统计分析电路15；当然，如图1所示，异或运算的结果，也有相应的触发器进行采样，再发送至随机数统计分析电路15。
随机数统计分析电路15，用于分析其收到的随机数序列并通过反馈回路16反馈分析结论至配置选择电路11；分析结论包含随机数质量信息，可以体现真随机数发生器的熵。
配置选择电路11，则根据所述随机数统计分析电路15的分析结论，发送控制信息调整所述真随机数发生器的配置。控制信息可以包括对采样时钟Fs的控制以及对环形振荡器阵列中环形振荡器数量或长度的控制，从而达到自适应调整熵，继而调整随机数序列质量。
当然，如果随机数统计分析电路15分析其收到的随机数序列质量信息符合预设要求，则输出所述随机数序列。在这种情况下，配置选择电路11即不再调整配置，整个真随机数发生器可按照当前状态工作。
图2为图1对应实施例中环形振荡器阵列的示意图，以对环形振荡器电路阵列12做进一步的说明。
请同同时参阅图2和图1，环形振荡器电路阵列12包括多个环形振荡器 电路，而每个环形振荡器电路包括由多个反相器1201串接所构成的反相器链路和多路选择器1202；所述多路选择器1202的控制端EN连接图1中所示的配置选择电路11以接收所述配置选择电路11的控制信息；所述多路选择器1202多个选择端1、2、和3则分别连接至所述反相器链路的不同位置；不同的位置可以根据实际需要设置，在一些实施方式中，所述不同位置中的任两个相邻的位置之间，反相器的数量相等。需要说明的是，图1和图2中的多路选择器有三个选择端，但在实际应用中，选择端的数量可以更多或更少，在一些具体实施方案中，可使用8选1多路选择器。所述多路选择器1202的输出端OUT连接至所述反相器链路的末尾；所述多路选择器1202的使能关闭端0置空；所述反相器链路的末尾则接至时钟采样阵列13。如此，每个环形振荡器电路的回路通过多个反相器1201和多路选择器1202构成。由于多路选择器1202多个选择端1、2、和3分别连接至所述反相器链路的不同位置，从而使得多路选择器1202可以根据配置选择电路11发送的长度控制信息控制接通某一个选择端，继而控制多个环形振荡器电路的长度。又由于多路选择器1202的使能关闭端0置空，即，多路选择器选择使能关闭端0时，相应的环形振荡器电路被断开，从而可以根据配置选择电路11发送的数量控制信息，调整多个环形振荡器电路的开启数量。
由多个反相器1201串接所构成的反相器链路的末尾则接至时钟采样阵列13。而配置选择电路11则可发送时钟控制信息以调整采样时钟Fs，时钟 采样阵列13中，与每个环形振荡器电路对应的触发器，根据采样时钟Fs进行采样。
在一些实施方式中，真随机数发生器还包括后处理电路，用于对输出的所述随机数序列进行后处理。后处理的方式包括：奇偶校验、冯-诺伊曼矫正、异或链、哈希函数、傅里叶变换、移位寄存器中的一种或多种
通过本发明实施例，多个环形振荡器电路以阵列方式排布，且能够通过随机数统计分析电路15分析随机数序列并反馈分析结论至配置选择电路11；配置选择电路11根据随机数统计分析电路15的分析结论，发送控制信息调整真随机数发生器的配置；而控制信息可以包括时钟控制信息、长度控制信息及数量控制信息中的至少一种，来达成对采样时钟Fs控制以及对环形振荡器阵列中环形振荡器数量或长度的控制，从而达到自适应调整熵，继而自动调整随机数序列质量，生成高质量的随机数序列，效率高；且由于可对环形振荡器的长度实现自适应调整控制，也避免了部分环形振荡器互锁情况的发生，不必将环形振荡器分散布置，不增加后端布局布线难度。
请参阅图3，为本发明实施例公开的一种真随机数发生方法的实施例示意图。
本实施例中，真随机数发生方法应用于前述实施例所描述的真随机数发生器。包括步骤：S301、采样，通过时钟采样阵列，根据采样时钟分别对环形振荡器电路阵列中，至少两个环形振荡器电路的信号进行采样；S302、异 或运算，通过异或电路将所述采样结果进行异或运算产生随机数序列；S303、统计分析，通过随机数统计分析电路统计分析所述随机数序列是否符合预设要求，并反馈分析结论至所述配置选择电路；所述分析结论包含随机数序列质量信息；若符合，则执行步骤S304、输出所述随机数序列；若不符合，则执行步骤S305、通过配置选择电路发送控制信息以调整所述真随机数发生器的配置；并重复执行所述步骤S301、S302和S303，直至随机数序列符合预设要求而输出。
其中，调整方式包括以下至少一种：调整所述多个环形振荡器电路的开启数量；调整所述多个环形振荡器电路的长度；以及，调整所述采样时钟。
请同时参照图1、图2、和图3。
具体的，通过配置选择电路11发送控制信息调整所述多个环形振荡器电路的开启数量，具体为：发送数量控制信息至所述多路选择器1202的控制端EN，以控制所述多路选择器1202选择使能关闭端0，从而断开环形振荡器电路；或，控制所述多路选择器选择任一选择端而维持环形振荡器电路的开启。
通过配置选择电路11发送控制信息调整所述多个环形振荡器电路的长度，具体为：发送长度控制信息至所述多路选择器1202的控制端EN，以控制所述多路选择器选择多个选择端1、2、3的其中一个，连通所述反相器链路的相应位置，从而调整所述多个环形振荡器电路的长度。
通过配置选择电路11发送控制信息调整所述采样时钟Fs，具体为：发 送新的时钟信号至所述触发器的时钟输入端CLK，替代原有的采样时钟。
在具体实现中，实施例还包括后处理的步骤，对输出的所述随机数序列以预设方式进行后处理；所述预设方式包括：奇偶校验、冯-诺伊曼矫正、异或链、哈希函数、傅里叶变换、移位寄存器中的一种或多种。
由于前述实施例对真随机数发生器的描述已经涉及到本发明实施例的方法实施例的主要步骤，可以理解本方法实施例的主要步骤适用于前述实施例的真随机数发生器，因此不再多加赘述。
以下进一步说明本发明实施例中，配置选择电路11和随机数统计分析电路15的工作方式。
在本发明实施例中，引入熵等级的概念，随机数统计分析电路15的统计分析结果不通过，即随机数序列不符合预设要求，则通过配置选择电路11提高一个熵等级。而熵等级分为三大类：采样时钟频率，开启环形振荡器电路的数量，以及环形振荡器电路的长度配置。其中，时钟频率分频倍数越高，则熵等级越高；环形振荡器电路开启数量越多，熵等级越高；环形振荡器电路的长度越长，熵等级越高。
对于配置选择电路11，一些实施方式中，在初始阶段，可配置为较低的熵等级，根据随机数统计分析电路15的统计分析结果，若统计分析结果通过，则保持当前配置；若不通过，则逐个提高熵等级，例如，首先逐次提高环形振荡器电路的长度，每次提高长度为提升一个熵等级；当环形振荡器电路的 长度已提高至最长，统计分析结果仍不通过，则增多开启环形振荡器电路的数量，每增多一个环形振荡器电路的开启，为提升一个熵等级；当开启环形振荡器电路的数量达到最多，统计分析结果仍不通过，则逐步提升采样时钟频率的分频倍数，每提升一次采样时钟频率的分频倍数，则为提升一个熵等级。依此类推，直至统计分析结果通过，则维持通过时的配置。
需要说明的是，提高环形振荡器电路的长度，增多开启环形振荡器电路的数量，提升采样时钟频率的分频倍数这三种方式的执行顺序并非一成不变，可以根据实际需要调整具体实施时的顺序。
对于随机数统计分析电路15，在一些实施方式中，统计分析方式使用频数测试和扑克测试两种测试，采用256WORD为一个样本量。在频数测试中，1的数量在这256WORD的样本中为4014至4018之间，则为单项通过；在扑克测试中，以4bit为一个十六进制数，在这256WORD的样本中，每种排列情况出现在96至160次之间，则为单项通过；在同一统计分析测试中，频数测试和扑克测试有任一项不通过，则该次统计分析测试不通过。
在配置选择电路11的同一配置下，进行三次统计分析测试，若三次中不通过为1次以上，即随机数序列质量不达预设标准，不能满足预设要求，反馈分析结论至配置选择电路11，以提升熵等级。
通过随机数统计分析电路15重复以上统计分析并反馈的步骤，以及配置选择电路11重复以上提升熵等级的步骤。
若在配置选择电路11的某一配置下，进行的三次统计分析，失败次数在1次以内，则对该配置进行进一步的大量验证，即，进行64次统计分析的测试，若这64次中共计失败6次以上，则说明随机数序列质量不达预设标准，不能满足预设要求，需通过配置选择电路11继续提升熵等级。这种情况下，为保证随机数序列尽可能满足随机数统计分析电路15的统计分析测试，通过配置选择电路11每次提升两个熵等级。
以上对次数的说明，和每次提升熵等级数量的说明仅为举例，并非本发明实施例的限制。
通过本发明实施例，多个环形振荡器电路以阵列方式排布，且能够通过随机数统计分析电路15分析随机数序列并反馈分析结论至配置选择电路11；配置选择电路11根据随机数统计分析电路15的分析结论，发送控制信息调整真随机数发生器的配置；而控制信息可以包括时钟控制信息、长度控制信息及数量控制信息中的至少一种，来达成对采样时钟Fs控制以及对环形振荡器阵列中环形振荡器数量或长度的控制，从而达到自适应调整熵等级，继而自动调整随机数序列质量，生成高质量的随机数序列，效率高；且由于可对环形振荡器的长度实现自适应调整控制，也避免了部分环形振荡器互锁情况的发生，不必将环形振荡器分散布置，不增加后端布局布线难度。
另外，由于当随机数序列符合预设要求后，即维持当前配置而不再提高熵等级，在保证了随机数序列的质量的情况下，还达成了真随机数发生器功 耗的最小化。
本领域普通技术人员可以理解上述实施例的方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于芯片或I P模块的可读存储介质中。
本发明实施例的方法的步骤顺序可以根据实际需要进行调整、合并或删减，且顺序不作为限制；本发明实施例的真随机数发生器的各组件可以根据实际需要进行整合，进一步添加、划分或删减，均应属于本发明保护范围。
以上对本发明实施例公开的一种真随机数发生器和真随机数发生方法进行了详细的介绍，本文中应用了具体实例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想，而不是对本发明的范围的限制。同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均可能会有改变之处，亦应属本发明保护范围。

Claims (11)

  1. 一种真随机数发生器，其特征在于，包括：依次连接的配置选择电路，环形振荡器电路阵列，时钟采样阵列，异或电路，随机数统计分析电路；所述随机数统计分析电路的反馈输出端与所述配置选择电路的输入端连接；其中，
    所述环形振荡器电路阵列，包括多个环形振荡器电路；
    所述时钟采样阵列，包括与所述多个环形振荡器电路所对应的多个触发器；所述多个触发器用于以根据采样时钟分别对多个环形振荡器电路的信号进行采样；所述采样时钟受所述配置选择电路控制；
    所述异或电路，用于将所述时钟采样阵列的采样结果进行异或运算，并将运算产生的随机数序列发送至随机数统计分析电路；
    所述随机数统计分析电路，用于分析所述随机数序列并反馈分析结论至配置选择电路；
    所述配置选择电路，用于根据所述随机数统计分析电路的分析结论，发送控制信息调整所述真随机数发生器的配置。
  2. 根据权利要求1所述的真随机数发生器，其特征在于，所述分析结论，包含随机数序列质量信息；所述随机数统计分析电路还用于，若所述随机数序列质量信息符合预设要求，则输出所述随机数序列。
  3. 根据权利要求2所述的真随机数发生器，其特征在于，所述环形振荡器电路，包括：反相器链路和多路选择器；
    所述反相器链路，包括串联连接的奇数个反相器；
    所述多路选择器的控制端连接所述配置选择电路以接收所述配置选择电路的控制信息；所述多路选择器多个选择端分别连接至所述反相器链路的不同位置；所述多路选择器的输出端连接至所述反相器链路的末尾；所述多路选择器的使能关闭端置空；从而与所述反相器链路构成环形振荡器电路的回路。
  4. 根据权利要求3所述的真随机数发生器，其特征在于，所述配置选择电路，根据所述随机数统计分析电路的分析结论，发送控制信息调整所述真随机数发生器的配置，包括通过以下方式中的至少一种：
    发送数量控制信息至所述环形振荡器电路阵列中的多路选择器，以控制所述多个环形振荡器电路的开启数量；
    发送长度控制信息至所述环形振荡器电路阵列中的多路选择器，以控制所述多个环形振荡器电路的长度；
    发送时钟控制信息至所述时钟采样阵列，以调整采样时钟。
  5. 根据权利要求2所述的真随机数发生器，其特征在于，还包括后处理 电路，用于对输出的所述随机数序列进行后处理。
  6. 一种真随机数发生方法，应用于真随机数发生器，其特征在于，所述真随机数发生器包括依次连接的配置选择电路、环形振荡器电路阵列、时钟采样阵列、异或电路以及随机数统计分析电路；所述随机数统计分析电路的反馈输出端与所述配置选择电路的输入端连接；
    所述方法包括：
    采样，通过时钟采样阵列，根据采样时钟分别对环形振荡器电路阵列中，至少两个环形振荡器电路的信号进行采样；
    异或运算，通过异或电路将所述采样结果进行异或运算产生随机数序列；
    统计分析，通过随机数统计分析电路统计分析所述随机数序列是否符合预设要求，并反馈分析结论至所述配置选择电路；所述分析结论包含随机数序列质量信息；
    若符合，则输出所述随机数序列；
    若不符合，则通过配置选择电路发送控制信息以调整所述真随机数发生器的配置，并重复所述采样、异或运算和统计分析的步骤，直至所述随机数序列符合预设要求；
    所述调整的方式包括以下至少一种：调整所述多个环形振荡器电路的开启数量；调整所述多个环形振荡器电路的长度；以及，调整所述采样时钟。
  7. 根据权利要求6所述的方法，其特征在于，所述环形振荡器电路，包括：由反相器链路和多路选择器所构成的环形振荡器电路的回路；其中，所述反相器链路由串联的奇数个反相器组成；所述多路选择器包括置空的使能关闭端，用于接收控制信息的控制端，和连接到所述反相器链路不同位置的多个选择端。
  8. 根据权利要求7所述的方法，其特征在于，所述调整所述多个环形振荡器电路的开启数量，具体为：发送数量控制信息至所述多路选择器的控制端，以控制所述多路选择器选择使能关闭端，从而断开环形振荡器电路；或，控制所述多路选择器选择任一选择端而维持环形振荡器电路的开启。
  9. 根据权利要求7所述方法，其特征在于，所述调整所述多个环形振荡器电路的长度，具体为：发送长度控制信息至所述多路选择器的控制端，以控制所述多路选择器选择多个选择端的其中一个，连通所述反相器链路的相应位置，从而调整所述多个环形振荡器电路的长度。
  10. 根据权利要求7所述的方法，其特征在于，所述时钟采样阵列，包括与所述多个环形振荡器电路所对应的多个触发器；所述多个触发器用于根据 采样时钟分别对多个环形振荡器电路的信号进行采样；
    调整所述采样时钟，具体为：发送新的时钟信号至所述触发器的时钟输入端，替代原有的采样时钟。
  11. 根据权利要求6所述的方法，其特征在于，还包括：
    后处理，对输出的所述随机数序列以预设方式进行后处理；所述预设方式包括：奇偶校验、冯-诺伊曼矫正、异或链、哈希函数、傅里叶变换、移位寄存器中的一种或多种。
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