WO2021085234A1 - Semiconductor module, power conversion apparatus, method for manufacturing semiconductor module, and method for manufacturing power conversion apparatus - Google Patents

Semiconductor module, power conversion apparatus, method for manufacturing semiconductor module, and method for manufacturing power conversion apparatus Download PDF

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Publication number
WO2021085234A1
WO2021085234A1 PCT/JP2020/039367 JP2020039367W WO2021085234A1 WO 2021085234 A1 WO2021085234 A1 WO 2021085234A1 JP 2020039367 W JP2020039367 W JP 2020039367W WO 2021085234 A1 WO2021085234 A1 WO 2021085234A1
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semiconductor module
metal film
insulating substrate
bonding material
semiconductor
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PCT/JP2020/039367
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French (fr)
Japanese (ja)
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辰則 柳本
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三菱電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • the technology disclosed in the specification of the present application relates to a semiconductor module, a power conversion device, a method for manufacturing a semiconductor module, and a method for manufacturing a power conversion device.
  • insulated gate bipolar transistors that is, IGBTs
  • metal-oxide-semiconductor transistors that is, MOSFET
  • a freewheeling diode connected in antiparallel to the switching device.
  • an IGBT made of a silicon (Si) semiconductor is used as a switching device, and a pin diode made of a Si semiconductor is used as a freewheeling diode.
  • SiC silicon carbide
  • SiC has a dielectric breakdown strength as high as about 10 times that of Si, and the thickness of the drift layer can be reduced to about 1/10 of Si. Therefore, it is possible to realize a low on-voltage of the semiconductor device, and it is also possible to operate in a high temperature environment.
  • a semiconductor device using SiC as a semiconductor material can be made smaller and more efficient than a conventional semiconductor device using Si as a semiconductor material.
  • Semiconductor devices for power conversion such as IGBTs, MOSFETs, and diodes are front-back conductive semiconductor devices in which the main current flows in the thickness direction of the semiconductor device.
  • the back electrode of the semiconductor device is soldered to the metal pattern of the ceramic substrate, and the front electrode of the semiconductor device is connected by wire bonding and soldering to the metal terminal. An energization path is formed.
  • Non-Patent Document 1 if abrupt load fluctuations occur repeatedly due to the operation of the power conversion device, temperature changes inside the module will occur repeatedly. Then, the solder sandwiched between the ceramic substrate and the base plate inside the power semiconductor module repeats volume expansion and contraction due to a temperature change, and cracks occur. Then, the crack lowers the heat dissipation of the entire power semiconductor module, which may lead to the module failure (see, for example, Non-Patent Document 1).
  • Patent Document 1 when joining an insulating member on which a power semiconductor element is mounted and a base plate, a convex step portion is provided on the solder joint surface of the base plate, so that the insulating member and the base plate are bonded to each other.
  • the thermal stress due to the difference in mutual thermal deformation is effectively relaxed, and the crack growth of the solder is suppressed.
  • the technique disclosed in the specification of the present application has been made in view of the problems described above, and is a technique for improving the heat dissipation performance of the semiconductor element provided on the insulating substrate.
  • the first aspect of the technique disclosed in the present specification is an insulating substrate provided with a conductor pattern on at least the upper surface, at least one semiconductor element provided on the upper surface of the conductor pattern, and a part of the lower surface of the insulating substrate.
  • the metal film is provided with a first bonding material provided in the above, and a metal film having a higher thermal conductivity than the first bonding material and provided on another part of the lower surface of the insulating substrate. It is provided on the lower surface of the insulating substrate at a position corresponding to the position where the semiconductor element is arranged.
  • the metal film is provided on the lower surface of the insulating substrate at the position corresponding to the position where the semiconductor element is arranged, the heat generated from the semiconductor element by the metal film is generated by the metal film. Efficient heat dissipation. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
  • FIG. 5 is a plan view of the configuration shown in FIG. 4 when viewed from the lower surface side (lower side of the paper surface in FIG. 4).
  • FIG. 5 is a cross-sectional view schematically showing another example of a part of the configuration of a power semiconductor module according to an embodiment.
  • FIG. 6 is a plan view of the configuration shown in FIG. 6 when viewed from the lower surface side (lower side of the paper surface in FIG. 6). It is sectional drawing which conceptually shows a part example of the structure of the semiconductor module for electric power with respect to embodiment.
  • FIG. 8 is a plan view of the configuration shown in FIG. 8 as viewed from the lower surface side (lower side of the paper surface in FIG. 8). It is a figure which conceptually shows the example of the structure of the power conversion system including the power conversion apparatus of embodiment.
  • the upper surface of " or “the lower surface of " in addition to the upper surface itself or the lower surface itself of the target component, the upper surface of the target component is added. Alternatively, it shall include a state in which other components are formed on the lower surface. That is, for example, when the description "B provided on the upper surface of the instep” is described, it does not prevent another component " ⁇ " from intervening between the instep and the second.
  • the expression "A and B are electrically connected" means that a current can flow in both directions between the configuration A and the configuration B.
  • FIG. 1 is a cross-sectional view schematically showing an example of the configuration of the power semiconductor module 100 according to the present embodiment.
  • FIG. 2 is a plan view of a part of the power semiconductor module 100 shown in FIG. 1 as viewed from the upper surface side (upper side of the paper surface in FIG. 1).
  • FIG. 1 corresponds to a cross-sectional view taken along the line ABA'of FIG. Further, in FIG. 2, the cover or sealing material for closing the opening, which is shown as an example in FIG. 1, is not shown.
  • the configuration of the power semiconductor module 100 will be described with reference to FIGS. 1 and 2.
  • the power semiconductor module 100 includes a base plate 101, a case 102, an insulating substrate 103, a semiconductor element 104, a wiring 106, a terminal 108, and a metal film 109. ing.
  • the case 102 is open on both the top surface side (upper side of the paper surface in FIG. 1) and the bottom surface side (lower side of the paper surface in FIG. 1).
  • the base plate 101 is joined to the case 102 with a resin material or the like, and is housed in the opening on the bottom surface side of the case 102.
  • the base plate 101 has the same shape and area as the opening on the bottom surface side of the case 102, and constitutes the bottom surface of the case 102.
  • the base plate 101 is made of, for example, a Cu plate or a composite material such as AlSiC or Cu—Mo. It is appropriate that the thickness of the base plate 101 is 5 mm or less, and if it has sufficient strength for use, it is more suitable that the thickness is thin.
  • a part of the upper surface of the base plate 101 is joined to a part of the lower surface of the insulating substrate 103 via the under-board bonding material 107b.
  • a part of the upper surface of the base plate 101 is subjected to a surface treatment that enhances the bondability with the under-board bonding material 107b, and for example, nickel (Ni) plating is formed.
  • the under-board bonding material 107b is, for example, a solder using tin (Sn) as a base material.
  • the substrate lower bonding material 107b may be an Ag sintered material or a bonding material for forming a liquid phase diffusion bonding layer, which will be described later.
  • the area other than the region where the insulating substrate 103 is bonded may be covered with a resin resist or the like so that the bonding material 107b under the substrate does not spread.
  • the case 102 is made of, for example, a polyphenyl sulfide resin (PPS), a polybutylene terephthalate resin (PBT), a polyethylene terephthalate resin (PET), or the like.
  • PPS polyphenyl sulfide resin
  • PBT polybutylene terephthalate resin
  • PET polyethylene terephthalate resin
  • sealing material 105 such as resin from the opening on the upper surface side of the case 102, the base plate 101, the insulating substrate 103, the semiconductor element 104, the wiring 106, and the terminal 108 are covered with the sealing material 105.
  • sealing material 105 for example, an epoxy material mixed with a filler, a silicon gel, or the like is used.
  • the encapsulant 105 may have sufficient insulating properties when the power semiconductor module 100 is used.
  • the lower conductor pattern 103f of the insulating substrate 103 is joined to a part of the upper surface of the base plate 101 via the under-board bonding material 107b (solder).
  • the insulating substrate 103 includes an insulating material 103e, an upper conductor pattern 103a formed on the upper surface of the insulating material 103e, an upper conductor pattern 103b formed on the upper surface of the insulating material 103e, and an upper side formed on the upper surface of the insulating material 103e. It includes a conductor pattern 103c, an upper conductor pattern 103d formed on the upper surface of the insulating material 103e, and a lower conductor pattern 103f formed on the lower surface of the insulating material 103e.
  • the insulating material 103e is, for example, a ceramic material such as aluminum oxide (Al 2 O 3 ), aluminum nitride (Al N) or silicon nitride (Si 3 N 4 ), or a binder material such as an epoxy material or a liquid crystal polymer, and silica or alumina. Alternatively, it is composed of an organic insulating material mixed with a filler such as boron nitride (BN).
  • the upper conductor pattern 103a, the upper conductor pattern 103b, the upper conductor pattern 103c, the upper conductor pattern 103d and the lower conductor pattern 103f are, for example, a Cu material alone, a Cu material plated with Ni or silver (Ag), or , Al material is Ni-plated or Ag-plated.
  • a region that includes a region that overlaps with the semiconductor element 104 in a plan view and is larger than the overlapping region is a metal instead of the under-board bonding material 107b.
  • a film 109 is formed. The center position of the metal film 109 overlaps with the center of the region on which the semiconductor element 104 is mounted in a plan view.
  • the outer shape of the semiconductor element 104 in a plan view is generally rectangular, the outer shape of the metal film 109 in a plan view does not have to be rectangular, and for example, the outer shape of the metal film 109 may be circular.
  • the metal film 109 is a metal film formed by a cold spray method, but the material may be any material that can be bonded to the lower conductor pattern 103f, and Cu is specifically applied. Is desirable.
  • the material of the metal film 109 may be any material having a thermal conductivity higher than that of the lower substrate bonding material 107b, and may be another metal material such as Ni or Ag which is a material that can be bonded to the surface material of the lower conductor pattern 103f. There may be.
  • a semiconductor element 104 is bonded to the upper surface of the upper conductor pattern 103a of the insulating substrate 103 via a chip bottom bonding material 107a.
  • the subchip bonding material 107a is obtained by sintering and bonding a paste material consisting of, for example, nanometer-order Ag particles, micrometer-order Ag particles, or a mixture of nanometer-order Ag particles and micrometer-order Ag particles. It is a made Ag sintered material.
  • the subchip bonding material 107a may be a bonding material that forms a liquid phase diffusion bonding layer, such as tin (Sn) and copper (Cu), or tin (Sn) and nickel (Ni).
  • a solder material using tin (Sn) or lead (Pb) as a base material may be used.
  • the semiconductor element 104 includes a switching device 104a and a freewheeling diode 104b.
  • the switching device 104a is, for example, a SiC-MOSFET or Si-IGBT
  • the freewheeling diode 104b is, for example, a SiC-Schottky barrier diode (that is, SBD) or a Si-free wheel diode (free-wheeling diode). That is, FWD).
  • the upper conductor pattern 103a is electrically connected to the drain electrode of the switching device 104a.
  • the semiconductor element 104 when it is not necessary to distinguish between the switching device 104a and the freewheeling diode 104b, it is simply referred to as the semiconductor element 104.
  • a main terminal 108a and a control terminal 108b are installed in the case 102.
  • the switching device 104a is connected to the main terminal 108a by the wire-shaped wiring 106a, and is connected to the control terminal 108b by the source signal wiring 106b and the gate signal wiring 106c.
  • the freewheeling diode 104b is connected to the main terminal 108a by a wire-shaped wiring 106a.
  • upper surface electrodes 110 are provided on the upper surface of the switching device 104a and the upper surface of the freewheeling diode 104b, respectively. Further, a gate pad 110a is provided on the upper surface of the switching device 104a.
  • a protective film 111 is formed on the peripheral edge of the upper surface of the switching device 104a. Further, the protective film 111 is formed on the upper surface of the switching device 104a so as to surround the gate pad 110a. That is, the upper surface electrode 110 and the gate pad 110a are insulated by the protective film 111.
  • the protective film 111 is provided to physically protect the upper surface of the switching device 104a and the upper surface of the freewheeling diode 104b and to increase the insulation distance.
  • polyimide which is an organic substance, SiO 2 or SiN, which is an inorganic substance, is used.
  • Pure Al, AlSi alloy, AlCu alloy and AlSiCu alloy are generally used for the outermost surface of the top electrode 110.
  • the mixing ratio of Si or Cu in this alloy is 5 wt% or less in terms of the weight ratio in the alloy.
  • the thickness of this alloy is about 5 ⁇ m.
  • the wire-shaped wiring 106a of the wiring 106 is an Al wire containing Al as a main component, and a small amount of metal such as Ni may be added in order to increase the strength.
  • the wire diameter of the wire-shaped wiring 106a is about ⁇ 400, but it is arbitrarily designed to satisfy the required energizing capacity such as the number of wedge bonding dots or the wire diameter, and is ⁇ 200 or more. , ⁇ 600 or less is arbitrarily selected.
  • the energizing capacity required for the source signal wiring 106b and the gate signal wiring 106c of the wiring 106 is much smaller than the current capacity required for the wire-shaped wiring 106a which is the main wiring. Therefore, a wire having a wire diameter equal to or smaller than that of the wire-shaped wiring 106a may be selected, and is generally selected between ⁇ 100 ⁇ m and more and ⁇ 400 ⁇ m or less.
  • a wire containing Al as a main component is applied, but a wire containing Cu as a main component may be applied.
  • the outermost surface of the top electrode 110 may be formed of a metal such that the semiconductor element 104 is not destroyed by the Cu wire, which is harder than Al.
  • an electrode by Cu plating or an electrode by Ni plating may be formed. Be selected.
  • the shape of the wire-shaped wiring 106a does not have to be wire-shaped, and may be, for example, plate-shaped wiring.
  • the wire-shaped wiring 106a extends above the semiconductor element 104 from the main terminal 108a.
  • the plate-shaped wiring and the top electrode 110 may be joined by, for example, solder.
  • the upper surface electrode 110 may be a metal capable of ensuring the wettability of the solder, and may be, for example, a metal having Au plating formed on the upper surface of Ni plating.
  • the plate thickness of the plate-shaped wiring is determined by the energized current, and for example, 0.3 mm or more and 1.5 mm or less is appropriate.
  • a diode for temperature detection is provided in the power semiconductor module 100. Similar to the gate signal wiring 106c, Cu wire or Al wire is also used for the wiring connected to the cathode electrode and the anode electrode of this diode.
  • the heat generated by the semiconductor element 104 is dissipated in the vertical direction (Z-axis direction in FIG. 1) of the base plate 101, and is endothermic (cooled) by a cooler (not shown here).
  • the solder which is the under-board bonding material 107b on the lower surface side of the insulating substrate 103, is indirectly sandwiched between the ceramic, which is the insulating material 103e having a small coefficient of linear expansion, and AlSiC, which is the base plate 101 having a small coefficient of linear expansion. Become.
  • the expansion and contraction of the insulating substrate 103 and the base plate 101 located above and below the underboard bonding material 107b is smaller than the expansion and contraction of the solder itself, which is the underboard bonding material 107b. Therefore, stresses of repeated compression and expansion are repeatedly applied to the inside of the solder which is the under-board bonding material 107b, and cracks are generated inside the solder in the vertical direction.
  • the cold spray method is performed at a position of the lower surface of the lower conductor pattern 103f on the lower surface side of the insulating substrate 103, which faces the mounting position of the semiconductor element 104.
  • the metal film 109 formed by the above is formed.
  • the metal film 109 is a cold spray film formed of Cu powder.
  • the coefficient of thermal expansion of Cu is a value between the coefficient of thermal expansion of the solder and the coefficient of thermal expansion of the base plate 101 or the coefficient of thermal expansion of the insulating material 103e. Therefore, it is possible to reduce the stress generated in the under-board bonding material 107b during the operation of the power semiconductor module 100.
  • the film forming rate is slow and the manufacturing cost is high.
  • a cold spray film is formed by laminating powder at high pressure, so that the metal film 109 is formed at an arbitrary position with an arbitrary shape and an arbitrary film thickness. A film can be formed.
  • the cold spray membrane is not a complete bulk body, and there are vacancies inside the membrane. These pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Therefore, it can be said that the cold spray method is a desirable film forming method for the metal film 109.
  • the thermal conductivity of Cu in bulk is 387.5 W / m ⁇ K.
  • the pore ratio can be controlled by the conditions of the cold spray method, the apparent thermal conductivity of the cold spray film having pores is 150 W / m ⁇ K or more and 300 W / K /.
  • the thermal conductivity of Sn or Pb-based solder which is in the range of m ⁇ K or less and has a thermal conductivity of 40 W / m ⁇ K or more and 50 W / m ⁇ K or less, It can be seen that it has a much higher thermal conductivity. From this, it can be said that the metal film 109 has sufficient heat dissipation.
  • a method for manufacturing a power semiconductor module having such a metal film 109 will be described. Assembly when the sub-chip bonding material 107a and the sub-board bonding material 107b are solders having the same composition, or when the melting point of the sub-chip bonding material 107a is lower than the melting point of the sub-chip bonding material 107b.
  • the insulating substrate 103 in which the metal film 109 is directly formed on a part of the lower surface of the lower conductor pattern 103f by cold spray is placed on the upper surface of the base plate 101, and the solder as the under-board bonding material 107b is placed on the upper surface of the base plate 101. Arrange so as to sandwich.
  • the lower surface of the semiconductor element 104 is arranged so as to sandwich the subchip bonding material 107a with the upper surface of the upper conductor pattern 103a, and soldering is performed by a reflow furnace.
  • the thickness of the substrate bottom bonding material 107b is determined based on the thickness of the cold spray film (metal film 109). It is appropriate that the thickness of the metal film 109 is 100 ⁇ m or more and 300 ⁇ m or less.
  • the solder thickness was secured by arranging wire bumps or the like on the base plate 101 so that the thickness of the under-board bonding material 107b was uniform, but there were a plurality of metal films 109. Since the semiconductor elements 104 are arranged at positions facing each other, it is not necessary to secure the solder thickness of the under-board bonding material 107b by wire bumps, and the number of related steps can be reduced.
  • the solder which is the under-board bonding material 107b arranged on the lower surface of the metal film 109 in the manufacturing process, is melted by heating with a reflow furnace. Then, the solder is excluded from the lower surface of the metal film 109 due to the weight of the insulating substrate 103 and the semiconductor element 104, but the solder remaining on the uneven surface on the lower surface of the metal film 109 and the upper surface of the base plate 101 are joined to form a bonding layer. .. In addition, the molten solder also penetrates into some of the pores inside the metal film 109, and by filling some of the pores with solder, the apparent thermal conductivity of the metal film 109 is also improved. To do. Further, at the contact portion between the metal film 109 and the solder, Cu is melted to form an intermetallic compound phase of Cu and Sn.
  • the structure in which the metal film 109 is formed on the lower conductor pattern 103f of the insulating substrate 103 has been described, but the state in which the metal film 109 is formed on the upper surface (solder joint surface) of the base plate 101. Even if the structure is joined by the under-board bonding material 107b, the heat dissipation and the reliability of the joint can be improved.
  • the solder layer is interposed between the lower surface of the lower conductor pattern 103f and the upper surface of the metal film 109, the metal film 109 is formed on the lower conductor pattern 103f in terms of improving heat dissipation. It is more effective when there is.
  • the semiconductor element 104 may be bonded to the upper surface of the upper conductor pattern 103a of the insulating substrate 103 in which the metal film 109 is previously formed on the lower surface of the lower conductor pattern 103f by the Ag sintering material. ..
  • the upper conductor pattern 103b, the upper conductor pattern 103c or the upper conductor pattern 103d and the upper surface electrode of the semiconductor element 104 are wired by an aluminum wire.
  • the semiconductor element 104 is bonded to the upper surface of the upper conductor pattern 103a on the insulating substrate 103 by Ag sintering or bonding to form a liquid layer diffusion bonding layer of Sn and Cu
  • the liquid of Ag sintering or Sn and Cu is used.
  • the insulating substrate 103 on which the semiconductor element 104 after heating and pressurization is mounted has a portion on which the semiconductor element 104 is mounted. It warps upward as a peak.
  • the heat dissipation can be improved more effectively as compared with the case where there is no cold spray film.
  • the semiconductor element 104 is bonded to the upper conductor pattern 103a by Ag sintering or forming a liquid phase diffusion bonding layer of Sn and Cu, and then a metal film 109 is formed by a cold spray method.
  • the metal film 109 is formed with the insulating substrate 103 warped upward in a convex shape with the portion on which the semiconductor element 104 is mounted as the apex.
  • the cold spray film (metal film 109) is formed thicker at the center than at the edges. At this time, the metal film 109 is not formed along the shape of the insulating substrate 103, but is formed so that the portion on which the semiconductor element 104 is mounted becomes thick.
  • a metal film 109 is formed between the base plate 101 and the insulating substrate 103, so that the metal film is formed by soldering.
  • the temperature of 109 rises, and the metal film 109 expands accordingly. This is preferable because the convex shape having the portion on which the semiconductor element 104 is mounted as the apex is relaxed.
  • a metal film 109 is mounted on a part of the lower surface (a portion on which the semiconductor element 104 is mounted) of the lower conductor pattern 103f of the insulating substrate 103 in a state where the semiconductor element 104 is mounted and the semiconductor element 104 is wired with an aluminum wire. Is formed.
  • the lower surface of the lower conductor pattern 103f is reflowed and soldered to the upper surface of the base plate 101 in which the plate-shaped sub-board bonding material 107b (solder) is arranged on the upper surface.
  • the case 102 in which the main terminal 108a or the control terminal 108b is installed by insert molding or outsert molding is adhered to the base plate 101 using an adhesive or the like. After that, it is connected to the insulating substrate 103, the main terminal 108a, and the control terminal 108b by wire wiring or the like. After that, the case 102 is filled with the sealing material 105, and the case 102 is further covered with a lid to complete the power semiconductor module 100.
  • FIG. 3 is a cross-sectional view for explaining a method for forming a metal film according to the present embodiment.
  • a metal film 109 is formed on the exposed portion of the lower conductor pattern 103f.
  • the thermal energy and kinetic energy of the metal powder are converted into frictional heat, and the metal powder and the surface to be bonded are respectively. Deformation occurs on the outermost surface of the and entangles with each other. Further, the metal oxide film on the outermost surface of each is removed, and a cold spray film is formed by the reaction occurring at the interface between the metal powder and the surface to be bonded. Further, the metal powder is continuously discharged from the cold spray device onto the previously formed cold spray film and collides with the cold spray film, so that the film thickness of the cold spray film is increased and finally becomes the metal film 109. ..
  • the metal powder supplied from the cold spray device is Cu powder, and its particle size is obtained by passing through a test fluid having a mesh size of 100 ⁇ m (149 mesh) conforming to JIS (Japanese Industrial Standards). Is controlled.
  • an electrolysis method As a method for producing Cu powder, an electrolysis method, a high-pressure swirling water atomizing method, a water atomizing method, or the like is used.
  • the particle shape of the Cu powder produced by the electrolytic method is close to the dendrite shape
  • the particle shape of the Cu powder produced by the high-pressure swirling water atomization method is close to the spherical shape. Regardless of the shape of Cu powder, when it collides with the surface to be joined, it becomes a thin flat shape that does not retain the prototype.
  • Particles that have passed through a sieve with a mesh size of 100 ⁇ m have a particle size distribution of 100 ⁇ m or less.
  • the frequency (number) is the maximum in the particle size distribution diagram in which the horizontal axis is the particle size and the vertical axis is the frequency (number). It is desirable that the particle size is about 20 ⁇ m. That is, it is desirable that particles having a particle size of about 20 ⁇ m form a peak of the distribution, and particles having a smaller particle size and particles having a particle size larger than that are present around the particles forming the peak.
  • the peak particle size is 20 ⁇ m, not only the particles having a particle size of 20 ⁇ m but also the particles having a particle size difference of ⁇ 10% with respect to 20 ⁇ m are used as the particles forming the peak.
  • the opening of the fluid may be less than 100 ⁇ m.
  • a sieve having a mesh size of 53 ⁇ m (270 mesh) is used, particles having a particle size of 53 ⁇ m or less can be obtained.
  • the opening of the fluid is small, the yield will be low. Therefore, in order to form a cold spray film at low cost, it is desirable that the opening of the fluid is about 100 ⁇ m.
  • Particles with a large particle size cannot obtain sufficient kinetic energy to form a cold spray film when they are discharged from the nozzle of a cold spray device described later. Therefore, even if the particles collide with the previously formed cold spray film, the particles do not bond with each other and are repelled by the flow of the discharged gas to the outside of the film, which does not contribute to the film formation.
  • the particle size of the metal powder is preferably small, and is 100 ⁇ m or less, more preferably 60 ⁇ m or less.
  • the lower limit of the particle size of the metal powder is, for example, 1.0 ⁇ m, but it is not necessary to perform sorting by a sieve in order to control the lower limit of the particle size. Further, for the reason described below, it is not necessary to make the particle size of the metal powder uniform, and it is not necessary to perform sorting by a fluid to make the particle size uniform.
  • the metal powder applied to the fluid having a predetermined opening has a particle size distribution equal to or less than the opening.
  • fine particles having a lighter weight preferentially collide with the lower conductor pattern 103f to form a cold spray film, and then the weight becomes heavier. Heavy, large particles collide with the previously formed cold spray film.
  • the side close to the lower conductor pattern 103f becomes a dense cold spray film composed of particles having a small particle size. Since the metal powder having a particle size distribution equal to or less than the above-mentioned opening collides with the dense cold spray film in sequence, a coarser cold spray film is formed on the dense cold spray film. When particles having a small particle size collide with each other, a film having a relatively small powder particle spacing is formed. Therefore, the upper layer of the metal film 109 is a relatively dense film.
  • the powder particle spacing of the metal film 109 is smaller as the powder particle spacing is closer to the lower conductor pattern 103f, and the powder particle spacing is larger as the distance from the lower conductor pattern 103f is larger. It has a film structure in which the powder particle spacing becomes smaller again as it approaches (the surface farthest from 103f).
  • the shape of the metal film 109 is determined by abutting the cold spray film mask 201 on the lower conductor pattern 103f and positioning it.
  • the cold spray film mask 201 is a mask made of SUS having an opening and has a thickness of about 1 mm.
  • the cold spray film mask 201 is a material that is not easily deformed by the collision of powder supplied from the cold spray device, and is not particularly limited as long as it is a material having a thickness that is difficult to be deformed.
  • the metal powder (Cu powder) does not adhere to the insulating material 103e.
  • the lower conductor pattern 103f is made of Cu
  • a Ni plating film may be formed on the surface thereof by a wet plating method, or a Ni sputter film may be formed on the surface thereof by vacuum vapor deposition.
  • Other solderable films may be formed.
  • Cu powder is used as the metal powder used as the material for the metal film 109.
  • the metal powder is a metal that forms a metal bond with the surface to be bonded and is a metal to be bonded when the base plate 101 and the insulating substrate 103 are soldered, for example, Ni. And so on.
  • the thickness of the metal film 109 can be controlled by the irradiation time of the spray, the irradiation speed (gas pressure), and the irradiation temperature. In the present embodiment, it is sufficient that the metal film 109 does not completely dissolve in the molten solder, and from that viewpoint, the metal film 109 having a thickness of 100 ⁇ m or more is sufficient.
  • the thickness of the metal film 109 is preferably 300 ⁇ m or less, for example.
  • the crystal size of the Cu film formed by the wet plating method is about 5 ⁇ m, whereas the cold spray film (metal film 109) is mainly formed by particles of about 20 ⁇ m. Therefore, the outermost surface of the metal film 109 is not smooth as compared with the Cu film formed by the wet plating method, but is non-uniform and has irregularities.
  • the arithmetic average roughness Ra derived from the line roughness measured in the range of 100 ⁇ m ⁇ 100 ⁇ m by a laser microscope is 1 ⁇ m or more and 10 ⁇ m or less.
  • the size of the unevenness here is measured by, for example, a non-contact white interferometer.
  • the presence of non-uniform unevenness on the outermost surface of the metal film 109 increases the area in which the under-board bonding material 107b (solder) wets and spreads. Therefore, the bonding strength between the substrate bottom bonding material 107b (solder) and the metal film 109 is improved.
  • the particle size in the cold spray film described above is, for example, a value measured by an electron backscatter diffraction method (EBSD) by observing a cross section of the metal film 109.
  • EBSD electron backscatter diffraction method
  • the film thickness is 2 ⁇ m or more and 3 ⁇ m or less, and the film thickness distribution is as flat as the nanometer order.
  • the film thickness is several ⁇ m or more and 30 ⁇ m or less, and the film thickness distribution is flat on the submicron order.
  • the metal film 109 is formed by the cold spray method using the cold spray film mask 201.
  • the cold spray film does not rise vertically along the wall surface of the opening of the cold spray film mask 201, but has a shape that is inclined toward the center of the film.
  • the thickness of the metal film 109 can be measured by an ultrasonic flaw detection inspection (Scanning Acoustic Tomography, that is, SAT). That is, the time required for the ultrasonic waves emitted from the ultrasonic probe to be applied to the semiconductor device after the metal film 109 is formed and the ultrasonic waves passing through the metal film 109, and the metal film 109 and the lower conductor. It is measured by the difference from the time until the ultrasonic wave is reflected and returned at the interface with the pattern 103f.
  • SAT Ultrasonic flaw detection inspection
  • a metal film 109 corresponding to each semiconductor element 104 is formed on the corresponding portion on the lower surface of the lower conductor pattern 103f.
  • FIG. 4 is a cross-sectional view schematically showing an example of a part of the configuration of the power semiconductor module according to the present embodiment.
  • FIG. 5 is a plan view of the configuration shown in FIG. 4 as viewed from the lower surface side (lower side of the paper surface in FIG. 4).
  • the other configurations including the substrate lower bonding material 107b are not shown for the sake of simplicity.
  • the power semiconductor module includes an insulating substrate 103, a semiconductor element 104, a wiring 106, and a metal film 109a.
  • the metal film 109a is formed over a portion where a plurality of semiconductor elements 104 (switching device 104a and freewheeling diode 104b) are mounted. In FIG. 5, the metal film 109a is formed over the entire mounting locations of the four semiconductor elements 104.
  • the method for creating the metal film 109a is the same as that described in the first embodiment. That is, a mask for a cold spray film having an opening provided in a portion where the metal film 109a is formed is arranged on the lower conductor pattern 103f, and the metal powder is further irradiated with the cold spray device to form the film. Can be done.
  • the power module can be produced without lowering the productivity.
  • FIG. 6 is a cross-sectional view schematically showing another example of a part of the configuration of the power semiconductor module according to the present embodiment.
  • FIG. 7 is a plan view of the configuration shown in FIG. 6 as viewed from the lower surface side (lower side of the paper surface of FIG. 6).
  • the other configurations including the substrate lower bonding material 107b are not shown for the sake of simplicity.
  • the power semiconductor module includes an insulating substrate 103, a semiconductor element 104, a wiring 106, and a metal film 109b.
  • a plurality of metal films 109b are formed corresponding to the locations where the respective semiconductor elements 104 (switching device 104a or freewheeling diode 104b) are mounted (that is, the metal films 109b are formed in a plurality of locations). .. In FIG. 7, six metal films 109b are formed on each mounting location of one semiconductor element 104, and a plurality of metal films 109b are also formed between the mounting locations of the semiconductor element 104.
  • the method for creating the metal film 109b is the same as that described in the first embodiment. That is, a mask for a cold spray film provided with a plurality of openings corresponding to a portion for forming a plurality of metal films 109b is arranged on the lower conductor pattern 103f, and further, the metal powder is irradiated by the cold spray device. By doing so, a film can be formed.
  • the amount of Cu powder required is suppressed, the heat dissipation is improved, and the heat dissipation is improved.
  • the joint reliability of the joint portion between the base plate 101 and the insulating substrate 103 is improved.
  • the metal film 109 corresponding to the semiconductor element 104 is formed at the corresponding portion on the lower surface of the lower conductor pattern 103f. It was filmed.
  • FIG. 8 is a cross-sectional view conceptually showing a part of an example of the configuration of the power semiconductor module according to the present embodiment.
  • FIG. 9 is a plan view of the configuration shown in FIG. 8 as viewed from the lower surface side (lower side of the paper surface in FIG. 8).
  • the power semiconductor module 100a includes an insulating substrate 103, a case 102, a semiconductor element 104, a wiring 106, a terminal 208, a metal film 109, and a base plate 101. And have.
  • a main terminal 208a and a control terminal 108b are installed in the case 102.
  • the switching device 104a is connected to the main terminal 208a by the wire-shaped wiring 106a, and is connected to the control terminal 108b by the source signal wiring 106b and the gate signal wiring 106c.
  • the freewheeling diode 104b is connected to the main terminal 208a by a wire-shaped wiring 106a.
  • the metal film 109 (or the metal film 109a) is located at a position facing the mounting position of the semiconductor element 104 and a position where the main terminal 208a is mounted.
  • Metal film 109b) is formed.
  • the metal film 109 is formed by arranging a mask for a cold spray film having an opening in a portion where the film is formed on the lower surface of the lower conductor pattern 103f, and further irradiating the metal powder with a cold spray device. A film can be formed.
  • the metal film 109 is formed in an area larger than the projected area of the joint portion 208b of the main terminal 208a (see FIG. 9).
  • a large current is energized in the main terminal 208a with the operation of the power semiconductor module 100a.
  • the cross-sectional area of the main terminal 208a is arbitrarily designed so as to satisfy the energizing capacity required for the operation of the power semiconductor module 100a.
  • the main terminal 208a is often formed of, for example, Cu having a plate thickness of 1 mm.
  • the main terminal 108a is connected to the upper conductor pattern 103b via a wire-shaped wiring material.
  • a wire-shaped wiring material When the energization capacity required for design cannot be obtained by connecting with a wire-shaped wiring material, it is necessary to join the joint portion 208b of the main terminal 208a and the upper conductor pattern 103b like the main terminal 208a.
  • the main terminal 208a and the upper conductor pattern 103b are joined by a solder material, but in recent years, the operating temperature range of the power semiconductor module has expanded, and the joining reliability required for the joining portion has increased. ing.
  • the main terminal 208a is made of a Cu material having a thickness of 1 mm
  • the upper conductor pattern 103b is a metal pattern made of a Cu material
  • the insulating material 103e is made of silicon nitride (AlN).
  • the materials of these configurations are not limited to the contents.
  • the main terminal 208a When energization occurs due to the operation of the power semiconductor module 100a, the main terminal 208a generates heat. Then, a temperature change based on the heat generation may occur.
  • the joint portion 208b Due to the temperature change based on the above heat generation or the temperature change in the ambient environment of the power semiconductor module 100a, the joint portion 208b is stressed (mainly) according to the difference in the coefficient of thermal expansion between the main terminal 208a and the material such as the insulating material 103e. Shear direction) occurs. Further, due to the above temperature change, expansion or contraction of the main terminal 208a occurs, and stress (mainly in the vertical direction) is generated at the joint portion 208b between the main terminal 208a and the upper conductor pattern 103b.
  • silicon nitride (AlN) which is the material of the insulating material 103e used in the present embodiment, has a large thermal conductivity and excellent heat dissipation. Therefore, it is often used in recent years.
  • the stress generated at the joint portion 208b is large, and in conventional solder bonding, solder, which is a bonding material (here). Then, the crack extends to (not shown). Then, the energization path becomes small, and the temperature of the joint rises, so that there is a risk of breakage and an open failure.
  • the Cu of the main terminal 208a and the Cu of the upper conductor pattern 103b are directly bonded to obtain a strong bonding portion 208b, and the required bonding reliability is also satisfied. be able to.
  • the stress generated at the joint was alleviated by creeping the solder material or expanding cracks in the solder material.
  • the stress generated by the difference in the coefficient of thermal expansion between the materials or the stress generated by the expansion or contraction of the main terminal 208a itself causes the main terminal 208a to be formed.
  • the solder which is the under-board bonding material 107b between the lower conductor pattern 103f and the base plate 101, just below the joint portion 208b, has deteriorated.
  • the heat generated by the main terminal 208a being energized or the heat generated by the operation of the semiconductor element 104 cannot be efficiently transmitted to the base plate 101. Then, the heat dissipation property deteriorates.
  • the deterioration of the solder locally progresses only in the portion directly below the main terminal 208a due to the operation of the power semiconductor module 100a.
  • the cold spray method is also performed at a position facing the mounting position of the main terminal 208a on the lower surface of the lower conductor pattern 103f on the lower surface side of the insulating substrate 103.
  • the metal film 109 formed by the above is formed.
  • the coefficient of thermal expansion of Cu is a value between the coefficient of thermal expansion of the solder and the coefficient of thermal expansion of the base plate 101 or the coefficient of thermal expansion of the insulating material 103e. Therefore, it is possible to reduce the stress generated in the substrate lower bonding material 107b during the operation of the power semiconductor module 100a.
  • the cold spray membrane is not a complete bulk body, and there are vacancies inside the membrane. These holes serve as a buffer layer, and alleviate the stress generated in the joint material 107b under the substrate immediately below the joint portion 208b of the main terminal 208a. Therefore, it can be said that the cold spray method is a desirable film forming method for the metal film 109.
  • the structure of the main terminal 208a which is a Cu material and the upper conductor pattern 103b which is a Cu pattern by solid-phase diffusion bonding by ultrasonic waves has been described, but not only that, the main terminal 208a and the upper side by laser irradiation have been described.
  • Direct laser bonding with the conductor pattern 103b or laser irradiation melts the brazing material sandwiched between the main terminal 208a and the upper conductor pattern 103b to bond the main terminal 208a and the upper conductor pattern 103b.
  • the method is also applicable.
  • the structure formed by bonding the main terminal 208a and the upper conductor pattern 103b has been described, but when the bonding portion between the control terminal 108b and the upper conductor pattern 103c is ultrasonically bonded, the control terminal is used.
  • the main terminal 208a and the upper conductor pattern 103b which is a Cu pattern, are ultrasonically bonded to improve the bonding strength as compared with the conventional solder bonding, the main terminal 208a It is possible to obtain a power semiconductor module 100a capable of improving heat dissipation by suppressing the expansion of cracks in the substrate bottom bonding material 107b between the lower conductor pattern 103f directly below and the base plate 101.
  • the semiconductor module according to the above-described embodiment is applied to a power conversion device.
  • the power conversion device to be applied is not limited to that for a specific application, but the case where it is applied to a three-phase inverter will be described below.
  • FIG. 10 is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion device of the present embodiment.
  • the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300.
  • the power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200.
  • the power supply 2100 can be configured by various types, for example, a DC system, a solar cell, a storage battery, or the like. Further, the power supply 2100 can be configured by a rectifier circuit connected to an AC system, an AC-DC converter, or the like. Further, the power supply 2100 can also be configured by a DC-DC converter that converts the DC power output from the DC system into a predetermined power.
  • the power converter 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300.
  • the power conversion device 2200 converts the DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.
  • the power conversion device 2200 converts a DC power into an AC power and outputs a conversion circuit 2201 and a drive signal for driving each switching element of the conversion circuit 2201. It includes a drive circuit 2202 that outputs power, and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.
  • the load 2300 is a three-phase electric motor driven by AC power supplied from the power converter 2200.
  • the load 2300 is not limited to a specific application, but is an electric motor mounted on various electric devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner. Is.
  • the details of the power conversion device 2200 will be described below.
  • the conversion circuit 2201 includes a switching element and a freewheeling diode (not shown here). Then, when the switching element performs the switching operation, the DC power supplied from the power supply 2100 is converted into AC power and further supplied to the load 2300.
  • the conversion circuit 2201 is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It includes six freewheeling diodes connected in antiparallel.
  • the semiconductor module according to any of the embodiments described above is applied to at least one of each switching element and each freewheeling diode in the conversion circuit 2201.
  • the six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (that is, U phase, V phase and W phase) of the full bridge circuit.
  • the output terminals of the respective upper and lower arms that is, the three output terminals of the conversion circuit 2201 are connected to the load 2300.
  • the conversion circuit 2201 includes a drive circuit (not shown here) for driving each switching element
  • the drive circuit may be built in the semiconductor module, and the semiconductor module is A drive circuit may be separately provided.
  • the drive circuit 2202 generates a drive signal for driving the switching element of the conversion circuit 2201, and further supplies the drive signal to the control electrode of the switching element of the conversion circuit 2201. Specifically, based on the control signal output from the control circuit 2203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements. To do.
  • the drive signal When the switching element is kept on, the drive signal is a voltage signal equal to or higher than the threshold voltage of the switching element (that is, the on signal), and when the switching element is kept off, the drive signal is the switching element. It becomes a voltage signal below the threshold voltage (that is, an off signal).
  • the control circuit 2203 controls the switching element of the conversion circuit 2201 so that the desired power is supplied to the load 2300. Specifically, the time (that is, the on-time) that each switching element of the conversion circuit 2201 should be in the on state is calculated based on the power to be supplied to the load 2300.
  • the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.
  • control circuit 2203 gives a control command to the drive circuit 2202 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. That is, the control signal) is output.
  • the drive circuit 2202 outputs an on signal or an off signal as a drive signal to the control electrodes of the respective switching elements based on the control signal.
  • the semiconductor module in any of the above-described embodiments is applied as the switching element or the freewheeling diode of the conversion circuit 2201, the on-resistance after the energization cycle is stabilized. Can be made to.
  • the two-level power conversion device has been described, but the semiconductor module in any of the embodiments described above may be applied to the three-level or multi-level power conversion device. .. Further, in the case of supplying electric power to the single-phase load, the semiconductor module in any of the embodiments described above may be applied to the single-phase inverter.
  • the semiconductor module in any of the above-described embodiments can be applied to the DC-DC converter or the AC-DC converter.
  • the power conversion device to which the semiconductor module in any of the above-described embodiments is applied is not limited to the case where the load described above is an electric motor, and is not limited to, for example, an electric discharge machine or a laser machine. It can also be used as a power source for machines, induction cookers or contactless power supply systems. Further, the power conversion device to which the semiconductor module in any of the above-described embodiments is applied can also be used as a power conditioner in a photovoltaic power generation system, a power storage system, or the like.
  • the semiconductor switching element used in the above-described embodiment is not limited to the switching element made of a silicon (Si) semiconductor.
  • the semiconductor switching element is a non-Si semiconductor having a wider band gap than the Si semiconductor. It may be made of a material.
  • Examples of wide bandgap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.
  • a switching element made of a wide bandgap semiconductor can be used even in a high voltage region where unipolar operation is difficult with a Si semiconductor, and switching loss generated during switching operation can be greatly reduced. Therefore, it is possible to greatly reduce the power loss.
  • switching elements made of wide bandgap semiconductors have low power loss and high heat resistance. Therefore, when a power module including a cooling unit is configured, the heat radiation fins of the heat sink can be miniaturized, so that the semiconductor module can be further miniaturized.
  • switching elements made of wide bandgap semiconductors are suitable for high frequency switching operation. Therefore, when applied to a converter circuit in which a high frequency demand is high, the reactor or capacitor connected to the converter circuit can be miniaturized by increasing the switching frequency.
  • the semiconductor switching element according to the above-described embodiment is a switching element made of a wide-gap semiconductor such as silicon carbide.
  • the replacement may be made across a plurality of embodiments. That is, it may be the case that the respective configurations shown in the examples in different embodiments are combined to produce the same effect.
  • the semiconductor module includes an insulating substrate 103, at least one semiconductor element 104, a first bonding material, and a metal film 109 (or metal film 109a, metal film 109b).
  • the first bonding material corresponds to, for example, the substrate lower bonding material 107b.
  • the insulating substrate 103 is provided with a conductor pattern at least on the upper surface.
  • the conductor pattern corresponds to, for example, the upper conductor pattern 103a.
  • the semiconductor element 104 is provided on the upper surface of the upper conductor pattern 103a.
  • the under-board bonding material 107b is provided on a part of the lower surface of the insulating substrate 103.
  • the metal film 109 has a higher thermal conductivity than the substrate bottom bonding material 107b. Further, the metal film 109 is provided on another part of the lower surface of the insulating substrate 103. The metal film 109 is provided on the lower surface of the insulating substrate 103 at a position corresponding to the position where the semiconductor element 104 is arranged.
  • the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved. Further, when the metal film 109 is made of Cu, the mechanical strength is higher than that of the bonding material made of solder, so that cracks unlike those of solder are less likely to occur, and when they occur. Even so, crack growth is slow. Therefore, the reliability of the joint is unlikely to decrease.
  • the metal film 109 is a cold spray film formed by a cold spray method.
  • the cold spray film does not become a complete bulk body, and since the pores are formed inside the membrane, the pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Has. Therefore, the reliability of the joint is unlikely to decrease. Further, since the apparent thermal conductivity of the cold spray film having pores is larger than that of solder or the like, heat dissipation is improved.
  • the cold spray film is a film formed by laminating powder at high pressure.
  • the cold spray film formed by this method has pores, has a higher thermal conductivity than solder or the like, is lower than a bulk body of the same substance, and has irregularities on the surface. ..
  • the cold spray film has a structure of another metal film (bonding material) including solder or the like, for example, by measuring the thermal conductivity and comparing it with the bulk body, or by measuring the arithmetic mean roughness Ra.
  • bonding material including solder or the like
  • cold spray membrane is a term that merely specifies the structure or characteristics of an object by indicating its state.
  • the metal film 109 is formed at least at a position where it overlaps with the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
  • the area where the metal film 109 is formed is larger than the area of the region where the semiconductor element 104 is arranged. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104 including the component spreading from the semiconductor element 104 in the surface direction of the insulating substrate 103.
  • the center position of the metal film 109 coincides with the center position of the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
  • the semiconductor module includes a second bonding material and a base plate 101.
  • the second bonding material corresponds to, for example, the chip bottom bonding material 107a.
  • the chip bottom bonding material 107a joins the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a.
  • the base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b.
  • the melting point of the subchip bonding material 107a is higher than the melting point of the substrate bottom bonding material 107b.
  • the metal is used when the base plate 101 and the insulating substrate 103 are soldered.
  • the temperature of the film 109 rises, and the metal film 109 expands accordingly. Therefore, it is possible to relax the convex shape having the portion on which the semiconductor element 104 is mounted as the apex.
  • the metal film 109b is provided on the lower surface of the insulating substrate 103 at a plurality of locations with respect to the corresponding semiconductor element 104. According to such a configuration, heat dissipation can be improved while suppressing the amount of Cu powder required as compared with the case where the number of semiconductor elements 104 and the number of metal films 109a are the same. ..
  • a plurality of semiconductor elements 104 are provided.
  • the metal film 109a is provided on the lower surface of the insulating substrate 103 at a position straddling each position where the plurality of semiconductor elements 104 are arranged. According to such a configuration, heat dissipation can be improved as compared with the case where the number of semiconductor elements 104 and the number of metal films 109a are the same. Further, even when different types of semiconductor elements are mounted on the same insulating substrate, setup change does not occur in the process of forming the metal film. Therefore, the power module can be produced without lowering the productivity.
  • the power conversion device has the above-mentioned semiconductor module, and drives the conversion circuit 2201 that converts and outputs the input power and the semiconductor module.
  • the drive circuit 2202 that outputs the drive signal of the above to the semiconductor module and the control circuit 2203 that outputs the control signal for controlling the drive circuit 2202 to the drive circuit 2202 are provided. According to such a configuration, since the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
  • At least one semiconductor element 104 is provided on the upper surface of the upper conductor pattern 103a of the insulating substrate 103 on which the upper conductor pattern 103a is provided on at least the upper surface.
  • the under-board bonding material 107b is provided on a part of the lower surface of the insulating substrate 103.
  • a metal film 109 having a higher thermal conductivity than the under-board bonding material 107b is provided on the other part of the lower surface of the insulating substrate 103.
  • providing the metal film 109 means providing the metal film 109 on the lower surface of the insulating substrate 103 at a position corresponding to the position where the semiconductor element 104 is arranged.
  • the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
  • providing the metal film 109 means forming the metal film 109 into a film by a cold spray method.
  • the cold spray film does not become a complete bulk body, and since the pores are formed inside the membrane, the pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Has. Therefore, the reliability of the joint is unlikely to decrease. Further, since the apparent thermal conductivity of the cold spray film having pores is larger than that of solder or the like, heat dissipation is improved.
  • the provision of the metal film 109 means that the metal film 109 is formed at least at a position where it overlaps with the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
  • the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a are joined by the chip bottom bonding material 107a. Then, after joining the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a, the base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b.
  • the melting point of the subchip bonding material 107a is higher than the melting point of the substrate sublayer bonding material 107b.
  • the lower surface of the insulating substrate 103 and the base plate 101 are joined by the substrate lower bonding material 107b.
  • the temperature of the metal film 109 rises when the base plate 101 and the insulating substrate 103 are soldered, and the metal film 109 is formed accordingly. Inflate. Therefore, it is possible to relax the convex shape having the portion on which the semiconductor element 104 is mounted as the apex.
  • the base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b. Then, after joining the lower surface of the insulating substrate 103 and the upper surface of the base plate 101, the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a are joined by the subchip bonding material 107a.
  • the melting point of the subchip bonding material 107a is equal to or lower than the melting point of the substrate bottom bonding material 107b. According to such a configuration, the joining of the base plate 101 can be completed before the semiconductor element 104 is mounted on the insulating substrate 103, so that the degree of freedom of the routing can be increased in addition to the different routing described above. it can.
  • a conversion circuit having a semiconductor module manufactured by the above manufacturing method and converting and outputting input power. 2201 is provided. Then, a drive circuit 2202 that outputs a drive signal for driving the semiconductor module to the semiconductor module is provided. Then, a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202 is provided.
  • the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
  • the material when a material name or the like is described without being specified, the material contains other additives, for example, an alloy, etc., as long as there is no contradiction. It shall be included.
  • each component in the above-described embodiment is a conceptual unit, and within the scope of the technology disclosed in the present specification, one component is composed of a plurality of structures. And the case where one component corresponds to a part of a structure, and further, the case where a plurality of components are provided in one structure.
  • each component in the above-described embodiment shall include a structure having another structure or shape as long as it exhibits the same function.
  • 100 power semiconductor module 102 case, 101 base plate, 103 insulating substrate, 103a, 103b, 103c, 103d upper conductor pattern, 103e insulating material, 103f lower conductor pattern, 104 semiconductor element, 104a switching device, 104b freewheeling diode, 105 Encapsulant, 106 Wiring, 106a Wire-shaped wiring, 106b Source signal wiring, 106c Gate signal wiring, 107a Subchip bonding material, 107b Subboard bonding material, 108 terminal, 108a Main terminal, 108b Control terminal, 109,109a 109b metal film, 110 top electrode, 110a gate pad, 111 protective film, 201 cold spray film mask, 202 insulating substrate holding jig, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

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Abstract

Techniques disclosed herein improve the heat-dissipating performance of a semiconductor element provided on an insulating substrate. A semiconductor module related to the techniques disclosed herein is provided with: an insulating substrate having a conductor pattern on at least an upper surface thereof; at least one semiconductor element provided on an upper surface of the conductor pattern; a first bonding material provided in a part of a lower surface of the insulating substrate; and a metal film which has a thermal conductivity higher than that of the first bonding material, and which is provided in another part of the lower surface of the insulating substrate. The metal film is provided on the lower surface of the insulating substrate at a position corresponding to the position at which the semiconductor element is disposed.

Description

半導体モジュール、電力変換装置、半導体モジュールの製造方法、および、電力変換装置の製造方法Semiconductor module, power conversion device, semiconductor module manufacturing method, and power conversion device manufacturing method
　本願明細書に開示される技術は、半導体モジュール、電力変換装置、半導体モジュールの製造方法、および、電力変換装置の製造方法に関するものである。 The technology disclosed in the specification of the present application relates to a semiconductor module, a power conversion device, a method for manufacturing a semiconductor module, and a method for manufacturing a power conversion device.
　インバータまたはコンバータなどの電力変換器を構成する電力用半導体モジュールの多くは、絶縁ゲート型バイポーラトランジスタ（ｉｎｓｕｌａｔｅｄ　ｇａｔｅ　ｂｉｐｏｌａｒ　ｔｒａｎｓｉｓｔｏｒ、すなわち、ＩＧＢＴ）または金属－酸化膜－半導体電界効果トランジスタ（ｍｅｔａｌ－ｏｘｉｄｅ－ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ｆｉｅｌｄ－ｅｆｆｅｃｔ　ｔｒａｎｓｉｓｔｏｒ、すなわち、ＭＯＳＦＥＴ）などのスイッチングデバイスと、スイッチングデバイスに逆並列に接続された還流ダイオードとを備えている。 Most of the power semiconductor modules that make up a power converter such as an inverter or converter are insulated gate bipolar transistors (that is, IGBTs) or metal-oxide-semiconductor transistors. It includes a switching device such as a field-effect transistor (that is, MOSFET) and a freewheeling diode connected in antiparallel to the switching device.
　一般的に、スイッチングデバイスにはケイ素（Ｓｉ）半導体を材料とするＩＧＢＴが用いられ、還流ダイオードにはＳｉ半導体を材料とするｐｉｎダイオードが用いられる。 Generally, an IGBT made of a silicon (Si) semiconductor is used as a switching device, and a pin diode made of a Si semiconductor is used as a freewheeling diode.
　近年、Ｓｉ半導体よりもバンドギャップが広いワイドバンドギャップ半導体である炭化ケイ素（ＳｉＣ）を用いる半導体装置が開発されている。 In recent years, semiconductor devices using silicon carbide (SiC), which is a wide bandgap semiconductor having a wider bandgap than Si semiconductors, have been developed.
　ＳｉＣは、絶縁破壊強度がＳｉの約１０倍と高く、ドリフト層の厚みをＳｉの約１／１０に低減することができる。そのため、半導体装置の低オン電圧を実現することができ、また、高温環境下での動作も可能となる。 SiC has a dielectric breakdown strength as high as about 10 times that of Si, and the thickness of the drift layer can be reduced to about 1/10 of Si. Therefore, it is possible to realize a low on-voltage of the semiconductor device, and it is also possible to operate in a high temperature environment.
　よって、ＳｉＣを半導体材料とする半導体装置は、従来のＳｉを半導体材料とする半導体装置に比較して、小型化および高効率化が可能となる。 Therefore, a semiconductor device using SiC as a semiconductor material can be made smaller and more efficient than a conventional semiconductor device using Si as a semiconductor material.
　ＩＧＢＴ、ＭＯＳＦＥＴまたはダイオードなどの電力変換用の半導体装置は、主電流が半導体装置の厚み方向に流れる表裏導通型の半導体装置である。表裏導通型の半導体装置をセラミック基板に実装する場合、半導体装置の裏面電極はセラミック基板の金属パターンとはんだ付けされ、半導体装置の表面電極はワイヤーボンディングおよび金属端子とのはんだ付けによって結線されて、通電経路が形成される。 Semiconductor devices for power conversion such as IGBTs, MOSFETs, and diodes are front-back conductive semiconductor devices in which the main current flows in the thickness direction of the semiconductor device. When mounting a front-back conductive semiconductor device on a ceramic substrate, the back electrode of the semiconductor device is soldered to the metal pattern of the ceramic substrate, and the front electrode of the semiconductor device is connected by wire bonding and soldering to the metal terminal. An energization path is formed.
　しかしながら、電力用半導体モジュール（以下、単にモジュールと称する場合がある）に占める半導体装置の製造コストは大きいため、モジュールの低コスト化および小型化のために、それぞれの半導体装置に通電される電流密度およびそれぞれの配線に流される電流密度は上昇する傾向にある。 However, since the manufacturing cost of semiconductor devices occupies a large amount of power semiconductor modules (hereinafter, may be simply referred to as modules), the current density of each semiconductor device is energized in order to reduce the cost and size of the module. And the current density flowing through each wiring tends to increase.
　電流密度が上昇すると、動作時の半導体装置の発熱量は増加し、半導体装置の温度と配線温度とが上昇する。これに対し、たとえば、モジュール内部の放熱性を向上させるなどの対策がとられている。 When the current density increases, the amount of heat generated by the semiconductor device during operation increases, and the temperature of the semiconductor device and the wiring temperature rise. On the other hand, for example, measures such as improving the heat dissipation inside the module are taken.
　また、電力変換装置の動作によって急峻な負荷変動が繰り返し発生すると、モジュール内部の温度変化が繰り返し発生する。そして、電力用半導体モジュールの内部におけるセラミック基板とベース板とで挟まれたはんだが、温度変化によって体積膨張と収縮とを繰り返し、クラックが発生する。そうすると、クラックが電力用半導体モジュール全体の放熱性を低下させてしまい、モジュールの故障に至る場合がある（たとえば、非特許文献１を参照）。 Also, if abrupt load fluctuations occur repeatedly due to the operation of the power conversion device, temperature changes inside the module will occur repeatedly. Then, the solder sandwiched between the ceramic substrate and the base plate inside the power semiconductor module repeats volume expansion and contraction due to a temperature change, and cracks occur. Then, the crack lowers the heat dissipation of the entire power semiconductor module, which may lead to the module failure (see, for example, Non-Patent Document 1).
　たとえば、特許文献１には、パワー半導体素子が搭載された絶縁部材とベース板とを接合する際に、ベース板のはんだ接合面に凸状段差部を設けることによって、絶縁部材とベース板との相互の熱変形差による熱応力を有効に緩和して、はんだの亀裂進展を抑制している。 For example, in Patent Document 1, when joining an insulating member on which a power semiconductor element is mounted and a base plate, a convex step portion is provided on the solder joint surface of the base plate, so that the insulating member and the base plate are bonded to each other. The thermal stress due to the difference in mutual thermal deformation is effectively relaxed, and the crack growth of the solder is suppressed.
特開平１１－２６５９７６号公報Japanese Unexamined Patent Publication No. 11-265976
　しかしながら、特許文献１に示される場合では、パワー半導体素子が搭載された絶縁部材の下面全体とベース板の対応する凸状段差部全体とをはんだを用いて接合しているため、放熱性能が十分ではなかった。 However, in the case shown in Patent Document 1, since the entire lower surface of the insulating member on which the power semiconductor element is mounted and the entire corresponding convex step portion of the base plate are joined by using solder, the heat dissipation performance is sufficient. It wasn't.
　本願明細書に開示される技術は、以上に記載されたような問題を鑑みてなされたものであり、絶縁基板に設けられた半導体素子の放熱性能を向上させるための技術である。 The technique disclosed in the specification of the present application has been made in view of the problems described above, and is a technique for improving the heat dissipation performance of the semiconductor element provided on the insulating substrate.
　本願明細書に開示される技術の第１の態様は、少なくとも上面に導体パターンが設けられる絶縁基板と、前記導体パターンの上面に設けられる少なくとも１つの半導体素子と、前記絶縁基板の下面の一部に設けられる第１の接合材と、前記第１の接合材よりも熱伝導率が高く、かつ、前記絶縁基板の下面の他の一部に設けられる金属膜とを備え、前記金属膜は、前記半導体素子が配置される位置に対応する位置の、前記絶縁基板の下面に設けられる。 The first aspect of the technique disclosed in the present specification is an insulating substrate provided with a conductor pattern on at least the upper surface, at least one semiconductor element provided on the upper surface of the conductor pattern, and a part of the lower surface of the insulating substrate. The metal film is provided with a first bonding material provided in the above, and a metal film having a higher thermal conductivity than the first bonding material and provided on another part of the lower surface of the insulating substrate. It is provided on the lower surface of the insulating substrate at a position corresponding to the position where the semiconductor element is arranged.
　本願明細書に開示される技術の第１の態様によれば、半導体素子が配置される位置に対応する位置の絶縁基板の下面に金属膜が設けられるため、金属膜によって半導体素子から生じる熱が効率よく放熱される。したがって、絶縁基板に設けられた半導体素子の放熱性能を向上させることができる。 According to the first aspect of the technique disclosed in the present specification, since the metal film is provided on the lower surface of the insulating substrate at the position corresponding to the position where the semiconductor element is arranged, the heat generated from the semiconductor element by the metal film is generated by the metal film. Efficient heat dissipation. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
　また、本願明細書に開示される技術に関連する目的と、特徴と、局面と、利点とは、以下に示される詳細な説明と添付図面とによって、さらに明白となる。 Further, the objectives, features, aspects, and advantages related to the technology disclosed in the present specification will be further clarified by the detailed description and the accompanying drawings shown below.
実施の形態に関する、電力用半導体モジュールの構成の例を概略的に示す断面図である。It is sectional drawing which shows typically the example of the structure of the semiconductor module for electric power which concerns on embodiment. 図１に例が示された電力用半導体モジュールの一部を上面側（図１の紙面上側）から見た場合の平面図である。It is a top view when a part of the power semiconductor module whose example is shown in FIG. 1 is seen from the upper surface side (the upper side of the paper surface of FIG. 1). 実施の形態に関する、金属膜の成膜方法を説明するための断面図である。It is sectional drawing for demonstrating the film-forming method of a metal film which concerns on embodiment. 実施の形態に関する、電力用半導体モジュールの構成の一部の例を概略的に示す断面図である。It is sectional drawing which shows typically the example of a part of the structure of the semiconductor module for electric power which concerns on embodiment. 図４に例が示された構成を下面側（図４の紙面下側）から見た場合の平面図である。FIG. 5 is a plan view of the configuration shown in FIG. 4 when viewed from the lower surface side (lower side of the paper surface in FIG. 4). 実施の形態に関する、電力用半導体モジュールの構成の一部の他の例を概略的に示す断面図である。FIG. 5 is a cross-sectional view schematically showing another example of a part of the configuration of a power semiconductor module according to an embodiment. 図６に例が示された構成を下面側（図６の紙面下側）から見た場合の平面図である。6 is a plan view of the configuration shown in FIG. 6 when viewed from the lower surface side (lower side of the paper surface in FIG. 6). 実施の形態に関する、電力用半導体モジュールの構成の一部の例を概念的に示す断面図である。It is sectional drawing which conceptually shows a part example of the structure of the semiconductor module for electric power with respect to embodiment. 図８に例が示された構成を下面側（図８の紙面下側）から見た場合の平面図である。FIG. 8 is a plan view of the configuration shown in FIG. 8 as viewed from the lower surface side (lower side of the paper surface in FIG. 8). 実施の形態の電力変換装置を含む電力変換システムの構成の例を概念的に示す図である。It is a figure which conceptually shows the example of the structure of the power conversion system including the power conversion apparatus of embodiment.
　以下、添付される図面を参照しながら実施の形態について説明する。以下の実施の形態では、技術の説明のために詳細な特徴なども示されるが、それらは例示であり、実施の形態が実施可能となるためにそれらすべてが必ずしも必須の特徴ではない。 Hereinafter, embodiments will be described with reference to the attached drawings. In the following embodiments, detailed features and the like are also shown for the purpose of explaining the technique, but they are examples, and not all of them are necessarily essential features in order for the embodiments to be feasible.
　なお、図面は概略的に示されるものであり、説明の便宜のため、適宜、構成の省略、または、構成の簡略化が図面においてなされるものである。また、異なる図面にそれぞれ示される構成などの大きさおよび位置の相互関係は、必ずしも正確に記載されるものではなく、適宜変更され得るものである。また、断面図ではない平面図などの図面においても、実施の形態の内容を理解することを容易にするために、ハッチングが付される場合がある。 Note that the drawings are shown schematically, and for convenience of explanation, the configuration is omitted or the configuration is simplified as appropriate in the drawings. Further, the interrelationship between the sizes and positions of the configurations and the like shown in different drawings is not always accurately described and can be changed as appropriate. Further, even in a drawing such as a plan view which is not a cross-sectional view, hatching may be added to facilitate understanding of the contents of the embodiment.
　また、以下に示される説明では、同様の構成要素には同じ符号を付して図示し、それらの名称と機能とについても同様のものとする。したがって、それらについての詳細な説明を、重複を避けるために省略する場合がある。 Further, in the explanation shown below, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description of them may be omitted to avoid duplication.
　また、以下に記載される説明において、ある構成要素を「備える」、「含む」または「有する」などと記載される場合、特に断らない限りは、他の構成要素の存在を除外する排他的な表現ではない。 Further, in the description described below, when it is described that a certain component is "equipped", "included", or "has", the existence of another component is excluded unless otherwise specified. Not an expression.
　また、以下に記載される説明において、「第１の」または「第２の」などの序数が用いられる場合があっても、これらの用語は、実施の形態の内容を理解することを容易にするために便宜上用いられるものであり、これらの序数によって生じ得る順序などに限定されるものではない。 Also, even if ordinal numbers such as "first" or "second" are used in the description described below, these terms make it easy to understand the content of the embodiments. It is used for convenience, and is not limited to the order that can be generated by these ordinal numbers.
　また、以下に記載される説明における、相対的または絶対的な位置関係を示す表現、たとえば、「一方向に」、「一方向に沿って」、「平行」、「直交」、「中心」、「同心」または「同軸」などは、特に断らない限りは、その位置関係を厳密に示す場合、および、公差または同程度の機能が得られる範囲において角度または距離が変位している場合を含むものとする。 Also, in the description described below, expressions indicating relative or absolute positional relationships, for example, "in one direction", "along one direction", "parallel", "orthogonal", "center", Unless otherwise specified, "concentric" or "coaxial" shall include cases where the positional relationship is strictly indicated, and cases where the angle or distance is displaced within the range where tolerance or similar function can be obtained. ..
　また、以下に記載される説明において、等しい状態であることを示す表現、たとえば、「同一」、「等しい」、「均一」または「均質」などは、特に断らない限りは、厳密に等しい状態であることを示す場合、および、公差または同程度の機能が得られる範囲において差が生じている場合を含むものとする。 Further, in the description described below, expressions indicating equality, for example, "same", "equal", "uniform" or "homogeneous", are strictly equal unless otherwise specified. It shall include the case where it indicates that there is, and the case where there is a difference within the range where tolerance or similar function can be obtained.
　また、以下に記載される説明において、「上」、「下」、「左」、「右」、「側」、「底」、「表」または「裏」などの特定の位置または方向を意味する用語が用いられる場合があっても、これらの用語は、実施の形態の内容を理解することを容易にするために便宜上用いられるものであり、実際に実施される際の位置または方向とは関係しないものである。 Also, in the description described below, it means a specific position or direction such as "top", "bottom", "left", "right", "side", "bottom", "front" or "back". Even if terms are used, these terms are used for convenience to facilitate understanding of the contents of the embodiment, and are the positions or directions when they are actually implemented. It has nothing to do with it.
　また、以下に記載される説明において、「…の上面」または「…の下面」などと記載される場合、対象となる構成要素の上面自体または下面自体に加えて、対象となる構成要素の上面または下面に他の構成要素が形成された状態も含むものとする。すなわち、たとえば、「甲の上面に設けられる乙」と記載される場合、甲と乙との間に別の構成要素「丙」が介在することを妨げるものではない。 Further, in the description described below, when "the upper surface of ..." or "the lower surface of ..." is described, in addition to the upper surface itself or the lower surface itself of the target component, the upper surface of the target component is added. Alternatively, it shall include a state in which other components are formed on the lower surface. That is, for example, when the description "B provided on the upper surface of the instep" is described, it does not prevent another component "丙" from intervening between the instep and the second.
　＜第１の実施の形態＞
　以下、本実施の形態に関する半導体モジュール、および、半導体モジュールの製造方法について説明する。 <First Embodiment>
Hereinafter, the semiconductor module according to the present embodiment and the method for manufacturing the semiconductor module will be described.
　また、以下の説明においては、「ＡとＢとが電気的に接続される」という表現は、構成Ａと構成Ｂとの間で双方向に電流が流れ得ることを意味するものとする。 Further, in the following description, the expression "A and B are electrically connected" means that a current can flow in both directions between the configuration A and the configuration B.
　＜半導体モジュールの構成について＞
　図１は、本実施の形態に関する電力用半導体モジュール１００の構成の例を概略的に示す断面図である。また、図２は、図１に例が示された電力用半導体モジュール１００の一部を上面側（図１の紙面上側）から見た場合の平面図である。 <Semiconductor module configuration>
FIG. 1 is a cross-sectional view schematically showing an example of the configuration of the power semiconductor module 100 according to the present embodiment. Further, FIG. 2 is a plan view of a part of the power semiconductor module 100 shown in FIG. 1 as viewed from the upper surface side (upper side of the paper surface in FIG. 1).
　図１は、図２のＡ－Ｂ－Ａ’線に沿う断面図に相当する。また、図２においては、図１に例が示されている、開口部を閉じるカバーまたは封止材などは、図示が省略されている。以下、図１および図２を参照しつつ、電力用半導体モジュール１００の構成について説明する。 FIG. 1 corresponds to a cross-sectional view taken along the line ABA'of FIG. Further, in FIG. 2, the cover or sealing material for closing the opening, which is shown as an example in FIG. 1, is not shown. Hereinafter, the configuration of the power semiconductor module 100 will be described with reference to FIGS. 1 and 2.
　図１に例が示されるように、電力用半導体モジュール１００は、ベース板１０１と、ケース１０２と、絶縁基板１０３と、半導体素子１０４と、配線１０６と、端子１０８と、金属膜１０９とを備えている。 As an example is shown in FIG. 1, the power semiconductor module 100 includes a base plate 101, a case 102, an insulating substrate 103, a semiconductor element 104, a wiring 106, a terminal 108, and a metal film 109. ing.
　ケース１０２は、上面側（図１における紙面上側）および底面側（図１における紙面下側）がともに開口している。 The case 102 is open on both the top surface side (upper side of the paper surface in FIG. 1) and the bottom surface side (lower side of the paper surface in FIG. 1).
　ベース板１０１は、樹脂材などでケース１０２と接合され、かつ、ケース１０２の底面側の開口部に収納される。ベース板１０１は、ケース１０２の底面側の開口部と形状および面積が同一であり、ケース１０２の底面を構成する。 The base plate 101 is joined to the case 102 with a resin material or the like, and is housed in the opening on the bottom surface side of the case 102. The base plate 101 has the same shape and area as the opening on the bottom surface side of the case 102, and constitutes the bottom surface of the case 102.
　ベース板１０１は、たとえば、Ｃｕ板、ＡｌＳｉＣまたはＣｕ－Ｍｏなどの複合材によって構成される。ベース板１０１の厚みは５ｍｍ以下であることが適当であり、使用に際して十分な強度を有しているのであれば、当該厚みは薄いほうがより適している。 The base plate 101 is made of, for example, a Cu plate or a composite material such as AlSiC or Cu—Mo. It is appropriate that the thickness of the base plate 101 is 5 mm or less, and if it has sufficient strength for use, it is more suitable that the thickness is thin.
　ベース板１０１の上面の一部は、絶縁基板１０３の下面の一部に基板下接合材１０７ｂを介して接合される。ベース板１０１の上面の一部には、基板下接合材１０７ｂとの接合性が高まる表面処理が施されており、たとえば、ニッケル（Ｎｉ）めっきが成膜されている。 A part of the upper surface of the base plate 101 is joined to a part of the lower surface of the insulating substrate 103 via the under-board bonding material 107b. A part of the upper surface of the base plate 101 is subjected to a surface treatment that enhances the bondability with the under-board bonding material 107b, and for example, nickel (Ni) plating is formed.
　基板下接合材１０７ｂは、たとえば、すず（Ｓｎ）を基材とするはんだである。しかしながら、基板下接合材１０７ｂは、後述するＡｇ焼結材または液相拡散接合層を形成する接合材であってもよい。なお、基板下接合材１０７ｂが広がらないように、樹脂レジストなどによって絶縁基板１０３が接合される領域以外が被覆されていてもよい。 The under-board bonding material 107b is, for example, a solder using tin (Sn) as a base material. However, the substrate lower bonding material 107b may be an Ag sintered material or a bonding material for forming a liquid phase diffusion bonding layer, which will be described later. The area other than the region where the insulating substrate 103 is bonded may be covered with a resin resist or the like so that the bonding material 107b under the substrate does not spread.
　ケース１０２は、たとえば、ポリフェニルサルファイド樹脂（ＰＰＳ）、ポリブチレンテレフタレート樹脂（ＰＢＴ）またはポリエチレンテレフタレート樹脂（ＰＥＴ）などで構成される。 The case 102 is made of, for example, a polyphenyl sulfide resin (PPS), a polybutylene terephthalate resin (PBT), a polyethylene terephthalate resin (PET), or the like.
　ケース１０２の上面側の開口部から樹脂などの封止材１０５を導入することで、ベース板１０１、絶縁基板１０３、半導体素子１０４、配線１０６および端子１０８が封止材１０５で覆われる。 By introducing a sealing material 105 such as resin from the opening on the upper surface side of the case 102, the base plate 101, the insulating substrate 103, the semiconductor element 104, the wiring 106, and the terminal 108 are covered with the sealing material 105.
　封止材１０５には、たとえば、フィラーが混入されたエポキシ材、または、シリコンゲルなどが用いられる。封止材１０５は、電力用半導体モジュール１００の使用に際して十分な絶縁性を有していればよい。 For the sealing material 105, for example, an epoxy material mixed with a filler, a silicon gel, or the like is used. The encapsulant 105 may have sufficient insulating properties when the power semiconductor module 100 is used.
　ベース板１０１の上面の一部には、絶縁基板１０３の下側導体パターン１０３ｆが基板下接合材１０７ｂ（はんだ）を介して接合される。 The lower conductor pattern 103f of the insulating substrate 103 is joined to a part of the upper surface of the base plate 101 via the under-board bonding material 107b (solder).
　絶縁基板１０３は、絶縁材１０３ｅと、絶縁材１０３ｅの上面に形成される上側導体パターン１０３ａと、絶縁材１０３ｅの上面に形成される上側導体パターン１０３ｂと、絶縁材１０３ｅの上面に形成される上側導体パターン１０３ｃと、絶縁材１０３ｅの上面に形成される上側導体パターン１０３ｄと、絶縁材１０３ｅの下面に形成される下側導体パターン１０３ｆとを備えている。 The insulating substrate 103 includes an insulating material 103e, an upper conductor pattern 103a formed on the upper surface of the insulating material 103e, an upper conductor pattern 103b formed on the upper surface of the insulating material 103e, and an upper side formed on the upper surface of the insulating material 103e. It includes a conductor pattern 103c, an upper conductor pattern 103d formed on the upper surface of the insulating material 103e, and a lower conductor pattern 103f formed on the lower surface of the insulating material 103e.
　絶縁材１０３ｅは、たとえば、酸化アルミニウム（Ａｌ２Ｏ３）、窒化アルミニウム（ＡｌＮ）または窒化ケイ素（Ｓｉ３Ｎ４）などのセラミックス材、または、エポキシ材または液晶ポリマーなどのバインダー材にシリカ、アルミナまたは窒化ホウ素（ＢＮ）などのフィラーが混入された有機絶縁材で構成される。 The insulating material 103e is, for example, a ceramic material such as aluminum oxide (Al 2 O 3 ), aluminum nitride (Al N) or silicon nitride (Si 3 N 4 ), or a binder material such as an epoxy material or a liquid crystal polymer, and silica or alumina. Alternatively, it is composed of an organic insulating material mixed with a filler such as boron nitride (BN).
　上側導体パターン１０３ａ、上側導体パターン１０３ｂ、上側導体パターン１０３ｃ、上側導体パターン１０３ｄおよび下側導体パターン１０３ｆは、たとえば、Ｃｕ材単体、Ｃｕ材にＮｉめっきまたは銀（Ａｇ）めっきを施したもの、または、Ａｌ材にＮｉめっきまたはＡｇめっきを施したもので構成される。 The upper conductor pattern 103a, the upper conductor pattern 103b, the upper conductor pattern 103c, the upper conductor pattern 103d and the lower conductor pattern 103f are, for example, a Cu material alone, a Cu material plated with Ni or silver (Ag), or , Al material is Ni-plated or Ag-plated.
　絶縁基板１０３の下側導体パターン１０３ｆの下面のうち、平面視において半導体素子１０４と平面視において重なる領域を含み、かつ、当該重なる領域よりも大きい領域には、基板下接合材１０７ｂの代わりに金属膜１０９が形成されている。金属膜１０９の中心位置は、半導体素子１０４が搭載される領域の中心と平面視において重なる。 Of the lower surface of the lower conductor pattern 103f of the insulating substrate 103, a region that includes a region that overlaps with the semiconductor element 104 in a plan view and is larger than the overlapping region is a metal instead of the under-board bonding material 107b. A film 109 is formed. The center position of the metal film 109 overlaps with the center of the region on which the semiconductor element 104 is mounted in a plan view.
　なお、一般的に平面視における半導体素子１０４の外形は矩形であるが、平面視における金属膜１０９の外形も矩形である必要はなく、たとえば、金属膜１０９の外形が円形であってもよい。 Although the outer shape of the semiconductor element 104 in a plan view is generally rectangular, the outer shape of the metal film 109 in a plan view does not have to be rectangular, and for example, the outer shape of the metal film 109 may be circular.
　また、金属膜１０９は、コールドスプレー法によって成膜される金属膜であるが、その材質は、下側導体パターン１０３ｆと接合可能な材料であればよく、具体的にはＣｕが適用されていることが望ましい。金属膜１０９の材料は、基板下接合材１０７ｂよりも熱伝導率が大きい材料であればよく、下側導体パターン１０３ｆの表面材料と接合可能な材料であるＮｉまたはＡｇなどの他の金属材料であってもよい。 Further, the metal film 109 is a metal film formed by a cold spray method, but the material may be any material that can be bonded to the lower conductor pattern 103f, and Cu is specifically applied. Is desirable. The material of the metal film 109 may be any material having a thermal conductivity higher than that of the lower substrate bonding material 107b, and may be another metal material such as Ni or Ag which is a material that can be bonded to the surface material of the lower conductor pattern 103f. There may be.
　絶縁基板１０３の上側導体パターン１０３ａの上面には、半導体素子１０４がチップ下接合材１０７ａを介して接合されている。チップ下接合材１０７ａは、たとえば、ナノメートルオーダーのＡｇ粒子、マイクロメートルオーダーのＡｇ粒子、または、ナノメートルオーダーのＡｇ粒子とマイクロメートルオーダーのＡｇ粒子との混合粒子からなるペースト材料を焼結接合させたＡｇ焼結材である。または、チップ下接合材１０７ａは、すず（Ｓｎ）および銅（Ｃｕ）、または、すず（Ｓｎ）およびニッケル（Ｎｉ）などの、液相拡散接合層を形成する接合材であってもよい。または、チップ下接合材１０７ａに代えて、すず（Ｓｎ）または鉛（Ｐｂ）を基材とするはんだ材が用いられてもよい。 A semiconductor element 104 is bonded to the upper surface of the upper conductor pattern 103a of the insulating substrate 103 via a chip bottom bonding material 107a. The subchip bonding material 107a is obtained by sintering and bonding a paste material consisting of, for example, nanometer-order Ag particles, micrometer-order Ag particles, or a mixture of nanometer-order Ag particles and micrometer-order Ag particles. It is a made Ag sintered material. Alternatively, the subchip bonding material 107a may be a bonding material that forms a liquid phase diffusion bonding layer, such as tin (Sn) and copper (Cu), or tin (Sn) and nickel (Ni). Alternatively, instead of the chip bottom bonding material 107a, a solder material using tin (Sn) or lead (Pb) as a base material may be used.
　半導体素子１０４は、スイッチングデバイス１０４ａと還流ダイオード１０４ｂとを含む。スイッチングデバイス１０４ａは、たとえば、ＳｉＣ－ＭＯＳＦＥＴまたはＳｉ－ＩＧＢＴであり、還流ダイオード１０４ｂは、たとえば、ＳｉＣ－ショットキーバリアダイオード（Ｓｃｈｏｔｔｋｙ　ｂａｒｒｉｅｒ　ｄｉｏｄｅ、すなわち、ＳＢＤ）またはＳｉ－フリーホイールダイオード（ｆｒｅｅ－ｗｈｅｅｌｉｎｇ　ｄｉｏｄｅ、すなわち、ＦＷＤ）である。 The semiconductor element 104 includes a switching device 104a and a freewheeling diode 104b. The switching device 104a is, for example, a SiC-MOSFET or Si-IGBT, and the freewheeling diode 104b is, for example, a SiC-Schottky barrier diode (that is, SBD) or a Si-free wheel diode (free-wheeling diode). That is, FWD).
　上側導体パターン１０３ａは、スイッチングデバイス１０４ａのドレイン電極に電気的に接続される。以降の説明において、スイッチングデバイス１０４ａと還流ダイオード１０４ｂとを区別する必要がない場合には、単に半導体素子１０４と称する。 The upper conductor pattern 103a is electrically connected to the drain electrode of the switching device 104a. In the following description, when it is not necessary to distinguish between the switching device 104a and the freewheeling diode 104b, it is simply referred to as the semiconductor element 104.
　ケース１０２には、主端子１０８ａと制御端子１０８ｂとが設置されている。スイッチングデバイス１０４ａは、主端子１０８ａとワイヤー状配線１０６ａによって結線され、制御端子１０８ｂとソース信号配線１０６ｂおよびゲート信号配線１０６ｃによって結線される。還流ダイオード１０４ｂは、主端子１０８ａとワイヤー状配線１０６ａによって結線される。 A main terminal 108a and a control terminal 108b are installed in the case 102. The switching device 104a is connected to the main terminal 108a by the wire-shaped wiring 106a, and is connected to the control terminal 108b by the source signal wiring 106b and the gate signal wiring 106c. The freewheeling diode 104b is connected to the main terminal 108a by a wire-shaped wiring 106a.
　図１では図示が省略されているが、図２に例が示されるように、スイッチングデバイス１０４ａの上面と還流ダイオード１０４ｂの上面とには、それぞれ上面電極１１０が設けられている。さらに、スイッチングデバイス１０４ａの上面には、ゲートパッド１１０ａが設けられている。 Although not shown in FIG. 1, as shown in FIG. 2, upper surface electrodes 110 are provided on the upper surface of the switching device 104a and the upper surface of the freewheeling diode 104b, respectively. Further, a gate pad 110a is provided on the upper surface of the switching device 104a.
　スイッチングデバイス１０４ａの上面の周縁部には保護膜１１１が形成されている。また、保護膜１１１はスイッチングデバイス１０４ａの上面において、ゲートパッド１１０ａを囲むようにして形成されている。すなわち、上面電極１１０とゲートパッド１１０ａとは保護膜１１１によって絶縁されている。 A protective film 111 is formed on the peripheral edge of the upper surface of the switching device 104a. Further, the protective film 111 is formed on the upper surface of the switching device 104a so as to surround the gate pad 110a. That is, the upper surface electrode 110 and the gate pad 110a are insulated by the protective film 111.
　保護膜１１１は、スイッチングデバイス１０４ａの上面および還流ダイオード１０４ｂの上面の物理的な保護と、絶縁距離を増加させるために設けられる。保護膜１１１には、有機物であるポリイミドの他、無機物であるＳｉＯ２またはＳｉＮなどが用いられる。 The protective film 111 is provided to physically protect the upper surface of the switching device 104a and the upper surface of the freewheeling diode 104b and to increase the insulation distance. For the protective film 111, in addition to polyimide, which is an organic substance, SiO 2 or SiN, which is an inorganic substance, is used.
　上面電極１１０の最表面は、一般に純Ａｌ、ＡｌＳｉ合金、ＡｌＣｕ合金およびＡｌＳｉＣｕ合金が用いられる。この合金中のＳｉまたはＣｕの混合比率は、合金中での重量比で５ｗｔ％以下である。また、この合金厚みは５μｍ程度である。 Pure Al, AlSi alloy, AlCu alloy and AlSiCu alloy are generally used for the outermost surface of the top electrode 110. The mixing ratio of Si or Cu in this alloy is 5 wt% or less in terms of the weight ratio in the alloy. The thickness of this alloy is about 5 μm.
　また、配線１０６のうちのワイヤー状配線１０６ａは、Ａｌを主成分とするＡｌワイヤーであり、強度を高くするために微量のＮｉなどの金属が添加されていてもよい。一般に、ワイヤー状配線１０６ａの線径はΦ４００程度が妥当であるが、ウェッジボンディングの打点の数または線径など、必要な通電容量を満たすように任意に設計されるものであり、Φ２００以上、かつ、Φ６００以下の間で任意に選定される。 Further, the wire-shaped wiring 106a of the wiring 106 is an Al wire containing Al as a main component, and a small amount of metal such as Ni may be added in order to increase the strength. Generally, the wire diameter of the wire-shaped wiring 106a is about Φ400, but it is arbitrarily designed to satisfy the required energizing capacity such as the number of wedge bonding dots or the wire diameter, and is Φ200 or more. , Φ600 or less is arbitrarily selected.
　また、配線１０６のうちのソース信号配線１０６ｂおよびゲート信号配線１０６ｃに必要な通電容量は、主配線であるワイヤー状配線１０６ａに求められる電流容量と比較してはるかに小さい。そのため、ワイヤー状配線１０６ａと同じ線径かそれよりも小さい線径のワイヤーが選定されればよく、Φ１００μｍ以上、かつ、Φ４００μｍ以下の間で選定されることが一般的である。 Further, the energizing capacity required for the source signal wiring 106b and the gate signal wiring 106c of the wiring 106 is much smaller than the current capacity required for the wire-shaped wiring 106a which is the main wiring. Therefore, a wire having a wire diameter equal to or smaller than that of the wire-shaped wiring 106a may be selected, and is generally selected between Φ100 μm and more and Φ400 μm or less.
　本実施の形態ではＡｌを主成分とするワイヤーが適用されたが、Ｃｕを主成分とするワイヤーが適用されてもよい。この場合、上面電極１１０の最表面は、Ａｌと比較して硬いＣｕワイヤーによって半導体素子１０４が破壊されないような金属が成膜されていればよく、たとえば、Ｃｕめっきによる電極またはＮｉめっきによる電極が選定される。 In the present embodiment, a wire containing Al as a main component is applied, but a wire containing Cu as a main component may be applied. In this case, the outermost surface of the top electrode 110 may be formed of a metal such that the semiconductor element 104 is not destroyed by the Cu wire, which is harder than Al. For example, an electrode by Cu plating or an electrode by Ni plating may be formed. Be selected.
　また、図示は省略されるが、ワイヤー状配線１０６ａの形状はワイヤー状である必要はなく、たとえば、板状の配線であってもよく、この場合、主端子１０８ａから半導体素子１０４の上方に延びる板状配線と上面電極１１０とが、たとえば、はんだによって接合されていればよい。また、この場合、上面電極１１０は、はんだの濡れ性を確保することができる金属であればよく、たとえば、Ｎｉめっきの上面にＡｕめっきが成膜された金属であればよい。板状配線の板厚は、通電される電流によって決定されるが、たとえば、０．３ｍｍ以上、かつ、１．５ｍｍ以下程度が適当である。 Further, although not shown, the shape of the wire-shaped wiring 106a does not have to be wire-shaped, and may be, for example, plate-shaped wiring. In this case, the wire-shaped wiring 106a extends above the semiconductor element 104 from the main terminal 108a. The plate-shaped wiring and the top electrode 110 may be joined by, for example, solder. Further, in this case, the upper surface electrode 110 may be a metal capable of ensuring the wettability of the solder, and may be, for example, a metal having Au plating formed on the upper surface of Ni plating. The plate thickness of the plate-shaped wiring is determined by the energized current, and for example, 0.3 mm or more and 1.5 mm or less is appropriate.
　図１および図２には図示されていないが、電力用半導体モジュール１００内には温度検知用のダイオードが設けられている。このダイオードのカソード電極およびアノード電極に接続される配線にも、ゲート信号配線１０６ｃと同様に、ＣｕワイヤーまたはＡｌワイヤーが用いられる。 Although not shown in FIGS. 1 and 2, a diode for temperature detection is provided in the power semiconductor module 100. Similar to the gate signal wiring 106c, Cu wire or Al wire is also used for the wiring connected to the cathode electrode and the anode electrode of this diode.
　電力用半導体モジュール１００の動作に伴う急峻な温度変化が半導体素子１０４で発生する場合について、以下説明する。 The case where a steep temperature change occurs in the semiconductor element 104 due to the operation of the power semiconductor module 100 will be described below.
　半導体素子１０４で発生する熱はベース板１０１の鉛直方向（図１におけるＺ軸方向）に向かって放熱され、冷却器（ここでは、図示しない）によって吸熱（冷却）される。 The heat generated by the semiconductor element 104 is dissipated in the vertical direction (Z-axis direction in FIG. 1) of the base plate 101, and is endothermic (cooled) by a cooler (not shown here).
　絶縁基板１０３の下面側の基板下接合材１０７ｂであるはんだは、線膨張係数が小さい絶縁材１０３ｅであるセラミックと、線膨張係数が小さいベース板１０１であるＡｌＳｉＣとに間接的に挟まれることとなる。 The solder, which is the under-board bonding material 107b on the lower surface side of the insulating substrate 103, is indirectly sandwiched between the ceramic, which is the insulating material 103e having a small coefficient of linear expansion, and AlSiC, which is the base plate 101 having a small coefficient of linear expansion. Become.
　基板下接合材１０７ｂであるはんだ自身の膨張収縮に対して、基板下接合材１０７ｂの上下に位置する絶縁基板１０３およびベース板１０１の膨張収縮が小さい。そのため、基板下接合材１０７ｂであるはんだの内部に繰り返し圧縮および膨張の応力が加わり、はんだ内部に鉛直方向に亀裂が発生する。 The expansion and contraction of the insulating substrate 103 and the base plate 101 located above and below the underboard bonding material 107b is smaller than the expansion and contraction of the solder itself, which is the underboard bonding material 107b. Therefore, stresses of repeated compression and expansion are repeatedly applied to the inside of the solder which is the under-board bonding material 107b, and cracks are generated inside the solder in the vertical direction.
　温度変化が激しい半導体素子１０４直下のチップ下接合材１０７ａであるはんだにも亀裂が発生する。そうすると、放熱性を悪化させるだけでなく、接合部の信頼性まで損なわれる。 Cracks also occur in the solder, which is the under-chip bonding material 107a directly under the semiconductor element 104 where the temperature changes drastically. Then, not only the heat dissipation is deteriorated, but also the reliability of the joint is impaired.
　これに対し、本実施の形態に関する電力用半導体モジュール１００においては、絶縁基板１０３の下面側における下側導体パターン１０３ｆの下面のうち、半導体素子１０４の搭載位置に対向する位置には、コールドスプレー法によって成膜された金属膜１０９が形成されている。具体的には、金属膜１０９は、Ｃｕ粉によって成膜されたコールドスプレー膜である。 On the other hand, in the power semiconductor module 100 according to the present embodiment, the cold spray method is performed at a position of the lower surface of the lower conductor pattern 103f on the lower surface side of the insulating substrate 103, which faces the mounting position of the semiconductor element 104. The metal film 109 formed by the above is formed. Specifically, the metal film 109 is a cold spray film formed of Cu powder.
　半導体素子１０４の直下の領域に、基板下接合材１０７ｂであるはんだよりも熱伝導率が大きいＣｕによって構成される金属膜１０９が成膜されていることで、電力用半導体モジュール１００の放熱性が向上する。 A metal film 109 composed of Cu, which has a higher thermal conductivity than solder, which is a bonding material under the substrate 107b, is formed in a region directly below the semiconductor element 104, so that the heat dissipation of the power semiconductor module 100 can be improved. improves.
　また、Ｃｕの熱膨張率は、はんだの熱膨張率と、ベース板１０１の熱膨張率または絶縁材１０３ｅの熱膨張率との間の値である。したがって、電力用半導体モジュール１００の動作時に基板下接合材１０７ｂに発生する応力を低減させることができる。 The coefficient of thermal expansion of Cu is a value between the coefficient of thermal expansion of the solder and the coefficient of thermal expansion of the base plate 101 or the coefficient of thermal expansion of the insulating material 103e. Therefore, it is possible to reduce the stress generated in the under-board bonding material 107b during the operation of the power semiconductor module 100.
　さらに、Ｃｕははんだと比較して機械的強度が高いことから、はんだの場合のような亀裂が発生しにくく、また、発生した場合であっても亀裂進展が遅い。そのため、Ｃｕによれば、接合部の信頼性が低下しにくい。 Furthermore, since Cu has higher mechanical strength than solder, cracks are less likely to occur as in the case of solder, and even if they do occur, crack growth is slow. Therefore, according to Cu, the reliability of the joint portion is unlikely to decrease.
　金属膜１０９を湿式めっき法で成膜する場合、成膜レートが遅いため製造コストが高くなる。一方で、コールドスプレー法では後述のように、高圧で粉体を積層することによってコールドスプレー膜が成膜されることから、任意の位置に、任意の形状および任意の膜厚で金属膜１０９を成膜することができる。 When the metal film 109 is formed by the wet plating method, the film forming rate is slow and the manufacturing cost is high. On the other hand, in the cold spray method, as will be described later, a cold spray film is formed by laminating powder at high pressure, so that the metal film 109 is formed at an arbitrary position with an arbitrary shape and an arbitrary film thickness. A film can be formed.
　さらに、コールドスプレー膜は完全なバルク体とはならず、膜内部に空孔が生じている。この空孔が緩衝層となり、金属膜１０９に発生する応力を緩和する効果を有する。そのため、金属膜１０９の成膜法として、コールドスプレー法は望ましい成膜法といえる。 Furthermore, the cold spray membrane is not a complete bulk body, and there are vacancies inside the membrane. These pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Therefore, it can be said that the cold spray method is a desirable film forming method for the metal film 109.
　バルク体のＣｕの熱伝導率は３８７．５Ｗ／ｍ・Ｋである。これに対して、コールドスプレー法の条件によって空孔率は制御可能であるが、空孔を有しているコールドスプレー膜の見かけの熱伝導率は、１５０Ｗ／ｍ・Ｋ以上、かつ、３００Ｗ／ｍ・Ｋ以下の範囲であり、熱伝導率が４０Ｗ／ｍ・Ｋ以上、かつ、５０Ｗ／ｍ・Ｋ以下の範囲であるＳｎまたはＰｂを基材とするはんだの熱伝導率と比較して、遥かに大きい熱伝導率を有していることが分かる。このことから、金属膜１０９が十分な放熱性を有しているといえる。 The thermal conductivity of Cu in bulk is 387.5 W / m · K. On the other hand, although the pore ratio can be controlled by the conditions of the cold spray method, the apparent thermal conductivity of the cold spray film having pores is 150 W / m · K or more and 300 W / K /. Compared with the thermal conductivity of Sn or Pb-based solder, which is in the range of m · K or less and has a thermal conductivity of 40 W / m · K or more and 50 W / m · K or less, It can be seen that it has a much higher thermal conductivity. From this, it can be said that the metal film 109 has sufficient heat dissipation.
　＜半導体モジュールの製造方法について＞
　このような金属膜１０９を有する電力用半導体モジュールの製造方法について説明する。チップ下接合材１０７ａと基板下接合材１０７ｂとが同一組成のはんだである場合、または、チップ下接合材１０７ａの融点が基板下接合材１０７ｂの融点よりも低いはんだ材である場合には、アセンブリ投入前に、下側導体パターン１０３ｆの下面の一部に直接コールドスプレーで金属膜１０９が成膜された状態の絶縁基板１０３を、ベース板１０１の上面に、基板下接合材１０７ｂであるはんだを挟むように配置する。 <Manufacturing method of semiconductor module>
A method for manufacturing a power semiconductor module having such a metal film 109 will be described. Assembly when the sub-chip bonding material 107a and the sub-board bonding material 107b are solders having the same composition, or when the melting point of the sub-chip bonding material 107a is lower than the melting point of the sub-chip bonding material 107b. Before charging, the insulating substrate 103 in which the metal film 109 is directly formed on a part of the lower surface of the lower conductor pattern 103f by cold spray is placed on the upper surface of the base plate 101, and the solder as the under-board bonding material 107b is placed on the upper surface of the base plate 101. Arrange so as to sandwich.
　その後、上側導体パターン１０３ａの上面との間にチップ下接合材１０７ａを挟むように半導体素子１０４の下面を配置して、リフロー炉によってはんだ付けを行う。 After that, the lower surface of the semiconductor element 104 is arranged so as to sandwich the subchip bonding material 107a with the upper surface of the upper conductor pattern 103a, and soldering is performed by a reflow furnace.
　基板下接合材１０７ｂの厚さは、コールドスプレー膜（金属膜１０９）の厚さに基づいて定められる。金属膜１０９の厚さは１００μｍ以上、かつ、３００μｍ以下であることが適切である。 The thickness of the substrate bottom bonding material 107b is determined based on the thickness of the cold spray film (metal film 109). It is appropriate that the thickness of the metal film 109 is 100 μm or more and 300 μm or less.
　金属膜１０９が形成されていない場合、基板下接合材１０７ｂの厚みが均一になるようにワイヤーバンプなどをベース板１０１に配置することではんだ厚が確保されていたが、金属膜１０９が、複数の半導体素子１０４の搭載位置と対向する位置にそれぞれ配置されていることから、ワイヤーバンプによる基板下接合材１０７ｂのはんだ厚確保の必要性がなくなり、関連する工程数を削減することができる。 When the metal film 109 was not formed, the solder thickness was secured by arranging wire bumps or the like on the base plate 101 so that the thickness of the under-board bonding material 107b was uniform, but there were a plurality of metal films 109. Since the semiconductor elements 104 are arranged at positions facing each other, it is not necessary to secure the solder thickness of the under-board bonding material 107b by wire bumps, and the number of related steps can be reduced.
　製造工程において金属膜１０９の下面に配置された状態の基板下接合材１０７ｂであるはんだは、リフロー炉による加熱によって溶融する。そして、絶縁基板１０３および半導体素子１０４の自重によって金属膜１０９の下面から排斥されるが、金属膜１０９の下面における凹凸に留まるはんだとベース板１０１の上面とが接合して接合層が形成される。また、この溶融しているはんだは、金属膜１０９内部の一部の空孔内にも侵入し、一部の空孔がはんだで埋められることによって、金属膜１０９の見かけの熱伝導率も改善する。また、金属膜１０９とはんだとの接触部では、Ｃｕが溶融してＣｕとＳｎとの金属間化合物相が形成される。 The solder, which is the under-board bonding material 107b arranged on the lower surface of the metal film 109 in the manufacturing process, is melted by heating with a reflow furnace. Then, the solder is excluded from the lower surface of the metal film 109 due to the weight of the insulating substrate 103 and the semiconductor element 104, but the solder remaining on the uneven surface on the lower surface of the metal film 109 and the upper surface of the base plate 101 are joined to form a bonding layer. .. In addition, the molten solder also penetrates into some of the pores inside the metal film 109, and by filling some of the pores with solder, the apparent thermal conductivity of the metal film 109 is also improved. To do. Further, at the contact portion between the metal film 109 and the solder, Cu is melted to form an intermetallic compound phase of Cu and Sn.
　以上では、金属膜１０９が絶縁基板１０３の下側導体パターン１０３ｆに成膜されている構造について説明されたが、ベース板１０１の上面（はんだ接合面）に金属膜１０９が成膜されている状態で基板下接合材１０７ｂによって接合される構造であっても、放熱性の向上および接合部の信頼性の向上が実現される。 In the above, the structure in which the metal film 109 is formed on the lower conductor pattern 103f of the insulating substrate 103 has been described, but the state in which the metal film 109 is formed on the upper surface (solder joint surface) of the base plate 101. Even if the structure is joined by the under-board bonding material 107b, the heat dissipation and the reliability of the joint can be improved.
　この場合、下側導体パターン１０３ｆの下面と金属膜１０９の上面との間にはんだ層が介在するため、放熱性を向上させるという点では、下側導体パターン１０３ｆに金属膜１０９が成膜されている場合の方が効果的である。 In this case, since the solder layer is interposed between the lower surface of the lower conductor pattern 103f and the upper surface of the metal film 109, the metal film 109 is formed on the lower conductor pattern 103f in terms of improving heat dissipation. It is more effective when there is.
　次に、チップ下接合材１０７ａの組成と基板下接合材１０７ｂの組成とが異なる場合、特にチップ下接合材１０７ａの融点が基板下接合材１０７ｂの融点よりも高い場合の電力用半導体モジュールの製造方法について説明する。 Next, the manufacture of a power semiconductor module when the composition of the subchip bonding material 107a and the composition of the substrate sublayer bonding material 107b are different, particularly when the melting point of the chip subbonding material 107a is higher than the melting point of the subchip bonding material 107b. The method will be described.
　具体的には、チップ下接合材にＡｇ焼結材料またはＳｎとＣｕとによる液層拡散接合層を形成する接合を適用する製造方法である。もちろん、前述の通り、下側導体パターン１０３ｆの下面にあらかじめ金属膜１０９が成膜されている絶縁基板１０３における上側導体パターン１０３ａの上面に、Ａｇ焼結材料によって半導体素子１０４が接合されてもよい。 Specifically, it is a manufacturing method in which an Ag sintered material or a bonding that forms a liquid layer diffusion bonding layer of Sn and Cu is applied to the bonding material under the chip. Of course, as described above, the semiconductor element 104 may be bonded to the upper surface of the upper conductor pattern 103a of the insulating substrate 103 in which the metal film 109 is previously formed on the lower surface of the lower conductor pattern 103f by the Ag sintering material. ..
　半導体素子１０４が接合された後、上側導体パターン１０３ｂ、上側導体パターン１０３ｃまたは上側導体パターン１０３ｄと半導体素子１０４の上面電極とを、アルミワイヤーによって配線する。 After the semiconductor element 104 is joined, the upper conductor pattern 103b, the upper conductor pattern 103c or the upper conductor pattern 103d and the upper surface electrode of the semiconductor element 104 are wired by an aluminum wire.
　このように、ベース板１０１を接合させる前の絶縁基板１０３に、アルミワイヤーによる配線をしておくことで、半導体素子１０４の不具合を事前に確認することができる。 In this way, by wiring the insulating substrate 103 with the aluminum wire before joining the base plate 101, it is possible to confirm the defect of the semiconductor element 104 in advance.
　そうすると、一括で半導体素子１０４と絶縁基板１０３とをはんだ付け（リフロー）する場合と比較して、半導体素子１０４の不具合確認時の仕損費を軽減することができる。 Then, as compared with the case where the semiconductor element 104 and the insulating substrate 103 are soldered (reflowed) all at once, it is possible to reduce the defective cost at the time of confirming the defect of the semiconductor element 104.
　また、Ａｇ焼結またはＳｎとＣｕとによる液層拡散接合層を形成する接合によって半導体素子１０４を絶縁基板１０３における上側導体パターン１０３ａの上面に接合する場合、Ａｇ焼結またはＳｎとＣｕとによる液相拡散接合層を形成する接合を均一に発生させるために、これらの構成を加熱および加圧して接合させる必要がある。 Further, when the semiconductor element 104 is bonded to the upper surface of the upper conductor pattern 103a on the insulating substrate 103 by Ag sintering or bonding to form a liquid layer diffusion bonding layer of Sn and Cu, the liquid of Ag sintering or Sn and Cu is used. In order to uniformly generate the bonding forming the phase diffusion bonding layer, it is necessary to heat and pressurize these configurations to bond them.
　上側導体パターン１０３ａの上面に、熱膨張率が小さい半導体素子１０４が接合されることから、加熱および加圧後の半導体素子１０４が搭載された絶縁基板１０３は、半導体素子１０４が搭載された部分を頂点として上に凸の形状に反る。 Since the semiconductor element 104 having a small coefficient of thermal expansion is bonded to the upper surface of the upper conductor pattern 103a, the insulating substrate 103 on which the semiconductor element 104 after heating and pressurization is mounted has a portion on which the semiconductor element 104 is mounted. It warps upward as a peak.
　そのため、Ａｇ焼結またはＳｎとＣｕとによる液層拡散接合層を形成する接合の後に、下側導体パターン１０３ｆの下面とベース板１０１の上面を基板下接合材１０７ｂではんだ付けする場合、半導体素子１０４が搭載された位置の直下における下側導体パターン１０３ｆとベース板１０１との間の接合層が厚くなるため放熱性が悪化する。 Therefore, when the lower surface of the lower conductor pattern 103f and the upper surface of the base plate 101 are soldered with the under-board bonding material 107b after Ag sintering or bonding to form a liquid layer diffusion bonding layer with Sn and Cu, the semiconductor element Since the bonding layer between the lower conductor pattern 103f and the base plate 101 immediately below the position where the 104 is mounted becomes thicker, the heat dissipation property deteriorates.
　しかしながら、コールドスプレー法によってコールドスプレー膜（金属膜１０９）を当該箇所に形成することで、コールドスプレー膜がない場合と比較して、より効果的に放熱性を向上することができる。 However, by forming the cold spray film (metal film 109) at the relevant portion by the cold spray method, the heat dissipation can be improved more effectively as compared with the case where there is no cold spray film.
　また、半導体素子１０４を上側導体パターン１０３ａに対して、Ａｇ焼結またはＳｎとＣｕとによる液相拡散接合層を形成する接合をした後に、金属膜１０９をコールドスプレー法によって成膜することによって、半導体素子１０４が搭載された部分を頂点として絶縁基板１０３が上に凸形状に反った状態で、金属膜１０９が成膜される。 Further, the semiconductor element 104 is bonded to the upper conductor pattern 103a by Ag sintering or forming a liquid phase diffusion bonding layer of Sn and Cu, and then a metal film 109 is formed by a cold spray method. The metal film 109 is formed with the insulating substrate 103 warped upward in a convex shape with the portion on which the semiconductor element 104 is mounted as the apex.
　コールドスプレー膜（金属膜１０９）は、その端部と比較してその中心部が厚く成膜される。この際に、金属膜１０９は絶縁基板１０３の形状に沿って成膜されるのではなく、半導体素子１０４が搭載される部分が厚くなるように成膜される。 The cold spray film (metal film 109) is formed thicker at the center than at the edges. At this time, the metal film 109 is not formed along the shape of the insulating substrate 103, but is formed so that the portion on which the semiconductor element 104 is mounted becomes thick.
　ベース板１０１と絶縁基板１０３とが基板下接合材１０７ｂによってはんだ付けされる際に、ベース板１０１と絶縁基板１０３との間に金属膜１０９が成膜されていることで、はんだ付けによって金属膜１０９の温度が上昇し、それに伴って金属膜１０９が膨張する。そうすると、半導体素子１０４が搭載された部分を頂点とする凸形状が緩和されるため好ましい。 When the base plate 101 and the insulating substrate 103 are soldered by the under-board bonding material 107b, a metal film 109 is formed between the base plate 101 and the insulating substrate 103, so that the metal film is formed by soldering. The temperature of 109 rises, and the metal film 109 expands accordingly. This is preferable because the convex shape having the portion on which the semiconductor element 104 is mounted as the apex is relaxed.
　半導体素子１０４が搭載され、かつ、半導体素子１０４がアルミワイヤーで配線された状態の絶縁基板１０３の下側導体パターン１０３ｆの下面の一部（半導体素子１０４が搭載された部分）に、金属膜１０９が成膜される。この状態で、下側導体パターン１０３ｆの下面を、上面に板状の基板下接合材１０７ｂ（はんだ）が配置された状態のベース板１０１の上面にリフローしてはんだ付けする。 A metal film 109 is mounted on a part of the lower surface (a portion on which the semiconductor element 104 is mounted) of the lower conductor pattern 103f of the insulating substrate 103 in a state where the semiconductor element 104 is mounted and the semiconductor element 104 is wired with an aluminum wire. Is formed. In this state, the lower surface of the lower conductor pattern 103f is reflowed and soldered to the upper surface of the base plate 101 in which the plate-shaped sub-board bonding material 107b (solder) is arranged on the upper surface.
　次に、主端子１０８ａまたは制御端子１０８ｂがインサート成形またはアウトサート成形によって設置されたケース１０２を、接着剤などを用いてベース板１０１に接着する。その後、絶縁基板１０３、主端子１０８ａおよび制御端子１０８ｂにワイヤー配線などで結線する。その後、封止材１０５をケース１０２内に充填し、さらに、蓋を被せて電力用半導体モジュール１００を完成させる。 Next, the case 102 in which the main terminal 108a or the control terminal 108b is installed by insert molding or outsert molding is adhered to the base plate 101 using an adhesive or the like. After that, it is connected to the insulating substrate 103, the main terminal 108a, and the control terminal 108b by wire wiring or the like. After that, the case 102 is filled with the sealing material 105, and the case 102 is further covered with a lid to complete the power semiconductor module 100.
　金属膜１０９の成膜方法について、図３を参照しつつ以下説明する。ここで、図３は、本実施の形態に関する金属膜の成膜方法を説明するための断面図である。 The film forming method of the metal film 109 will be described below with reference to FIG. Here, FIG. 3 is a cross-sectional view for explaining a method for forming a metal film according to the present embodiment.
　半導体素子１０４を上側導体パターン１０３ａに搭載して、ワイヤー状配線１０６ａを配線した後の絶縁基板１０３を、半導体素子１０４を傷つけず、かつ、ワイヤー状配線１０６ａを変形させないように絶縁基板保持治具２０２上に配置する。そして、金属膜１０９が形成される面である下側導体パターン１０３ｆを部分的に露出させた状態で、金属膜１０９の形状を決定するためのコールドスプレー膜用マスク２０１を配置する。 An insulating substrate holding jig for mounting the semiconductor element 104 on the upper conductor pattern 103a and wiring the wire-shaped wiring 106a so as not to damage the semiconductor element 104 and deform the wire-shaped wiring 106a. Place on 202. Then, the cold spray film mask 201 for determining the shape of the metal film 109 is arranged in a state where the lower conductor pattern 103f, which is the surface on which the metal film 109 is formed, is partially exposed.
　そして、コールドスプレー装置（ここでは、図示しない）から金属粉体を吐出することによって、下側導体パターン１０３ｆの露出している部分に金属膜１０９が成膜される。 Then, by discharging the metal powder from a cold spray device (not shown here), a metal film 109 is formed on the exposed portion of the lower conductor pattern 103f.
　コールドスプレー装置から吐出された金属粉体が被接合面である下側導体パターン１０３ｆに衝突すると、金属粉体の熱エネルギーと運動エネルギーとが摩擦熱に変わり、金属粉体および被接合面のそれぞれの最表面で変形が生じて相互に絡み合う。また、それぞれの最表面における金属酸化膜が除去されて、金属粉体と被接合面との界面で生じる反応によりコールドスプレー膜が形成される。また、先に形成されたコールドスプレー膜の上に、連続的にコールドスプレー装置から金属粉体が吐出されて衝突することでコールドスプレー膜の膜厚が増加し、最終的に金属膜１０９となる。 When the metal powder discharged from the cold spray device collides with the lower conductor pattern 103f, which is the surface to be bonded, the thermal energy and kinetic energy of the metal powder are converted into frictional heat, and the metal powder and the surface to be bonded are respectively. Deformation occurs on the outermost surface of the and entangles with each other. Further, the metal oxide film on the outermost surface of each is removed, and a cold spray film is formed by the reaction occurring at the interface between the metal powder and the surface to be bonded. Further, the metal powder is continuously discharged from the cold spray device onto the previously formed cold spray film and collides with the cold spray film, so that the film thickness of the cold spray film is increased and finally becomes the metal film 109. ..
　なお、コールドスプレー装置から供給される金属粉体は、Ｃｕ粉体であり、ＪＩＳ（日本工業規格）に適合する目開きが１００μｍ（１４９メッシュ）の試験用フルイを通過することによって、その粒径が制御されている。 The metal powder supplied from the cold spray device is Cu powder, and its particle size is obtained by passing through a test fluid having a mesh size of 100 μm (149 mesh) conforming to JIS (Japanese Industrial Standards). Is controlled.
　Ｃｕ粉体の製法としては、電解法、高圧旋回水アトマイズ法、または、水アトマイズ法などが用いられる。電解法によって生成されたＣｕ粉体の粒子形状は、樹枝（デンドライト）形状に近く、高圧旋回水アトマイズ法によって生成されたＣｕ粉体の粒子形状は、球形状に近い。いずれの形状のＣｕ粉体であっても、被接合面に衝突することで原型を留めない薄い扁平状となる。 As a method for producing Cu powder, an electrolysis method, a high-pressure swirling water atomizing method, a water atomizing method, or the like is used. The particle shape of the Cu powder produced by the electrolytic method is close to the dendrite shape, and the particle shape of the Cu powder produced by the high-pressure swirling water atomization method is close to the spherical shape. Regardless of the shape of Cu powder, when it collides with the surface to be joined, it becomes a thin flat shape that does not retain the prototype.
　目開きが１００μｍのフルイを通過した粒子は、粒径が１００μｍ以下の粒径分布を有する。ただし、レーザー回折法によって回折散乱パターンを解析して粒径を測定した場合、横軸を粒径とし、縦軸を頻度（個数）とする粒径分布図において、頻度（個数）が最大となる粒径が２０μｍ程度であることが望ましい。すなわち、粒径が２０μｍ程度の粒子が分布のピークを形成し、当該ピークを形成する粒子を中心に、それよりも粒径が小さな粒子および大きな粒子が存在することが望ましい。どちらかといえば、粒径が２０μｍ以下の粒子ができるだけ多い方が、粒子間隔が緻密なコールドスプレー膜を得るという観点からは望ましく、このような粒径分布の金属粉体を得られるように、粒子の製造条件を制御することが望ましい。 Particles that have passed through a sieve with a mesh size of 100 μm have a particle size distribution of 100 μm or less. However, when the diffraction scattering pattern is analyzed by the laser diffraction method and the particle size is measured, the frequency (number) is the maximum in the particle size distribution diagram in which the horizontal axis is the particle size and the vertical axis is the frequency (number). It is desirable that the particle size is about 20 μm. That is, it is desirable that particles having a particle size of about 20 μm form a peak of the distribution, and particles having a smaller particle size and particles having a particle size larger than that are present around the particles forming the peak. If anything, it is desirable to have as many particles as possible having a particle size of 20 μm or less from the viewpoint of obtaining a cold spray film having a fine particle spacing, so that a metal powder having such a particle size distribution can be obtained. It is desirable to control the manufacturing conditions of the particles.
　なお、ここで粒径のピークが２０μｍとする場合、粒径が２０μｍの粒子だけでなく、２０μｍに対して±１０％の差を有する粒径の粒子も、ピークを形成する粒子とする。 When the peak particle size is 20 μm, not only the particles having a particle size of 20 μm but also the particles having a particle size difference of ± 10% with respect to 20 μm are used as the particles forming the peak.
　フルイの目開きは、１００μｍ未満であってもよい。たとえば、目開きが５３μｍ（２７０メッシュ）のフルイを用いる場合は、粒径が５３μｍ以下の粒子が得られる。 The opening of the fluid may be less than 100 μm. For example, when a sieve having a mesh size of 53 μm (270 mesh) is used, particles having a particle size of 53 μm or less can be obtained.
　ただし、フルイの目開きが小さいと収率が低くなるため、安価にコールドスプレー膜を形成するには、フルイの目開きが１００μｍ程度であることが望ましい。 However, if the opening of the fluid is small, the yield will be low. Therefore, in order to form a cold spray film at low cost, it is desirable that the opening of the fluid is about 100 μm.
　粒径が大きな粒子は、後述するコールドスプレー装置のノズルから吐出される際に、コールドスプレー膜の形成に十分な運動エネルギーを得られない。そのため、先に形成されたコールドスプレー膜に衝突しても粒子どうしの接合が生じず、吐出ガスの流れによって膜外にはじかれ、成膜に寄与しない。 Particles with a large particle size cannot obtain sufficient kinetic energy to form a cold spray film when they are discharged from the nozzle of a cold spray device described later. Therefore, even if the particles collide with the previously formed cold spray film, the particles do not bond with each other and are repelled by the flow of the discharged gas to the outside of the film, which does not contribute to the film formation.
　そのため、均一に金属膜１０９を形成するためには、金属粉体の粒径が小さいほうがよく、１００μｍ以下、より好ましくは６０μｍ以下である。 Therefore, in order to uniformly form the metal film 109, the particle size of the metal powder is preferably small, and is 100 μm or less, more preferably 60 μm or less.
　なお、金属粉体の粒径の下限は、たとえば、１．０μｍであるが、粒径の下限を制御するためにフルイによる選別を行う必要はない。また、以下に説明する理由から、金属粉体の粒径を均一にする必要はなく、均一にするためにフルイによる選別を行う必要はない。 The lower limit of the particle size of the metal powder is, for example, 1.0 μm, but it is not necessary to perform sorting by a sieve in order to control the lower limit of the particle size. Further, for the reason described below, it is not necessary to make the particle size of the metal powder uniform, and it is not necessary to perform sorting by a fluid to make the particle size uniform.
　すなわち、所定の目開きを有するフルイにかけられた金属粉体は、当該目開き以下の粒径分布を有する。このような金属粉体を用いてコールドスプレーによる成膜を行うと、より重量の軽い微細な粒子から優先的に下側導体パターン１０３ｆに衝突してコールドスプレー膜を形成し、その後、より重量が重く粒径の大きな粒子が先に形成されたコールドスプレー膜に衝突する。 That is, the metal powder applied to the fluid having a predetermined opening has a particle size distribution equal to or less than the opening. When a film is formed by cold spray using such a metal powder, fine particles having a lighter weight preferentially collide with the lower conductor pattern 103f to form a cold spray film, and then the weight becomes heavier. Heavy, large particles collide with the previously formed cold spray film.
　さらに、成膜の初期段階では微細な粒子が下側導体パターン１０３ｆに衝突するため、下側導体パターン１０３ｆに近い側は、粒径の小さな粒子によって構成された緻密なコールドスプレー膜となる。この緻密なコールドスプレー膜の上に、上述の目開き以下の粒径分布の金属粉体が順次に衝突するので、緻密なコールドスプレー膜上に、より粗いコールドスプレー膜が成膜される。なお、粒径の大きな粒子間に粒径の小さな粒子が衝突することで、粉体粒子間隔が比較的小さな膜が成膜される。そのため、金属膜１０９の上層は比較的緻密な膜となる。 Further, since fine particles collide with the lower conductor pattern 103f in the initial stage of film formation, the side close to the lower conductor pattern 103f becomes a dense cold spray film composed of particles having a small particle size. Since the metal powder having a particle size distribution equal to or less than the above-mentioned opening collides with the dense cold spray film in sequence, a coarser cold spray film is formed on the dense cold spray film. When particles having a small particle size collide with each other, a film having a relatively small powder particle spacing is formed. Therefore, the upper layer of the metal film 109 is a relatively dense film.
　その結果、金属膜１０９は、その粉体粒子間隔が下側導体パターン１０３ｆに近いほど小さく、下側導体パターン１０３ｆから離れるほど粉体粒子間隔が大きく、金属膜１０９の最表面（下側導体パターン１０３ｆから最も遠い面）に近づくにつれて再び粉体粒子間隔が小さくなる膜構造を有する。 As a result, the powder particle spacing of the metal film 109 is smaller as the powder particle spacing is closer to the lower conductor pattern 103f, and the powder particle spacing is larger as the distance from the lower conductor pattern 103f is larger. It has a film structure in which the powder particle spacing becomes smaller again as it approaches (the surface farthest from 103f).
　金属膜１０９の形状については、コールドスプレー膜用マスク２０１を下側導体パターン１０３ｆに張り合わせて位置決めすることで決定する。コールドスプレー膜用マスク２０１は、開口部を有するＳＵＳ製のマスクであり、厚みが１ｍｍ程度である。コールドスプレー膜用マスク２０１は、コールドスプレー装置からの供給される粉体の衝突によっては変形しにくい材料であり、変形しにくい程度の厚みを有する材料であれば特に制限されない。 The shape of the metal film 109 is determined by abutting the cold spray film mask 201 on the lower conductor pattern 103f and positioning it. The cold spray film mask 201 is a mask made of SUS having an opening and has a thickness of about 1 mm. The cold spray film mask 201 is a material that is not easily deformed by the collision of powder supplied from the cold spray device, and is not particularly limited as long as it is a material having a thickness that is difficult to be deformed.
　コールドスプレー膜用マスク２０１の開口部が下側導体パターン１０３ｆに張り合わせられた状態で粉体が供給されるため、絶縁材１０３ｅに金属粉体（Ｃｕ粉）が付着することがない。 Since the powder is supplied in a state where the opening of the cold spray film mask 201 is attached to the lower conductor pattern 103f, the metal powder (Cu powder) does not adhere to the insulating material 103e.
　なお、下側導体パターン１０３ｆはＣｕからなるが、その表面に湿式めっき法によってＮｉめっき膜が形成されていてもよいし、その表面に真空蒸着によってＮｉスパッタ膜が形成されていてもよいし、はんだ付け可能な他の膜が形成されていてもよい。 Although the lower conductor pattern 103f is made of Cu, a Ni plating film may be formed on the surface thereof by a wet plating method, or a Ni sputter film may be formed on the surface thereof by vacuum vapor deposition. Other solderable films may be formed.
　本実施の形態では、金属膜１０９の材料となる金属粉体としてＣｕ粉体が用いられている。しかしながら、当該金属粉体は、被接合面との間で金属接合を形成し、かつ、ベース板１０１と絶縁基板１０３とをはんだ付けする際の被接合材となる金属であれば、たとえば、Ｎｉなどであってもよい。 In this embodiment, Cu powder is used as the metal powder used as the material for the metal film 109. However, if the metal powder is a metal that forms a metal bond with the surface to be bonded and is a metal to be bonded when the base plate 101 and the insulating substrate 103 are soldered, for example, Ni. And so on.
　金属膜１０９の厚みは、スプレーの照射時間、照射速度（ガス圧）および照射温度によって制御可能である。本実施の形態では、金属膜１０９が溶融状態のはんだにそのすべてが溶解しなければよく、その観点からは、金属膜１０９は１００μｍ以上の厚みがあれば十分である。 The thickness of the metal film 109 can be controlled by the irradiation time of the spray, the irradiation speed (gas pressure), and the irradiation temperature. In the present embodiment, it is sufficient that the metal film 109 does not completely dissolve in the molten solder, and from that viewpoint, the metal film 109 having a thickness of 100 μm or more is sufficient.
　また、金属膜１０９が厚くなり過ぎると、絶縁基板１０３が反り返り、割れてしまう。そのため、金属膜１０９の厚みは、たとえば、３００μｍ以下が望ましい。 Also, if the metal film 109 becomes too thick, the insulating substrate 103 will warp and crack. Therefore, the thickness of the metal film 109 is preferably 300 μm or less, for example.
　湿式めっき法によって形成されたＣｕ膜の結晶サイズは５μｍ程度であるのに対して、コールドスプレー膜（金属膜１０９）は、主として２０μｍ程度の粒子によって形成される。したがって、金属膜１０９の最表面は、湿式めっき法によって形成されたＣｕ膜に比べて平滑ではなく、不均一であって凹凸が生じている。 The crystal size of the Cu film formed by the wet plating method is about 5 μm, whereas the cold spray film (metal film 109) is mainly formed by particles of about 20 μm. Therefore, the outermost surface of the metal film 109 is not smooth as compared with the Cu film formed by the wet plating method, but is non-uniform and has irregularities.
　この凹凸は、たとえば、レーザー顕微鏡によって１００μｍ×１００μｍの範囲で測定された線粗さから導出される算術平均粗さＲａが１μｍ以上、かつ、１０μｍ以下であることが望ましい。ここでの凹凸の大きさは、たとえば、非接触式の白色干渉計によって測定される。 For this unevenness, for example, it is desirable that the arithmetic average roughness Ra derived from the line roughness measured in the range of 100 μm × 100 μm by a laser microscope is 1 μm or more and 10 μm or less. The size of the unevenness here is measured by, for example, a non-contact white interferometer.
　このように、金属膜１０９最表面に不均一な凹凸が存在することで、基板下接合材１０７ｂ（はんだ）が濡れ拡がる面積が大きくなる。そのため、基板下接合材１０７ｂ（はんだ）と金属膜１０９との接合強度が向上する。 As described above, the presence of non-uniform unevenness on the outermost surface of the metal film 109 increases the area in which the under-board bonding material 107b (solder) wets and spreads. Therefore, the bonding strength between the substrate bottom bonding material 107b (solder) and the metal film 109 is improved.
　なお、上述のコールドスプレー膜中の粒子サイズは、たとえば、金属膜１０９を断面観察して電子線後方散乱回折法（ｅｌｅｃｔｒｏｎ　ｂａｃｋｓｃａｔｔｅｒ　ｄｉｆｆｒａｃｔｉｏｎ、すなわち、ＥＢＳＤ）によって測定された値である。 The particle size in the cold spray film described above is, for example, a value measured by an electron backscatter diffraction method (EBSD) by observing a cross section of the metal film 109.
　通常、Ｃｕなどの金属膜は、スパッタ蒸着法によって成膜されると、膜厚が２μｍ以上、かつ、３μｍ以下であり、膜厚分布はナノメートルオーダーと平坦である。 Normally, when a metal film such as Cu is formed by a sputtering vapor deposition method, the film thickness is 2 μm or more and 3 μm or less, and the film thickness distribution is as flat as the nanometer order.
　また、めっき法によって金属膜を形成する場合、膜厚が数μｍ以上、かつ、３０μｍ以下であり、膜厚分布はサブミクロンオーダーと平坦である。 When a metal film is formed by a plating method, the film thickness is several μm or more and 30 μm or less, and the film thickness distribution is flat on the submicron order.
　一方で、本実施の形態では、金属膜１０９をコールドスプレー法によってコールドスプレー膜用マスク２０１を用いて成膜する。コールドスプレー膜は、コールドスプレー膜用マスク２０１の開口部の壁面に沿って鉛直には立ち上がらず、膜中央部に向かって傾斜を有する形状となる。 On the other hand, in the present embodiment, the metal film 109 is formed by the cold spray method using the cold spray film mask 201. The cold spray film does not rise vertically along the wall surface of the opening of the cold spray film mask 201, but has a shape that is inclined toward the center of the film.
　金属膜１０９の厚さは、超音波探傷検査（Ｓｃａｎｎｉｎｇ　Ａｃｏｕｓｔｉｃ　Ｔｏｍｏｇｒａｐｈｙ、すなわち、ＳＡＴ）によって測定することができる。すなわち、金属膜１０９が成膜された後の半導体装置に対して超音波プローブから発せられる超音波を当て、超音波が金属膜１０９を通過するために要する時間と、金属膜１０９と下側導体パターン１０３ｆとの間の界面で当該超音波が反射されて返ってくるまでの時間との差によって測定される。 The thickness of the metal film 109 can be measured by an ultrasonic flaw detection inspection (Scanning Acoustic Tomography, that is, SAT). That is, the time required for the ultrasonic waves emitted from the ultrasonic probe to be applied to the semiconductor device after the metal film 109 is formed and the ultrasonic waves passing through the metal film 109, and the metal film 109 and the lower conductor. It is measured by the difference from the time until the ultrasonic wave is reflected and returned at the interface with the pattern 103f.
　＜第２の実施の形態＞
　本実施の形態に関する半導体モジュール、および、半導体モジュールの製造方法について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Second embodiment>
A semiconductor module according to the present embodiment and a method for manufacturing the semiconductor module will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..
　＜半導体モジュールの構成について＞
　第１の実施の形態では、１つの半導体素子１０４（スイッチングデバイス１０４ａまたは還流ダイオード１０４ｂ）に対して、それぞれ対応する金属膜１０９が下側導体パターン１０３ｆの下面の対応箇所に成膜されていた。 <Semiconductor module configuration>
In the first embodiment, a metal film 109 corresponding to each semiconductor element 104 (switching device 104a or freewheeling diode 104b) is formed on the corresponding portion on the lower surface of the lower conductor pattern 103f.
　一方で、本実施の形態では、異なる形態について説明する。図４は、本実施の形態に関する電力用半導体モジュールの構成の一部の例を概略的に示す断面図である。また、図５は、図４に例が示された構成を下面側（図４の紙面下側）から見た場合の平面図である。なお、図４および図５においては、基板下接合材１０７ｂを含む他の構成は、簡単のために図示が省略されている。 On the other hand, in the present embodiment, different forms will be described. FIG. 4 is a cross-sectional view schematically showing an example of a part of the configuration of the power semiconductor module according to the present embodiment. Further, FIG. 5 is a plan view of the configuration shown in FIG. 4 as viewed from the lower surface side (lower side of the paper surface in FIG. 4). In addition, in FIG. 4 and FIG. 5, the other configurations including the substrate lower bonding material 107b are not shown for the sake of simplicity.
　図４および図５に例が示されるように、電力用半導体モジュールは、絶縁基板１０３と、半導体素子１０４と、配線１０６と、金属膜１０９ａとを備えている。 As an example is shown in FIGS. 4 and 5, the power semiconductor module includes an insulating substrate 103, a semiconductor element 104, a wiring 106, and a metal film 109a.
　金属膜１０９ａは、複数の半導体素子１０４（スイッチングデバイス１０４ａおよび還流ダイオード１０４ｂ）が搭載される箇所にまたがって成膜されている。図５においては、金属膜１０９ａは、４つの半導体素子１０４の搭載箇所全体にまたがって成膜されている。 The metal film 109a is formed over a portion where a plurality of semiconductor elements 104 (switching device 104a and freewheeling diode 104b) are mounted. In FIG. 5, the metal film 109a is formed over the entire mounting locations of the four semiconductor elements 104.
　金属膜１０９ａの作成方法は、第１の実施の形態で説明された場合と同様である。すなわち、金属膜１０９ａを成膜する部分に開口部が設けられたコールドスプレー膜用マスクを下側導体パターン１０３ｆに配置し、さらに、コールドスプレー装置によって金属粉体を照射することで成膜することができる。 The method for creating the metal film 109a is the same as that described in the first embodiment. That is, a mask for a cold spray film having an opening provided in a portion where the metal film 109a is formed is arranged on the lower conductor pattern 103f, and the metal powder is further irradiated with the cold spray device to form the film. Can be done.
　このような構成によれば、同一の絶縁基板上に異なる種類の半導体素子を搭載する場合であっても、金属膜の成膜過程において段取り替えが生じない。したがって、生産性を下げずにパワーモジュールを生産することができる。 According to such a configuration, even when different types of semiconductor elements are mounted on the same insulating substrate, setup change does not occur in the process of forming the metal film. Therefore, the power module can be produced without lowering the productivity.
　図６は、本実施の形態に関する電力用半導体モジュールの構成の一部の他の例を概略的に示す断面図である。また、図７は、図６に例が示された構成を下面側（図６の紙面下側）から見た場合の平面図である。なお、図６および図７においては、基板下接合材１０７ｂを含む他の構成は、簡単のために図示が省略されている。 FIG. 6 is a cross-sectional view schematically showing another example of a part of the configuration of the power semiconductor module according to the present embodiment. Further, FIG. 7 is a plan view of the configuration shown in FIG. 6 as viewed from the lower surface side (lower side of the paper surface of FIG. 6). In addition, in FIG. 6 and FIG. 7, the other configurations including the substrate lower bonding material 107b are not shown for the sake of simplicity.
　図６および図７に例が示されるように、電力用半導体モジュールは、絶縁基板１０３と、半導体素子１０４と、配線１０６と、金属膜１０９ｂとを備えている。 As an example is shown in FIGS. 6 and 7, the power semiconductor module includes an insulating substrate 103, a semiconductor element 104, a wiring 106, and a metal film 109b.
　金属膜１０９ｂは、それぞれの半導体素子１０４（スイッチングデバイス１０４ａまたは還流ダイオード１０４ｂ）が搭載される箇所に対応して複数個ずつ成膜されている（すなわち、複数箇所に分かれて成膜されている）。図７においては、金属膜１０９ｂは、１つの半導体素子１０４の搭載箇所に対して６つずつ成膜され、また、半導体素子１０４の搭載箇所間においても、複数個が成膜されている。 A plurality of metal films 109b are formed corresponding to the locations where the respective semiconductor elements 104 (switching device 104a or freewheeling diode 104b) are mounted (that is, the metal films 109b are formed in a plurality of locations). .. In FIG. 7, six metal films 109b are formed on each mounting location of one semiconductor element 104, and a plurality of metal films 109b are also formed between the mounting locations of the semiconductor element 104.
　金属膜１０９ｂの作成方法は、第１の実施の形態で説明された場合と同様である。すなわち、複数の金属膜１０９ｂを成膜する部分に対応して複数の開口部が設けられたコールドスプレー膜用マスクを下側導体パターン１０３ｆに配置し、さらに、コールドスプレー装置によって金属粉体を照射することで成膜することができる。 The method for creating the metal film 109b is the same as that described in the first embodiment. That is, a mask for a cold spray film provided with a plurality of openings corresponding to a portion for forming a plurality of metal films 109b is arranged on the lower conductor pattern 103f, and further, the metal powder is irradiated by the cold spray device. By doing so, a film can be formed.
　このような構成によれば、半導体素子１０４の数と金属膜１０９ａの数とが同一である場合と比較して、必要となるＣｕ粉体の量を抑えつつ、放熱性が向上し、また、ベース板１０１と絶縁基板１０３との間の接合部の接合信頼性が向上する。 According to such a configuration, as compared with the case where the number of semiconductor elements 104 and the number of metal films 109a are the same, the amount of Cu powder required is suppressed, the heat dissipation is improved, and the heat dissipation is improved. The joint reliability of the joint portion between the base plate 101 and the insulating substrate 103 is improved.
　＜第３の実施の形態＞
　本実施の形態に関する半導体モジュール、および、半導体モジュールの製造方法について説明する。なお、以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Third embodiment>
A semiconductor module according to the present embodiment and a method for manufacturing the semiconductor module will be described. In the following description, components similar to the components described in the above-described embodiment will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. ..
　＜半導体モジュールの構成について＞
　第１の実施の形態および第２の実施の形態では、半導体素子１０４（スイッチングデバイス１０４ａまたは還流ダイオード１０４ｂ）に対して、それぞれ対応する金属膜１０９が下側導体パターン１０３ｆの下面の対応箇所に成膜されていた。 <Semiconductor module configuration>
In the first embodiment and the second embodiment, the metal film 109 corresponding to the semiconductor element 104 (switching device 104a or freewheeling diode 104b) is formed at the corresponding portion on the lower surface of the lower conductor pattern 103f. It was filmed.
　一方で、本実施の形態では、異なる形態について説明する。図８は、本実施の形態に関する電力用半導体モジュールの構成の一部の例を概念的に示す断面図である。また、図９は、図８に例が示された構成を下面側（図８の紙面下側）から見た場合の平面図である。 On the other hand, in the present embodiment, different forms will be described. FIG. 8 is a cross-sectional view conceptually showing a part of an example of the configuration of the power semiconductor module according to the present embodiment. Further, FIG. 9 is a plan view of the configuration shown in FIG. 8 as viewed from the lower surface side (lower side of the paper surface in FIG. 8).
　図８および図９に例が示されるように、電力用半導体モジュール１００ａは、絶縁基板１０３と、ケース１０２と、半導体素子１０４と、配線１０６と、端子２０８と、金属膜１０９と、ベース板１０１とを備えている。 As an example is shown in FIGS. 8 and 9, the power semiconductor module 100a includes an insulating substrate 103, a case 102, a semiconductor element 104, a wiring 106, a terminal 208, a metal film 109, and a base plate 101. And have.
　ケース１０２には、主端子２０８ａと制御端子１０８ｂとが設置されている。スイッチングデバイス１０４ａは、主端子２０８ａとワイヤー状配線１０６ａによって結線され、制御端子１０８ｂとソース信号配線１０６ｂおよびゲート信号配線１０６ｃによって結線される。還流ダイオード１０４ｂは、主端子２０８ａとワイヤー状配線１０６ａによって結線される。 A main terminal 208a and a control terminal 108b are installed in the case 102. The switching device 104a is connected to the main terminal 208a by the wire-shaped wiring 106a, and is connected to the control terminal 108b by the source signal wiring 106b and the gate signal wiring 106c. The freewheeling diode 104b is connected to the main terminal 208a by a wire-shaped wiring 106a.
　絶縁基板１０３の下面側における下側導体パターン１０３ｆの下面のうち、半導体素子１０４の搭載位置に対向する位置、および、主端子２０８ａが搭載される位置には、金属膜１０９（または、金属膜１０９ａ、金属膜１０９ｂ）が形成されている。金属膜１０９は、当該膜を成膜する部分に開口部が設けられたコールドスプレー膜用マスクを下側導体パターン１０３ｆの下面に配置し、さらに、コールドスプレー装置によって金属粉体を照射することによって成膜することができる。金属膜１０９は、主端子２０８ａの接合部２０８ｂの投影面積よりも大きい面積で成膜されている（図９を参照）。 On the lower surface of the lower conductor pattern 103f on the lower surface side of the insulating substrate 103, the metal film 109 (or the metal film 109a) is located at a position facing the mounting position of the semiconductor element 104 and a position where the main terminal 208a is mounted. , Metal film 109b) is formed. The metal film 109 is formed by arranging a mask for a cold spray film having an opening in a portion where the film is formed on the lower surface of the lower conductor pattern 103f, and further irradiating the metal powder with a cold spray device. A film can be formed. The metal film 109 is formed in an area larger than the projected area of the joint portion 208b of the main terminal 208a (see FIG. 9).
　電力用半導体モジュール１００ａの動作に伴い、主端子２０８ａには大電流が通電される。主端子２０８ａの断面積は、電力用半導体モジュール１００ａの動作に必要な通電容量を満たすように任意に設計されるものである。主端子２０８ａは、たとえば、板厚が１ｍｍのＣｕから形成されていることが多い。 A large current is energized in the main terminal 208a with the operation of the power semiconductor module 100a. The cross-sectional area of the main terminal 208a is arbitrarily designed so as to satisfy the energizing capacity required for the operation of the power semiconductor module 100a. The main terminal 208a is often formed of, for example, Cu having a plate thickness of 1 mm.
　第１の実施の形態では、主端子１０８ａは、ワイヤー状配線材を介して上側導体パターン１０３ｂと結線されていた。ワイヤー状配線材での結線では設計上必要な通電容量が得られない場合には、主端子２０８ａのように、主端子２０８ａの接合部２０８ｂと上側導体パターン１０３ｂとを接合する必要がある。 In the first embodiment, the main terminal 108a is connected to the upper conductor pattern 103b via a wire-shaped wiring material. When the energization capacity required for design cannot be obtained by connecting with a wire-shaped wiring material, it is necessary to join the joint portion 208b of the main terminal 208a and the upper conductor pattern 103b like the main terminal 208a.
　一般的に、主端子２０８ａと上側導体パターン１０３ｂとの接合ははんだ材によって接合されるが、近年、電力用半導体モジュールの動作温度範囲が拡大し、当該接合部に要求される接合信頼性が高まっている。 Generally, the main terminal 208a and the upper conductor pattern 103b are joined by a solder material, but in recent years, the operating temperature range of the power semiconductor module has expanded, and the joining reliability required for the joining portion has increased. ing.
　本実施の形態では、主端子２０８ａの接合部２０８ｂと上側導体パターン１０３ｂとを直接接合するために、超音波による固相拡散接合を用いる。 In the present embodiment, in order to directly bond the joint portion 208b of the main terminal 208a and the upper conductor pattern 103b, solid phase diffusion bonding by ultrasonic waves is used.
　なお、本実施の形態では、主端子２０８ａは厚さが１ｍｍのＣｕ材からなり、上側導体パターン１０３ｂはＣｕ材からなる金属パターンであり、絶縁材１０３ｅは窒化ケイ素（ＡｌＮ）からなるものとするが、これらの構成の材料は当該内容に限定されるものではない。 In the present embodiment, the main terminal 208a is made of a Cu material having a thickness of 1 mm, the upper conductor pattern 103b is a metal pattern made of a Cu material, and the insulating material 103e is made of silicon nitride (AlN). However, the materials of these configurations are not limited to the contents.
　電力用半導体モジュール１００ａの動作に伴う通電が生じると、主端子２０８ａが発熱する。そうすると、当該発熱に基づく温度変化が生じ得る。 When energization occurs due to the operation of the power semiconductor module 100a, the main terminal 208a generates heat. Then, a temperature change based on the heat generation may occur.
　上記の発熱に基づく温度変化、または、電力用半導体モジュール１００ａの周囲環境の温度変化によって、主端子２０８ａと絶縁材１０３ｅなどの材料との熱膨張係数の差に応じて接合部２０８ｂに応力（主にせん断方向）が生じる。また、上記の温度変化によって、主端子２０８ａの膨張または収縮などが生じて主端子２０８ａと上側導体パターン１０３ｂとの接合部２０８ｂに応力（主に縦方向）が生じる。 Due to the temperature change based on the above heat generation or the temperature change in the ambient environment of the power semiconductor module 100a, the joint portion 208b is stressed (mainly) according to the difference in the coefficient of thermal expansion between the main terminal 208a and the material such as the insulating material 103e. Shear direction) occurs. Further, due to the above temperature change, expansion or contraction of the main terminal 208a occurs, and stress (mainly in the vertical direction) is generated at the joint portion 208b between the main terminal 208a and the upper conductor pattern 103b.
　特に、本実施の形態で用いられる絶縁材１０３ｅの材料である窒化ケイ素（ＡｌＮ）は、熱伝導率が大きく、かつ、放熱性に優れる。そのため、近年用いられることが多くなっている。 In particular, silicon nitride (AlN), which is the material of the insulating material 103e used in the present embodiment, has a large thermal conductivity and excellent heat dissipation. Therefore, it is often used in recent years.
　Ｃｕ材である主端子２０８ａと窒化ケイ素（ＡｌＮ）である絶縁材１０３ｅとの熱膨張係数の差が大きい場合、接合部２０８ｂに生じる応力が大きく、従来のはんだ接合では接合材であるはんだ（ここでは、図示しない）に亀裂が伸展してしまう。そうすると、通電経路が小さくなり、さらに、接合部の温度が上昇するため、破断してオープン故障してしまう恐れがあった。 When the difference in the coefficient of thermal expansion between the main terminal 208a, which is a Cu material, and the insulating material 103e, which is silicon nitride (AlN), is large, the stress generated at the joint portion 208b is large, and in conventional solder bonding, solder, which is a bonding material (here). Then, the crack extends to (not shown). Then, the energization path becomes small, and the temperature of the joint rises, so that there is a risk of breakage and an open failure.
　このような課題に対して、本実施の形態では、主端子２０８ａのＣｕと上側導体パターン１０３ｂのＣｕとを直接接合して強固な接合部２０８ｂが得られ、要求される接合信頼性も満足することができる。 In response to such a problem, in the present embodiment, the Cu of the main terminal 208a and the Cu of the upper conductor pattern 103b are directly bonded to obtain a strong bonding portion 208b, and the required bonding reliability is also satisfied. be able to.
　従来のはんだ接合では、接合部に発生する応力は、はんだ材のクリープまたははんだ材に亀裂が伸展することで緩和されていた。しかしながら、ＣｕとＣｕとの直接接合で強固な接合部を形成する場合、材料間の熱膨張率の差により発生する応力または主端子２０８ａ自体の膨張または収縮などで生じる応力によって、主端子２０８ａの接合部２０８ｂの直下の、下側導体パターン１０３ｆとベース板１０１との間の基板下接合材１０７ｂであるはんだが劣化することになった。 In the conventional solder joint, the stress generated at the joint was alleviated by creeping the solder material or expanding cracks in the solder material. However, when a strong joint is formed by direct bonding between Cu and Cu, the stress generated by the difference in the coefficient of thermal expansion between the materials or the stress generated by the expansion or contraction of the main terminal 208a itself causes the main terminal 208a to be formed. The solder, which is the under-board bonding material 107b between the lower conductor pattern 103f and the base plate 101, just below the joint portion 208b, has deteriorated.
　基板下接合材１０７ｂであるはんだの劣化によって、主端子２０８ａが通電されることで生じる発熱または半導体素子１０４の動作で生じる発熱を、効率的にベース板１０１に伝えることができなくなる。そうすると、放熱性が悪化する。 Due to the deterioration of the solder, which is the under-board bonding material 107b, the heat generated by the main terminal 208a being energized or the heat generated by the operation of the semiconductor element 104 cannot be efficiently transmitted to the base plate 101. Then, the heat dissipation property deteriorates.
　特に、はんだの劣化は、電力用半導体モジュール１００ａの動作によって主端子２０８ａの直下部分だけで局所的に進むことになる。 In particular, the deterioration of the solder locally progresses only in the portion directly below the main terminal 208a due to the operation of the power semiconductor module 100a.
　これに対し、本実施の形態に関する電力用半導体モジュール１００ａにおいては、絶縁基板１０３の下面側における下側導体パターン１０３ｆの下面の内、主端子２０８ａの搭載位置に対向する位置にも、コールドスプレー法によって成膜された金属膜１０９が形成されている。 On the other hand, in the power semiconductor module 100a according to the present embodiment, the cold spray method is also performed at a position facing the mounting position of the main terminal 208a on the lower surface of the lower conductor pattern 103f on the lower surface side of the insulating substrate 103. The metal film 109 formed by the above is formed.
　主端子２０８ａの直下の領域に、基板下接合材１０７ｂであるはんだよりも熱伝導率が大きいＣｕで構成される金属膜１０９が成膜されていることで、電力用半導体モジュール１００ａの放熱性が向上する。 A metal film 109 made of Cu, which has a higher thermal conductivity than solder, which is a bonding material under the substrate 107b, is formed in the region directly below the main terminal 208a, so that the heat dissipation of the power semiconductor module 100a can be improved. improves.
　また、Ｃｕの熱膨張率は、はんだの熱膨張率と、ベース板１０１の熱膨張率または絶縁材１０３ｅの熱膨張率との間の値である。したがって、電力用半導体モジュール１００ａの動作時に、基板下接合材１０７ｂに発生する応力を低減させることができる。 The coefficient of thermal expansion of Cu is a value between the coefficient of thermal expansion of the solder and the coefficient of thermal expansion of the base plate 101 or the coefficient of thermal expansion of the insulating material 103e. Therefore, it is possible to reduce the stress generated in the substrate lower bonding material 107b during the operation of the power semiconductor module 100a.
　さらに、Ｃｕははんだと比較して機械的強度が高いことから、はんだ接合の場合のような亀裂が発生しにくく、また、そのような亀裂が生じた場合であっても亀裂進展が遅い。そのため、Ｃｕによれば、接合部の信頼性が低下しにくい。 Furthermore, since Cu has higher mechanical strength than solder, cracks are less likely to occur as in the case of solder bonding, and even if such cracks occur, crack growth is slow. Therefore, according to Cu, the reliability of the joint portion is unlikely to decrease.
　さらに、コールドスプレー膜は完全なバルク体とはならず、膜内部に空孔が生じている。この空孔が緩衝層となり、主端子２０８ａの接合部２０８ｂの直下の、基板下接合材１０７ｂに生じる応力を緩和する。そのため、金属膜１０９の成膜法として、コールドスプレー法は望ましい成膜法と言える。 Furthermore, the cold spray membrane is not a complete bulk body, and there are vacancies inside the membrane. These holes serve as a buffer layer, and alleviate the stress generated in the joint material 107b under the substrate immediately below the joint portion 208b of the main terminal 208a. Therefore, it can be said that the cold spray method is a desirable film forming method for the metal film 109.
　本実施の形態では、Ｃｕ材である主端子２０８ａとＣｕパターンである上側導体パターン１０３ｂとの超音波による固相拡散接合による構造を説明したが、それだけでなく、レーザー照射による主端子２０８ａと上側導体パターン１０３ｂとのレーザー直接接合、または、レーザー照射で主端子２０８ａと上側導体パターン１０３ｂとの間にはさんだ接合材であるろう材を溶融させて主端子２０８ａと上側導体パターン１０３ｂとを接合する方法でも同様に適用可能である。 In the present embodiment, the structure of the main terminal 208a which is a Cu material and the upper conductor pattern 103b which is a Cu pattern by solid-phase diffusion bonding by ultrasonic waves has been described, but not only that, the main terminal 208a and the upper side by laser irradiation have been described. Direct laser bonding with the conductor pattern 103b or laser irradiation melts the brazing material sandwiched between the main terminal 208a and the upper conductor pattern 103b to bond the main terminal 208a and the upper conductor pattern 103b. The method is also applicable.
　本実施の形態では、主端子２０８ａと上側導体パターン１０３ｂとの接合によって形成される構造が説明されたが、制御端子１０８ｂと上側導体パターン１０３ｃとの接合部を超音波接合した場合に、制御端子１０８ｂの直下の領域に、基板下接合材１０７ｂであるはんだよりも熱伝導率が大きいＣｕによって構成される金属膜１０９が成膜されていることで、基板下接合材１０７ｂの亀裂を抑制するとともに、電力用半導体モジュール１００ａの放熱性が向上することが可能となる。 In the present embodiment, the structure formed by bonding the main terminal 208a and the upper conductor pattern 103b has been described, but when the bonding portion between the control terminal 108b and the upper conductor pattern 103c is ultrasonically bonded, the control terminal is used. A metal film 109 composed of Cu, which has a higher thermal conductivity than solder, which is the under-subboard bonding material 107b, is formed in the region directly below 108b, thereby suppressing cracks in the under-subboard bonding material 107b and suppressing cracks. It is possible to improve the heat dissipation of the power semiconductor module 100a.
　このような構成によれば、主端子２０８ａとＣｕパターンである上側導体パターン１０３ｂとを超音波接合することによって従来のはんだ接合よりも接合強度を向上させた場合であっても、主端子２０８ａの直下の下側導体パターン１０３ｆとベース板１０１との間の基板下接合材１０７ｂに亀裂が伸展することが抑制され、放熱性を向上させることが可能な電力用半導体モジュール１００ａを得ることができる。 According to such a configuration, even when the main terminal 208a and the upper conductor pattern 103b, which is a Cu pattern, are ultrasonically bonded to improve the bonding strength as compared with the conventional solder bonding, the main terminal 208a It is possible to obtain a power semiconductor module 100a capable of improving heat dissipation by suppressing the expansion of cracks in the substrate bottom bonding material 107b between the lower conductor pattern 103f directly below and the base plate 101.
　＜第４の実施の形態＞
　本実施の形態に関する電力変換装置、および、電力変換装置の製造方法について説明する。以下の説明においては、以上に記載された実施の形態で説明された構成要素と同様の構成要素については同じ符号を付して図示し、その詳細な説明については適宜省略するものとする。 <Fourth Embodiment>
The power conversion device and the method of manufacturing the power conversion device according to the present embodiment will be described. In the following description, components similar to the components described in the above-described embodiments will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate.
　＜電力変換装置の構成について＞
　本実施の形態は、以上に記載された実施の形態に関する半導体モジュールを電力変換装置に適用するものである。適用する電力変換装置は特定の用途のものに限定されるものではないが、以下では、三相のインバータに適用する場合について説明する。 <About the configuration of the power converter>
In this embodiment, the semiconductor module according to the above-described embodiment is applied to a power conversion device. The power conversion device to be applied is not limited to that for a specific application, but the case where it is applied to a three-phase inverter will be described below.
　図１０は、本実施の形態の電力変換装置を含む電力変換システムの構成の例を概念的に示す図である。 FIG. 10 is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion device of the present embodiment.
　図１０に例が示されるように、電力変換システムは、電源２１００と、電力変換装置２２００と、負荷２３００とを備える。電源２１００は、直流電源であり、かつ、電力変換装置２２００に直流電力を供給する。電源２１００は種々のもので構成することが可能であり、たとえば、直流系統、太陽電池または蓄電池などで構成することができる。また、電源２１００は、交流系統に接続された整流回路またはＡＣ－ＤＣコンバータなどで構成することができる。また、電源２１００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ－ＤＣコンバータによって構成することもできる。 As an example is shown in FIG. 10, the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured by various types, for example, a DC system, a solar cell, a storage battery, or the like. Further, the power supply 2100 can be configured by a rectifier circuit connected to an AC system, an AC-DC converter, or the like. Further, the power supply 2100 can also be configured by a DC-DC converter that converts the DC power output from the DC system into a predetermined power.
　電力変換装置２２００は、電源２１００と負荷２３００との間に接続される三相のインバータである。電力変換装置２２００は、電源２１００から供給された直流電力を交流電力に変換し、さらに、負荷２３００に当該交流電力を供給する。 The power converter 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts the DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.
　また、電力変換装置２２００は、図１０に例が示されるように、直流電力を交流電力に変換して出力する変換回路２２０１と、変換回路２２０１のそれぞれのスイッチング素子を駆動するための駆動信号を出力する駆動回路２２０２と、駆動回路２２０２を制御するための制御信号を駆動回路２２０２に出力する制御回路２２０３とを備える。 Further, as shown in FIG. 10, the power conversion device 2200 converts a DC power into an AC power and outputs a conversion circuit 2201 and a drive signal for driving each switching element of the conversion circuit 2201. It includes a drive circuit 2202 that outputs power, and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.
　負荷２３００は、電力変換装置２２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷２３００は特定の用途に限られるものではなく、各種電気機器に搭載される電動機であり、たとえば、ハイブリッド自動車、電気自動車、鉄道車両、エレベータ、または、空調機器向けの電動機として用いられるものである。 The load 2300 is a three-phase electric motor driven by AC power supplied from the power converter 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electric devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner. Is.
　以下、電力変換装置２２００の詳細を説明する。変換回路２２０１は、スイッチング素子と還流ダイオードとを備える（ここでは、図示しない）。そして、スイッチング素子がスイッチング動作をすることによって、電源２１００から供給される直流電力を交流電力に変換し、さらに、負荷２３００に供給する。 The details of the power conversion device 2200 will be described below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown here). Then, when the switching element performs the switching operation, the DC power supplied from the power supply 2100 is converted into AC power and further supplied to the load 2300.
　変換回路２２０１の具体的な回路構成は種々のものがあるが、本実施の形態に関する変換回路２２０１は、２レベルの三相フルブリッジ回路であり、かつ、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列に接続される６つの還流ダイオードとを備えるものである。 There are various specific circuit configurations of the conversion circuit 2201, but the conversion circuit 2201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It includes six freewheeling diodes connected in antiparallel.
　変換回路２２０１におけるそれぞれのスイッチング素子とそれぞれの還流ダイオードの少なくとも一方には、以上に記載された実施の形態のいずれかにおける半導体モジュールを適用する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続されて上下アームを構成し、それぞれの上下アームは、フルブリッジ回路のそれぞれの相（すなわち、Ｕ相、Ｖ相およびＷ相）を構成する。そして、それぞれの上下アームの出力端子（すなわち、変換回路２２０１の３つの出力端子）は、負荷２３００に接続される。 The semiconductor module according to any of the embodiments described above is applied to at least one of each switching element and each freewheeling diode in the conversion circuit 2201. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (that is, U phase, V phase and W phase) of the full bridge circuit. Then, the output terminals of the respective upper and lower arms (that is, the three output terminals of the conversion circuit 2201) are connected to the load 2300.
　また、変換回路２２０１は、それぞれのスイッチング素子を駆動するための駆動回路（ここでは、図示しない）を備えているが、当該駆動回路は半導体モジュールに内蔵されていてもよいし、半導体モジュールとは別に駆動回路を備える構成であってもよい。 Further, although the conversion circuit 2201 includes a drive circuit (not shown here) for driving each switching element, the drive circuit may be built in the semiconductor module, and the semiconductor module is A drive circuit may be separately provided.
　駆動回路２２０２は、変換回路２２０１のスイッチング素子を駆動するための駆動信号を生成し、さらに、変換回路２２０１のスイッチング素子の制御電極に当該駆動信号を供給する。具体的には、後述する制御回路２２０３から出力される制御信号に基づいて、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とをそれぞれのスイッチング素子の制御電極に出力する。 The drive circuit 2202 generates a drive signal for driving the switching element of the conversion circuit 2201, and further supplies the drive signal to the control electrode of the switching element of the conversion circuit 2201. Specifically, based on the control signal output from the control circuit 2203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements. To do.
　スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子のしきい値電圧以上の電圧信号（すなわち、オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子のしきい値電圧以下の電圧信号（すなわち、オフ信号）となる。 When the switching element is kept on, the drive signal is a voltage signal equal to or higher than the threshold voltage of the switching element (that is, the on signal), and when the switching element is kept off, the drive signal is the switching element. It becomes a voltage signal below the threshold voltage (that is, an off signal).
　制御回路２２０３は、負荷２３００に所望の電力が供給されるよう変換回路２２０１のスイッチング素子を制御する。具体的には、負荷２３００に供給すべき電力に基づいて変換回路２２０１のそれぞれのスイッチング素子がオン状態となるべき時間（すなわち、オン時間）を算出する。たとえば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって、変換回路２２０１を制御することができる。 The control circuit 2203 controls the switching element of the conversion circuit 2201 so that the desired power is supplied to the load 2300. Specifically, the time (that is, the on-time) that each switching element of the conversion circuit 2201 should be in the on state is calculated based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.
　そして、制御回路２２０３は、それぞれの時点においてオン状態となるべきスイッチング素子にはオン信号が、オフ状態となるべきスイッチング素子にはオフ信号がそれぞれ出力されるように、駆動回路２２０２に制御指令（すなわち、制御信号）を出力する。駆動回路２２０２は、当該制御信号に基づいて、それぞれのスイッチング素子の制御電極にオン信号またはオフ信号を駆動信号として出力する。 Then, the control circuit 2203 gives a control command to the drive circuit 2202 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. That is, the control signal) is output. The drive circuit 2202 outputs an on signal or an off signal as a drive signal to the control electrodes of the respective switching elements based on the control signal.
　本実施の形態に関する電力変換装置２２００では、変換回路２２０１のスイッチング素子または還流ダイオードとして以上に記載された実施の形態のいずれかにおける半導体モジュールを適用するため、通電サイクルを経た後のオン抵抗を安定させることができる。 In the power conversion device 2200 according to the present embodiment, since the semiconductor module in any of the above-described embodiments is applied as the switching element or the freewheeling diode of the conversion circuit 2201, the on-resistance after the energization cycle is stabilized. Can be made to.
　なお、本実施の形態では、２レベルの三相インバータに以上に記載された実施の形態のいずれかにおける半導体モジュールを適用する例が説明されたが、適用例はこれに限られるものではなく、種々の電力変換装置に以上に記載された実施の形態のいずれかにおける半導体モジュールを適用することができる。 In the present embodiment, an example of applying the semiconductor module in any of the above-described embodiments to the two-level three-phase inverter has been described, but the application example is not limited to this. The semiconductor module in any of the embodiments described above can be applied to various power conversion devices.
　また、本実施の形態では、２レベルの電力変換装置について説明されたが、３レベルまたはマルチレベルの電力変換装置に以上に記載された実施の形態のいずれかにおける半導体モジュールが適用されてもよい。また、単相負荷に電力を供給する場合には、単相のインバータに以上に記載された実施の形態のいずれかにおける半導体モジュールが適用されてもよい。 Further, in the present embodiment, the two-level power conversion device has been described, but the semiconductor module in any of the embodiments described above may be applied to the three-level or multi-level power conversion device. .. Further, in the case of supplying electric power to the single-phase load, the semiconductor module in any of the embodiments described above may be applied to the single-phase inverter.
　また、直流負荷などに電力を供給する場合には、ＤＣ－ＤＣコンバータまたはＡＣ－ＤＣコンバータに、以上に記載された実施の形態のいずれかにおける半導体モジュールを適用することもできる。 Further, when supplying electric power to a DC load or the like, the semiconductor module in any of the above-described embodiments can be applied to the DC-DC converter or the AC-DC converter.
　また、以上に記載された実施の形態のいずれかにおける半導体モジュールが適用された電力変換装置は、上述された負荷が電動機である場合に限定されるものではなく、たとえば、放電加工機、レーザー加工機、誘導加熱調理器または非接触給電システムの電源装置として用いることもできる。また、以上に記載された実施の形態のいずれかにおける半導体モジュールが適用された電力変換装置は、太陽光発電システムまたは蓄電システムなどにおけるパワーコンディショナーとして用いることもできる。 Further, the power conversion device to which the semiconductor module in any of the above-described embodiments is applied is not limited to the case where the load described above is an electric motor, and is not limited to, for example, an electric discharge machine or a laser machine. It can also be used as a power source for machines, induction cookers or contactless power supply systems. Further, the power conversion device to which the semiconductor module in any of the above-described embodiments is applied can also be used as a power conditioner in a photovoltaic power generation system, a power storage system, or the like.
　以上に記載された実施の形態において用いられる半導体スイッチング素子は、シリコン（Ｓｉ）半導体から成るスイッチング素子に限られるものではなく、たとえば、半導体スイッチング素子は、Ｓｉ半導体よりもバンドギャップが広い非Ｓｉ半導体材料から成るものであってもよい。 The semiconductor switching element used in the above-described embodiment is not limited to the switching element made of a silicon (Si) semiconductor. For example, the semiconductor switching element is a non-Si semiconductor having a wider band gap than the Si semiconductor. It may be made of a material.
　非Ｓｉ半導体材料であるワイドバンドギャップ半導体としては、たとえば、炭化珪素、窒化ガリウム系材料またはダイヤモンドなどがある。 Examples of wide bandgap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.
　ワイドバンドギャップ半導体から成るスイッチング素子は、Ｓｉ半導体ではユニポーラ動作が困難な高電圧領域でも使用可能であり、スイッチング動作時に発生するスイッチング損失を大きく低減することができる。そのため、電力損失の大きな低減が可能となる。 A switching element made of a wide bandgap semiconductor can be used even in a high voltage region where unipolar operation is difficult with a Si semiconductor, and switching loss generated during switching operation can be greatly reduced. Therefore, it is possible to greatly reduce the power loss.
　また、ワイドバンドギャップ半導体から成るスイッチング素子は、電力損失が小さく、耐熱性も高い。そのため、冷却部を備えるパワーモジュールを構成する場合、ヒートシンクの放熱フィンを小型化することが可能であるため、半導体モジュールの一層の小型化が可能となる。 In addition, switching elements made of wide bandgap semiconductors have low power loss and high heat resistance. Therefore, when a power module including a cooling unit is configured, the heat radiation fins of the heat sink can be miniaturized, so that the semiconductor module can be further miniaturized.
　また、ワイドバンドギャップ半導体から成るスイッチング素子は、高周波スイッチング動作に適している。そのため、高周波化の要求が大きいコンバータ回路に適用された場合、スイッチング周波数の高周波化によって、コンバータ回路に接続されるリアクトルまたはコンデンサなどを小型化することもできる。 Also, switching elements made of wide bandgap semiconductors are suitable for high frequency switching operation. Therefore, when applied to a converter circuit in which a high frequency demand is high, the reactor or capacitor connected to the converter circuit can be miniaturized by increasing the switching frequency.
　よって、以上に記載された実施の形態における半導体スイッチング素子は、炭化珪素などのワイドギャップ半導体から成るスイッチング素子となる場合にも、同様な効果が得られる。 Therefore, the same effect can be obtained when the semiconductor switching element according to the above-described embodiment is a switching element made of a wide-gap semiconductor such as silicon carbide.
　＜以上に記載された実施の形態によって生じる効果について＞
　次に、以上に記載された実施の形態によって生じる効果の例を示す。なお、以下の説明においては、以上に記載された実施の形態に例が示された具体的な構成に基づいて当該効果が記載されるが、同様の効果が生じる範囲で、本願明細書に例が示される他の具体的な構成と置き換えられてもよい。 <About the effect caused by the above-described embodiment>
Next, an example of the effect produced by the above-described embodiment will be shown. In the following description, the effect is described based on the specific configuration shown in the embodiment described above, but to the extent that the same effect occurs, the examples in the present specification. May be replaced with other specific configurations indicated by.
　また、当該置き換えは、複数の実施の形態に跨ってなされてもよい。すなわち、異なる実施の形態において例が示されたそれぞれの構成が組み合わされて、同様の効果が生じる場合であってもよい。 Further, the replacement may be made across a plurality of embodiments. That is, it may be the case that the respective configurations shown in the examples in different embodiments are combined to produce the same effect.
　以上に記載された実施の形態によれば、半導体モジュールは、絶縁基板１０３と、少なくとも１つの半導体素子１０４と、第１の接合材と、金属膜１０９（または、金属膜１０９ａ、金属膜１０９ｂ）とを備える。ここで、第１の接合材は、たとえば、基板下接合材１０７ｂなどに対応するものである。絶縁基板１０３は、少なくとも上面に導体パターンが設けられる。ここで、導体パターンは、たとえば、上側導体パターン１０３ａなどに対応するものである。半導体素子１０４は、上側導体パターン１０３ａの上面に設けられる。基板下接合材１０７ｂは、絶縁基板１０３の下面の一部に設けられる。金属膜１０９は、基板下接合材１０７ｂよりも熱伝導率が高い。また、金属膜１０９は、絶縁基板１０３の下面の他の一部に設けられる。そして、金属膜１０９は、半導体素子１０４が配置される位置に対応する位置の、絶縁基板１０３の下面に設けられる。 According to the embodiment described above, the semiconductor module includes an insulating substrate 103, at least one semiconductor element 104, a first bonding material, and a metal film 109 (or metal film 109a, metal film 109b). And. Here, the first bonding material corresponds to, for example, the substrate lower bonding material 107b. The insulating substrate 103 is provided with a conductor pattern at least on the upper surface. Here, the conductor pattern corresponds to, for example, the upper conductor pattern 103a. The semiconductor element 104 is provided on the upper surface of the upper conductor pattern 103a. The under-board bonding material 107b is provided on a part of the lower surface of the insulating substrate 103. The metal film 109 has a higher thermal conductivity than the substrate bottom bonding material 107b. Further, the metal film 109 is provided on another part of the lower surface of the insulating substrate 103. The metal film 109 is provided on the lower surface of the insulating substrate 103 at a position corresponding to the position where the semiconductor element 104 is arranged.
　このような構成によれば、半導体素子１０４が配置される位置に対応する位置の絶縁基板１０３の下面に金属膜１０９が設けられるため、金属膜によって半導体素子から生じる熱が効率よく放熱される。したがって、絶縁基板に設けられた半導体素子の放熱性能を向上させることができる。また、金属膜１０９がＣｕで形成されている場合、はんだで構成される接合材と比較して機械的強度が高いことから、はんだの場合のような亀裂が発生しにくく、また、発生した場合であっても亀裂進展が遅い。そのため、接合部の信頼性が低下しにくい。 According to such a configuration, since the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved. Further, when the metal film 109 is made of Cu, the mechanical strength is higher than that of the bonding material made of solder, so that cracks unlike those of solder are less likely to occur, and when they occur. Even so, crack growth is slow. Therefore, the reliability of the joint is unlikely to decrease.
　なお、上記の構成に本願明細書に例が示された他の構成を適宜追加した場合、すなわち、上記の構成としては言及されなかった本願明細書中の他の構成が適宜追加された場合であっても、同様の効果を生じさせることができる。 In addition, when other configurations shown in the present specification are appropriately added to the above configurations, that is, when other configurations in the present specification not mentioned as the above configurations are appropriately added. Even if there is, the same effect can be produced.
　また、以上に記載された実施の形態によれば、金属膜１０９は、コールドスプレー法によって成膜されるコールドスプレー膜である。このような構成によれば、コールドスプレー膜は完全なバルク体とはならず、膜内部に空孔が生じているため、空孔が緩衝層となり、金属膜１０９に発生する応力を緩和する効果を有する。したがって、接合部の信頼性が低下しにくい。また、空孔を有しているコールドスプレー膜の見かけの熱伝導率は、はんだなどの熱伝導率と比較して大きいため、放熱性が高まる。 Further, according to the embodiment described above, the metal film 109 is a cold spray film formed by a cold spray method. According to such a configuration, the cold spray film does not become a complete bulk body, and since the pores are formed inside the membrane, the pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Has. Therefore, the reliability of the joint is unlikely to decrease. Further, since the apparent thermal conductivity of the cold spray film having pores is larger than that of solder or the like, heat dissipation is improved.
　なお、コールドスプレー膜は、高圧で粉体を積層することによって成膜される膜である。当該方法によって成膜されたコールドスプレー膜は、空孔を有し、熱伝導率がはんだなどよりも高く同一物質のバルク体などよりも低く、また、表面に凹凸を有するという特徴を備えている。 The cold spray film is a film formed by laminating powder at high pressure. The cold spray film formed by this method has pores, has a higher thermal conductivity than solder or the like, is lower than a bulk body of the same substance, and has irregularities on the surface. ..
　すなわち、コールドスプレー膜は、たとえば、熱伝導率を測定してバルク体と比較すること、または、算術平均粗さＲａを測定するなどによって、はんだなどを含む他の金属膜（接合材）の構造とは明らかに区別される構造を指すものである。 That is, the cold spray film has a structure of another metal film (bonding material) including solder or the like, for example, by measuring the thermal conductivity and comparing it with the bulk body, or by measuring the arithmetic mean roughness Ra. Refers to a structure that is clearly distinguished from.
　したがって、コールドスプレー膜との用語は、単に状態を示すことにより物の構造または物の特性を特定しているにすぎない用語である。 Therefore, the term cold spray membrane is a term that merely specifies the structure or characteristics of an object by indicating its state.
　また、以上に記載された実施の形態によれば、金属膜１０９は、少なくとも、平面視において半導体素子１０４と重なる位置に成膜される。このような構成によれば、金属膜１０９によって、半導体素子１０４から生じる熱を効率よく放熱することができる。 Further, according to the embodiment described above, the metal film 109 is formed at least at a position where it overlaps with the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
　また、以上に記載された実施の形態によれば、金属膜１０９が成膜される面積は、半導体素子１０４が配置される領域の面積よりも大きい。このような構成によれば、金属膜１０９によって、半導体素子１０４から生じる熱を、半導体素子１０４から絶縁基板１０３の面方向に広がる成分を含めて効率よく放熱することができる。 Further, according to the embodiment described above, the area where the metal film 109 is formed is larger than the area of the region where the semiconductor element 104 is arranged. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104 including the component spreading from the semiconductor element 104 in the surface direction of the insulating substrate 103.
　また、以上に記載された実施の形態によれば、金属膜１０９の中心位置は、平面視において、半導体素子１０４の中心位置と一致する。このような構成によれば、金属膜１０９によって、半導体素子１０４から生じる熱を効率よく放熱することができる。 Further, according to the embodiment described above, the center position of the metal film 109 coincides with the center position of the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
　また、以上に記載された実施の形態によれば、半導体モジュールは、第２の接合材と、ベース板１０１とを備える。ここで、第２の接合材は、たとえば、チップ下接合材１０７ａなどに対応するものである。チップ下接合材１０７ａは、半導体素子１０４の下面と上側導体パターン１０３ａの上面とを接合する。ベース板１０１は、基板下接合材１０７ｂによって絶縁基板１０３の下面と接合される。そして、チップ下接合材１０７ａの融点が、基板下接合材１０７ｂの融点よりも高い。このような構成によれば、半導体素子１０４が先に搭載されて絶縁基板１０３が上に凸形状に反った状態であっても、ベース板１０１と絶縁基板１０３とがはんだ付けされる際に金属膜１０９の温度が上昇し、それに伴って金属膜１０９が膨張する。したがって、半導体素子１０４が搭載された部分を頂点とする凸形状を緩和することができる。 Further, according to the embodiment described above, the semiconductor module includes a second bonding material and a base plate 101. Here, the second bonding material corresponds to, for example, the chip bottom bonding material 107a. The chip bottom bonding material 107a joins the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a. The base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b. The melting point of the subchip bonding material 107a is higher than the melting point of the substrate bottom bonding material 107b. According to such a configuration, even if the semiconductor element 104 is mounted first and the insulating substrate 103 is in a state of being warped upward in a convex shape, the metal is used when the base plate 101 and the insulating substrate 103 are soldered. The temperature of the film 109 rises, and the metal film 109 expands accordingly. Therefore, it is possible to relax the convex shape having the portion on which the semiconductor element 104 is mounted as the apex.
　また、以上に記載された実施の形態によれば、金属膜１０９ｂは、対応する１つの半導体素子１０４に対して複数箇所に分かれて絶縁基板１０３の下面に設けられる。このような構成によれば、半導体素子１０４の数と金属膜１０９ａの数とが同一である場合と比較して、必要となるＣｕ粉体の量を抑えつつ、放熱性を向上させることができる。 Further, according to the embodiment described above, the metal film 109b is provided on the lower surface of the insulating substrate 103 at a plurality of locations with respect to the corresponding semiconductor element 104. According to such a configuration, heat dissipation can be improved while suppressing the amount of Cu powder required as compared with the case where the number of semiconductor elements 104 and the number of metal films 109a are the same. ..
　また、以上に記載された実施の形態によれば、半導体素子１０４は、複数備えられる。そして、金属膜１０９ａは、複数の半導体素子１０４が配置されるそれぞれの位置にまたがる位置の、絶縁基板１０３の下面に設けられる。このような構成によれば、半導体素子１０４の数と金属膜１０９ａの数とが同一である場合と比較して、放熱性を向上させることができる。また、同一の絶縁基板上に異なる種類の半導体素子を搭載する場合であっても、金属膜の成膜過程において段取り替えが生じない。したがって、生産性を下げずにパワーモジュールを生産することができる。 Further, according to the embodiment described above, a plurality of semiconductor elements 104 are provided. The metal film 109a is provided on the lower surface of the insulating substrate 103 at a position straddling each position where the plurality of semiconductor elements 104 are arranged. According to such a configuration, heat dissipation can be improved as compared with the case where the number of semiconductor elements 104 and the number of metal films 109a are the same. Further, even when different types of semiconductor elements are mounted on the same insulating substrate, setup change does not occur in the process of forming the metal film. Therefore, the power module can be produced without lowering the productivity.
　また、以上に記載された実施の形態によれば、電力変換装置は、上記の半導体モジュールを有し、かつ、入力される電力を変換して出力する変換回路２２０１と、半導体モジュールを駆動するための駆動信号を半導体モジュールに出力する駆動回路２２０２と、駆動回路２２０２を制御するための制御信号を駆動回路２２０２に出力する制御回路２２０３とを備える。このような構成によれば、半導体素子１０４が配置される位置に対応する位置の絶縁基板１０３の下面に金属膜１０９が設けられるため、金属膜によって半導体素子から生じる熱が効率よく放熱される。したがって、絶縁基板に設けられた半導体素子の放熱性能を向上させることができる。 Further, according to the embodiment described above, the power conversion device has the above-mentioned semiconductor module, and drives the conversion circuit 2201 that converts and outputs the input power and the semiconductor module. The drive circuit 2202 that outputs the drive signal of the above to the semiconductor module and the control circuit 2203 that outputs the control signal for controlling the drive circuit 2202 to the drive circuit 2202 are provided. According to such a configuration, since the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
　以上に記載された実施の形態によれば、半導体モジュールの製造方法において、少なくとも上面に上側導体パターン１０３ａが設けられる絶縁基板１０３の上側導体パターン１０３ａの上面に、少なくとも１つの半導体素子１０４を設ける。そして、絶縁基板１０３の下面の一部に基板下接合材１０７ｂを設ける。そして、絶縁基板１０３の下面の他の一部に、基板下接合材１０７ｂよりも熱伝導率が高い金属膜１０９を設ける。そして、金属膜１０９を設けることは、半導体素子１０４が配置される位置に対応する位置の絶縁基板１０３の下面に、金属膜１０９を設けることである。 According to the above-described embodiment, in the method for manufacturing a semiconductor module, at least one semiconductor element 104 is provided on the upper surface of the upper conductor pattern 103a of the insulating substrate 103 on which the upper conductor pattern 103a is provided on at least the upper surface. Then, the under-board bonding material 107b is provided on a part of the lower surface of the insulating substrate 103. Then, a metal film 109 having a higher thermal conductivity than the under-board bonding material 107b is provided on the other part of the lower surface of the insulating substrate 103. Then, providing the metal film 109 means providing the metal film 109 on the lower surface of the insulating substrate 103 at a position corresponding to the position where the semiconductor element 104 is arranged.
　このような構成によれば、半導体素子１０４が配置される位置に対応する位置の絶縁基板１０３の下面に金属膜１０９が設けられるため、金属膜によって半導体素子から生じる熱が効率よく放熱される。したがって、絶縁基板に設けられた半導体素子の放熱性能を向上させることができる。 According to such a configuration, since the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
　なお、特段の制限がない場合には、それぞれの処理が行われる順序は変更することができる。 If there are no special restrictions, the order in which each process is performed can be changed.
　なお、上記の構成に本願明細書に例が示された他の構成を適宜追加した場合、すなわち、上記の構成としては言及されなかった本願明細書中の他の構成が適宜追加された場合であっても、同様の効果を生じさせることができる。 In addition, when other configurations shown in the present specification are appropriately added to the above configurations, that is, when other configurations in the present specification not mentioned as the above configurations are appropriately added. Even if there is, the same effect can be produced.
　また、以上に記載された実施の形態によれば、金属膜１０９を設けることは、金属膜１０９を、コールドスプレー法によって成膜することである。このような構成によれば、コールドスプレー膜は完全なバルク体とはならず、膜内部に空孔が生じているため、空孔が緩衝層となり、金属膜１０９に発生する応力を緩和する効果を有する。したがって、接合部の信頼性が低下しにくい。また、空孔を有しているコールドスプレー膜の見かけの熱伝導率は、はんだなどの熱伝導率と比較して大きいため、放熱性が高まる。 Further, according to the embodiment described above, providing the metal film 109 means forming the metal film 109 into a film by a cold spray method. According to such a configuration, the cold spray film does not become a complete bulk body, and since the pores are formed inside the membrane, the pores serve as a buffer layer and have the effect of relaxing the stress generated in the metal film 109. Has. Therefore, the reliability of the joint is unlikely to decrease. Further, since the apparent thermal conductivity of the cold spray film having pores is larger than that of solder or the like, heat dissipation is improved.
　また、以上に記載された実施の形態によれば、金属膜１０９を設けることは、金属膜１０９を、少なくとも、平面視において半導体素子１０４と重なる位置に成膜することである。このような構成によれば、金属膜１０９によって、半導体素子１０４から生じる熱を効率よく放熱することができる。 Further, according to the embodiment described above, the provision of the metal film 109 means that the metal film 109 is formed at least at a position where it overlaps with the semiconductor element 104 in a plan view. According to such a configuration, the metal film 109 can efficiently dissipate the heat generated from the semiconductor element 104.
　また、以上に記載された実施の形態によれば、半導体素子１０４の下面と上側導体パターン１０３ａの上面とをチップ下接合材１０７ａによって接合する。そして、半導体素子１０４の下面と上側導体パターン１０３ａの上面とを接合した後に、基板下接合材１０７ｂによって、絶縁基板１０３の下面にベース板１０１を接合する。ここで、チップ下接合材１０７ａの融点は、基板下接合材１０７ｂの融点よりも高い。このような構成によれば、半導体素子１０４と上側導体パターン１０３ａとをチップ下接合材１０７ａによって接合された後に、絶縁基板１０３の下面とベース板１０１とが基板下接合材１０７ｂによって接合される場合に、絶縁基板１０３が上に凸形状に反った状態であっても、ベース板１０１と絶縁基板１０３とがはんだ付けされる際に金属膜１０９の温度が上昇し、それに伴って金属膜１０９が膨張する。したがって、半導体素子１０４が搭載された部分を頂点とする凸形状を緩和することができる。 Further, according to the embodiment described above, the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a are joined by the chip bottom bonding material 107a. Then, after joining the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a, the base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b. Here, the melting point of the subchip bonding material 107a is higher than the melting point of the substrate sublayer bonding material 107b. According to such a configuration, after the semiconductor element 104 and the upper conductor pattern 103a are joined by the chip lower bonding material 107a, the lower surface of the insulating substrate 103 and the base plate 101 are joined by the substrate lower bonding material 107b. In addition, even when the insulating substrate 103 is warped upward in a convex shape, the temperature of the metal film 109 rises when the base plate 101 and the insulating substrate 103 are soldered, and the metal film 109 is formed accordingly. Inflate. Therefore, it is possible to relax the convex shape having the portion on which the semiconductor element 104 is mounted as the apex.
　また、以上に記載された実施の形態によれば、基板下接合材１０７ｂによって、絶縁基板１０３の下面にベース板１０１を接合する。そして、絶縁基板１０３の下面とベース板１０１の上面とを接合した後に、半導体素子１０４の下面と上側導体パターン１０３ａの上面とをチップ下接合材１０７ａによって接合する。ここで、チップ下接合材１０７ａの融点は、基板下接合材１０７ｂの融点以下である。このような構成によれば、半導体素子１０４を絶縁基板１０３に搭載する前にベース板１０１の接合を終わらせることができるため、前述の異なる工順と併せて工順の自由度を高めることができる。 Further, according to the embodiment described above, the base plate 101 is joined to the lower surface of the insulating substrate 103 by the substrate lower bonding material 107b. Then, after joining the lower surface of the insulating substrate 103 and the upper surface of the base plate 101, the lower surface of the semiconductor element 104 and the upper surface of the upper conductor pattern 103a are joined by the subchip bonding material 107a. Here, the melting point of the subchip bonding material 107a is equal to or lower than the melting point of the substrate bottom bonding material 107b. According to such a configuration, the joining of the base plate 101 can be completed before the semiconductor element 104 is mounted on the insulating substrate 103, so that the degree of freedom of the routing can be increased in addition to the different routing described above. it can.
　また、以上に記載された実施の形態によれば、電力変換装置の製造方法において、上記の製造方法で製造される半導体モジュールを有し、かつ、入力される電力を変換して出力する変換回路２２０１を設ける。そして、半導体モジュールを駆動するための駆動信号を半導体モジュールに出力する駆動回路２２０２を設ける。そして、駆動回路２２０２を制御するための制御信号を駆動回路２２０２に出力する制御回路２２０３を設ける。このような構成によれば、半導体素子１０４が配置される位置に対応する位置の絶縁基板１０３の下面に金属膜１０９が設けられるため、金属膜によって半導体素子から生じる熱が効率よく放熱される。したがって、絶縁基板に設けられた半導体素子の放熱性能を向上させることができる。 Further, according to the above-described embodiment, in the method for manufacturing a power conversion device, a conversion circuit having a semiconductor module manufactured by the above manufacturing method and converting and outputting input power. 2201 is provided. Then, a drive circuit 2202 that outputs a drive signal for driving the semiconductor module to the semiconductor module is provided. Then, a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202 is provided. According to such a configuration, since the metal film 109 is provided on the lower surface of the insulating substrate 103 at the position corresponding to the position where the semiconductor element 104 is arranged, the heat generated from the semiconductor element is efficiently dissipated by the metal film. Therefore, the heat dissipation performance of the semiconductor element provided on the insulating substrate can be improved.
　＜以上に記載された実施の形態の変形例について＞
　以上に記載された実施の形態では、それぞれの構成要素の材質、材料、寸法、形状、相対的配置関係または実施の条件などについても記載する場合があるが、これらはすべての局面においてひとつの例であって、本願明細書に記載されたものに限られることはないものとする。 <About the modified example of the embodiment described above>
In the embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relationships, implementation conditions, etc. of each component may also be described, but these are one example in all aspects. However, it is not limited to those described in the present specification.
　したがって、例が示されていない無数の変形例、および、均等物が、本願明細書に開示される技術の範囲内において想定される。たとえば、少なくとも１つの構成要素を変形する場合、追加する場合または省略する場合、さらには、少なくとも１つの実施の形態における少なくとも１つの構成要素を抽出し、他の実施の形態における構成要素と組み合わせる場合が含まれるものとする。 Therefore, innumerable variants and equivalents for which examples are not shown are envisioned within the scope of the technology disclosed herein. For example, when transforming, adding or omitting at least one component, or when extracting at least one component in at least one embodiment and combining it with the component in another embodiment. Shall be included.
　また、以上に記載された実施の形態において、特に指定されずに材料名などが記載された場合は、矛盾が生じない限り、当該材料に他の添加物が含まれた、たとえば、合金などが含まれるものとする。 Further, in the above-described embodiment, when a material name or the like is described without being specified, the material contains other additives, for example, an alloy, etc., as long as there is no contradiction. It shall be included.
　また、矛盾が生じない限り、以上に記載された実施の形態において「１つ」備えられるものとして記載された構成要素は、「１つ以上」備えられていてもよいものとする。 Further, as long as there is no contradiction, "one or more" components described as being provided in the above-described embodiment may be provided.
　さらに、以上に記載された実施の形態におけるそれぞれの構成要素は概念的な単位であって、本願明細書に開示される技術の範囲内には、１つの構成要素が複数の構造物から成る場合と、１つの構成要素がある構造物の一部に対応する場合と、さらには、複数の構成要素が１つの構造物に備えられる場合とを含むものとする。 Further, each component in the above-described embodiment is a conceptual unit, and within the scope of the technology disclosed in the present specification, one component is composed of a plurality of structures. And the case where one component corresponds to a part of a structure, and further, the case where a plurality of components are provided in one structure.
　また、以上に記載された実施の形態におけるそれぞれの構成要素には、同一の機能を発揮する限り、他の構造または形状を有する構造物が含まれるものとする。 Further, each component in the above-described embodiment shall include a structure having another structure or shape as long as it exhibits the same function.
　また、本願明細書における説明は、本技術に関連するすべての目的のために参照され、いずれも、従来技術であると認めるものではない。 Further, the description in the present specification is referred to for all purposes related to the present technology, and none of them is recognized as a prior art.
　１００　電力用半導体モジュール、１０２　ケース、１０１　ベース板、１０３　絶縁基板、１０３ａ，１０３ｂ，１０３ｃ，１０３ｄ　上側導体パターン、１０３ｅ　絶縁材、１０３ｆ　下側導体パターン、１０４　半導体素子、１０４ａ　スイッチングデバイス、１０４ｂ　還流ダイオード、１０５　封止材、１０６　配線、１０６ａ　ワイヤー状配線、１０６ｂ　ソース信号配線、１０６ｃ　ゲート信号配線、１０７ａ　チップ下接合材、１０７ｂ　基板下接合材、１０８　端子、１０８ａ　主端子、１０８ｂ　制御端子、１０９，１０９ａ，１０９ｂ　金属膜、１１０　上面電極、１１０ａ　ゲートパッド、１１１　保護膜、２０１　コールドスプレー膜用マスク、２０２　絶縁基板保持治具、２１００　電源、２２００　電力変換装置、２２０１　変換回路、２２０２　駆動回路、２２０３　制御回路、２３００　負荷。 100 power semiconductor module, 102 case, 101 base plate, 103 insulating substrate, 103a, 103b, 103c, 103d upper conductor pattern, 103e insulating material, 103f lower conductor pattern, 104 semiconductor element, 104a switching device, 104b freewheeling diode, 105 Encapsulant, 106 Wiring, 106a Wire-shaped wiring, 106b Source signal wiring, 106c Gate signal wiring, 107a Subchip bonding material, 107b Subboard bonding material, 108 terminal, 108a Main terminal, 108b Control terminal, 109,109a 109b metal film, 110 top electrode, 110a gate pad, 111 protective film, 201 cold spray film mask, 202 insulating substrate holding jig, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

Claims (19)

  1. 　少なくとも上面に導体パターンが設けられる絶縁基板と、
    　前記導体パターンの上面に設けられる少なくとも１つの半導体素子と、
    　前記絶縁基板の下面の一部に設けられる第１の接合材と、
    　前記第１の接合材よりも熱伝導率が高く、かつ、前記絶縁基板の下面の他の一部に設けられる金属膜とを備え、
    　前記金属膜は、前記半導体素子が配置される位置に対応する位置の、前記絶縁基板の下面に設けられる、
    　半導体モジュール。     An insulating substrate with a conductor pattern on at least the top surface,
    At least one semiconductor element provided on the upper surface of the conductor pattern and
    With the first bonding material provided on a part of the lower surface of the insulating substrate,
    It has a higher thermal conductivity than the first bonding material, and is provided with a metal film provided on another part of the lower surface of the insulating substrate.
    The metal film is provided on the lower surface of the insulating substrate at a position corresponding to the position where the semiconductor element is arranged.
    Semiconductor module.
  2. 　請求項１に記載の半導体モジュールであり、
    　前記金属膜は、コールドスプレー法によって成膜されるコールドスプレー膜である、
    　半導体モジュール。     The semiconductor module according to claim 1.
    The metal film is a cold spray film formed by a cold spray method.
    Semiconductor module.
  3. 　請求項１または２に記載の半導体モジュールであり、
    　前記金属膜の表面における凹凸に前記第１の接合材が侵入し接合することによって、金属間化合物相が形成される、
    　半導体モジュール。     The semiconductor module according to claim 1 or 2.
    The intermetallic compound phase is formed by the first bonding material invading and joining the irregularities on the surface of the metal film.
    Semiconductor module.
  4. 　請求項１から３のうちのいずれか１つに記載の半導体モジュールであり、
    　前記金属膜は、少なくとも、平面視において前記半導体素子と重なる位置に成膜される、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 3.
    The metal film is formed at least at a position overlapping the semiconductor element in a plan view.
    Semiconductor module.
  5. 　請求項１から４のうちのいずれか１つに記載の半導体モジュールであり、
    　前記金属膜が成膜される面積は、前記半導体素子が配置される領域の面積よりも大きい、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 4.
    The area where the metal film is formed is larger than the area of the region where the semiconductor element is arranged.
    Semiconductor module.
  6. 　請求項１から５のうちのいずれか１つに記載の半導体モジュールであり、
    　前記金属膜の中心位置は、平面視において、前記半導体素子の中心位置と一致する、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 5.
    The center position of the metal film coincides with the center position of the semiconductor element in a plan view.
    Semiconductor module.
  7. 　請求項１から６のうちのいずれか１つに記載の半導体モジュールであり、
    　前記半導体素子の下面と前記導体パターンの上面とを接合する第２の接合材と、
    　前記第１の接合材によって前記絶縁基板の下面と接合されるベース板とをさらに備え、
    　前記第２の接合材の融点が、前記第１の接合材の融点よりも高い、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 6.
    A second bonding material that joins the lower surface of the semiconductor element and the upper surface of the conductor pattern,
    A base plate to be joined to the lower surface of the insulating substrate by the first joining material is further provided.
    The melting point of the second bonding material is higher than the melting point of the first bonding material.
    Semiconductor module.
  8. 　請求項１から７のうちのいずれか１つに記載の半導体モジュールであり、
    　前記金属膜は、対応する１つの前記半導体素子に対して複数箇所に分かれて、前記絶縁基板の下面に設けられる、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 7.
    The metal film is divided into a plurality of locations with respect to the corresponding semiconductor element and is provided on the lower surface of the insulating substrate.
    Semiconductor module.
  9. 　請求項１から７のうちのいずれか１つに記載の半導体モジュールであり、
    　前記半導体素子は、複数備えられ、
    　前記金属膜は、複数の前記半導体素子が配置されるそれぞれの位置にまたがる位置の、前記絶縁基板の下面に設けられる、
    　半導体モジュール。     The semiconductor module according to any one of claims 1 to 7.
    A plurality of the semiconductor elements are provided.
    The metal film is provided on the lower surface of the insulating substrate at a position straddling each position where the plurality of semiconductor elements are arranged.
    Semiconductor module.
  10. 　少なくとも上面に導体パターンが設けられる絶縁基板と、
    　前記導体パターンの上面に設けられる少なくとも１つの半導体素子と、
    　前記導体パターンの上面に設けられる少なくとも１つの電極と、
    　前記絶縁基板の下面の一部に設けられる第１の接合材と、
    　前記第１の接合材よりも熱伝導率が高く、かつ、前記絶縁基板の下面の他の一部に設けられる金属膜とを備え、
    　前記金属膜は、前記電極が配置される位置に対応する位置の、前記絶縁基板の下面に設けられる、
    　半導体モジュール。     An insulating substrate with a conductor pattern on at least the top surface,
    At least one semiconductor element provided on the upper surface of the conductor pattern and
    With at least one electrode provided on the upper surface of the conductor pattern,
    With the first bonding material provided on a part of the lower surface of the insulating substrate,
    It has a higher thermal conductivity than the first bonding material, and is provided with a metal film provided on another part of the lower surface of the insulating substrate.
    The metal film is provided on the lower surface of the insulating substrate at a position corresponding to the position where the electrode is arranged.
    Semiconductor module.
  11. 　請求項１０に記載の半導体モジュールであり、
    　前記電極と前記導体パターンとが、超音波による固相拡散接合で接続される、
    　半導体モジュール。     The semiconductor module according to claim 10.
    The electrode and the conductor pattern are connected by solid-phase diffusion bonding by ultrasonic waves.
    Semiconductor module.
  12. 　請求項１０または１１に記載の半導体モジュールであり、
    　前記金属膜は、コールドスプレー法によって成膜されるコールドスプレー膜である、
    　半導体モジュール。     The semiconductor module according to claim 10 or 11.
    The metal film is a cold spray film formed by a cold spray method.
    Semiconductor module.
  13. 　請求項１から請求項１２のうちのいずれか１項に記載の半導体モジュールを有し、かつ、入力される電力を変換して出力する変換回路と、
    　前記半導体モジュールを駆動するための駆動信号を前記半導体モジュールに出力する駆動回路と、
    　前記駆動回路を制御するための制御信号を前記駆動回路に出力する制御回路とを備える、
    　電力変換装置。     A conversion circuit having the semiconductor module according to any one of claims 1 to 12 and converting and outputting input power.
    A drive circuit that outputs a drive signal for driving the semiconductor module to the semiconductor module, and a drive circuit.
    A control circuit for outputting a control signal for controlling the drive circuit to the drive circuit is provided.
    Power converter.
  14. 　少なくとも上面に導体パターンが設けられる絶縁基板の前記導体パターンの上面に、少なくとも１つの半導体素子を設け、
    　前記絶縁基板の下面の一部に第１の接合材を設け、
    　前記絶縁基板の下面の他の一部に、前記第１の接合材よりも熱伝導率が高い金属膜を設け、
    　前記金属膜を設けることは、前記半導体素子が配置される位置に対応する位置の前記絶縁基板の下面に、前記金属膜を設けることである、
    　半導体モジュールの製造方法。     At least one semiconductor element is provided on the upper surface of the conductor pattern of the insulating substrate on which the conductor pattern is provided on at least the upper surface.
    A first bonding material is provided on a part of the lower surface of the insulating substrate.
    A metal film having a higher thermal conductivity than that of the first bonding material is provided on the other part of the lower surface of the insulating substrate.
    Providing the metal film means providing the metal film on the lower surface of the insulating substrate at a position corresponding to the position where the semiconductor element is arranged.
    Manufacturing method of semiconductor module.
  15. 　請求項１４に記載の半導体モジュールの製造方法であり、
    　前記金属膜を設けることは、前記金属膜を、コールドスプレー法によって成膜することである、
    　半導体モジュールの製造方法。     The method for manufacturing a semiconductor module according to claim 14.
    Providing the metal film means forming the metal film by a cold spray method.
    Manufacturing method of semiconductor module.
  16. 　請求項１４または１５に記載の半導体モジュールの製造方法であり、
    　前記金属膜を設けることは、前記金属膜を、少なくとも、平面視において前記半導体素子と重なる位置に成膜することである、
    　半導体モジュールの製造方法。     The method for manufacturing a semiconductor module according to claim 14 or 15.
    Providing the metal film means forming the metal film at least at a position where it overlaps with the semiconductor element in a plan view.
    Manufacturing method of semiconductor module.
  17. 　請求項１４から１６のうちのいずれか１つに記載の半導体モジュールの製造方法であり、
    　前記半導体素子の下面と前記導体パターンの上面とを第２の接合材によって接合し、
    　前記半導体素子の下面と前記導体パターンの上面とを接合した後に、前記第１の接合材によって、前記絶縁基板の下面にベース板を接合し、
    　前記第２の接合材の融点は、前記第１の接合材の融点よりも高い、
    　半導体モジュールの製造方法。     The method for manufacturing a semiconductor module according to any one of claims 14 to 16.
    The lower surface of the semiconductor element and the upper surface of the conductor pattern are joined by a second joining material.
    After joining the lower surface of the semiconductor element and the upper surface of the conductor pattern, the base plate is joined to the lower surface of the insulating substrate by the first bonding material.
    The melting point of the second bonding material is higher than the melting point of the first bonding material.
    Manufacturing method of semiconductor module.
  18. 　請求項１４から１６のうちのいずれか１つに記載の半導体モジュールの製造方法であり、
    　前記第１の接合材によって、前記絶縁基板の下面にベース板を接合し、
    　前記絶縁基板の下面と前記ベース板の上面とを接合した後に、前記半導体素子の下面と前記導体パターンの上面とを第２の接合材によって接合し、
    　前記第２の接合材の融点は、前記第１の接合材の融点以下である、
    　半導体モジュールの製造方法。     The method for manufacturing a semiconductor module according to any one of claims 14 to 16.
    The base plate is bonded to the lower surface of the insulating substrate by the first bonding material.
    After joining the lower surface of the insulating substrate and the upper surface of the base plate, the lower surface of the semiconductor element and the upper surface of the conductor pattern are joined by a second joining material.
    The melting point of the second bonding material is equal to or lower than the melting point of the first bonding material.
    Manufacturing method of semiconductor module.
  19. 　請求項１４から請求項１８のうちのいずれか１項に記載の製造方法で製造される半導体モジュールを有し、かつ、入力される電力を変換して出力する変換回路を設け、
    　前記半導体モジュールを駆動するための駆動信号を前記半導体モジュールに出力する駆動回路を設け、
    　前記駆動回路を制御するための制御信号を前記駆動回路に出力する制御回路を設ける、
    　電力変換装置の製造方法。     A conversion circuit having a semiconductor module manufactured by the manufacturing method according to any one of claims 14 to 18 and converting and outputting input power is provided.
    A drive circuit for outputting a drive signal for driving the semiconductor module to the semiconductor module is provided.
    A control circuit for outputting a control signal for controlling the drive circuit to the drive circuit is provided.
    Manufacturing method of power converter.
PCT/JP2020/039367 2019-10-31 2020-10-20 Semiconductor module, power conversion apparatus, method for manufacturing semiconductor module, and method for manufacturing power conversion apparatus WO2021085234A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010134580A (en) * 2008-12-03 2010-06-17 Seiko Epson Corp Fiscal printer
JP2012138029A (en) * 2010-12-27 2012-07-19 Mitsubishi Heavy Ind Ltd Maintenance information delivery system and maintenance information delivery method
JP2017139345A (en) * 2016-02-04 2017-08-10 株式会社日立製作所 Semiconductor device, and method of manufacturing the same
JP2018142582A (en) * 2017-02-27 2018-09-13 三菱電機株式会社 Power semiconductor device, manufacturing method thereof, and power conversion device
JP2018182198A (en) * 2017-04-19 2018-11-15 株式会社東芝 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340719A (en) * 1999-05-26 2000-12-08 Hitachi Ltd Power semiconductor device
JP5328740B2 (en) * 2010-10-04 2013-10-30 三菱電機株式会社 Semiconductor device and manufacturing method of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010134580A (en) * 2008-12-03 2010-06-17 Seiko Epson Corp Fiscal printer
JP2012138029A (en) * 2010-12-27 2012-07-19 Mitsubishi Heavy Ind Ltd Maintenance information delivery system and maintenance information delivery method
JP2017139345A (en) * 2016-02-04 2017-08-10 株式会社日立製作所 Semiconductor device, and method of manufacturing the same
JP2018142582A (en) * 2017-02-27 2018-09-13 三菱電機株式会社 Power semiconductor device, manufacturing method thereof, and power conversion device
JP2018182198A (en) * 2017-04-19 2018-11-15 株式会社東芝 Semiconductor device

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