WO2021084964A1 - Switching control circuit and switching power supply apparatus - Google Patents

Abstract

The purpose of the present invention is to generate an output voltage by switching from an input voltage applied to a series circuit of an inductor and a switching element. A control unit performs a PWM operation or a burst operation on the basis of a feedback voltage corresponding to the magnitude of a load. During the burst operation, switching is stopped and a turn-on instruction for the switching element is given on the basis of the feedback voltage, and, upon the value of a current (I_P) flowing through the switching element exceeding a turn-off threshold value (I_OFF), a turn-off instruction for the switching element is given. The turn-off threshold value is increased over time in a predetermined interval after the turn-on instruction.

Description

Switching control circuit and switching power supply

The present invention relates to a switching control circuit and a switching power supply device.

A switching power supply device that generates an output voltage by switching a switching element from an input voltage applied to a series circuit of an inductor and a switching element is known. Typically, for example, in an AC / DC converter using a transformer, a switching element is connected in series to the primary winding as an inductor, and an AC voltage is full-wave rectified to those series circuits to obtain a direct current. The output voltage is obtained on the secondary side by applying the input voltage of the above and switching driving the switching element.

In this type of switching power supply, a PWM operation is usually performed in which a switching element is switched at a switching frequency by using pulse width modulation. There is also a type of switching power supply that executes burst operation for the purpose of reducing power consumption when the load is light (see, for example, Patent Document 1 below). In the burst operation, the switching element is switched only when necessary in a non-periodic manner without switching according to the switching frequency.

Japanese Patent Publication No. 2008-541688

In a switching power supply device capable of switching and executing PWM operation and burst operation, the magnitude of the load is monitored, and the PWM operation and burst operation are switched and executed based on the feedback voltage according to the magnitude of the load. At this time, there is a boundary power (burst boundary power) for switching between PWM operation and burst operation, but in the conventional switching power supply device, this boundary power changes depending on the magnitude of the input voltage. was there.

That is, for example, when considering an AC / DC converter, the effective value of the input AC voltage to the AC / DC converter may be 100V or 240V, and in conjunction with this, the primary winding of the transformer The DC input voltage applied to the circuit in series with the switching element also changes in various ways. In a conventional switching power supply device, the boundary power changes depending on the magnitude of the input voltage (for example, depending on whether the effective value of the input AC voltage to the AC / DC converter is 100V or 240V). was there. This means that the load power consumption is the same, but the burst operation is performed or not performed depending on the input voltage (the reason for this phenomenon will be explained in detail later).

It is not desirable that the burst operation is performed or not performed depending on the input voltage (in other words, the execution condition of the burst operation depends on the input voltage), which hinders the optimization of the power design related to the burst operation.

An object of the present invention is to provide a switching control circuit and a switching power supply device that suppress the execution conditions of burst operation from changing according to an input voltage.

The switching control circuit according to the present invention transfers a current flowing through the switching element in a switching control circuit for generating an output voltage by switching the switching element from an input voltage applied to a series circuit of the inductor and the switching element. A PWM operation or burst operation for switching the switching element at a set switching frequency is executed based on the current detection unit that detects the target current and the feedback voltage according to the magnitude of the load to which the output voltage is supplied. The control unit includes a set signal generation unit that generates a set signal instructing the turn-on of the switching element, and a reset signal generation unit that generates a reset signal instructing the turn-off of the switching element. , The signal for turning on the switching element when receiving the set signal is supplied to the switching element, and the signal for turning off the switching element when receiving the reset signal is switched. It has a drive unit that supplies the element, and in the burst operation, the switching of the switching element at the switching frequency is stopped, and in the burst operation, the set signal generating unit generates the set signal based on the feedback voltage. After that, the reset signal generation unit generates the reset signal when the value of the target current exceeds the turn-off threshold, and the reset signal generation unit is set in a predetermined section after the generation of the set signal. Therefore, the turn-off threshold is increased with the passage of time (first configuration).

In the switching control circuit according to the first configuration, the turn-off threshold value may have a value corresponding to the feedback voltage (second configuration).

In the switching control circuit according to the first or second configuration, the reset signal generator adds a slope compensation signal whose signal value increases with the passage of time in the predetermined section to a signal proportional to the feedback voltage. A configuration (third) in which a turn-off threshold signal indicating the turn-off threshold is generated, and in the burst operation, the reset signal is generated by comparing the current detection signal indicating the value of the target current with the turn-off threshold signal (third). The configuration of) may be used.

In the switching control circuit according to the third configuration, the set signal generator has an oscillator that generates a signal of the switching frequency, and in the PWM operation, the set signal is used at the switching frequency by using the oscillator. In the PWM operation, the reset signal generating unit generates the reset signal based on the current detection signal, the turn-off threshold signal, and the overcurrent threshold signal indicating a predetermined overcurrent threshold. (Fourth configuration) may be used.

In the switching control circuit according to the fourth configuration, the reset signal generating unit is a first comparator that compares the current detection signal with the turn-off threshold signal, and the current detection signal and the overcurrent threshold. It has a second comparator that compares with a signal, and in the PWM operation, the value of the target current is higher than the turn-off threshold or the overcurrent threshold based on the comparison results of the first comparator and the second comparator. The configuration may be such that the reset signal is generated when the value becomes large (fifth configuration).

In the switching control circuit according to the fourth or fifth configuration, the reset signal generation unit adds a first slope compensation signal whose signal value increases with the passage of time in the predetermined section to a signal proportional to the feedback voltage. As a result, the turn-off threshold signal is generated, and the overcurrent threshold signal is generated by adding the second slope compensation signal whose signal value increases with the passage of time in the predetermined section to the signal having the predetermined value. It may be the configuration (sixth configuration).

In the switching control circuit according to any one of the first to sixth configurations, the feedback voltage decreases as the magnitude of the load decreases, and the control unit has the feedback voltage higher than the predetermined burst determination voltage. When the state is maintained, the PWM operation may be continuously executed, and the burst operation may be started when the feedback voltage falls below the burst determination voltage (seventh configuration).

In the switching control circuit according to the seventh configuration, the control unit starts the burst operation in response to the transition from a state in which the feedback voltage is higher than the burst determination voltage to a state in which the feedback voltage is lower than the burst determination voltage. After the start of the burst operation, the switching element is kept in the off state until the feedback voltage exceeds a predetermined burst release voltage higher than the burst determination voltage, and when the feedback voltage exceeds the burst release voltage, the set signal Even in the configuration (eighth configuration), the set signal is generated by the generating unit, and then the reset signal is generated by the reset signal generating unit in response to the value of the target current exceeding the turn-off threshold. good.

In the switching control circuit according to any one of the first to sixth configurations, the feedback voltage increases as the magnitude of the load decreases, and the control unit has the feedback voltage lower than a predetermined burst determination voltage. When the state is maintained, the PWM operation may be continuously executed, and the burst operation may be started when the feedback voltage exceeds the burst determination voltage (9th configuration).

In the switching control circuit according to the ninth configuration, the control unit starts the burst operation in response to the transition from the state where the feedback voltage is lower than the burst determination voltage to the state where the feedback voltage is higher than the burst determination voltage. After the start of the burst operation, the switching element is kept in the off state until the feedback voltage falls below a predetermined burst release voltage lower than the burst determination voltage, and when the feedback voltage falls below the burst release voltage, the set signal Even in the configuration (10th configuration), the set signal is generated by the generating unit, and then the reset signal is generated by the reset signal generating unit in response to the value of the target current exceeding the turn-off threshold. good.

In the switching control circuit according to any one of the first to tenth configurations, a transformer having the inductor and the secondary winding is used as the primary winding, and the input voltage applied to the primary side is two. The configuration may be such that the output voltage is generated on the next side (11th configuration).

The switching power supply device according to the present invention is a switching power supply device that uses a transformer having a primary side winding and a secondary side winding to generate an output voltage on the secondary side from an input voltage applied to the primary side by a switching method. A switching element connected in series to the primary winding as an inductor, a switching control circuit according to any one of the first to eleventh configurations, and a feedback voltage generation that generates the feedback voltage based on the output voltage. It is a configuration (12th configuration) including a circuit.

In the switching power supply device according to the twelfth configuration, the input voltage may be a configuration (13th configuration) generated by rectifying and smoothing an AC voltage.

According to the present invention, it is possible to provide a switching control circuit and a switching power supply device that suppress the execution conditions of burst operation from changing according to the input voltage.

Is an overall configuration diagram of the AC / DC converter according to the first embodiment of the present invention. Is an external perspective view of an electronic component as an AC / DC converter according to the first embodiment of the present invention. Is a partial configuration diagram of an AC / DC converter according to the first embodiment of the present invention. Is an explanatory diagram of a mode setting according to a feedback voltage according to the first embodiment of the present invention. Is an explanatory diagram of a burst operation according to the first embodiment of the present invention. (A) to (c) are diagrams showing the waveform of the primary side current in a virtual situation according to the first embodiment of the present invention. Is a relationship diagram of an input voltage and a burst boundary voltage in a virtual situation according to the first embodiment of the present invention. Is a diagram showing a waveform of a primary side current in an actual situation according to the first embodiment of the present invention. Is a relationship diagram of an input voltage and a burst boundary voltage in an actual situation according to the first embodiment of the present invention. Is a schematic internal block diagram of a primary side control circuit according to the first embodiment of the present invention. Is a configuration diagram of a main control unit according to the first embodiment of the present invention. Is a waveform diagram of various voltages and signals related to burst operation according to the first embodiment of the present invention. Is a functional block diagram of a set signal generation unit according to the first embodiment of the present invention. Is a relationship diagram of a feedback voltage and a frequency related to switching according to the first embodiment of the present invention. Is a diagram for explaining a waveform of a slope compensation signal according to the first embodiment of the present invention. Is a waveform diagram of a plurality of signals related to the operation of the drive unit according to the first embodiment of the present invention. Is a diagram showing current waveforms (five types of current waveforms) to be compared with the primary side current in order to generate a reset signal according to the first embodiment of the present invention. Is a diagram showing how the relationship between the secondary power and the switching frequency does not depend on the input voltage according to the first embodiment of the present invention. Is a basic waveform diagram of voltages, signals, etc. related to burst operation. Is a deformed waveform diagram of a voltage, a signal, etc. related to a burst operation.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc., the information, a signal, a physical quantity, an element or a part corresponding to the symbol or the code is described. Etc. may be omitted or abbreviated. For example, the switching transistor referred to by "14" described later (see FIG. 1) may be referred to as a switching transistor 14 or abbreviated as a transistor 14, but they are all the same. Point to.

First, some terms used in the description of the embodiment of the present invention will be explained. In the embodiment of the present invention, IC is an abbreviation for Integrated Circuit. PWM is an abbreviation for Pulse Width Modulation. Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage. For any signal or voltage, switching from low level to high level is called the up edge, and switching from high level to low level is called the down edge.

For any transistor configured as a FET (Field Effect Transistor) including a MOSFET, the on state means that the drain and source of the transistor are in a conductive state, and the off state means the drain of the transistor. And it means that there is a non-conduction state (interruption state) between the sources. The same applies to transistors that are not classified as FETs. Hereinafter, the on state and the off state may be simply expressed as on and off. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". For any transistor, switching from the off state to the on state is expressed as turn-on, and switching from the on state to the off state is expressed as turn-off.

<< First Embodiment >>
The first embodiment of the present invention will be described. FIG. 1 is an overall configuration diagram of an AC / DC converter 1 according to the first embodiment of the present invention. FIG. 1 also shows a load LD connected to the AC / DC converter 1. The AC / DC converter 1 includes a primary side circuit 10 which is a circuit provided on the primary side and a secondary side circuit 20 which is a circuit provided on the secondary side. In the AC / DC converter 1, the primary side and the secondary side are insulated from each other, in other words, the primary side circuit 10 and the secondary side circuit 20 are insulated from each other. Further, the AC / DC converter 1 includes a transformer TR and a photocoupler PC provided over the primary side circuit 10 and the secondary side circuit 20. The transformer TR includes a primary winding W1 arranged in the primary circuit 10 and a secondary winding W2 arranged in the secondary circuit 20. In the transformer TR, the primary winding W1 and the secondary winding W2 are electrically insulated and magnetically coupled to each other with opposite polarities. The photocoupler PC includes a light emitting element PCe arranged in the secondary side circuit 20 and a light receiving element PCr arranged in the primary side circuit 10.

In the AC / DC converter 1, an output voltage V _OUT is generated in an _{isolated form from the input voltage V IN by using a transformer TR.} The ground in the primary side circuit 10 is referred to by "GND1", and the ground in the secondary side circuit 20 is referred to by "GND2". The input voltage V _IN is the primary side voltage with reference to the ground GND 1, and the output voltage V _OUT is the secondary side voltage with reference to the ground GND 2. In each of the primary side circuit 10 and the secondary side circuit 20, ground refers to a conductive portion (predetermined potential point) having a reference potential of 0 V (zero volt) or refers to the reference potential itself. However, since the ground GND1 and the ground GND2 are insulated from each other, they may have different potentials from each other.

The primary side circuit 10 will be described. The primary side circuit 10 includes a filter 11, a rectifier circuit 12, a smoothing capacitor 13, a switching transistor 14, a current sense resistor 15, a primary side control circuit 16 which is an example of a switching control circuit, a power supply generation circuit 17, and a feedback capacitor 18. It is provided. The switching transistor 14 is configured as an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor).

The filter 11 removes noise of the _AC voltage VAC input to the AC / DC converter 1. AC voltage V _AC may be a commercial AC voltage. The rectifier circuit 12 is a diode bridge circuit that full-wave rectifies the _{AC voltage DAC supplied through the filter 11.} Smoothing capacitor 13 produces an input voltage V _IN by smoothing the voltage full-wave rectified by the rectifier circuit 12. _{An input voltage V IN} is applied between both ends of the smoothing capacitor 13 with reference to the ground GND1. Across the smoothing capacitor 13 is understood when connected corresponding to input terminals _{TM IN} input voltage _{V IN} is applied or to the input terminal _{TM IN.} The input voltage V _IN is a positive DC voltage having a voltage value corresponding to the effective value of the _AC voltage VAC. The input voltage V _IN may pulsate slightly in the cycle of the _AC voltage VAC, but the pulsation is ignored here.

An input voltage V _IN is applied to one end of the primary winding W1, and the other end of the primary winding W1 is connected to the drain of the switching transistor 14. The source of the switching transistor 14 is connected to the ground GND1 via the current sense resistor 15. Voltage drop caused by the current sensing resistor 15, i.e. the voltage between the two terminals of the current sensing resistor 15 is input to the primary side control circuit 16 as a current sense voltage V _CS. The current sense voltage _VCS has a voltage value proportional to the value of the current flowing through the switching transistor 14. Further, the current flowing through the switching transistor 14, that is, the current flowing through the primary winding W1, is referred to as a primary side current and is represented by the reference _{numeral "IP".}

The primary side control circuit 16 is provided with an output terminal TM1, a current sense terminal TM2, a feedback terminal TM3, a power supply terminal TM4, and a ground terminal TM5. The output terminal TM1 is connected to the gate of the switching transistor 14. Receive a current sense voltage _{V CS} of the above-mentioned by the current sense terminal TM2. The feedback terminal TM3 receives _{the feedback voltage VFB described later.} The feedback voltage V _FB corresponds to the voltage between both terminals of the feedback capacitor 18, one end of the capacitor 18 is connected to the feedback terminal TM3, and the other end of the capacitor 18 is connected to the ground GND1. Power terminal TM4 receives power supply voltage _{V CC} of the direct current supplied from the power generating circuit 17. The ground terminal TM5 is connected to the ground GND1 on the primary side. The primary side control circuit 16 is driven based on the _{power supply voltage VCC.}

The power supply generation circuit 17 generates a power supply voltage V _{CC based on the input voltage V IN} , and supplies the power supply voltage V _CC to the primary side control circuit 16. An auxiliary winding (not shown) may be provided on the primary side of the transformer TR. In this case, the power supply generation circuit 17 can be a circuit switching transistor 14 generates a power supply voltage V _CC by rectifying the induced voltage generated in the auxiliary winding when the driven switching. Alternatively, the power supply generation circuit 17, the input voltage _{V IN} may be a DC / DC converter for generating a supply voltage _{V CC} by converting DC / DC.

The primary side control circuit 16 switches and drives the transistor 14 by supplying a switching signal to the gate of the transistor 14 and controlling the gate voltage of the transistor 14. The switching signal is a rectangular wavy signal whose signal level switches between low level and high level. When a low level signal and a high level signal are supplied to the gate of the transistor 14, the transistor 14 is turned off and turned on, respectively.

The primary side control circuit 16 may be formed in the form of a power supply IC. Figure 2 shows a perspective view of an electronic component 1 _IC as a power supply IC. The electronic component 1 _IC includes a semiconductor chip in which a semiconductor integrated circuit constituting the primary side control circuit 16 is formed, a housing (package) for accommodating the semiconductor chip, and a plurality of ICs attached to the housing and exposed from the housing. It is an electronic component (semiconductor device) provided with an external terminal, and is formed by enclosing a semiconductor chip in a housing made of resin. The terminals TM1 to TM5 of FIG. 1 are included in the plurality of external terminals.

The secondary side circuit 20 will be described. The secondary side circuit 20 is provided with a rectifier diode 21, a smoothing capacitor 22, and a feedback circuit 23. Here, among the components of the AC / DC converter 1, the circuit arranged on the secondary side is referred to as the secondary side circuit 20. Therefore, although the load LD not included in the components of the AC / DC converter 1 is arranged on the secondary side, it does not belong to the secondary side circuit 20.

In the transformer TR, one end of the secondary winding W2 is connected to the anode of the rectifier diode 21, and the other end of the secondary winding W2 is connected to the ground GND2. The cathode of the rectifying diode 21 is connected to one end of the smoothing capacitor 22, and the other end of the smoothing capacitor 22 is connected to the ground GND2. Therefore, when the switching transistor 14 is on, a _{current based on the input voltage VIN} flows to the primary winding W1 to accumulate energy in the primary winding W1, and then the switching transistor 14 is turned off. The stored energy is output from the secondary winding W2 to the smoothing capacitor 22 through the rectifying diode 21. As a result, an output voltage V _OUT is generated between both ends of the smoothing capacitor 22. Across the smoothing capacitor 22 it is understood when connected to the corresponding or output terminal _{TM OUT} to the output terminal _{TM OUT} of the output voltage _{V OUT} is applied. The output voltage V _OUT is a positive DC voltage having a voltage value corresponding to the ratio of the input voltage V _IN to the number of turns of the primary winding W1 and the number of turns of the secondary winding W2. The output voltage V _OUT may pulsate slightly, but the pulsation is ignored here. Normally, the number of turns of the secondary winding W2 is smaller than the number of turns of the primary winding W1, so that the output voltage V _OUT is smaller than the input voltage V _IN (that is, the output voltage V _OUT is smaller than the input voltage V _IN) . Also has a low voltage value).

The load LD is _{an arbitrary load connected to the output terminal TM OUT} and driven based on the output voltage V _OUT , and is, for example, a microcomputer computer, a DSP (Digital Signal Processor), or a DC / DC converter. The current consumed by the load LD, that is, the current flowing between the smoothing capacitor 22 and the load LD in the direction of discharging the smoothing capacitor 22, is referred to as a load current or an output current, and is represented by the _{symbol "ILD".}

The feedback circuit 23 drives the light emitting element PCe of the photocoupler PC so that _{the output voltage V OUT} matches the predetermined target voltage V _TG. For example, the feedback circuit 23 supplies the light emitting element PCe with a current corresponding to an error between the _{output voltage V OUT} and the predetermined target voltage V _TG. The feedback circuit 23 is composed of a shunt regulator, an error amplifier, and the like. The target voltage V _TG is the target voltage of the output voltage V _OUT that the output voltage V _OUT should match.

_{A feedback current I FB} flows through the light receiving element PCr of the photocoupler PC. The magnitude of the feedback current I _FB increases as the magnitude of the current flowing through the light emitting element PCe increases, decreases by decreasing to. Receiving element PCr is provided between the feedback terminal TM3 and ground GND1, the feedback current _{I FB} flows toward the feedback terminal TM3 to ground GND1.

Here, although an example of generating an output voltage V _OUT at the diode rectification (asynchronous rectification type) and a flyback type, the AC / DC converter 1, the output voltage V _OUT at synchronous rectification It may be generated, or the output voltage V _OUT may be generated by a forward method.

With reference to FIG. 3, _{the relationship between the output voltage V OUT} and the load current _ILD and the feedback voltage V _FB will be described. In the primary side control circuit 16, a predetermined internal power supply voltage Vreg based is generating the power supply voltage V _CC. The internal power supply voltage Vreg is a positive DC voltage with reference to the ground GND1, and is, for example, 4V. The primary side control circuit 16 is provided with a _{feedback resistor R FB.} The internal power supply voltage Vreg is applied to one end of the feedback resistor _{R FB,} feedback terminal TM3 is connected to the other end of the feedback resistor _{R FB.}

Load current _{I LD} represents the magnitude of the load LD for the AC / DC converter 1, the magnitude of the load current _{I LD} larger the load LD is large, the magnitude of the load current _{I LD} smaller the load LD small. A large load LD is also expressed as a heavy load LD, and a small load LD is also expressed as a light load LD. Incidentally, the large / small of the load current I _LD is not a large / small of the instantaneous value of the load current I _LD, may be construed to refer to large / small of the mean value of the load current I _LD.

A series of operations in which the switching transistor 14 is turned on and then turned off is referred to as a unit switching operation. Power supplied from the AC / DC converter 1 to the load LD, the switching operation per unit time (i.e., repeatedly executed the number of unit switching operations per unit time), the peak of the primary-side current I _P of each unit switching operation It is determined by the current value (hereinafter, may be simply referred to as the peak current value I _PEAK).

When the magnitude of the load LD increases (that is, when the load current I _LD increases) starting from a certain state in which the output voltage V _OUT is stabilized by the target voltage V _TG , the output voltage V _OUT becomes the target voltage V. It goes down from _TG. In response to this, the feedback circuit 23 reduces (can be zero) the amount of current supplied to the light emitting element PCe. As a result, the feedback current I _FB decreases and the feedback voltage V _FB rises. At this time, as the load current I _LD increases, the amount of decrease in the _{feedback current I FB and} the amount of increase in the _{feedback voltage V FB increase.} However, _{the increase in the feedback voltage VFB} is limited to the internal power supply voltage Vreg.

When the feedback voltage _VFB rises, the primary side control circuit 16 executes switching control of the switching transistor 14 so that the average number of switching operations per unit time or the peak current value I _{PEAK in each unit switching operation increases.} To do. Thus, to stabilize the output voltage _{V OUT} against the increase in the load current _{I LD} with the target voltage _{V TG.}

On the contrary, when the magnitude of the load LD becomes smaller (that is, when the load current I _{LD decreases) starting from a certain state in which the output voltage V OUT} is stabilized at the target voltage V _TG , the output voltage V _OUT becomes higher. It goes in the direction of rising from the target voltage _VTG. In response to this, the feedback circuit 23 increases the amount of current supplied to the light emitting element PCe. As a result, the feedback current I _FB increases and the feedback voltage V _FB decreases. At this time, as the load current I _LD becomes smaller, the amount of increase in the _{feedback current I FB and} the amount of decrease in the _{feedback voltage V FB become larger.} However, _{the decrease in the feedback voltage VFB} is limited to the potential of the ground GND1.

When the feedback voltage V _FB decreases, the primary side control circuit 16 executes switching control of the switching transistor 14 so that the average number of switching operations per unit time or the peak current value I _{PEAK in each unit switching operation decreases.} To do. Thus, to stabilize the output voltage _{V OUT} against the decrease of the load current _{I LD} with the target voltage _{V TG.}

In this way, the feedback voltage V _FB becomes a voltage corresponding to the magnitude of the load LD. In the configuration according to the present embodiment, the load current _{I LD} is higher (the larger the average value of the load current _{I LD)} large feedback voltage _{V FB} is high, the load current as _{I LD} is small (average value of the load current _{I LD} (The smaller), the lower the _{feedback voltage VFB.}

The primary side control circuit 16 sets any of a plurality of modes to its own operation mode, and operates in the set operation mode. Here, it is assumed that the first to fifth modes are included in the plurality of modes. The primary side control circuit 16 sets any of the first to fifth modes as the operation mode based on the _{feedback voltage V FB.} FIG. 4 _{shows the relationship between the feedback voltage VFB} and the operation mode.

In the second to fourth modes, the PWM operation is executed by the primary side control circuit 16. In the PWM operation, the switching transistor 14 is periodically switched at the _{set switching frequency fSW.} That is, the switching frequency _fSW is the switching frequency of the switching transistor 14 at the time of executing the PWM operation (that is, the number of times the unit switching operation is repeatedly executed per second). Details will become apparent from the following description, in each unit switching operation in the PWM operation, after the switching transistor 14 is turned on, based on the primary-side current I value certain current value of _P (e.g., foot-back voltage V _FB When the current value or the current value based on the overcurrent detection voltage is reached, the switching transistor 14 is turned off. That is, the primary side control circuit 16 can perform switching control of the transistor 14 in the so-called PWM current mode.

Operation mode of the primary side control circuit 16, a predetermined voltage _{V A, V B, V C} , based on the relationship between _{V D} and _{V E} and the feedback voltage _{V FB, "V FB <V} A" first upon establishment of is set in the _{mode, "V a ≦ V FB <} V B" is set to the second mode when the establishment of, is set to the third mode when the establishment of _{"V B ≦ V FB <V} C", "V C ≦ V _{When FB} < _VE "is established, the fourth mode is set, and when" _VE ≤ V _FB "is established, the fifth mode is set. _{"0 <V A <V B} <V C <V D <V E" satisfied, where the voltage _{V A, V B, V C} , V D, V E , respectively, 0.40 V, 0. It is assumed that the voltage is 55V, 1.25V, 2.00V, and 2.80V (volt). The significance of the voltage V _D becomes clear from the explanation described later.

As described above, the PWM operation is executed in the second to fourth modes. Among them, the second mode is f fixed mode the switching frequency f _SW is fixed at a predetermined frequency f _L, in the fourth mode the switching frequency f _SW predetermined frequency f is higher than _L predetermined frequency f _H It is a fixed f fixed mode. Here, the frequencies f _{L and f H} are assumed to be 25 kHz and 100 kHz (kilohertz), respectively. The third mode is an f reduction mode in which the switching frequency f _{SW is lowered as the feedback voltage V FB is lowered.} Specifically, in the third mode, the switching frequency _{f SW} is linear manner is caused to drop to a frequency _{f L} from the frequency _{f H} as the feedback voltage _{V FB} falls from the voltage _{V C} to the voltage _{V B,} conversely, the switching frequency _{f SW} is brought into linearly increased to a frequency _{f H} from the frequency _{f L} as the feedback voltage _{V FB} rises from the voltage _{V B} to the voltage _{V C.}

When the PWM operation is executed, the switching frequency _fSW is reduced when the load LD is relatively light, so that the power conversion efficiency can be improved. The second mode may be deleted. In this case, it may be regarded as " _VA = V _B".

The fifth mode is an overload mode. In the fifth mode, if the _{"V E} ≦ V _FB" state is established continues for a predetermined time (e.g. 64 ms) or more, a primary side control circuit 16, determines that the AC / DC converter 1 is overloaded And perform overload protection operation. In the overload protection operation, the switching of the switching transistor 14 is stopped and the transistor 14 is maintained in the off state without performing the PWM operation or the burst operation described later. Incidentally, after shifting to hold state from the non-establishment state of _{"V E ≦ V FB""} V E ≦ V FB", until the overload protection operation is _performed, the PWM operation by the _"f SW = f _H" Will be executed. Since the fifth mode does not relate to the peculiar feature of the present invention, the existence of the fifth mode is ignored below, assuming that _{"V FB} <_{VE" is always established unless otherwise necessary.}

The first mode is a burst mode. _{When the feedback voltage V FB} drops from the state in which the PWM operation is performed and “V _FB < _VA ” is established, the transition to the burst mode occurs, and the burst operation is executed by the primary side control circuit 16. In the burst operation, _{the switching of the switching transistor 14 at the switching frequency fSW} is stopped, and the switching transistor 14 is switched in a non-periodic manner. The switching of the switching transistor 14 in the burst operation may have periodicity by chance, but the switching frequency of the switching transistor 14 at this time is lower than the _{frequency f L.} The details will be clarified from the explanation described later, _{but in the section where "V FB} < _VA " is established, the switching transistor 14 is kept in the off state, and the feedback voltage V _FB fluctuates in the vicinity of the _{voltage VA.} Burst operation will be realized with.

The burst operation will be described with reference to FIG. _{FIG. 5 shows the waveform of the feedback voltage VFB} and the state change of the switching transistor 14 when the burst operation is executed. The voltage V _BST1 is a predetermined burst determination voltage, and the voltage V _BST2 is a predetermined burst release voltage. The burst determination voltage V _BST1 corresponds to the voltage V _A in FIG. 4, which is 0.40 V here. The burst release voltage V _BST2 is higher than the burst determination voltage V _BST1 , and here, it is assumed to be 0.45V.

Consider the _{timing t 1 at which "V FB} <V _BST1 " is established because the load LD is light. Switching transistor 14 at the timing _{t 1} is in the OFF state. When the transistor 14 is kept in the off state, the feedback voltage V _FB increases as the _{output voltage V OUT decreases.} Then, when the feedback voltage V _FB exceeds the burst release voltage V _{BST 2} at the timing t 2, the transistor 14 is turned on by the primary side control circuit 16 as a trigger. In the burst operation, the transistor 14 after being turned on, when the value of the primary current I _P at a timing t ₃ reaches the turn-off threshold value I _OFF, the switching transistor 14 is turned off.

In the example of FIG. 5, the feedback voltage V _FB at a dose of switching transistor 14 is below the burst determination voltage V _BST1 again, thereafter, the same operation as the operation between the timings t _{1 ~} t ₃ is repeated in the burst operation Is done. After the feedback voltage _{V FB} at a timing _{t 2} exceeds the burst release voltage _{V BST2,} sometimes the feedback voltage _{V FB} at a dose of switching transistor 14 does not fall below a burst determination voltage _{V BST1,} in this case The turn-on of the transistor 14 is repeated at the _{frequency f L} until the feedback voltage V _FB falls below the burst determination voltage V _BST1. If the feedback voltage V _FB stably exceeds the burst determination voltage V _{BST1 due} to the heavy load LD, the operation executed by the primary side control circuit 16 shifts from the burst operation to the PWM operation.

Here, with reference to FIGS. 6 (a) to 6 (c), a burst operation when it is assumed that a turn-off threshold value I _{OFF [const] having a fixed value is used as the above-mentioned turn-off threshold value I OFF will be considered.} The solid line waveform 610 in FIG. 6 (a), the broken line waveform 620 in FIG. 6 (b), respectively, first, shows the waveform of the primary-side current _{I P} in the second virtual situation. The first virtual situation is _{a situation in which a burst operation is executed when “I OFF} = I _OFF [const]” and “V _IN = V _INL ”, and the second virtual situation is a situation in which “I _OFF = I _OFF [const]”. ] ”And“ V _IN = V _INH ”, the burst operation is executed. Here, voltage _{V INL} is the first example of the input voltage _{V IN} is lower than the voltage _{V INH} is a second example of the input voltage _{V IN.} For example, the voltage _{V INL, V INH,} respectively, the effective value of the AC voltage _{V AC} in FIG. 1 corresponds to the input voltage _{V IN} when 100 V, is 240V. First, the primary-side current _{I P} in the second virtual status, respectively, the code _{"I P [V INL]"} , are referred to by _{"I P [V INH]"} . In FIG. 6 (c), and the primary-side current _I P primary current shown in the waveform 610 and FIG. 6 (b) of _{[V INL] I P [V} INH] waveforms 620 shown in FIG. 6 (a) It is shown superimposed. However, for convenience of illustration, in FIG. 6C, the waveforms 610 and 620 are slightly shifted vertically from each other.

In any of the first and second virtual situation, after the switching transistor 14 is turned on in a burst operation, the value of the primary-side current _{I P} (here _{the I} OFF [const]) off threshold _{I OFF} reached The switching transistor 14 is turned off as an opportunity. However, the timing has been reached _(I OFF [const] in this case) the value of the primary current _{I P} is turned off threshold _{I OFF,} after _{the t DLY} has predetermined delay time has elapsed, the switching transistor 14 is actually turned off. The delay time t _DLY is based on the signal delay in the primary side control circuit 16 and the charge / discharge time of the gate capacitance of the switching transistor 14.

The delay time t _DLY is constant regardless of the magnitude of the input voltage _VIN. However, the variation of the primary current _{I P} with respect to the delay time _{t DLY} is dependent on the magnitude of the input voltage _{V IN.} The amount of change per unit time of the primary-side current I _P when switching transistor 14 is on, is proportional to the inverse proportion and the input voltage V _IN to the inductance value of the primary winding W1. Result, the peak current value _{I P1} is the peak current value _{I PEAK} of the primary-side current _{I P} in the first virtual situation, the peak current value is the peak current value _{I PEAK} of the primary-side current _{I P} in the second virtual situation _{I P2} When compared with, it becomes " _IP1 <_IP2".

Then, if "I _OFF = I _OFF [const]", as shown in FIG. 7, the burst boundary power _BPST depends on the magnitude of the input voltage V _IN (in other words, the magnitude of the _{AC voltage V AC).} Will change (according to). Burst boundary power _PBST refers to the power that is the boundary between the burst operation and the PWM operation. That is, the electric power supplied from the AC / DC converter 1 to the load LD (i.e. the product of the output voltage _{V OUT} and load current _{I LD)} is, PWM operation is executed is larger than the burst boundary power _{P BST,} a burst boundary power P If it is smaller than _{BST, burst operation is executed.}

The burst operation reduces the power consumption of the AC / DC converter 1 at the time of a light load, but it is not desirable that the burst operation is performed or not performed depending on the _{input voltage VIN, which is related to the burst operation.} It hinders power design optimization.

In consideration of this, in the primary side control circuit 16, after the switching transistor 14 is turned on, _{compensation for gradually increasing the turn-off threshold value I OFF} (hereinafter referred to as upslope compensation) is performed.

8, the solid line waveform 630, the dashed line waveform 640, respectively, first, shows the waveform of the primary-side current _{I P} in the second real situation. The first actual situation is a situation in which upslope compensation is applied to the _{turn-off threshold value I OFF and a burst operation is executed when "V IN} = V _INL ", and the second actual situation is an up slope to the _{turn-off threshold value I OFF.} This is a situation in which a burst operation is executed when compensation is applied and “V _IN = V _INH”. For convenience of illustration, in FIG. 8, the waveforms 630 and 640 are slightly shifted vertically from each other.

In any of the first and second actual status, after the switching transistor 14 is turned on in a burst operation, the switching transistor 14 is turned off in response to the value of the primary-side current I _P reaches the turn-off threshold value I _OFF .. However, the timing at which the value of the primary-side current I _P reaches the turn-off threshold value I _OFF, after the t _DLY has predetermined delay time has elapsed, the switching transistor 14 is actually turned off.

In the first and second actual situations, the turn-off threshold value I _OFF gradually increases after the switching transistor 14 is turned on. Therefore, the peak current value _{I P1} 'is the peak current value _{I PEAK} of the primary-side current _{I P} in the first real situation, the peak current value is the peak current value _{I PEAK} of the primary-side current _{I P} in the second real situation 'when compared with the magnitude of their difference _{| I P1' I P2 -I P2} '| , the magnitude of the difference corresponding to the virtual status of the above _| I P1 _{-I P2 |} is smaller than. _{Ideally, | I P1 '-I P2'} | is to be zero (the up-slope compensation make it so designed). In all _{circumstances, | I P1 '-I P2'} | While some cases difficult to _{zero, | I P1 '-I P2'} | such approaches as much as possible to zero up slope compensation is designed.

FIG. 9 shows the relationship _{between the input voltage VIN} and the burst boundary power _PBS T when the upslope compensation is applied to the turn-off threshold value I _OFF. The use of up-slope compensation, decrease dependency on the input voltage V _IN at the burst boundary power P _BST, it is possible to substantially constant independently of the burst boundary power P _BST to the input voltage V _IN .. As a result, it becomes easy to optimize the power design related to the burst operation of the device including the AC / DC converter 1.

FIG. 10 shows a schematic internal block diagram of the primary side control circuit 16. The primary side control circuit 16 includes a main control unit 100 having a set signal generation unit 110, a reset signal generation unit 120, and a drive unit 130, and a current detection unit 140. Current detecting unit 140 detects the primary-side current I _{P (target} current) flowing through the switching transistor 14 with a current sensing resistor 15, and generates and outputs a current detection signal S _CS indicating the detection result. Specifically, the current detection unit 140 is given _{a voltage drop (that is, a current sense voltage VCS} ) that occurs in the current sense resistor 15 with reference to the ground GND1. Current detecting section 140 is configured to include amplifiers and filters, etc., to generate and output a voltage signal having a voltage value k times the current sense voltage V _CS as a current detection signal S _CS. Here, k is any positive real number.

The current detection signal _SCS is given to the main control unit 100. Further, the feedback voltage _VFB is also given to the main control unit 100. The main control unit 100 supplies a switching signal to the gate of the switching transistor 14 based on _{the feedback voltage V FB} and the current detection signal S _CS (thus, based on the feedback voltage V _FB and the current sense voltage V _{CS), and the transistor 14} The gate voltage is controlled, thereby switching and driving the transistor 14. The signal supplied to the gate of the transistor 14 may be referred to as a gate signal.

The set signal generation unit 110 generates a signal SET. The reset signal generation unit 120 generates the signal RST. The signals SET and RST are supplied to the drive unit 130. Each of the signal SET and RST is a binarized signal that takes either a low level or a high level signal level. The high-level signal SET functions as a set signal instructing the turn-on of the switching transistor 14, and the low-level signal SET does not function as a set signal (invalid). The high-level signal RST functions as a reset signal instructing the turn-off of the switching transistor 14, and the low-level signal RST does not function as a reset signal (invalid).

When the drive unit 130 receives the set signal (that is, when it receives the high-level signal SET), the drive unit 130 sends a signal for turning on the switching transistor 14 (that is, a high-level gate signal) to the gate of the switching transistor 14. Supply. When the drive unit 130 receives the reset signal (that is, when it receives the high-level signal RST), the drive unit 130 sends a signal for turning off the switching transistor 14 (that is, a low-level gate signal) to the gate of the switching transistor 14. Supply.

The main control unit 100, based on the feedback voltage _{V FB,} PWM operation for switching at a switching frequency _{f SW} that is set to the switching transistor 14, or to perform a burst operation. In the burst operation, as described above, the switching of the transistor 14 at the _{switching frequency fSW is stopped.}

In the burst operation, the set signal generator 110 generates a set signal _{based on the feedback voltage V FB} (see FIG. 5; generates a set signal in response to _{"V FB} > V _{BST2"), and then resets.} signal generating unit 120 generates a reset signal in response to the value of the current detection signal S reference to _CS and the primary-side current I _P exceeds the turn-off threshold I _OFF. Here, the above-mentioned upslope compensation is applied to the turn-off threshold value I _OFF.

FIG. 11 shows a detailed configuration example of the main control unit 100.

The set signal generation unit 110 will be described. In the configuration example of FIG. 11, the set signal generation unit 110 includes a comparator 111 and an oscillator 112. The comparator 111 is a comparator with hysteresis, and generates an _{enable signal EN OSC} for the oscillator 112 based on the feedback signal S _{FB2 corresponding to the feedback voltage V FB.} Here, it is assumed that the feedback signal S _FB2 is a voltage signal having a voltage value that is 1/2 times the feedback voltage V _FB. The comparator 111, a feedback signal _{S FB2} compared voltage _(V FB / 2) and a voltage _{(V BST1} / 2) or voltage _{(V BST2} / 2) by the signal enable signal EN indicating their magnitude relationship Output as _OSC. The enable signal EN _OSC is a binarized signal that takes either a low level or a high level signal level.

In the comparator 111, the comparison between the voltage (V _FB / 2) and the voltage (V _BST1 / 2) or the voltage (V _BST2 / 2) is made with the feedback voltage V _FB and the burst determination voltage V _BST1 or the burst release voltage V _BST2 . Is equivalent to the comparison of. Therefore, the operation of the comparator 111 will be described by paying attention to the magnitude relationship between the voltage V _FB and the voltage V _BST1 or V _BST2. 12, the voltage _{V FB,} and _{V BST1} and _{V BST2,} (described later signal _{OUT VCO} shown in FIG. 12) showing the relationship between the various signals, including an enable signal _{EN OSC.}

Immediately after the primary side control circuit 16 is started, the feedback voltage V _FB is sufficiently higher than the burst determination voltage V _BST1 and the burst release voltage V _{BST2 according} to a predetermined start sequence, and at this time, the enable which is the output signal of the comparator 111. The signal EN _OSC is at a high level.

As shown in FIG. 12, when the output signal (EN _OSC ) of the comparator 111 is at a high level, in the comparator 111, the feedback voltage V _FB and the burst determination voltage V _BST1 are compared, and “V _FB > V _BST1 ”. The enable signal EN _OSC is maintained at a high level when is established, while the enable signal EN _OSC is switched from a high level to a low level _{when "V FB} <V _{BEST1" is established.} When the output signal of the comparator 111 is high level and “V _FB = V _BST1 ”, the enable signal EN _OSC is either high level or low level.

As shown in FIG. 12, when the output signal (EN _OSC ) of the comparator 111 is low level, the comparator 111 compares the feedback voltage V _FB and the burst release voltage V _BST2, and “V _FB <V _BST2 ”. The enable signal EN _OSC is maintained at the low level when is established, while the enable signal EN _OSC is switched from the low level to the high level _{when “V FB} > V _{BEST2” is established.} When the output signal of the comparator 111 is low level and “V _FB = V _BST2 ”, the enable signal EN _OSC is either high level or low level.

The oscillator 112 generates a square wave signal having a frequency corresponding to _{the feedback voltage VFB,} and outputs the generated square wave signal as a signal SET only when _{the enable signal EN OSC is at a high level.} If the enable signal EN _OSC is low level, the signal SET is maintained at low level.

FIG. 13 shows a functional block diagram of the oscillator 112. Also referring to FIG. 12, the oscillator 112 has a voltage controlled oscillator 112a that continuously generates and outputs a square wave signal OUT _VCO having a frequency f _{VCO corresponding to the feedback voltage V FB , and an enable signal EN OSC} at a high level. Only when this is the case, it can be considered that the switch unit 112b outputs the _{rectangular wave signal OUT VCO} output from the voltage controlled oscillator 112a to the outside of the oscillator 112 as a signal SET. When the enable signal EN _OSC is low level, the signal SET shall be fixed at low level.

FIG. 14 shows the relationship between the _{feedback voltage V FB} and the frequency f _VCO. The frequency f _VCO has an upper limit and a lower limit. The upper limit of the frequency f _VCO is the above-mentioned frequency f _H , and _{the lower limit of the frequency f VCO} is the above-mentioned frequency f _L (see FIG. 4). When the PWM operation is performed, the frequency f _VCO becomes the above-mentioned switching frequency f _SW . Frequency _{f VCO} during establishment of _{"V FB} ≦ _{V B"} is fixed at a frequency _{f L,} the frequency _{f VCO} during establishment of _{"V C} ≦ _{V FB"} is fixed at the frequency _{f H.} During establishment of _{"V B} ≦ _{V FB} ≦ _{V C",} the frequency _{f VCO} as the feedback voltage _{V FB} rises from the voltage _{V B} to the voltage _{V C} is linearly be increased to a frequency _{f H} from the frequency _{f L.}

In the rectangular wave signal OUT _VCO , pulses having a high signal level for a short time are repeatedly generated at the _{frequency f VCO.} Therefore, when the enable signal EN _OSC is at a high level, the up edge will repeatedly occur at the _{frequency f VCO in the signal SET.}

The reset signal generation unit 120 will be described with reference to FIG. 11 again. In the configuration example of FIG. 11, the reset signal generation unit 120 includes slope compensation signal generation units 121 and 124, adders 122 and 125, comparators 123 and 126, and an OR circuit 127.

The slope compensation signal generation unit 121 _{generates and outputs the slope compensation signal S SLPA} , and the slope compensation signal generation unit 124 generates and outputs the _{slope compensation signal S SLPB. Each of the} slope compensation signals S SLPA and S _SLPB is a voltage signal whose signal value changes with the passage of time. For any voltage signal, the signal value of the voltage signal corresponds to the voltage value of the voltage signal. In each of the slope compensation signals S _SLPA and S _SLPB , the change in signal value has periodicity, and the reciprocal of the period coincides with the _{frequency f VCO.}

The feedback signal S _FB1 corresponding to the feedback voltage V _{FB and the slope compensation signal S SLPA} from the slope compensation signal generation unit 121 are input to the adder 122. Here, it is assumed that the feedback signal S _FB1 is a voltage signal having a voltage value that is 1/4 times the feedback voltage V _FB. The adder 122 adds the slope compensation signal S _{SLPA to the feedback signal S FB 1,} and outputs a voltage signal based on the addition result as a turn-off threshold signal S _OFFA . The signal value (that is, voltage value) of the turn-off threshold signal S _{OFFA is the signal value of the feedback signal S FB1} (that is, the voltage value; here V _FB / 4) and _{the signal value of the slope compensation signal S SLPA} (that is, the voltage value). It becomes the sum of. The turn-off threshold signal S _OFFA represents the above-mentioned turn-off threshold I _OFF in the form of a voltage signal, and the turn- _{off threshold I OFF} is indicated by the turn-off threshold _{signal S OFFA.}

In comparator 123, the turn-off threshold signal S _OFFA to the inverting input terminal is input, the non-inverting input terminal a current detection signal S _CS inputted. As it will be understood from reference to the description of FIG. 10 or the like, the current detection signal S _CS is a voltage signal that indicates the value of the primary-side current I _P.

Establishment of _{"S CS> S OFFA"} is equivalent to the establishment of _{"I P>} I _OFF", the establishment of _{"S CS <S OFFA"} is equivalent to the establishment of _{"I P <I OFF".} In the comparator 123, when "S _CS > S _OFFA " is established, that is, _{the signal value (voltage value) of the current detection signal S CS} is larger than the signal value (voltage value) of the turn-off threshold signal S _OFFA. When it outputs a high level signal, when it does not, it outputs a low level signal. However, when "S _CS = S _OFFA " is established, the output signal of the comparator 123 may be at a high level.

A voltage signal S _LIM indicating a predetermined overcurrent detection voltage V _{LIM and a slope compensation signal S SLPB} from the slope compensation signal generation unit 124 are input to the adder 125. The overcurrent detection voltage _VLIM has a fixed voltage value. However, when the soft start operation is executed when the primary side control circuit 16 is started, the overcurrent detection voltage _VLIM may be set to be smaller than the fixed voltage value. The adder 125 adds the slope compensation signal S _SLPB to the voltage signal S _{LIM indicating the overcurrent detection voltage V LIM,} and outputs the voltage signal based on the addition result as the overcurrent threshold signal S _OFFB . The signal value of the overcurrent threshold signal _{S OFFB} (i.e. voltage value), the signal value of the voltage signal _{S LIM} (i.e. the voltage value; _{V LIM} here) and the signal value of the slope compensation signal _{S SLPB} (ie voltage value) It becomes the sum of. Signal _{S OFFB} overcurrent threshold is a representation of the over-current threshold _{I LIM} to the primary-side current _{I P} in the form of a voltage signal, the signal for overcurrent threshold _{S OFFB} Therefore overcurrent threshold _{I LIM} is pointed.

The comparator 126, to the inverting input terminal is input overcurrent threshold signal S _OFFB, to the non-inverting input terminal a current detection signal S _CS inputted.

Establishment of _{"S CS> S OFFB"} is equivalent to the establishment of _{"I P>} I _LIM", the establishment of _{"S CS <S OFFB"} is equivalent to the establishment of _{"I P <I LIM".} In the comparator 126, when "S _CS > S _OFFB " is established, that is, _{the signal value (voltage value) of the current detection signal S CS} is larger than the signal value (voltage value) of the overcurrent threshold signal S _OFFB. When it is large, it outputs a high-level signal, and when it is not, it outputs a low-level signal. However, when "S _CS = S _OFFB " is established, the output signal of the comparator 126 may be at a high level.

The OR circuit 127 outputs the OR signal of the output signals of the comparators 123 and 126 as a signal RST. Therefore, the signal RST is low level only when both the output signal of the comparator 123 and the output signal of the comparator 126 are low level, and the signal RST is high level when at least one of them is high level. ..

Therefore, it is reset by any block of the first block including the slope compensation signal generator 121, the adder 122 and the comparator 123, and the second block consisting of the slope compensation signal generator 124, the adder 125 and the comparator 126. A signal (ie, a high level signal RST) will be generated. As will be explained later, the function of generating the reset signal _{is carried out by the first block in "V FB} <V _D " and by the second block in "V _D ≤ V _FB " (with _{respect to the voltage V D} , FIG. 4). reference).

FIG. 15 shows the relationship between _{the signals OUT VCO} , SET, S _SLPA and S _SLPB. In FIG. 15, since _{it is assumed that the signal EN OSC} is maintained at a high level, the signal OUT _VCO and the signal SET match.

The slope compensation signals S _SLPA and S _SLPB each have predetermined initial signal values INI _A and INI _B at the timing when the up edge of the signal OUT _{VCO occurs.} The initial signal values INI _A and INI _B are zero, but may be non-zero.

The section from the timing at which the up edge occurs at the signal OUT _VCO to the occurrence of the next up edge is referred to as a unit interval. The length of one unit interval coincides with the reciprocal of the frequency f _{VCO of the signal OUT VCO.} Each unit interval consists of a front section P1 and a rear section P2. In each unit interval, the pre-stage section P1 may be started at the same time as the start of the unit section, and the post-stage section P2 may be started at the same time as the end of the pre-stage section P1.

In each unit section, in the pre-stage section P1, the signal value (that is, the voltage value) of _{the slope compensation signal S SLPA increases with the passage of time starting from the initial signal value INI A,} and the slope at the end timing of the pre-stage section P1. The signal value of the compensation signal _SLPA has a predetermined signal value TOP _A. Naturally, "INI _A <TOP _A ". In each unit section, in the latter section P2, the signal value (that is, the voltage value) of _{the slope compensation signal S SLPA decreases with the passage of time starting from the signal value TOP A,} and the slope compensation is performed at the end timing of the latter section P2. The signal value of the signal S _SLPA has a predetermined signal value BTM _A. In the example of FIG. 15, "BTM _A <INI _A " is set, but it may be "BTM _A = INI _A " or "BTM _A > INI _A ".

In each unit section, in the pre-stage section P1, the signal value (that is, the voltage value) of _{the slope compensation signal S SLPB increases with the passage of time starting from the initial signal value INI B,} and the slope at the end timing of the pre-stage section P1. The signal value of the compensation signal S _SLPB has a predetermined signal value TOP _B. Naturally, "INI _B <TOP _B ". In each unit section, in the latter section P2, the signal value (that is, the voltage value) of _{the slope compensation signal S SLPB decreases with the passage of time starting from the signal value TOP B,} and the slope compensation is performed at the end timing of the latter section P2. The signal value of the signal S _SLPB has a predetermined signal value BTM _B. In the example of FIG. 15, "BTM _B <INI _B " is set, but "BTM _B = INI _B " or "BTM _B > INI _B " may be used.

The above-mentioned upslope compensation is realized in the preceding section P1. The decrease in the signal values of the slope compensation signals S _SLPA and S _SLPB in the latter section P2 is referred to as down slope compensation. Down slope compensation (generally also referred to as AC slope compensation) is introduced for the purpose of preventing subharmonic oscillation. Since the principle of preventing subharmonic oscillation by downslope compensation is known, the description thereof will be omitted.

In each unit interval, the start timing of the latter section P2 is set to be the timing after the start timing of the unit interval by the time “q · 1 / f _VCO”. “1 / f _VCO ” corresponds to the length of each unit interval. The coefficient q has a value greater than 0 and less than 1. In order to effectively prevent subharmonic oscillation, it is preferable to give the coefficient q a value of 0.5 or less, for example, “0.35 <q <0.49”.

In the example of FIG. 15, each unit section is formed only from the front section P1 and the rear section P2, but in each unit section, the slope is formed after the end of the front section P1 and before the start of the rear section P2. There may be a finite interval in which the signal values of the compensation signals S _SLPA and S _{SLPB are fixed by the signal values TOP A} and TOP _B , respectively, and the next unit interval is started after the end of the latter section P2. Before this, there may be a finite interval in which the signal values of the slope compensation signals S _SLPA and S _{SLPB are fixed by the signal values BTM A} and BTM _{B, respectively.}

Further, in the example of FIG. 15, although the enable signal _{EN OSC} is assumed that it is maintained at a high level, the signal _OUT VCO when the enable signal _{EN OSC} is at a low _level, the relationship of _{S SLPA} and _{S SLPB} May be the same as described above. However, when the enable signal EN _OSC is at a low level, _{the changes in the signals S SLPA} and S _SLPB have no meaning, so that _{the signal values of the signals S SLPA} and S _SLPB may be fixed to zero.

Here, it is assumed that the slope compensation signals S _SLPA and S _SLPB are the same signals. When the slope compensation signal S _SLPA and S _SLPB are the same signal, the slope compensation signal generation unit 124 is deleted, and the slope compensation signal S _SLPA generated by the slope compensation signal generation unit 121 is sent to the adder 122. At the same time, it may be input to the adder 125 as a slope compensation signal S _SLPB . However, the slope compensation signals S _SLPA and S _SLPB may be different signals from each other.

The drive unit 130 will be described with reference to FIG. 11 again. In the configuration example of FIG. 11, the drive unit 130 includes an RS-type flip-flop 131 (hereinafter referred to as FF131) and a driver 132.

The FF131 includes a set input terminal (S), a reset input terminal (R), and an output terminal (Q). In the FF131, the signal SET is input to the set input terminal, the signal RST is input to the reset input terminal, and the signal DRV is output from the output terminal. As shown in FIG. 16, the FF131 outputs a high-level signal DRV from the output terminal if the signal SET is at a high level, and thereafter maintains a high level of the output signal DRV until the signal RST becomes a high level. If the signal RST is high level, the FF131 outputs a low level signal DRV from the output terminal, and thereafter maintains the low level of the output signal DRV until the signal SET becomes high level. In the main control unit 100, the signal SET and the RST do not become high levels at the same time (the high level pulse width of the signal SET is set sufficiently short so as to do so).

The driver 132 is connected to the gate of the switching transistor 14 via the output terminal TM1 (see FIG. 1) of the primary side control circuit 16 and controls the gate voltage of the switching transistor 14 based on the output signal DRV of the FF131. If the output signal DRV is high level, the driver 132 turns on the transistor 14 by raising the gate voltage of the transistor 14 to a high level, and if the output signal DRV is low level, the driver 132 lowers the gate voltage of the transistor 14. By setting the level, the transistor 14 is turned off. However, there is a delay before the transistor 14 actually switches to the on state in response to the up edge of the output signal DRV of the FF131, and the transistor 14 actually turns off in response to the down edge of the output signal DRV of the FF131. There is a delay before switching to.

The burst operation will be described with respect to the configuration example of FIG. _"V FB _{<V D"} in the establishment of a _"S OFFA _{<S OFFB"} that holds overcurrent detection voltage _{V LIM} is set (with respect to the voltage _{V D,} see FIG. 4). Thus, in a burst operation, (in response to that or primary-side current I _P is above the turn-off threshold value I _OFF) current detection signal S _CS signal value in response to exceed the signal value of the signal S _OFFA off threshold, A reset signal (high level signal RST) is generated. When the burst operation is performed, since the Fordback voltage _VFB is sufficiently small, the reset signal generation timing always belongs to the preceding section P1, and the upslope compensation functions effectively, as shown in FIGS. 8 and 9. The same effect can be obtained.

Next, the PWM operation under the establishment of _{"V FB} <V _{D" will be described.} As described _{above, "V} FB <V _D" in the establishment of a _"S OFFA _{<S OFFB"} that holds overcurrent detection voltage _{V LIM} is set. Therefore, in the PWM operation under the establishment of _{"V FB} <V _{D ", as in the burst operation, the signal value of the current detection signal S CS} exceeds the signal value of the turn-off threshold signal S _OFFA (that is, the primary). triggered by the side current _{I P} is above the turn-off threshold value _{I OFF),} the reset signal (high level signal RST) is generated. If the generation timing of this reset signal belongs to the preceding section P1, the upslope compensation functions effectively. On the other hand, suppression of sub-harmonic oscillation is also important, and if the reset signal generation timing belongs to the latter section P2, the effect of suppressing sub-harmonic oscillation by downslope compensation can be obtained.

If the _{feedback voltage V FB} is relatively low when the PWM operation is performed under the establishment of _{"V FB} <V _D ", the reset signal is predominantly generated in the preceding section P1 and the upslope compensation is performed. Easy to function effectively. If the _{feedback voltage V FB} is relatively high when the PWM operation is performed while _{“V FB} <V _D ” is established, the reset signal is predominantly generated in the subsequent section P2, and the downslope compensation is achieved. Easy to function effectively.

Next, the PWM operation under the establishment of _{“V D} <V _{FB” will be described.} Under the establishment of "V _D <V _FB ", the overcurrent detection voltage V _LIM is set _{so that "S OFFA} > S _{OFFB" is established. Thus, "V} D _{<V FB"} in the PWM operation in establishment of a current detection signal _{S CS} signal value overcurrent threshold signal _S signal values _OFFB triggered by exceeding (or primary-side current _{I P Triggered} to exceed the overcurrent threshold ILIM), a reset signal (high level signal RST) is generated. If the generation timing of this reset signal belongs to the preceding section P1, the upslope compensation functions effectively. On the other hand, suppression of sub-harmonic oscillation is also important, and if the reset signal generation timing belongs to the latter section P2, the effect of suppressing sub-harmonic oscillation by downslope compensation can be obtained.

Among the fourth modes (see FIG. 4), the mode in which "V _D <V _FB " is established is particularly referred to as the current limit mode. In current limit mode, so that the reset signal is generated when the primary-side current I _P reaches the over-current threshold I _LIM. If the upslope compensation is not applied to _{the overcurrent detection voltage VLIM} in the current limit mode, the maximum power on the secondary side depends on the magnitude of the _{input voltage VIN due to the influence of the delay time t DLY described above.} It will change. In the configuration of FIG. 11, in the current limit mode, upslope compensation is applied by using the slope compensation signal generator 124 and the adder 125, so that the maximum power on the secondary side depends on the _{input voltage VIN.} Change is suppressed.

17 shows the waveforms 661-665 of currents to be compared with the primary current I _P to generate a reset signal. Waveform 661 is a current waveform to be compared with the primary-side current I _P (waveform current having a turn-off threshold value I _OFF) in the burst operation. Waveform 662 is a current waveform to be compared with the primary-side current _{I P} in the PWM operation in the second mode (the waveform of current having a turn-off threshold value _{I OFF).} Waveform 663 is a current waveform to be compared with the primary-side current _{I P} in the PWM operation in the third mode (waveform current having a turn-off threshold value _{I OFF).} Waveform 664 is the fourth mode and _"V FB <V _D" in the primary-side current _{I P} Contrast electrical current waveform in the PWM mode (the waveform of current having a turn-off threshold value _{I OFF).} Waveform 665 is a current waveform to be compared with the primary-side current I _P in the current limit mode (the waveform of the current with the overcurrent threshold value I _LIM).

Since the upslope compensation is executed not only when the burst operation is performed but also when the PWM operation is performed, the secondary side power P _OUT (= V _OUT × I _LD ) is the input voltage V _{IN in the PWM operation.} It becomes unaffected or less susceptible to the fluctuation of (however, when the reset signal is generated in the first half section P1). That is, the effect shown in FIG. 9 can be obtained even when the PWM operation is executed.

As a result, when the PWM operation is performed, as shown in FIG. 18, the relationship between the _{secondary power P OUT} and the switching frequency f _SW can be made invariant with respect to the change of the _{input voltage VIN.} As a result, _{circuit design can be performed without worrying about fluctuations in the input voltage V IN} , and simplification of the design is expected (when there is no upslope compensation, for example, "V _IN = V _INL". It is necessary to design the circuit in consideration of both the case of "" and the case of "V _IN = V _INH"). In FIG. 18, the solid line polygonal line 681 shows the relationship between the secondary power P _OUT and the switching frequency f _{SW when “V IN} = V _INL ”, and the broken line polygonal line 682 shows the relationship between “V _IN = V _INH ”. The relationship between the secondary side power P _OUT and the switching frequency f _{SW is shown.} For convenience of illustration, the polygonal lines 681 and 682 are shown slightly offset from each other in FIG. 18, but ideally the polygonal lines 681 and 682 completely overlap.

As can be understood from the above description, the set signal generation unit 110 uses the oscillator 112 to generate a set signal at a _{predetermined frequency f VCO} (corresponding to the switching frequency f _{SW) in the PWM operation.} Reset signal generating unit 120, the PWM operation, and the current detection signal _{S CS,} and the turn-off threshold signal _{S OFFA} indicating the turn-off threshold value _{I OFF,} and overcurrent threshold signal _{S OFFB} indicating the overcurrent threshold _{I LIM,} the Based on this, a reset signal is generated.

More specifically, in the PWM operation, the comparison result of the comparator 123 comparing the _{current detection signal S CS} and the turn-off threshold signal S _{OFFA , and the current detection signal S CS} and the overcurrent threshold signal S _{OFF B} comparison result of the comparator 126 to be compared is referred to, based on their comparison result, when the value of the primary current I _P becomes larger than the turn-off threshold I _OFF or overcurrent threshold I _LIM, the reset signal is generated It will be. As described _{above, "S CS>} S _OFFA" establishment of means that the value of the primary-side current _{I P} is greater than the turn-off threshold value _{I OFF, "S CS> S} OFFB" established value of the primary current _{I P} of Indicates that is greater than the overcurrent threshold _ILIM.

In the predetermined section after the set signal is generated (corresponding to the _previous section P1), the slope compensation signal S SLPA whose signal value increases with the passage of time is added to the signal S _FB1 proportional to the feedback voltage V _FB for the turn-off threshold. The signal S _OFFA is generated, and the overcurrent threshold signal S _OFFB is generated by _{adding the slope compensation signal S SLPB} whose signal value increases with the passage of time to the signal S _{LIM having a predetermined value.} As a result, upslope compensation is realized. After the predetermined section, downslope compensation for the purpose of preventing subharmonic oscillation is applied.

<< Second Embodiment >>
A second embodiment of the present invention will be described. In the second embodiment, a modification technique, an applied technique, and the like with respect to the first embodiment will be described. The matters described in the second embodiment can be applied to the first embodiment.

The second embodiment includes the following examples EX2_1 to EX2_3. Unless otherwise specified and without contradiction, the above-mentioned matters in the first embodiment are applied to the following Examples EX2_1 to EX2_3, and in each embodiment, the matters inconsistent with the above-mentioned matters in the first embodiment The description in each embodiment may be prioritized. Further, as long as there is no contradiction, the matters described in any of the examples EX2_1 to EX2_3 can be applied to any other embodiment (that is, any two or more implementations in the plurality of examples). It is also possible to combine examples).

Prior to the description of Example EX2_1, the operation and configuration of the first embodiment will be supplemented. In the first embodiment, a configuration is adopted in which the _{feedback voltage VFB} decreases as the magnitude of the load LD decreases. Therefore, the main control unit 100 according to the first embodiment, when the feedback voltage _{V FB} is kept higher than the predetermined burst determination voltage _{V BST1,} continuously performs PWM operation, the feedback voltage _{V FB Starts} burst operation when the voltage falls below the burst determination voltage V BST1.

That is, the main control unit 100 according to the first embodiment starts the burst operation in response to the transition from the state where _{the feedback voltage V FB} is higher than the burst judgment voltage V _BST1 to the state where the feedback voltage V FB is lower than the burst judgment voltage V _{BST1 and bursts.} after starting the operation, as shown in FIG. 19, and maintains the switching transistor 14 off until the feedback voltage _{V FB} exceeds a predetermined burst release voltage _{V BST2,} the feedback voltage _{V FB} exceeds the burst release voltage _{V BST2} set to generate a set signal (high-level signal sET) by the signal generating unit 110, then the reset signal by the reset signal generating unit 120 receives the value of the primary-side current I _P exceeds the turn-off threshold value I _OFF (high level Signal RST) is generated. In the first embodiment, "V _BST2 > V _BST1 ".

In FIG. 19, it is assumed that the switching transistor 14 turns on at the same time as the set signal is generated (the delay time t _DLY is shown only for the turn-off). In the configuration of FIG. 11, the value of the primary current _{I P} is when it exceeds the turn-off threshold value _{I OFF,} so that the _{"S CS>} S _OFFA" is established reset signal (high level signal RST) is generated.

[Example EX2_1]
Example EX2_1 will be described. _{In the AC / DC converter 1, a configuration in which the feedback voltage VFB} increases as the magnitude of the load LD decreases may be adopted, and this configuration will be described as Example EX2_1.

_{In Example EX2_1, since the configuration in which the feedback voltage V FB} increases as the magnitude of the load LD decreases is adopted, the feedback voltage V _{FB of} the main control unit 100 is lower than the predetermined burst determination voltage V _BST1. When the state is maintained, the PWM operation is continuously executed, and when the feedback voltage V _FB exceeds the burst determination voltage V _BST1 , the burst operation is started.

That is, the main control unit 100 according to the embodiment EX2_1 starts the burst operation in response to the transition from the state where _{the feedback voltage V FB} is lower than the burst judgment voltage V _BST1 to the state where the feedback voltage V FB is higher than the burst judgment voltage V _BST1. after the start, as shown in FIG. 20, and maintains the switching transistor 14 off until the feedback voltage _{V FB} falls below a predetermined burst release voltage _{V BST2,} a set signal when the feedback voltage _{V FB} is below the burst release voltage _{V BST2} to generate a set signal (high-level signal sET) by generating unit 110, then the primary current I _P values by receiving that exceeds the turn-off threshold value I _OFF the reset signal generator 120 by the reset signal (high level Signal RST) is generated. In Example EX2_1, "V _BST2 <V _BST1 ".

In FIG. 20, it is assumed that the switching transistor 14 turns on at the same time as the set signal is generated (the delay time t _DLY is shown only for the turn-off). In the configuration of FIG. 11, the value of the primary current _{I P} is when it exceeds the turn-off threshold value _{I OFF,} so that the _{"S CS>} S _OFFA" is established reset signal (high level signal RST) is generated.

[Example EX2_2]
Example EX2_2 will be described. The AC / DC converter 1 of FIG. 1 is a kind of switching power supply device according to the present invention. In FIG. 1, the switching transistor 14 is an example of a switching element connected in series with the primary side winding W1 as an inductor, and the primary side control circuit 16 is an example of a switching control circuit for switching the switching element. It is possible to modify the switching element as a P-channel MOSFET, or as a bipolar transistor, junction FET or IGBT (Insulated Gate Bipolar Transistor). _{In any case, the input voltage V IN} is applied to the series circuit of the inductor and the switching element, and the output voltage V _OUT is generated at the _{output terminal TM OUT} by switching the switching element.

The feedback circuit 23, the photocoupler PC, and the feedback capacitor 18 form a feedback voltage generation circuit that generates a feedback voltage _{V FB} based on the _{output voltage V OUT.}

The power adapter may be configured by using the AC / DC converter 1. Alternatively, an electric device incorporating the AC / DC converter 1 may be configured. The type of electrical equipment is not particularly limited, and any equipment such as an audio equipment, a refrigerator, a washing machine, and a vacuum cleaner having an AC / DC converter 1 built-in is arbitrary.

The switching power supply device according to the present invention is not limited to an AC / DC converter, and is an isolated DC / DC converter _{that uses a transformer TR to generate an output voltage V OUT} on the secondary side in an isolated form from _{the input voltage V IN on the primary side.} It may be a non-isolated DC / DC converter that generates an output voltage V _OUT from an input voltage V _IN.

[Example EX2_3]
Example EX2_3 will be described. The relationship between high level and low level may be reversed for any signal or voltage without compromising the above-mentioned gist.

The embodiment of the present invention can be appropriately modified within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and the constituent requirements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1 AC / DC converter (switching power supply)
14 Switching transistor (switching element)
16 Primary side control circuit (switching control circuit)
100 Main control unit 110 Set signal generation unit 120 Reset signal generation unit 130 Drive unit 140 Current detection unit

Claims (13)

1. In a switching control circuit for generating an output voltage by switching the switching element from the input voltage applied to the series circuit of the inductor and the switching element, a current detector that detects the current flowing through the switching element as a target current. A control unit that executes a PWM operation or a burst operation for switching the switching element at a set switching frequency based on a feedback voltage according to the magnitude of a load supplied with the output voltage.
   When the control unit receives the set signal generation unit that generates a set signal instructing the turn-on of the switching element, the reset signal generation unit that generates the reset signal instructing the turn-off of the switching element, and the set signal. A drive unit that supplies a signal for turning on the switching element to the switching element and supplies a signal for turning off the switching element to the switching element when the reset signal is received. In the burst operation, the switching of the switching element at the switching frequency is stopped.
   In the burst operation, the set signal generating unit generates the set signal based on the feedback voltage, and then the reset signal generating unit generates the reset signal when the value of the target current exceeds the turn-off threshold value. Generate,
   The reset signal generation unit is a switching control circuit characterized in that the turn-off threshold value is increased with the passage of time in a predetermined section after the generation of the set signal.
2. The switching control circuit according to claim 1, wherein the turn-off threshold value has a value corresponding to the feedback voltage.
3. The reset signal generator is
   A turn-off threshold signal indicating the turn-off threshold is generated by adding a slope compensation signal whose signal value increases with the passage of time in the predetermined section to a signal proportional to the feedback voltage.
   The switching control circuit according to claim 1 or 2, wherein in the burst operation, the reset signal is generated by comparing the current detection signal indicating the value of the target current with the turn-off threshold signal.
4. The set signal generation unit has an oscillator that generates a signal of the switching frequency, and in the PWM operation, the set signal is generated at the switching frequency by using the oscillator.
   In the PWM operation, the reset signal generating unit generates the reset signal based on the current detection signal, the turn-off threshold signal, and the overcurrent threshold signal indicating a predetermined overcurrent threshold. The switching control circuit according to claim 3.
5. The reset signal generator includes a first comparator that compares the current detection signal with the turn-off threshold signal, and a second comparator that compares the current detection signal with the overcurrent threshold signal. In the PWM operation, the reset signal is generated when the value of the target current becomes larger than the turn-off threshold or the overcurrent threshold based on the comparison results of the first comparator and the second comparator. The switching control circuit according to claim 4.
6. The reset signal generation unit generates the turn-off threshold signal by adding a first slope compensation signal whose signal value increases with the passage of time in the predetermined section to a signal proportional to the feedback voltage, and also generates the predetermined signal. The switching control according to claim 4 or 5, wherein the overcurrent threshold signal is generated by adding a second slope compensation signal whose signal value increases with the passage of time in a section to a signal having a predetermined value. circuit.
7. As the magnitude of the load decreases, the feedback voltage decreases.
   The control unit continuously executes the PWM operation when the feedback voltage is kept higher than a predetermined burst determination voltage, and starts the burst operation when the feedback voltage falls below the burst determination voltage. The switching control circuit according to any one of claims 1 to 6, wherein the switching control circuit is characterized.
8. The control unit starts the burst operation in response to the transition from a state in which the feedback voltage is higher than the burst determination voltage to a state in which the feedback voltage is lower than the burst determination voltage. The switching element is kept in the off state until a predetermined burst release voltage higher than the burst determination voltage is exceeded, and when the feedback voltage exceeds the burst release voltage, the set signal generator generates the set signal, and then the set signal is generated. The switching control circuit according to claim 7, wherein the reset signal is generated by the reset signal generator in response to the value of the target current exceeding the turn-off threshold.
9. The feedback voltage rises as the magnitude of the load decreases,
   The control unit continuously executes the PWM operation when the feedback voltage is kept lower than a predetermined burst determination voltage, and starts the burst operation when the feedback voltage exceeds the burst determination voltage. The switching control circuit according to any one of claims 1 to 6, wherein the switching control circuit is characterized.
10. The control unit starts the burst operation in response to the transition from a state in which the feedback voltage is lower than the burst determination voltage to a state in which the feedback voltage is higher than the burst determination voltage. The switching element is kept in the off state until it falls below a predetermined burst release voltage lower than the burst determination voltage, and when the feedback voltage falls below the burst release voltage, the set signal generator generates the set signal, and then the set signal is generated. The switching control circuit according to claim 9, wherein the reset signal is generated by the reset signal generator in response to the value of the target current exceeding the turn-off threshold.
11. A claim, wherein a transformer having the inductor and a secondary winding is used as the primary winding, and the output voltage is generated on the secondary side from the input voltage applied to the primary side. The switching control circuit according to any one of 1 to 10.
12. In a switching power supply that uses a transformer with a primary winding and a secondary winding to generate an output voltage on the secondary side from an input voltage applied to the primary side by a switching method.
    A switching element connected in series with the primary winding as an inductor,
    The switching control circuit according to any one of claims 1 to 11.
    A switching power supply device including a feedback voltage generation circuit that generates the feedback voltage based on the output voltage.
13. The switching power supply device according to claim 12, wherein the input voltage is generated by rectifying and smoothing an AC voltage.

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