CN114600355A - Switch control circuit and switching power supply device - Google Patents

Abstract

A switching control circuit generates an output voltage by switching in accordance with an input voltage applied to a series circuit of an inductor and a switching element. The control unit executes a PWM operation or a burst operation based on a feedback voltage corresponding to the magnitude of the load. In the burst operation, the switching is stopped and the switching element is turned on in accordance with the feedback voltage instruction so that the current (I) flowing through the switching element flows_P) Exceeds a turn-off threshold (I)_OFF) When the command is received, the switching element is instructed to be turned off. In thatIn a predetermined section after the on instruction, the off threshold is increased with the passage of time.

Description

Switch control circuit and switching power supply device

Technical Field

The present invention relates to a switch control circuit and a switching power supply device.

Background

There is known a switching power supply device that generates an output voltage by switching a switching element in accordance with an input voltage applied to a series circuit of an inductance and the switching element. Typically, in an AC/DC converter using a transformer, for example, a switching element is connected in series with a primary winding as an inductor, a DC input voltage obtained by full-wave rectifying an AC voltage is applied to these series circuits, and the switching element is switched and driven, whereby an output voltage is obtained on the secondary side.

In such a switching power supply device, a PWM operation for switching the switching element at a switching frequency is generally performed by pulse width modulation. There is also a switching power supply device of a type that performs a burst operation for the purpose of reducing power consumption at the time of light load (see, for example, patent document 1 below). In the burst operation, switching is not performed based on the switching frequency, and switching of the switching element is performed only when necessary in a state where periodicity is not present.

Documents of the prior art

Patent document

Patent document 1: japanese Kokai publication No. 2008-541688

Disclosure of Invention

Problems to be solved by the invention

In a switching power supply device capable of switching between a PWM operation and a burst operation, the load size is monitored, and the PWM operation and the burst operation are switched and executed in accordance with a feedback voltage corresponding to the load size. At this time, there is a critical power (burst critical power) for switching between the PWM operation and the burst operation, but in the conventional switching power supply device, the critical power may vary depending on the magnitude of the input voltage.

That is, for example, when considered as an AC/DC converter, an effective value of an input AC voltage to the AC/DC converter may be 100V or 240V, and a DC input voltage applied to a series circuit of a primary winding and a switching element of a transformer varies in a variety of ways in conjunction with the effective value. In a conventional switching power supply device, the above-mentioned critical power may vary depending on the magnitude of the input voltage (for example, depending on whether the effective value of the input AC voltage to the AC/DC converter is 100V or 240V). This means that although the power consumption of the load is the same, the burst operation may be performed depending on the input voltage, and the burst operation may not be performed (the cause of this phenomenon will be described later in detail).

It is undesirable that the burst operation is performed depending on the input voltage and the burst operation is not performed (in other words, the execution condition of the burst operation depends on the input voltage), which hinders the optimization of the power design related to the burst operation.

An object of the present invention is to provide a switching control circuit and a switching power supply device that can suppress a variation in the execution condition of a burst operation according to an input voltage.

Means for solving the problems

A switching control circuit according to the present invention is a switching control circuit that generates an output voltage by switching a switching element in accordance with an input voltage applied to a series circuit of an inductor and the switching element, the switching control circuit including: a current detection unit that detects a current flowing through the switching element as a target current; and a control unit that performs a PWM operation or a burst operation for switching the switching element at a set switching frequency, based on a feedback voltage corresponding to a load size to which the output voltage is supplied, the control unit including: a set signal generating section that generates a set signal instructing to turn on the switching element; a reset signal generating section that generates a reset signal instructing to turn off the switching element; and a driving unit configured to supply a signal for turning the switching element into an on state to the switching element when receiving the set signal, and supply a signal for turning the switching element into an off state to the switching element when receiving the reset signal, wherein the control unit stops switching of the switching element at the switching frequency in the burst operation, the set signal generating unit generates the set signal based on the feedback voltage in the burst operation, and then the reset signal generating unit generates the reset signal when a value of the target current exceeds a turn-off threshold, and the reset signal generating unit increases the turn-off threshold with time in a predetermined interval after the set signal is generated (a first configuration).

In the switch control circuit according to the first configuration, the turn-off threshold may have a value corresponding to the feedback voltage (second configuration).

In the switching control circuit according to the first or second configuration, the reset signal generating unit may generate the off-threshold signal indicating the off-threshold by adding a slope compensation signal whose signal value increases with time in the predetermined section to a signal proportional to the feedback voltage, and generate the reset signal by comparing a current detection signal indicating a value of the target current with the off-threshold signal in the burst operation (a third configuration).

In the switch control circuit of the third configuration, the set signal generating section may include: and an oscillator that generates a signal of the switching frequency, wherein the set signal generating unit generates the set signal at the switching frequency using the oscillator in the PWM operation, and wherein the reset signal generating unit generates the reset signal based on the current detection signal, the off-threshold signal, and an overcurrent-threshold signal indicating a predetermined overcurrent threshold in the PWM operation (a fourth configuration).

In the switch control circuit of the fourth configuration, the reset signal generating unit may include: a first comparator that compares the current detection signal with the off-threshold signal; and a second comparator that compares the current detection signal with the overcurrent threshold signal, wherein in the PWM operation, the reset signal generation unit generates the reset signal when the value of the target current is greater than the shutdown threshold or the overcurrent threshold, based on each comparison result of the first comparator and the second comparator (a fifth configuration).

In the switching control circuit according to the fourth or fifth configuration, the reset signal generation unit may generate the off-threshold signal by adding a first slope compensation signal whose signal value increases with time in the predetermined section and a signal proportional to the feedback voltage, and generate the overcurrent-threshold signal by adding a second slope compensation signal whose signal value increases with time in the predetermined section and a signal having a predetermined value (a sixth configuration).

In the switch control circuit according to any one of the first to sixth configurations, the feedback voltage may decrease as the load size decreases, the controller may continue the PWM operation while the feedback voltage remains higher than a predetermined burst determination voltage, and the controller may start the burst operation while the feedback voltage is lower than the burst determination voltage (a seventh configuration).

In the switch control circuit according to the seventh configuration, the control unit may start the burst operation upon receiving a transition of the feedback voltage from a state higher than the burst determination voltage to a state lower than the burst determination voltage, maintain the switching element in an off state until the feedback voltage exceeds a predetermined burst release voltage higher than the burst determination voltage after the burst operation starts, generate the set signal by the set signal generation unit when the feedback voltage exceeds the burst release voltage, and generate the reset signal by the reset signal generation unit upon receiving a transition of the target current value beyond an off threshold (an eighth configuration).

In the switching control circuit according to any one of the first to sixth configurations, the feedback voltage may be increased as the load size decreases, the control unit may continue the PWM operation while the feedback voltage remains lower than a predetermined burst determination voltage, and the control unit may start the burst operation while the feedback voltage exceeds the burst determination voltage (a ninth configuration).

In the switch control circuit according to the ninth configuration, the control unit may start the burst operation upon receiving a transition of the feedback voltage from a state lower than the burst determination voltage to a state higher than the burst determination voltage, maintain the switching element in an off state until the feedback voltage is lower than a predetermined burst release voltage lower than the burst determination voltage after the burst operation starts, generate the set signal by the set signal generation unit when the feedback voltage is lower than the burst release voltage, and generate the reset signal by the reset signal generation unit upon receiving a transition of the target current value to a state higher than an off threshold value (a tenth configuration).

In the switching control circuit according to any one of the first to tenth configurations described above, a transformer having the inductor as a primary winding and a secondary winding may be used, and the output voltage may be generated on the secondary side in accordance with the input voltage applied to the primary side (an eleventh configuration).

A switching power supply device according to the present invention is a switching power supply device that generates an output voltage on a secondary side in accordance with an input voltage applied to a primary side by a switching method using a transformer having a primary winding and a secondary winding, the switching power supply device including: a switching element connected in series with the primary winding as an inductor; a switch control circuit having any one of the first to eleventh configurations described above; and a feedback voltage generation circuit that generates the feedback voltage from the output voltage (twelfth configuration).

In the switching power supply device according to the twelfth configuration, the input voltage may be generated by rectifying and smoothing an ac voltage (thirteenth configuration).

Effects of the invention

According to the present invention, there are provided a switching control circuit and a switching power supply device capable of suppressing a variation in the execution condition of a burst operation depending on an input voltage.

Drawings

Fig. 1 is an overall configuration diagram of an AC/DC converter according to a first embodiment of the present invention.

Fig. 2 is an external perspective view of an electronic component as an AC/DC converter according to a first embodiment of the present invention.

Fig. 3 is a partial configuration diagram of an AC/DC converter according to a first embodiment of the present invention.

Fig. 4 is an explanatory diagram of mode setting according to the feedback voltage, according to the first embodiment of the present invention.

Fig. 5 is a diagram illustrating a burst operation according to the first embodiment of the present invention.

Fig. 6 (a) to (c) relate to the first embodiment of the present invention, and are diagrams showing a primary-side current waveform in a virtual state.

Fig. 7 is a diagram showing a relationship between an input voltage and a burst threshold voltage in a virtual situation according to the first embodiment of the present invention.

Fig. 8 is a diagram showing a primary-side current waveform in an actual situation according to the first embodiment of the present invention.

Fig. 9 is a diagram showing a relationship between an input voltage and a burst threshold voltage in an actual situation according to the first embodiment of the present invention.

Fig. 10 is a schematic internal block diagram of a primary-side control circuit according to a first embodiment of the present invention.

Fig. 11 is a configuration diagram of a main control unit according to a first embodiment of the present invention.

Fig. 12 is a waveform diagram of various voltages and signals related to burst operation according to the first embodiment of the present invention.

Fig. 13 is a functional block diagram of a set signal generating unit according to the first embodiment of the present invention.

Fig. 14 is a graph showing a relationship between a feedback voltage and a frequency related to switching according to the first embodiment of the present invention.

Fig. 15 is a diagram illustrating a waveform of a slope compensation signal according to a first embodiment of the present invention.

Fig. 16 is a waveform diagram of a plurality of signals relating to the operation of the driving unit according to the first embodiment of the present invention.

Fig. 17 is a diagram showing current waveforms (5 types of current waveforms) compared with a primary side current for generating a reset signal according to the first embodiment of the present invention.

Fig. 18 is a diagram showing a case where the relationship between the secondary-side power and the switching frequency does not depend on the input voltage according to the first embodiment of the present invention.

Fig. 19 is a basic waveform diagram of a voltage, a signal, and the like associated with a burst operation.

Fig. 20 is a waveform diagram of variations of voltages, signals, and the like associated with burst operations.

Detailed Description

Hereinafter, an example of the embodiment of the present invention will be specifically described with reference to the drawings. In the drawings referred to, the same components are denoted by the same reference numerals, and the overlapping description of the same components is omitted in principle. In the present specification, for the sake of simplifying the description, a reference numeral or symbol for referring to information, a signal, a physical quantity, an element, a part, or the like may be described, and a name of the information, the signal, the physical quantity, the element, the part, or the like corresponding to the reference numeral or symbol may be omitted or abbreviated. For example, a switching transistor denoted by "14" described later (see fig. 1) may be referred to as a switching transistor 14, and may be abbreviated as a transistor 14.

First, several terms used in the description of the embodiments of the present invention will be explained. In the embodiment of the present invention, the IC is an abbreviation of Integrated Circuit (Integrated Circuit). PWM is short for Pulse Width Modulation (Pulse Width Modulation). The level is a level of an electric potential, and a high level has a higher electric potential than a low level for an arbitrary signal or voltage. In any signal or voltage, switching from a low level to a high level is referred to as a rising edge (up edge), and switching from a high level to a low level is referred to as a falling edge (down edge).

In any transistor configured as an FET (field effect transistor) including a MOSFET, an ON state (ON) means that a conduction state is established between a drain and a source of the transistor, and an OFF state (OFF) means that a non-conduction state is established between the drain and the source of the transistor (OFF state). The same is true for transistors that are not classified as FETs. Hereinafter, the on state and the off state may be simply referred to as on and off. The MOSFET is a short name for "metal-oxide-semiconductor field-effect transistor". For any transistor, switching from an off state to an on state is represented as on (turn on), and switching from an on state to an off state is represented as off (turn off).

< first embodiment >

A first embodiment of the present invention will be explained. Fig. 1 is an overall configuration diagram of an AC/DC converter 1 according to a first embodiment of the present invention. Fig. 1 also shows a load LD connected to the AC/DC converter 1. The AC/DC converter 1 includes a primary-side circuit 10 as a circuit provided on the primary side and a secondary-side circuit 20 as a circuit provided on the secondary side. In the AC/DC converter 1, the primary side and the secondary side are insulated from each other, in other words, the primary-side circuit 10 and the secondary-side circuit 20 are insulated from each other. In addition, the AC/DC converter 1 has a transformer TR and a photocoupler PC provided across the primary-side circuit 10 and the secondary-side circuit 20. The transformer TR includes a primary winding W1 disposed in the primary circuit 10 and a secondary winding W2 disposed in the secondary circuit 20. In the transformer TR, the primary winding W1 and the secondary winding W2 are electrically insulated and magnetically coupled with each other in opposite polarities. The photo coupler PC includes a light emitting element PCe disposed in the secondary-side circuit 20 and a light receiving element PCr disposed in the primary-side circuit 10.

In the AC/DC converter 1, use the transformerThe transformer TR receives an input voltage V_INGenerating an output voltage V in an insulated manner_OUT. The ground in the primary-side circuit 10 is represented by "GND 1", and the ground in the secondary-side circuit 20 is represented by "GND 2". Input voltage V_INIs a primary side voltage based on the ground GND1, and outputs a voltage V_OUTIs the secondary side voltage referenced to ground GND 2. In each of the primary side circuit 10 and the secondary side circuit 20, the ground refers to a conductive portion (a predetermined potential point) having a reference potential of 0V (zero volts) or to the reference potential itself. However, the ground GND1 and the ground GND2 are insulated from each other, and therefore can have different potentials from each other.

The primary-side circuit 10 will be explained. The primary-side circuit 10 includes a filter 11, a rectifier circuit 12, a smoothing capacitor 13, a switching transistor 14, a current sensing resistor 15, a primary-side control circuit 16 as an example of a switching control circuit, a power supply generation circuit 17, and a feedback capacitor 18. The switching transistor 14 is configured as an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor).

The filter 11 removes the alternating voltage V input to the AC/DC converter 1_ACThe noise of (2). AC voltage V_ACMay be a commercial ac voltage. The rectifying circuit 12 is for the alternating voltage V supplied by the filter 11_ACAnd a diode bridge circuit for performing full-wave rectification. The smoothing capacitor 13 smoothes the voltage full-wave rectified by the rectifying circuit 12 to generate an input voltage V_IN. An input voltage V is applied between both ends of the smoothing capacitor 13 with reference to the ground GND1_IN. Is understood to be the voltage between both ends of the smoothing capacitor 13 and the applied input voltage V_INInput terminal TM of_INEquivalent to or equal to the input terminal TM_INAnd (4) connecting. Input voltage V_INIs provided with an alternating voltage V_ACA positive dc voltage having a voltage value corresponding to the effective value of (a). Input voltage V_INCan be at an alternating voltage V_ACThe period of (a) is slightly pulsating but the pulsation is ignored here.

An input voltage V is applied to one end of the primary winding W1_INThe other end of the primary winding W1 is connected to the drain of the switching transistor 14And (6) connecting. The source of the switching transistor 14 is connected to the ground GND1 via the current sensing resistor 15. The voltage drop generated by the current sensing resistor 15, i.e. the voltage between two terminals of the current sensing resistor 15, is used as the current sensing voltage V_CSIs input to the primary-side control circuit 16. Current sensing voltage V_CSHas a voltage value proportional to the value of the current flowing in the switching transistor 14. The current flowing through the switching transistor 14, i.e., the current flowing through the primary winding W1 is referred to as a primary current and is denoted by the symbol "I_P"means.

The primary-side control circuit 16 is provided with an output terminal TM1, a current sense terminal TM2, a feedback terminal TM3, a power supply terminal TM4, and a ground terminal TM 5. The output terminal TM1 is connected to the gate of the switching transistor 14. The current sensing voltage V is received by the current sensing terminal TM2_CS. A feedback voltage V described later is received by a feedback terminal TM3_FB. Feedback voltage V_FBOne end of the capacitor 18 is connected to the feedback terminal TM3, and the other end of the capacitor 18 is connected to the ground GND1, corresponding to the voltage between both terminals of the feedback capacitor 18. The power supply terminal TM4 receives the dc power supply voltage V supplied from the power supply generation circuit 17_CC. The ground terminal TM5 is connected to the primary-side ground GND 1. The primary side control circuit 16 is based on the power supply voltage V_CCThe driving is performed.

The power supply generation circuit 17 inputs the voltage V_INGenerating a supply voltage V on the basis_CCWill supply voltage V_CCIs supplied to the primary-side control circuit 16. An auxiliary winding (not shown) may be provided on the primary side of the transformer TR. In this case, the power supply generation circuit 17 may be a circuit as follows: rectifies an induced voltage generated in the auxiliary winding when the switching transistor 14 is switched to generate a power supply voltage V_CCThe circuit of (1). Alternatively, the power supply generation circuit 17 may be: for input voltage V_INPerforming DC/DC conversion to thereby generate a power supply voltage V_CCThe DC/DC converter of (1).

The primary-side control circuit 16 supplies a switching signal to the gate of the transistor 14 to control the gate voltage of the transistor 14, thereby switching-driving the transistor 14. The switching signal is a rectangular wave signal whose signal level is switched between a low level and a high level. When a low-level signal and a high-level signal are supplied to the gate of the transistor 14, the transistor 14 is in an off state and an on state, respectively.

The primary-side control circuit 16 may be formed as a power supply IC. FIG. 2 shows an electronic component 1 as a power supply IC_ICIs a perspective view of the appearance of (1). Electronic component 1_ICAn electronic component (semiconductor device) having: a semiconductor chip on which a semiconductor integrated circuit constituting the primary-side control circuit 16 is formed; a case (package) housing the semiconductor chip; and a plurality of external terminals attached to and exposed from the housing. Electronic component 1 is formed by encapsulating a semiconductor chip in a case made of resin_IC. The plurality of external terminals include terminals TM1 to TM5 in fig. 1.

The secondary-side circuit 20 will be explained. The secondary-side circuit 20 is provided with a rectifier diode 21, a smoothing capacitor 22, and a feedback circuit 23. Here, a circuit disposed on the secondary side among the components of the AC/DC converter 1 is referred to as a secondary-side circuit 20. Therefore, the load LD not included in the components of the AC/DC converter 1 is disposed on the secondary side, but does not belong to the secondary-side circuit 20.

In the transformer TR, one end of the secondary winding W2 is connected to the anode of the rectifier diode 21, and the other end of the secondary winding W2 is connected to the ground GND 2. The cathode of the rectifying diode 21 is connected to one end of the smoothing capacitor 22, and the other end of the smoothing capacitor 22 is connected to the ground GND 2. Therefore, when the switching transistor 14 is turned on, it is based on the input voltage V_INThe current (c) flows through the primary winding W1, energy is stored in the primary winding W1, and then when the switching transistor 14 is turned off, the stored energy is output from the secondary winding W2 to the smoothing capacitor 22 through the rectifier diode 21. As a result, an output voltage V is generated across the smoothing capacitor 22_OUT. Is understood to mean the voltage between both ends of the smoothing capacitor 22 and the applied output voltage V_OUTOutput terminal TM of_OUTEquivalent to or equal to the output terminal TM_OUTAnd (4) connecting. Output voltage V_OUTIs provided with an input voltage V_INPrimary side windingA positive dc voltage of a voltage value corresponding to a ratio of the number of turns of W1 to the number of turns of the secondary winding W2. Output voltage V_OUTIt may be slightly pulsating, but the pulsation is ignored here. Normally, the number of turns of the secondary winding W2 is small relative to the number of turns of the primary winding W1, and therefore, the output voltage V is output_OUTSpecific input voltage V_INSmall (i.e. output voltage V)_OUTHaving a specific input voltage V_INLow voltage value).

Load LD is connected with output terminal TM_OUTConnected and dependent on the output voltage V_OUTExamples of the arbitrary load to be driven include a microcomputer, a DSP (Digital Signal Processor), and a DC/DC converter. The consumption current of the load LD, i.e., the current flowing between the smoothing capacitor 22 and the load LD in the direction of discharging the smoothing capacitor 22, is referred to as a load current or an output current, and is denoted by a symbol "I_LD"means.

The feedback circuit 23 drives the light emitting element PCe of the photocoupler PC to make the output voltage V_OUTWith a predetermined target voltage V_TGAnd (5) the consistency is achieved. For example, the feedback circuit 23 will be coupled to the output voltage V_OUTAnd a prescribed target voltage V_TGThe current corresponding to the error is supplied to the light emitting element PCe. The feedback circuit 23 is constituted by a shunt regulator, an error amplifier, and the like. Target voltage V_TGIs an output voltage V_OUTShould be consistent, output voltage V_OUTThe target voltage of (1).

Feedback current I_FBFlows through the light receiving element PCr of the photocoupler PC. Feedback current I_FBIncreases as the magnitude of the current flowing through the light-emitting element PCe increases, and decreases as the magnitude of the current flowing through the light-emitting element PCe decreases. The light receiving element PCR is provided between a feedback terminal TM3 and a ground GND1, and feeds back a current I_FBFlows from the feedback terminal TM3 toward the ground GND 1.

Here, the output voltage V is generated by a diode rectification method (asynchronous rectification method) and a free-wheeling method (flyback back)_OUTHowever, in the AC/DC converter 1, the output voltage V may be generated by a synchronous rectification method_OUTAlso in a forward manner (forward) to generate an output voltage V_OUT。

Referring to FIG. 3, for the output voltage V_OUTAnd a load current I_LDAnd a feedback voltage V_FBThe relationship of (c) is illustrated. In the primary side control circuit 16, a power supply voltage V is applied_CCA specified internal supply voltage Vreg is generated on the basis. The internal power supply voltage Vreg is a positive dc voltage with reference to the ground GND1, and is 4V, for example. The primary-side control circuit 16 is provided with a feedback resistor R_FB. To the resistor R for feedback_FBOne terminal of the resistor is applied with an internal power supply voltage Vreg, and a feedback resistor R_FBAnd the other end thereof is connected to a feedback terminal TM 3.

Load current I_LDRepresents the magnitude of the load LD, the load current I, for the AC/DC converter 1_LDThe larger the load LD, the larger the load current I_LDThe smaller the load LD is. A larger size of the load LD also indicates a heavier load LD, and a smaller size of the load LD also indicates a lighter load LD. In addition, the load current I_LDCan be understood as not being the load current I_LDIs the magnitude of the instantaneous value of (b), but the load current I_LDThe magnitude/small of the average value of (a).

A series of operations in which the switching transistor 14 is turned off after being turned on is referred to as a unit switching operation. The power supplied from the AC/DC converter 1 to the load LD is determined by the number of switching operations per unit time (i.e., the number of times of repetition of the unit switching operation per unit time) and the primary-side current I in each unit switching operation_PPeak current value (hereinafter, may be simply referred to as peak current value I)_PEAK) And (6) determining.

To output a voltage V_OUTStabilized at a target voltage V_TGIs a starting point, and when the magnitude of the load LD is increased (i.e., the load current I)_LDAt increase), the output voltage V_OUTTowards the slave target voltage V_TGThe direction of lowering. Accordingly, the feedback circuit 23 reduces (may be zero) the amount of current supplied to the light emitting element PCe. As a result, the current I is fed back_FBReducing, the feedback voltage V_FBAnd (4) rising. At this time, with the load current I_LDIncrease and feedback currentI_FBAmount of decrease of (2) and feedback voltage V_FBThe amount of rise of (2) becomes large. However, the feedback voltage V_FBIs limited to the internal supply voltage Vreg.

At a feedback voltage V_FBWhen the switching operation is started, the primary side control circuit 16 controls the switching transistor 14 so that the average number of switching operations per unit time or the peak current value I in each unit switching operation is equal to or greater than the predetermined value_PEAKAnd is increased. Thereby opposing the load current I_LDIs increased to make the output voltage V_OUTStabilized at a target voltage V_TG。

On the contrary, to output a voltage V_OUTStabilized at a target voltage V_TGIs the starting point, when the load LD is reduced in size (i.e., the load current I)_LDReduced), the output voltage V_OUTTowards the slave target voltage V_TGThe direction of the rise. Accordingly, the feedback circuit 23 increases the amount of current supplied to the light emitting element PCe. As a result, the current I is fed back_FBIncrease, feedback voltage V_FBAnd decreases. At this time, with the load current I_LDReduced, feedback current I_FBIncrease amount of (3) and feedback voltage V_FBThe amount of reduction of (c) becomes large. However, the feedback voltage V_FBIs limited to the potential of ground GND 1.

At a feedback voltage V_FBWhen the voltage drops, the primary side control circuit 16 controls the switching of the switching transistor 14 so that the average number of switching operations per unit time or the peak current value I in each unit switching operation is equal to or higher than the predetermined value_PEAKAnd (4) reducing. Thereby opposing the load current I_LDIs reduced to make the output voltage V_OUTStabilized at a target voltage V_TG。

Thus, the feedback voltage V_FBIs a voltage corresponding to the size of the load LD. In the structure of the present embodiment, the load current I_LDThe larger (load current I)_LDLarger average value of) is set, the feedback voltage V is set to be larger_FBThe higher the load current I_LDThe smaller (load current I)_LDSmaller average value of) feedback voltage V_FBThe lower.

The primary side control circuit 16 sets any one of a plurality of modesThe operation mode is set and the operation is performed in the set operation mode. Here, the plurality of modes includes first to fifth modes. The primary side control circuit 16 is based on the feedback voltage V_FBAny one of the first to fifth modes is set as an operation mode. FIG. 4 shows the feedback voltage V_FBAnd the action pattern.

In the second to fourth modes, the primary-side control circuit 16 performs the PWM operation. In the PWM operation, the switching transistor 14 is switched at a set switching frequency f_SWThe switching is performed periodically. I.e. the switching frequency f_SWThe switching frequency of the switching transistor 14 when the PWM operation is performed (i.e., the number of repetitions of the switching operation per 1 second). As will be understood from the description given later, in each unit switching operation in the PWM operation, after the switching transistor 14 is turned on, the primary-side current I flows_PUp to a certain current value (e.g. based on the feedback voltage V)_FBOr a current value based on the overcurrent detection voltage), the switching transistor 14 is turned off. That is, the primary-side control circuit 16 can perform switching control of the transistor 14 in a so-called PWM current mode.

The operation mode of the primary side control circuit 16 is controlled in accordance with a predetermined voltage V_A、V_B、V_C、V_DAnd V_EAnd a feedback voltage V_FBIn relation to (1), at "V_FB＜V_AWhen true, set to the first mode at V_A≤V_FB＜V_BWhen true, set to the second mode at V_B≤V_FB＜V_CWhen true, set to the third mode at V_C≤V_FB＜V_EWhen it is established, the fourth mode is set at V_E≤V_FBIf "true," the fifth mode is set. 0 < V_A＜V_B＜V_C＜V_D＜V_E"true" here, the voltage V_A、V_B、V_C、V_D、V_ERespectively 0.40V, 0.55V, 1.25V, 2.00V, 2.80V (volt). Voltage V_DThe meaning of (A) is clear from the description below.

As described above, the PWM operation is performed in the second to fourth modes. Wherein the second mode is a switching frequency f_SWFixed to a predetermined frequency f_LF fixed mode, the fourth mode being the switching frequency f_SWFixed at a frequency f higher than the predetermined frequency_LHigh predetermined frequency f_HF fixed mode of (1). Here, the frequency f_L、f_H25kHz and 100kHz, respectively. The third mode is dependent on the feedback voltage V_FBTo reduce the switching frequency f_SWReduced f reduction mode. Specifically, in the third mode, the voltage V is fed back with the feedback voltage_FBFrom voltage V_CDown to a voltage V_BOf switching frequency f_SWFrom frequency f_HLinearly down to frequency f_LIn contrast, with the feedback voltage V_FBFrom voltage V_BUp to a voltage V_COf switching frequency f_SWFrom frequency f_LLinearly increasing to frequency f_H。

Reducing the switching frequency f when the load LD is relatively light while performing PWM action_SWThis can improve the power conversion efficiency. In addition, the second mode may also be deleted. At this time, it is regarded as "V_A＝V_B"is used.

The fifth mode is an overload mode. In the fifth mode, at "V_E≤V_FBWhen the "established state continues for a predetermined time (for example, 64 msec) or longer, the primary-side control circuit 16 determines that the AC/DC converter 1 is in an overload state and performs an overload protection operation. In the overload protection operation, the switching of the switching transistor 14 is stopped and the transistor 14 is maintained in an off state without performing the PWM operation or a burst operation described later. In addition, in the following "V_E≤V_FB"transfer to" V "in the non-satisfied state_E≤V_FBAfter the established state of "execute the operation based on" "f_SW＝f_H"until the overload protection operation is performed. The fifth mode is not related to the specific features of the present invention, and therefore, hereinafter, unless otherwise particularly required, "V" is always set_FB＜V_E"true and ignore the existence of the fifth mode.

First of allThe mode is a burst mode. Feedback voltage V from the state of PWM operation_FBIs reduced to_FB＜V_AWhen "hold", a transition to the burst mode occurs, and the primary-side control circuit 16 executes a burst operation. In burst operation, the switching frequency f is stopped_SWThe switching of the lower switching transistor 14 switches the switching transistor 14 in a manner not to have a periodicity. The switching of the switching transistor 14 in the burst operation may occasionally have periodicity, but the switching frequency of the switching transistor 14 at this time is higher than the frequency f_LLow. The details will be clear from the description below, but the term "V" means_FB＜V_AIn the satisfied period, the switching transistor 14 is kept in the off state, and the feedback voltage V is set_FBAt a voltage V_AThe vicinity is changed up and down, thereby realizing a burst operation.

The burst operation will be described with reference to fig. 5. FIG. 5 shows the feedback voltage V when a burst action is performed_FBAnd the state of the switching transistor 14. Voltage V_BST1Is a predetermined burst decision voltage, voltage V_BST2Is a predetermined burst release voltage. Burst decision voltage V_BST1Voltage V of FIG. 4_AHere, it is 0.40V. Burst release voltage V_BST2Specific burst determination voltage V_BST1High, here 0.45V.

Since the load LD is light, therefore, at "V_FB＜V_BST1"time t of establishment₁Considered as a benchmark. At time t₁The switching transistor 14 is in an off state. While the transistor 14 is kept in the off state, the feedback voltage V_FBWith the output voltage V_OUTIs lowered and is raised. And, at time t₂Feedback voltage V_FBExceeding the burst release voltage V_BST2When this occurs, the transistor 14 is turned on by the primary side control circuit 16. In burst operation, after the transistor 14 is turned on, at time t₃Primary side current I_PReaches the turn-off threshold I_OFFWhen this occurs, the switching transistor 14 is turned off.

In the example of fig. 5, the feedback voltage V is in the primary switching of the transistor 14_FBIs again lower than the burst decision voltage V_BST1Thereafter, the operation is repeated with the time t in the burst operation₁～t₃The same action is performed between the two actions. At time t₂Feedback voltage V_FBExceeding the burst release voltage V_BST2Thereafter, in the first switching of the transistor 14, the voltage V is fed back_FBSometimes not lower than the burst judgment voltage V_BST1In this case, at a frequency f_LThe switching on of the transistor 14 is repeated until the feedback voltage V_FBLower than the burst decision voltage V_BST1. If the feedback voltage V becomes heavy due to the load LD_FBStably exceeds the burst judgment voltage V_BST1The operation performed by the primary-side control circuit 16 is shifted from the burst operation to the PWM operation.

Here, referring to (a) to (c) of fig. 6, the off threshold I having a fixed value is assumed to be used_OFF[const]As the above-mentioned turn-off threshold I_OFFTemporal burst activity is considered. The solid-line waveform 610 of fig. 6 (a) and the broken-line waveform 620 of fig. 6 (b) show the primary-side current I in the first and second virtual conditions, respectively_PThe waveform of (2). The first hypothetical situation is at "I_OFF＝I_OFF[const]And V_IN＝V_INL"the condition of performing a burst action at the time" I "is the second hypothetical condition_OFF＝I_OFF[const]And V_IN＝V_INH"is a condition for performing a burst action. Here as the input voltage V_INVoltage V of the first example_INLRatio as input voltage V_INVoltage V of the second example_INHLow. For example, voltage V_INL、V_INHRespectively, with the alternating voltage V of figure 1_ACInput voltage V when the effective value of (A) is 100V or 240V_INAnd (4) the equivalent. Primary side current I under first and second virtual conditions_PRespectively by the symbol "I_P[V_INL]”、“I_P[V_INH]"means. In fig. 6 (c), the primary-side current I shown in fig. 6 (a)_P[V_INL]Waveform 610 of (c) and the primary-side current I shown in fig. 6 (b)_P[V_INH]Waveform 620 of (a) is shown superimposed. However, for convenience of the drawingIn fig. 6 (c), waveforms 610 and 620 are shown slightly offset above and below each other.

In one of the first and second virtual conditions, the switching transistor 14 is turned on in a burst operation, and then the primary-side current I is applied_PReaches the turn-off threshold I_OFF(here, I)_OFF[const]) In turn, the switching transistor 14 is turned off. However, the current I flows from the primary side_PReaches the turn-off threshold I_OFF(here, I)_OFF[const]) Has elapsed a predetermined delay time t_DLYAfter that, the switching transistor 14 is actually turned off. Delay time t_DLYIs based on the signal delay in the primary-side control circuit 16 and the charging/discharging time of the gate capacitance of the switching transistor 14.

Delay time t_DLYAnd an input voltage V_INIs fixed regardless of the size of the lens. However, the primary side current I_PRelative to the delay time t_DLYIs dependent on the input voltage V_INThe size of (2). This is because the primary-side current I when the switching transistor 14 is turned on_PIs inversely proportional to the inductance value of the primary winding W1 and is also proportional to the input voltage V_INIs in direct proportion. As a result, the primary side current I in the first virtual condition is set to be_PPeak current value of_PEAKI.e. peak current value I_P1And the primary side current I under the second hypothetical condition_PPeak current value of_PEAKI.e. peak current value I_P2When compared, is "I_P1＜I_P2”。

Thus, if "I" is present_OFF＝I_OFF[const]", then, as shown in FIG. 7, the burst critical power P_BSTAnd an input voltage V_INCorresponds to the magnitude of (in other words, corresponds to the AC voltage V)_ACCorrespondingly) change. Burst critical power P_BSTThe power is the power that is critical for switching between burst operation and PWM operation. That is, if the power (i.e., the output voltage V) is supplied from the AC/DC converter 1 to the load LD_OUTAnd the load current I_LDProduct of) the burst critical power P_BSTIf it is large, PWM action is executed, if it is larger than burst critical power P_BSTIf small, burst action is performed.

The burst operation is to reduce power consumption of the AC/DC converter 1 at the time of light load, and is undesirable in response to the input voltage V_INPerforming burst action or not, hampers power design optimization associated with burst action.

In view of this, in the primary-side control circuit 16, after the switching transistor 14 is turned on, the off-threshold I is made_OFFGradually increasing compensation (hereinafter, referred to as up slope compensation).

In fig. 8, a solid line waveform 630 and a dashed line waveform 640 show the primary-side current I in the first and second actual conditions, respectively_PThe waveform of (2). The first actual condition is for the switch-off threshold I_OFFApplying slope compensation and at "V_IN＝V_INL"the condition of performing a burst action at the time, the second actual condition being for the switch-off threshold I_OFFApplying slope compensation and at "V_IN＝V_INHA condition in which burst actions are performed. Additionally, for ease of illustration, waveforms 630 and 640 are shown slightly offset above and below each other in FIG. 8.

In one of the first and second actual conditions, the primary-side current I is applied after the switching transistor 14 is turned on in the burst operation_PReaches the turn-off threshold I_OFFAs a trigger, the switching transistor 14 is turned off. However, the current I flows from the primary side_PReaches the turn-off threshold I_OFFHas elapsed a predetermined delay time t_DLYAfter that, the switching transistor 14 is actually turned off.

In the first and second actual conditions, the threshold I is switched off after the switching transistor 14 is switched on_OFFAnd gradually increased. Therefore, the primary-side current I in the first practical condition_PPeak current value of_PEAKI.e. peak current value I_P1' with the primary side current I in the second practical situation_PPeak current value of (I)_PEAKI.e. peak current value I_P2' when making a comparison, the magnitude of their difference | I_P1’-I_P2' | ratio of the magnitude | I of the difference corresponding to the above-mentioned hypothetical situation_P1-I_P2And | is small.Ideally, let | I_P1’-I_P2' | is zero (the upper slope compensation is designed to do so). In all cases, it is sometimes difficult to make | I_P1’-I_P2' | is zero, the up slope compensation is designed such that | I_P1’-I_P2' | as close to zero as possible.

FIG. 9 shows the application of an upper slope compensation to the turn-off threshold I_OFFIn the case of (2), the input voltage V_INAnd burst critical power P_BSTThe relationship (2) of (c). Burst critical power P due to the use of upper slope compensation_BSTFor input voltage V_INCan also reduce the burst critical power P_BSTIndependent of input voltage V_INAnd is substantially stationary. As a result, power design optimization relating to burst operation of the apparatus including the AC/DC converter 1 becomes easy.

Fig. 10 shows a schematic internal block diagram of the primary-side control circuit 16. The primary-side control circuit 16 includes: a main control section 100 having a set signal generating section 110, a reset signal generating section 120, and a drive section 130, and a current detecting section 140. The current detection unit 140 detects the primary-side current I flowing in the switching transistor 14 using the current sense resistor 15_P(target current), and generates and outputs a current detection signal S indicating the detection result_CS. Specifically, the current detection unit 140 is supplied with a voltage drop (i.e., a current sense voltage V) generated by the current sense resistor 15 with reference to the ground GND1_CS). The current detector 140 includes an amplifier, a filter, and the like, and senses the voltage V with a current_CSk times to obtain a voltage value, and generating and outputting a voltage signal with the voltage value as a current detection signal S_CS. Here, k is a positive arbitrary real number.

Current detection signal S_CSIs supplied to the main control section 100. In addition, the feedback voltage V_FBIs also supplied to the main control section 100. The main control part 100 is based on the feedback voltage V_FBAnd a current detection signal S_CS(thus, according to the feedback voltage V_FBAnd a current sensing voltage V_CS) A switching signal is supplied to the gate of the switching transistor 14 to control the gate voltage of the transistor 14, thereby applying a voltage to the crystalThe body tube 14 performs switching drive. In addition, a signal supplied to the gate of the transistor 14 is also sometimes described as a gate signal.

The SET signal generating section 110 generates a signal SET. The reset signal generation unit 120 generates a signal RST. The signals SET and RST are supplied to the driving section 130. The signals SET and RST are binary signals having either a low level or a high level. The high-level signal SET functions as a SET signal for instructing the switching transistor 14 to turn on, and the low-level signal SET does not function as a SET signal (is disabled). The high-level signal RST functions as a reset signal instructing the switching transistor 14 to turn off, and the low-level signal RST does not function (is deactivated) as a reset signal.

When receiving the SET signal (i.e., when receiving the SET signal of high level), the driver 130 supplies a signal (i.e., a gate signal of high level) for turning the switching transistor 14 on to the gate of the switching transistor 14. When receiving the reset signal (i.e., when receiving the high-level signal RST), the driving unit 130 supplies a signal (i.e., a low-level gate signal) for turning off the switching transistor 14 to the gate of the switching transistor 14.

In addition, the main control part 100 is based on the feedback voltage V_FBPerforming the switching transistor 14 at a set switching frequency f_SWThe PWM operation or burst operation of the switch is performed. In the burst operation, the switching frequency f is set as described above_SWThe switching of the lower transistor 14 is stopped.

In burst operation, the set signal generating unit 110 generates a set signal based on the feedback voltage V_FBGenerating a set signal (refer to FIG. 5; accept "V_FB＞V_BST2"and generates the set signal"), and thereafter, the reset signal generating section 120 refers to the current detection signal S_CSWith a primary side current I_PExceeds a turn-off threshold I_OFFAnd generating a reset signal for triggering. For the turn-off threshold I_OFFThe above-described upper slope compensation is applied.

Fig. 11 shows a detailed configuration example of the main control unit 100.

The bit signal generating unit 110 will be described. In the structure of FIG. 11In the example, the set signal generating section 110 has a comparator 111 and an oscillator 112. The comparator 111 is a comparator with hysteresis, based on the feedback voltage V_FBCorresponding feedback signal S_FB2Generates an enable signal EN for the oscillator 112_OSC. Here, the feedback signal S_FB2To have a feedback voltage V _FB1/2 times the voltage value. The comparator 111 will be based on the feedback signal S_FB2Voltage (V) of_FB/2) and voltage (V)_BST1/2) or voltage (V)_BST2/2) comparing them and using the signal representing their magnitude relation as enable signal EN_OSCAnd (6) outputting. Enable signal EN_OSCThe binary signal is a binary signal having either a low level or a high level.

In the comparator 111, the voltage (V)_FB/2) and voltage (V)_BST1/2) or voltage (V)_BST2Comparison of/2) is equivalent to a feedback voltage V_FBAnd a burst decision voltage V_BST1Or burst release voltage V_BST2Comparison of (1). Therefore, the voltage V is of interest_FBAnd voltage V_BST1Or V_BST2The operation of the comparator 111 will be described with reference to the magnitude relationship of (a). FIG. 12 shows the voltage V_FB、V_BST1And V_BST2And includes an enable signal EN_OSCIn relation to the various signals (with respect to the signal OUT shown in FIG. 12)_VCOAs will be described later).

After the primary side control circuit 16 is started, the feedback voltage V is fed back in a predetermined starting sequence_FBIs sufficiently higher than the burst decision voltage V_BST1And a burst release voltage V_BST2At this time, the output signal of the comparator 111 is the enable signal EN_OSCIs high.

As shown in fig. 12, the output signal (EN) of the comparator 111_OSC) At high level, the comparator 111 feeds back the voltage V_FBAnd a burst decision voltage V_BST1Making a comparison at "V_FB＞V_BST1When true, enable signal EN_OSCIs maintained at high level, on the other hand, at "V_FB＜V_BST1When true, enable signal EN_OSCSwitching from high to low. In comparison withWhen the output signal of the device 111 is at high level, it is at V_FB＝V_BST1Time enable signal EN_OSCIs either high or low.

As shown in fig. 12, the output signal (EN) of the comparator 111_OSC) At low level, the comparator 111 feeds back the voltage V_FBAnd a burst release voltage V_BST2Making a comparison at "V_FB＜V_BST2When true, enable signal EN_OSCIs maintained at a low level, on the other hand, at "V_FB＞V_BST2When true, enable signal EN_OSCSwitching from low to high. When the output signal of the comparator 111 is at low level, it is at "V_FB＝V_BST2Time enable signal EN_OSCIs either high or low.

The oscillator 112 generates a feedback voltage V_FBRectangular wave signal of corresponding frequency, only in enable signal EN_OSCWhen the level is high, the generated rectangular wave signal is output as a signal SET. If enable signal EN_OSCAnd is low, the signal SET remains low.

Fig. 13 shows a functional block diagram of the oscillator 112. Referring to fig. 12, the oscillator 112 may be considered to be composed of: a voltage controlled oscillator 112a for continuously generating and outputting a feedback voltage V_FBCorresponding frequency f_VCOOf the rectangular wave signal OUT_VCO(ii) a A switch part 112b only in the enable signal EN_OSCWhen the level is high, the rectangular wave signal OUT outputted from the voltage controlled oscillator 112a_VCOIs output as a signal SET to the outside of the oscillator 112. At enable signal EN_OSCWhen the signal is low, the signal SET is fixed to be low.

FIG. 14 shows the feedback voltage V_FBAnd frequency f_VCOThe relationship (2) of (c). Frequency f_VCOThere are upper and lower limits. Frequency f_VCOHas an upper limit of the frequency f_HFrequency f_VCOHas a lower limit of the frequency f_L(refer to fig. 4). At the time of PWM operation, frequency f_VCOFor the above-mentioned switching frequency f_SW. At "V_FB≤V_BWhen "true, frequency f_VCOFixed to frequency f_LAt "V_C≤V_FBWhen "true, frequency f_VCOFixed to frequency f_H. At "V_B≤V_FB≤V_CWhen true, it follows the feedback voltage V_FBFrom voltage V_BUp to a voltage V_CFrequency f_VCOFrom frequency f_LLinearly increasing to frequency f_H。

In a rectangular wave signal OUT_VCOAt a frequency f_VCOPulses whose signal level becomes high for only a minute time are repeatedly generated. Therefore, in the enable signal EN_OSCAt a high level, at a frequency f in the signal SET_VCORising edges are repeatedly generated.

Referring again to fig. 11, the reset signal generating section 120 will be described. In the configuration example of fig. 11, the reset signal generating section 120 includes: slope compensation signal generating sections 121 and 124, adders 122 and 125, comparators 123 and 126, and an or circuit 127.

The slope compensation signal generating unit 121 generates and outputs a slope compensation signal S_SLPAThe slope compensation signal generating unit 124 generates and outputs a slope compensation signal S_SLPB. Slope compensation signal S_SLPAAnd S_SLPBIs a voltage signal whose signal value changes with the passage of time. For any voltage signal, the signal value of the voltage signal is equivalent to the voltage value of the voltage signal. At the slope compensation signal S_SLPAAnd S_SLPBHas a periodicity of the inverse of the period and a frequency f_VCOAnd (5) the consistency is achieved.

And a feedback voltage V_FBCorresponding feedback signal S_FB1And a slope compensation signal S from the slope compensation signal generating section 121_SLPAIs input to adder 122. Here, the signal S is fed back_FB1Is provided with a feedback voltage V _FB1/4 times the voltage value. The adder 122 adds the slope compensation signal S_SLPAAnd a feedback signal S_FB1Adding a voltage signal based on the addition result as a signal S for a turn-off threshold_OFFAAnd (6) outputting. Closing deviceSignal S for threshold interruption_OFFAThe signal value (i.e. voltage value) of (a) is the feedback signal S_FB1Is the signal value (i.e. voltage value; here is V)_FB/4) and slope compensation signal S_SLPAIs measured, i.e. the sum of the signal values (i.e. voltage values) of (c). Signal S for turning off threshold_OFFAThe turn-off threshold I is represented by a voltage signal_OFFBy turning off the threshold signal S_OFFAIndicating a shutdown threshold I_OFF。

In the comparator 123, the off-threshold signal S is input to the inverting input terminal_OFFAInputting a current detection signal S to the non-inverting input terminal_CS. As can be seen from the description with reference to fig. 10 and the like, the current detection signal S_CSIs indicative of a primary side current I_PVoltage signal of the value of (d).

“S_CS＞S_OFFA"is true to" I_P＞I_OFF"is true to the same thing," S_CS＜S_OFFA"is true to" I_P＜I_OFF"is true to the right. Comparator 123 is at "S_CS＞S_OFFAWhen "established, i.e. current detection signal S_CSSignal value (voltage value) of (1) is greater than the off-threshold signal S_OFFAWhen the signal value (voltage value) of (1) is large, a high level signal is output, otherwise, a low level signal is output. However, at "S_CS＝S_OFFAWhen "true," the output signal of the comparator 123 can be at a high level.

Adder 125 is supplied with an overcurrent detection voltage V representing a predetermined value_LIMVoltage signal S of_LIMAnd a slope compensation signal S from the slope compensation signal generation unit 124_SLPB. Overcurrent detection voltage V_LIMWith a fixed voltage value. However, when the soft start operation is performed at the time of starting the primary side control circuit 16, the overcurrent detection voltage V may be set to be the same as the overcurrent detection voltage V_LIMSet to be smaller than the fixed voltage value. The adder 125 adds the slope compensation signal S_SLPBAnd represents the overcurrent detection voltage V_LIMVoltage signal S of_LIMAdding a voltage signal based on the addition result as an overcurrent threshold signal S_OFFBAnd (6) outputting. Overcurrent threshold signal S_OFFBSignal value of (a), (b)I.e. voltage value) is the voltage signal S_LIMIs the signal value (i.e. voltage value; here is V)_LIM) And a slope compensation signal S_SLPBIs measured, i.e., the sum of the signal values (i.e., voltage values) of (a). Overcurrent threshold signal S_OFFBIs expressed in the form of a voltage signal for the primary side current I_POver-current threshold value I of_LIMFrom the signal S for overcurrent threshold_OFFBIndicating overcurrent threshold I_LIM。

In the comparator 126, the overcurrent threshold signal S is input to the inverting input terminal_OFFBInputting a current detection signal S to the non-inverting input terminal_CS。

“S_CS＞S_OFFB"is true to" I_P＞I_LIM"is true to the same thing," S_CS＜S_OFFB"is true to" I_P＜I_LIMThe same holds true. Comparator 126 is at "S_CS＞S_OFFBWhen "true, i.e. the current detection signal S_CSIs less than the overcurrent threshold signal S_OFFBWhen the signal value (voltage value) of (b) is large, a high-level signal is output, otherwise, a low-level signal is output. However, at "S_CS＝S_OFFBWhen true, the output signal of the comparator 126 can be high.

The or logic circuit 127 outputs a logical or signal of the output signals of the comparators 123 and 126 as a signal RST. Therefore, the signal RST is low only when both of the output signal of the comparator 123 and the output signal of the comparator 126 are low, and is high when at least one of the output signals is high.

Therefore, the reset signal (i.e., the high-level signal RST) is generated by any one of the first block including the slope compensation signal generating unit 121, the adder 122, and the comparator 123 and the second block including the slope compensation signal generating unit 124, the adder 125, and the comparator 126. Function of generating reset signal at "V_FB＜V_D"in is borne by the first block, at" V_D≤V_FBIs borne by the second block (with respect to voltage V)_DRefer to fig. 4), which will be done laterAnd (4) explanation.

FIG. 15 shows a signal OUT_VCO、SET、S_SLPAAnd S_SLPBThe relationship (2) of (c). In fig. 15, it is assumed that the signal EN_OSCIs maintained at a high level, and thus, the signal OUT_VCOIn accordance with the signal SET.

Slope compensation signal S_SLPAAnd S_SLPBIn generating a signal OUT_VCOHave a predetermined initial signal value INI at the time of the rising edge of_A、INI_B. Initial signal value INI_AAnd INI_BBut may be a value other than zero.

The following intervals are referred to as unit intervals: from the signal OUT_VCOUntil the next rising edge occurs at the time when the rising edge occurs. Length of 1 unit interval and signal OUT_VCOFrequency f of_VCOThe reciprocal of (a) is consistent. Each unit section is composed of a front section P1 and a rear section P2. In each unit section, the preceding section P1 may be started at the same time as the start of the unit section, and the subsequent section P2 may be started at the same time as the end of the preceding section P1.

In each unit interval, the slope compensation signal S is in the front interval P1_SLPAWith an initial signal value INI_AThe slope compensation signal S is such that the starting point increases with the passage of time_SLPAHas a predetermined signal value TOP at the end time of the preceding section P1_A. Of course "INI_A＜TOP_A". In each unit interval, the slope compensation signal S is in the subsequent interval P2_SLPASignal value (i.e., voltage value) of (2) and signal value TOP_AThe slope compensation signal S is such that the starting point decreases with the passage of time_SLPAHas a predetermined signal value BTM at the end of the subsequent interval P2_A. In the example of FIG. 15, the term "BTM" is used_A＜INI_A", but may also be a" BTM_A＝INI_A"OR" BTM_A＞INI_A”。

In each unit interval, the slope compensation signal S is in the front interval P1_SLPBWith an initial signal value INI_BThe slope compensation signal S is such that the starting point increases with the passage of time_SLPBHas a predetermined signal value TOP at the end time of the preceding section P1_B. Of course "INI_B＜TOP_B". In each unit interval, the slope compensation signal S is in the subsequent interval P2_SLPBSignal value (i.e., voltage value) of (d) and signal value TOP_BThe slope compensation signal S is such that the starting point decreases with the passage of time_SLPBHas a predetermined signal value BTM at the end of the subsequent interval P2_B. In the example of FIG. 15, this is "BTM_B＜INI_B", but may also be a" BTM_B＝INI_B"OR" BTM_B＞INI_B”。

The above-described upper slope compensation is realized in the preceding segment P1. Slope compensation signal S in the back-end interval P2_SLPAAnd S_SLPBThe reduction of the signal value of (b) is called downward slope compensation. The lower slope compensation (which can also be generally referred to as AC slope compensation) is introduced with the aim of preventing subharmonic oscillation. The principle of preventing subharmonic oscillation based on the downward slope compensation is well known, and thus, the description thereof is omitted.

In each unit interval, the start time of the subsequent interval P2 is as follows: from the start time of the unit interval, the time "q.1/f_VCO"time after. ' 1/f_VCO"corresponds to the length of each unit section. The coefficient q has a value greater than 0 and less than 1. In order to effectively prevent subharmonic oscillation, the coefficient q may have a value of 0.5 or less, for example, "0.35 < q < 0.49".

In the example of fig. 15, each unit section is formed only by the preceding section P1 and the succeeding section P2, but in each unit section, the slope compensation signal S may be present after the preceding section P1 is ended and before the succeeding section P2 is started_SLPA、S_SLPBRespectively fixed at the signal value TOP_A、TOP_BAfter the end of the subsequent section P2 and before the start of the next unit section, the slope compensation signal S may be present in the finite section of (3)_SLPA、S_SLPBRespectively fixed at the signal value BTM_A、BTM_BIs limited.

In addition, in the example of fig. 15, it is assumed that the enable signal EN_OSCIs maintained at a high level, and an enable signal EN_OSCSignal OUT at low level_VCO、S_SLPAAnd S_SLPBThe relationship of (c) may be the same as described above. However, in the enable signal EN_OSCAt low level, signal S_SLPAAnd S_SLPBIs not significant, and therefore the signal S_SLPAAnd S_SLPBMay be fixed to zero.

Here, the slope compensation signal S is set_SLPAAnd S_SLPBAre the same signals as each other. At the slope compensation signal S_SLPAAnd S_SLPBIn the case of the same signal, the slope compensation signal generation unit 124 may be eliminated and the slope compensation signal S generated in the slope compensation signal generation unit 121 may be used_SLPAIs input to the adder 122 and serves as a slope compensation signal S_SLPBInput to adder 125. However, the slope compensation signal S_SLPAAnd S_SLPBMay be different signals from each other.

Referring again to fig. 11, the driving unit 130 will be described. In the configuration example of fig. 11, the driving unit 130 includes an RS flip-flop 131 (hereinafter, referred to as FF131) and a driver 132.

The FF131 has: a set input terminal (S), a reset input terminal (R), and an output terminal (Q). In the FF131, a signal SET is input to the SET input terminal, a signal RST is input to the reset input terminal, and a signal DRV is output from the output terminal. As shown in fig. 16, when the signal SET is at a high level, the FF131 outputs the signal DRV at a high level from the output terminal, and thereafter, maintains the high level of the output signal DRV until the signal RST is at a high level. When the signal RST is at a high level, the FF131 outputs the signal DRV at a low level from the output terminal, and thereafter, maintains the low level of the output signal DRV until the signal SET is at a high level. In the main control unit 100, the signals SET and RST are not simultaneously high (in this way, the pulse width of the high level of the signal SET is SET sufficiently short).

The driver 132 is connected to the gate of the switching transistor 14 via an output terminal TM1 (see fig. 1) of the primary-side control circuit 16, and controls the gate voltage of the switching transistor 14 in accordance with the output signal DRV of the FF 131. When the output signal DRV is at a high level, the driver 132 turns on the transistor 14 by setting the gate voltage of the transistor 14 to a high level, and when the output signal DRV is at a low level, the driver 132 turns off the transistor 14 by setting the gate voltage of the transistor 14 to a low level. However, there is a delay until the transistor 14 actually switches to the on state in response to the rising edge of the output signal DRV of the FF131, and there is a delay until the transistor 14 actually switches to the off state in response to the falling edge of the output signal DRV of the FF 131.

The burst operation will be described with reference to the configuration example of fig. 11. Setting overcurrent detection voltage V_LIMAt "V" of_FB＜V_D"become immediately lower" S_OFFA＜S_OFFB"true (with respect to voltage V)_DRefer to fig. 4). Therefore, in the burst operation, the signal S is detected by the current_CSSignal S for the signal value of (1) exceeding the turn-off threshold_OFFAIs triggered by the signal value of (i.e. by the primary side current I)_PExceeding the switch-off threshold I_OFFTrigger on) the reset signal (high-level signal RST) is generated. During burst operation, the feedback voltage V_FBSince the generation timing of the reset signal is sufficiently small, it always belongs to the preceding section P1, and the upward slope compensation effectively functions, and the effects as shown in fig. 8 and 9 are obtained.

Then, for "V_FB＜V_D"the PWM operation when established" will be described. As described above, the overcurrent detection voltage V is set_LIMAt "V" of_FB＜V_D"become immediately lower" S_OFFA＜S_OFFB"true". Thus, at "V_FB＜V_DIn the PWM operation in the "hold", the current detection signal S is used in the same manner as the burst operation_CSSignal S for the signal value of (1) exceeding the turn-off threshold_OFFAIs triggered by the signal value of (i.e. by the primary side current I)_PExceeding the switch-off threshold I_OFFTrigger on) the reset signal (high-level signal RST) is generated. If the generation time of the reset signal belongs to the preceding section P1, the upper slope compensation is effectiveAnd functions as ground. On the other hand, it is also important to suppress subharmonic oscillation, and if the generation timing of the reset signal belongs to the subsequent stage interval P2, the effect of suppressing subharmonic oscillation by the down slope compensation is obtained.

At "V_FB＜V_D"if the PWM operation is performed under the condition of the above, the feedback voltage V is set_FBWhen the ratio is low, it is dominant to generate the reset signal in the front interval P1, and the upper slope compensation functions easily and effectively. At "V_FB＜V_D"if the PWM operation is performed under the condition of the above, the feedback voltage V is set_FBAs is relatively high, it is dominant to generate the reset signal in the subsequent interval P2, and the lower slope compensation is easy to function effectively.

Then, for "V_D＜V_FB"the PWM operation when established" will be described. At "V_D＜V_FB"set the overcurrent detection voltage V immediately_LIMSo as to make "S_OFFA＞S_OFFB"true". Thus, at "V_D＜V_FB"in the established PWM operation, the current detection signal S is used_CSSignal S for exceeding overcurrent threshold_OFFBIs triggered by the signal value of (i.e. by the primary side current I)_POver-current threshold I_LIMTrigger on) the reset signal (high-level signal RST) is generated. If the generation timing of the reset signal belongs to the preceding section P1, the upper slope compensation effectively functions. On the other hand, it is also important to suppress subharmonic oscillation, and if the generation timing of the reset signal belongs to the subsequent stage interval P2, the effect of suppressing subharmonic oscillation by the down slope compensation is obtained.

"V" in the fourth mode (refer to FIG. 4)_D＜V_FBThe established mode is particularly called a current limit mode (current limit mode). In the current limiting mode, the current I is in the primary side_POver-current threshold I is reached_LIMA reset signal is generated. In the current limiting mode, the voltage V is detected if the overcurrent is not detected_LIMApplying slope compensation, the delay time t is determined_DLYThe maximum power of the secondary side depends on the input voltage V_INMay vary in size. In the structure of FIG. 11In the current limit mode, since the slope compensation is applied using the slope compensation signal generation unit 124 and the adder 125, the maximum power on the secondary side is suppressed from being dependent on the input voltage V_INBut may vary.

FIG. 17 shows the primary side current I and the reset signal generated_PWaveforms 661 to 665 of the compared currents. Waveform 661 is related to primary side current I during burst operation_PComparative current waveform (with off threshold I)_OFFThe waveform of the current). Waveform 662 is related to the primary-side current I during the PWM operation in the second mode_PComparative current waveform (with off threshold I)_OFFThe waveform of the current). Waveform 663 is obtained by comparing the primary-side current I with the PWM operation in the third mode_PComparative current waveform (with off threshold I)_OFFThe waveform of the current). Waveform 664 is in the fourth mode and "V_FB＜V_D"lower PWM operation with primary side current I_PComparative current waveforms (with off-threshold I)_OFFThe waveform of the current). Waveform 665 is related to the primary current I in the current limiting mode_PComparative current waveform (with overcurrent threshold I)_LIMThe waveform of the current).

The upper slope compensation is performed not only during the burst operation but also during the PWM operation, and therefore, during the PWM operation, the secondary side power P is generated_OUT(＝V_OUT×I_LD) With respect to the input voltage V_INThe variation of (c) is not affected or hardly affected (however, in the case where the reset signal is generated in the first half section P1). That is, even when the PWM operation is performed, the effect as shown in fig. 9 can be obtained.

As a result, even in the PWM operation, as shown in fig. 18, the secondary side power P can be set_OUTAnd the switching frequency f_SWWith respect to the input voltage V_INIs unchanged. Thus, the input voltage V is not intentionally used_INThe variation of the slope can be used for circuit design, and it can be expected that the design is easy (in the case where no upper slope compensation is provided, for example, "V" needs to be taken into consideration_IN＝V_INL"time sum" V_IN＝V_INH"when both are used for circuit design). In the figureIn 18, the solid broken line 681 represents "V_IN＝V_INLSecondary side power P of time_OUTAnd the switching frequency f_SWIn relation to each other, broken line 682 represents "V_IN＝V_INHSecondary side power P of time_OUTAnd the switching frequency f_SWThe relationship between them. For ease of illustration, in FIG. 18, the fold lines 681 and 682 are shown slightly offset above one another, but ideally the fold lines 681 and 682 completely coincide.

As is clear from the above description, the set signal generating unit 110 uses the oscillator 112 to set the predetermined frequency f during the PWM operation_VCO(and switching frequency f_SWEquivalent) generates a set signal. The reset signal generating part 120 detects the signal S based on the current during the PWM operation_CSDenotes the turn-off threshold I_OFFSignal S for turn-off threshold_OFFAAnd represents an overcurrent threshold I_LIMSignal S for threshold value for overcurrent_OFFBAnd a reset signal is generated.

More specifically, in the PWM operation, the current detection signal S is referred to_CSAnd turn-off threshold signal S_OFFAComparison result of comparator 123 for comparison, and current detection signal S_CSAnd signal S for overcurrent threshold_OFFBThe comparison result of the comparator 126 for comparison is based on which the primary side current I is obtained_PIs less than the turn-off threshold I_OFFOr over-current threshold I_LIMWhen large, a reset signal is generated. As described above, "S_CS＞S_OFFA"is satisfied" indicates the primary side current I_PIs less than the turn-off threshold I_OFFBig, "S_CS＞S_OFFB"is satisfied" indicates the primary side current I_PIs greater than the overcurrent threshold I_LIMIs large.

In a predetermined section (corresponding to the previous section P1) after the set signal is generated, the slope compensation signal S is generated by increasing the signal value with the passage of time_SLPAAnd a feedback voltage V_FBProportional signal S_FB1Adding to generate a signal S for the turn-off threshold_OFFAAnd, by a slope compensation signal S in which the signal value increases with the passage of time_SLPBWith a signal S having a prescribed value_LIMAdding the signals to generate an overcurrent threshold signal S_OFFB. Thereby, an upper slope compensation is achieved. After the above-described predetermined interval, the down slope compensation is applied for the purpose of preventing subharmonic oscillation.

< second embodiment >

A second embodiment of the present invention will be explained. In the second embodiment, a description will be given of a modification technique, an application technique, and the like of the first embodiment. The matters described in the second embodiment can be applied to the first embodiment.

The second embodiment includes the following examples EX2_1 to EX2_ 3. The above-described matters in the first embodiment can be applied to the following examples EX2_1 to EX2_3 unless otherwise specified and contradictory, and in each example, the descriptions in each example can be prioritized for the matters contradictory to the matters in the first embodiment. Note that, as long as there is no contradiction, the matters described in any of embodiments EX2_1 to EX2_3 can be applied to any other embodiment (that is, 2 or more embodiments arbitrarily selected from a plurality of embodiments can be combined).

The operation and configuration of the first embodiment are supplemented before the example EX2_1 is performed. In the first embodiment, the feedback voltage V is adopted as the size of the load LD decreases_FBA lowered configuration. Therefore, the main control unit 100 of the first embodiment feeds back the voltage V_FBHeld at a burst determination voltage V higher than a predetermined value_BST1In a high state, the PWM operation is continued at a feedback voltage V_FBLower than the burst decision voltage V_BST1When this happens, burst action is initiated.

That is, the main control unit 100 of the first embodiment receives the feedback voltage V_FBDetermining voltage V from a burst_BST1High state transition to the more burst determination voltage V_BST1A low state, and a burst operation is started, and after the burst operation is started, the switching transistor 14 is maintained in an off state until the feedback voltage V is reached as shown in fig. 19_FBExceeding a predetermined burst release voltage V_BST2At a feedback voltage V_FBExceeding the burst release voltage V_BST2At this time, the SET signal generating unit 110 generates a SET signal (high-level signal SET), and then receives the primary-side current I_PExceeds a turn-off threshold I_OFFThe reset signal generating unit 120 generates a reset signal (high-level signal RST). In the first embodiment, "V_BST2＞V_BST1”。

In addition, in fig. 19, it is assumed that the switching transistor 14 is turned on while the set signal is generated (the delay time t is illustrated only for the off-state diagram_DLY). In the configuration of fig. 11, the primary-side current I_PExceeds a turn-off threshold I_OFFWhen is in the state of "S_CS＞S_OFFA"true" and a reset signal (high-level signal RST) is generated.

Example EX2_1

Example EX2_1 is explained. In the AC/DC converter 1, the feedback voltage V may be adopted as the size of the load LD decreases_FBThe ascending structure will be described as example EX2_ 1.

In embodiment EX2_1, the feedback voltage V is adopted as the size of the load LD decreases_FBThe rising structure, therefore, the main control part 100 feeds back the voltage V_FBHeld at a burst determination voltage V higher than a predetermined value_BST1In a low state, the PWM operation is continued at a feedback voltage V_FBExceeds the burst decision voltage V_BST1Burst action is initiated.

That is, the main control unit 100 of the embodiment EX2_1 receives the feedback voltage V_FBDetermining voltage V from a burst_BST1Low state transition to the more than burst determination voltage V_BST1High state, and a burst operation is started, and after the burst operation is started, the switching transistor 14 is maintained in an off state until the feedback voltage V is reached as shown in fig. 20_FBBelow a predetermined burst release voltage V_BST2At a feedback voltage V_FBBelow the burst release voltage V_BST2At this time, the SET signal generating unit 110 generates a SET signal (high-level signal SET), and then receives the primary-side current I_PExceeds a turn-off threshold I_OFFBy repeatingThe bit signal generating section 120 generates a reset signal (a high-level signal RST). "V" in example EX2_1_BST2＜V_BST1”。

In addition, in fig. 20, it is assumed that the switching transistor 14 is turned on while the set signal is generated (the delay time t is illustrated only for the off-state_DLY). In the configuration of fig. 11, the primary-side current I_PExceeds a turn-off threshold I_OFFWhen is in the state of "S_CS＞S_OFFA"true" and a reset signal (high-level signal RST) is generated.

Example EX2_2

An embodiment EX2_2 will be explained. The AC/DC converter 1 of fig. 1 is one of the switching power supply devices of the present invention. In fig. 1, the switching transistor 14 is an example of a switching element connected in series to the primary winding W1 as an inductor, and the primary side control circuit 16 is an example of a switching control circuit that switches the switching element. The switching element may be a variation of a P-channel MOSFET, or a variation of a Bipolar Transistor, a junction FET, or an IGBT (Insulated Gate Bipolar Transistor). In either case, the input voltage V is applied to the series circuit of the inductance and the switching element_INSwitching the switching element, thereby to output terminal TM_OUTGenerating an output voltage V_OUT。

The feedback circuit 23, the photocoupler PC and the feedback capacitor 18 are configured according to the output voltage V_OUTGenerating a feedback voltage V_FBThe feedback voltage generating circuit of (1).

The AC/DC converter 1 may be used to constitute a power adapter. Alternatively, an electric device incorporating the AC/DC converter 1 may be constructed. The type of the electric device is not particularly limited, and any device may be used as long as it has the AC/DC converter 1 built therein, for example, an acoustic device, a refrigerator, a washing machine, a vacuum cleaner, and the like.

The switching power supply device of the present invention is not limited to the AC/DC converter, and may be an input voltage V from the primary side using a transformer TR_INGenerating an output voltage V on the secondary side in an insulated manner_OUTThe insulation type DC/DC converter of (1) may be based on the inputInput voltage V_INGenerating an output voltage V_OUTThe non-insulated type DC/DC converter of (1).

Example EX2_3

An embodiment EX2_3 will be explained. In a form not to impair the above object, the relationship between the high level and the low level may be reversed for any signal or voltage.

The embodiments of the present invention can be modified in various ways as appropriate within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meaning of the present invention or each component term is not limited to the contents described in the above embodiments. The specific numerical values shown in the above description are examples only, and it is needless to say that they may be changed to various numerical values.

Description of the symbols

1 AC/DC converter (switching power supply device)

14 switching transistor (switching element)

16 Primary side control circuit (switch control circuit)

100 main control part

110 set signal generating part

120 reset signal generating part

130 driving part

140 current detection unit.

Claims (13)

1. A switching control circuit for generating an output voltage by switching a switching element in accordance with an input voltage applied to a series circuit of an inductor and the switching element,

the switch control circuit has:

a current detection unit that detects a current flowing through the switching element as a target current; and

a control unit that performs a PWM operation or a burst operation for switching the switching element at a set switching frequency in accordance with a feedback voltage corresponding to a load size to which the output voltage is supplied,

the control unit includes:

a set signal generating section that generates a set signal instructing to turn on the switching element;

a reset signal generating section that generates a reset signal instructing to turn off the switching element; and

a drive unit that supplies a signal for turning the switching element on to the switching element when receiving the set signal and supplies a signal for turning the switching element off to the switching element when receiving the reset signal,

in the burst operation, the control unit stops switching of the switching element at the switching frequency,

in the burst operation, the set signal generating unit generates the set signal based on the feedback voltage, and the reset signal generating unit generates the reset signal when the value of the target current exceeds a turn-off threshold,

the reset signal generation unit increases the turn-off threshold value with time in a predetermined interval after the set signal is generated.

2. The switch control circuit of claim 1,

the turn-off threshold has a value corresponding to the feedback voltage.

3. The switch control circuit according to claim 1 or 2,

the reset signal generation unit generates a shutdown threshold signal indicating the shutdown threshold by adding a slope compensation signal whose signal value increases with time in the predetermined interval to a signal proportional to the feedback voltage,

in the burst operation, the reset signal generating unit generates the reset signal by comparing a current detection signal indicating a value of the target current with the off-threshold signal.

4. The switch control circuit of claim 3,

the set signal generating section includes: an oscillator that generates a signal of the switching frequency,

in the PWM operation, the set signal generator generates the set signal at the switching frequency using the oscillator,

in the PWM operation, the reset signal generating unit generates the reset signal based on the current detection signal, the shutdown threshold signal, and an overcurrent threshold signal indicating a predetermined overcurrent threshold.

5. The switch control circuit of claim 4,

the reset signal generating section includes:

a first comparator that compares the current detection signal with the off-threshold signal; and

a second comparator that compares the current detection signal with the overcurrent threshold signal,

in the PWM operation, the reset signal generation unit generates the reset signal when the value of the target current is larger than the shutdown threshold or the overcurrent threshold, based on the comparison results of the first comparator and the second comparator.

6. The switch control circuit according to claim 4 or 5,

the reset signal generation unit generates the off-threshold signal by adding a first slope compensation signal whose signal value increases with time in the predetermined interval and a signal proportional to the feedback voltage, and generates the overcurrent-threshold signal by adding a second slope compensation signal whose signal value increases with time in the predetermined interval and a signal having a predetermined value.

7. The switch control circuit according to any one of claims 1 to 6,

as the load size decreases, the feedback voltage decreases,

the control unit continues the PWM operation when the feedback voltage is kept higher than a predetermined burst determination voltage, and starts the burst operation when the feedback voltage is lower than the burst determination voltage.

8. The switch control circuit of claim 7,

the control unit starts the burst operation upon receiving a transition of the feedback voltage from a state higher than the burst determination voltage to a state lower than the burst determination voltage, maintains the switching element in an off state until the feedback voltage exceeds a predetermined burst release voltage higher than the burst determination voltage after the burst operation starts, generates the set signal by the set signal generation unit when the feedback voltage exceeds the burst release voltage, and then generates the reset signal by the reset signal generation unit upon receiving a transition of the value of the target current exceeding an off threshold.

9. The switch control circuit according to any one of claims 1 to 6,

as the load size decreases, the feedback voltage rises,

the control unit continuously executes the PWM operation when the feedback voltage is kept lower than a predetermined burst determination voltage, and starts the burst operation when the feedback voltage exceeds the burst determination voltage.

10. The switch control circuit of claim 9,

the control unit starts the burst operation upon receiving a transition of the feedback voltage from a state lower than the burst determination voltage to a state higher than the burst determination voltage, maintains the switching element in an off state until the feedback voltage is lower than a predetermined burst release voltage lower than the burst determination voltage after the burst operation starts, generates the set signal by the set signal generation unit when the feedback voltage is lower than the burst release voltage, and then generates the reset signal by the reset signal generation unit upon receiving a transition of the value of the target current to a state higher than an off threshold value.

11. The switch control circuit according to any one of claims 1 to 10,

the output voltage is generated on the secondary side in accordance with the input voltage applied to the primary side using a transformer having the inductance as a primary winding and having a secondary winding.

12. A switching power supply apparatus which generates an output voltage on a secondary side in accordance with an input voltage applied to a primary side by a switching method using a transformer having a primary winding and a secondary winding,

the switching power supply device includes:

a switching element connected in series with the primary winding as an inductor;

the switch control circuit of any one of claims 1-11; and

a feedback voltage generation circuit that generates the feedback voltage from the output voltage.

13. The switching power supply device according to claim 12,

the input voltage is generated by rectifying and smoothing an alternating voltage.

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