JP7123733B2 - power control unit - Google Patents

Description

The invention disclosed in this specification relates to a power control device.

2. Description of the Related Art Conventionally, a power supply control device (so-called power supply IC) has been widely used as a control body for an isolated switching power supply.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2014-112996 A

However, in the conventional power supply control device, there is room for further improvement in terms of power consumption reduction during light load and no load.

The invention disclosed in this specification provides a power supply control device capable of reducing power consumption during light load and no load in view of the above problems found by the inventors of the present application. for the purpose.

The power supply control device disclosed in this specification is a main control unit for an isolated switching power supply, and includes a first output detection signal corresponding to a DC output voltage to a load, the DC output voltage and its The configuration includes a controller that monitors the second output detection signal corresponding to the difference value from the target value and switches between a plurality of operation modes with different power consumptions according to the results of both monitoring.

Further, the power supply control device disclosed in this specification is a control main body of the isolated switching power supply, and is a peak current switching unit that raises the peak current value of the primary current flowing through the output switch when a light load is detected. It is configured to have

It should be noted that other features, elements, steps, advantages, and characteristics of the present invention will become more apparent from the detailed description of the embodiments that follow and the accompanying drawings related thereto.

According to the invention disclosed in this specification, it is possible to provide a power control device capable of reducing power consumption during light load and no load.

Diagram showing the overall configuration of an electronic device equipped with an isolated switching power supply A diagram showing a configuration example of a power supply IC A diagram showing conditions for switching operation modes in a power supply IC Timing chart showing an example of operation mode switching in a power supply IC A diagram showing a first configuration example of the controller (parts related to operation mode switching) A diagram showing the internal operation state of the power supply IC in the light load mode. Timing chart showing an example of peak current control in light load mode Diagram showing the internal operation state of the power supply IC in no-load mode Timing chart showing an example of peak current control in no-load mode A diagram showing a second configuration example of the controller (parts related to burst control) Timing chart showing an example of burst control in no-load mode FIG. 11 is a diagram showing a configuration example of a gain adjustment section; Diagram showing an example of package layout

<Insulated switching power supply>
FIG. 1 is a diagram showing the overall configuration of an electronic device equipped with an insulated switching power supply. An electronic device X of this configuration example has an insulated switching power supply 1 and a load 2 that receives power from the insulated switching power supply 1 and operates.

The insulated switching power supply 1 electrically insulates between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system), while supplying alternating current from the commercial AC power supply PW to the primary circuit system 1p. Means for converting an input voltage Vac (for example, AC85 to 265V) into a desired DC output voltage Vo (for example, DC10 to 30V) and supplying it to the load 2 of the secondary circuit system 1s. and a conversion unit 20 .

The rectifying unit 10 is a circuit block that generates a DC input voltage Vi (for example, DC 120 to 375 V) from the AC input voltage Vac and supplies it to the DC/DC converting unit 20, and includes a filter 11, a diode bridge 12, a capacitor 13 and 14. Filter 11 removes noise and surge from AC input voltage Vac. Diode bridge 12 full-wave rectifies AC input voltage Vac to generate DC input voltage Vi. Capacitor 13 removes harmonic noise of AC input voltage Vac. Capacitor 14 smoothes the DC input voltage Vi. Note that a protective element such as a fuse may be provided at the front stage of the rectifying section 10 . Further, when the DC input voltage Vi is directly supplied to the insulated switching power supply 1, the rectifying section 10 can be omitted.

The DC/DC conversion unit 20 is a circuit block that generates a desired DC output voltage Vo from the DC input voltage Vi and supplies it to the load 2. The power supply IC 100 and various discrete components (transformer TR , resistors R1 to R8, capacitors C1 to C4, diodes D1 to D4, an N-channel MOS [metal oxide semiconductor] field effect transistor N1, a light emitting diode LED, a phototransistor PT, and a shunt regulator REG).

The transformer TR includes a primary winding L1 (number of turns Np) and a secondary winding L2 (number of turns Ns) magnetically coupled with opposite polarities while electrically insulating the primary circuit system 1p and the secondary circuit system 1s. including. Transformer TR also includes an auxiliary winding L3 (number of turns Nd) provided in primary circuit system 1p as means for generating power supply voltage Vcc for power supply IC 100 .

A first end of the primary winding L1 is connected to the application end of the DC input voltage Vi (=the output end of the diode bridge 12). A second end of the primary winding L11 is connected to the drain of the transistor N1. A first end of secondary winding L2 is connected to the anode of diode D4. A second end of the secondary winding L2 is connected to a ground terminal GND2 of the secondary circuit system 1s.

Note that the number of turns Np and Ns may be arbitrarily adjusted so as to obtain a desired DC output voltage Vo. For example, the larger the number of turns Np or the smaller the number of turns Ns, the lower the DC output voltage Vo. Conversely, the smaller the number of turns Np or the larger the number of turns Ns, the higher the DC output voltage Vo.

The power supply IC 100 is a semiconductor integrated circuit device provided in the primary circuit system 1p, and corresponds to a power supply control apparatus that controls the insulated switching power supply 1 (especially the DC/DC conversion section 20). The power supply IC 100 has external terminals T1 to T8 as means for establishing electrical connection with the outside of the device. Of course, the power supply IC 100 may be provided with external terminals other than those described above.

An external terminal T1 (auxiliary winding monitor/external latch stop terminal) is connected to a connection node (=application terminal of monitor voltage Vm) between resistors R1 and R2. The resistors R1 and R2 are connected in series between the first end (=applying end of the induced voltage Vp) and the second end (=grounding end GND1 of the primary circuit system 1p) of the auxiliary winding L3. there is The resistors R1 and R2 connected in this manner are divided voltages for outputting a monitor voltage Vm (={R2/(R1+R2)}×Vp) corresponding to the induced voltage Vp of the auxiliary winding L3 from the mutual connection node. functions as a department.

Here, if the voltage value of the induced voltage Vp during the ON period of the transistor N1 is Vpon, and the voltage value of the induced voltage Vp during the OFF period of the transistor N1 is Vpoff, then Vpon≈−Vi×(Nd/Np), Vpoff. ≈Vo×(Nd/Ns).

That is, the voltage value Vpon fluctuates according to the DC input voltage Vi, and the voltage value Vpoff fluctuates depending on the DC output voltage Vo. Therefore, for example, during the OFF period of the transistor N1, by monitoring the monitor voltage Vm corresponding to the induced voltage Vp, the overvoltage protection of the DC output voltage Vo can be applied, or the operation mode can be switched according to the DC output voltage Vo. later) can be performed.

Thus, the circuit element group (TR and R1 to R2) is the first output detection signal that generates the monitor voltage Vm (=corresponding to the first output detection signal) corresponding to the absolute value of the DC output voltage Vo. functions as a department.

The external terminal T2 (=feedback signal input terminal) is connected to the collector of the phototransistor PT and the first end of the capacitor C1. Both the emitter of the phototransistor PT and the second end of the capacitor C1 are connected to the ground terminal GND1. The phototransistor PT functions as a photocoupler together with the light emitting diode LED provided in the secondary circuit system 1s, and generates a feedback current Ifb according to the optical signal from the light emitting diode LED.

An external terminal T3 (=primary current sense terminal) is connected to the source and back gate of the transistor N1 and the first end of the resistor R3. A second end of the resistor R3 is connected to the ground terminal GND1. Note that the resistor R3 functions as a sense resistor for detecting the primary current Ip flowing through the transistor N1 as a sense voltage Vcs (=Ip×R3).

The external terminal T4 (=ground terminal) is connected to the ground terminal GND1.

The external terminal T5 (=external MOS drive terminal) is connected to the gate of the transistor N1 and outputs the gate signal G1 to the outside. The transistor N1 turns on/off the primary current Ip flowing through the primary winding L1 by conducting/interrupting a current path from the terminal to which the DC input voltage Vi is applied to the ground terminal GND1 via the primary winding L1. output switch. The transistor N1 is turned on when the gate signal G1 is at high level and turned off when the gate signal G1 is at low level.

The external terminal T6 (=power supply terminal) is connected to a connection node (=application terminal of power supply voltage Vcc) between the cathode of the diode D1 and the first end of the capacitor C2. The anode of diode D1 is connected to the first end of auxiliary winding L3. A second end of the capacitor C2 is connected to the ground terminal GND1. The diode D1 and the capacitor C2 connected in this manner function as a power supply voltage generator that rectifies and smoothes the induced voltage Vp generated in the auxiliary winding L3 to generate the power supply voltage Vcc of the power supply IC100. The winding ratio between the primary winding L1 and the auxiliary winding L3 of the transformer TR may be appropriately set in consideration of the power supply voltage Vcc required for the power supply IC100.

The external terminal T7 (non-connect terminal) is not connected anywhere.

The external terminal T8 (=activation/AC input voltage monitor terminal) is connected to the first end (=application end of high voltage VH) of the resistor R4. A second end of resistor R4 is connected to the cathodes of diodes D2 and D3. The anodes of the diodes D2 and D3 are connected to the positive and negative input terminals of the diode bridge 12 (=applying terminal of the AC input voltage Vac).

Next, the connection relationship of the circuit elements provided in the secondary circuit system 1s will be described.

The anode of diode D4 is connected to the first end of secondary winding L2 as previously described. The cathode of the diode D4 and the first end of the capacitor C3 are both connected to the output end of the DC output voltage Vo. A second end of the capacitor C3 is connected to the ground terminal GND2. The diode D4 and capacitor C3 connected in this manner function as a rectifying/smoothing section that rectifies and smoothes the induced voltage Vs generated in the secondary winding L2 to generate the DC output voltage Vo.

A first end of the resistor R5 is connected to the output end of the DC output voltage Vo. A second end of the resistor R5 is connected to the anode of the light emitting diode LED. The cathode of the light emitting diode LED is connected to the cathode of the shunt regulator REG. The anode of the shunt regulator REG is connected to the ground terminal GND2. The gate (=corresponding to the control terminal) of the shunt regulator REG is a connection node (=applying the divided voltage Vod end, Vod={R8/(R7+R8)}*Vo). A resistor R6 and a capacitor C4 are connected in series between the gate and cathode of the shunt regulator REG.

The shunt regulator REG controls the driving current ILED of the light emitting diode LED so that the divided voltage Vod applied to the gate and the predetermined internal reference voltage VoREF are imaginarily shorted.

More specifically, when Vod>VoREF, the drive current ILED increases as the difference between them (=|Vod-VoREF|) increases. As a result, the light emission of the light emitting diode LED becomes stronger, and the feedback current Ifb flowing through the phototransistor PT increases. On the other hand, when Vod<VoREF, the drive current ILED is reduced as the difference between them (=|Vod−VoREF|) increases. As a result, the light emission of the light emitting diode LED becomes weaker, and the feedback current Ifb flowing through the phototransistor PT is reduced.

That is, the above circuit element group (R5 to R8, C4, LED, REG, and PT) is determined according to the difference between the DC output voltage Vo and its target value (={(R7+R8)/R8}×VoREF). function as a second output detection section that generates a feedback current Ifb (=corresponding to a second output detection signal).

In addition, the insulated switching power supply 1 of this configuration example incorporates a function of performing variable control of the DC output voltage Vo according to the operating state of the electronic device X. FIG. By implementing such a function, it becomes possible to realize low standby power consumption of the electronic device X. FIG.

Note that the power supply IC 100 provided in the primary circuit system 1p does not have the function of setting the target value of the DC output voltage Vo. Therefore, variable control of the DC output voltage Vo is performed by the secondary circuit system 1s. This figure illustrates a configuration in which the DC output voltage Vo is variably controlled by adjusting the resistance value of the resistor R8 using a microcomputer to switch the voltage dividing ratio of the divided voltage Vod. The variable control method is not limited to this at all.

In the DC/DC converter 20 configured as described above, the transistor N1, the transformer TR, the diode D4, and the capacitor C3 form a flyback step-down switching output stage that generates the DC output voltage Vo from the DC input voltage Vi. function as

A step-down operation of the switching output stage will be briefly described. When the transistor N1 is turned on, the primary current Ip flows from the terminal to which the DC input voltage Vi is applied to the ground terminal GND1 through the primary winding L1, the transistor N1, and the resistor R3. is stored.

After that, when the transistor N1 is turned off, an induced voltage Vs is generated in the secondary winding L2 magnetically coupled with the primary winding L1, and a voltage Vs is generated from the secondary winding L2 to the ground terminal GND2 via the diode D4. The following current Is flows. At this time, the load 2 is supplied with the DC output voltage Vo obtained by rectifying and smoothing the induced voltage Vs of the secondary winding L2.

After that, the switching operation similar to the above is repeated by turning on/off the transistor N1.

As described above, according to the isolated switching power supply 1 of this configuration example, the DC output voltage Vo is generated from the AC input voltage Vac while electrically insulating the primary circuit system 1p and the secondary circuit system 1s. can be supplied to the load 2.

<Power supply IC>
FIG. 2 is a diagram showing a configuration example of the power supply IC 100. As shown in FIG. The power supply IC 100 of this configuration example includes comparators 101 to 108, a starter 109, a controller 110, an RS flip-flop 111, a driver 112, a gain adjustment section 113, a slope compensation section 114, an addition section 115, An oscillator 116, a maximum duty setting section 117, a resistor 118, and a P-channel MOS field effect transistor 119 are integrated.

The comparator 101 compares the monitor voltage Vm input from the external terminal T1 to the non-inverting input terminal (+) with the threshold voltage Vth1 (=corresponding to the overvoltage detection value) input to the inverting input terminal (-). An overvoltage detection signal S1 is generated. The overvoltage detection signal S1 becomes high level when Vm>Vth1, and becomes low level when Vm<Vth1.

The comparator 102 selects a monitor voltage Vm input to the non-inverting input terminal (+) from the external terminal T1 and a threshold voltage Vth2 (<Vth1, corresponding to the light load detection value) input to the inverting input terminal (-). A light load detection signal S2 is generated by comparison. The light load detection signal S2 becomes high level when Vm>Vth2, and becomes low level when Vm<Vth1.

The comparator 103 selects a monitor voltage Vm input to the non-inverting input terminal (+) from the external terminal T1 and a threshold voltage Vth3 (<Vth2, corresponding to the no-load detection value) input to the inverting input terminal (-). A no-load detection signal S3 is generated by comparison. The no-load detection signal S3 becomes high level when Vm>Vth3, and becomes low level when Vm<Vth3.

The comparator 104 compares the feedback voltage Vfb input to the non-inverting input terminal (+) from the external terminal T2 with the threshold voltage Vth4 (=corresponding to the immediate return detection value) input to the inverting input terminal (-). to generate an immediate return detection signal S4. The immediate return detection signal S4 becomes high level when Vfb>Vth4, and becomes low level when Vfb<Vth4.

The comparator 105 compares the feedback voltage Vfb input to the inverting input terminal (-) from the external terminal T2 with the threshold voltage Vth5 (<Vth4, corresponding to the burst detection value) input to the non-inverting input terminal (+). to generate a burst detection signal S5. Therefore, the burst detection signal S5 becomes high level when Vfb<Vth5, and becomes low level when Vfb>Vth5.

Comparator 106 receives reference voltage Vref input to non-inverting input terminal (+) from adding section 115 and divided feedback voltage Vfb2 (=α×Vfb, However, 0<α<1) is compared to generate an off-timing signal S6. The off-timing signal S6 becomes high level when Vref>Vfb2, and becomes low level when Vref<Vfb2.

The comparator 107 compares the sense voltage Vcs input to the non-inverting input terminal (+) from the external terminal T3 with the threshold voltage Vth7 (=corresponding to the overload detection value) input to the inverting input terminal (-). to generate an overload detection signal S7. The overload detection signal S7 becomes high level when Vcs>Vth7, and becomes low level when Vcs<Vth7.

The comparator 108 compares the sense voltage Vcs input to the non-inverting input terminal (+) from the external terminal T3 with the threshold voltage Vth8 (=corresponding to the overcurrent detection value) input to the inverting input terminal (-). to generate an overcurrent detection signal S8. The overcurrent detection signal S8 becomes high level when Vcs>Vth8, and becomes low level when Vcs<Vth8.

Although not shown in the figure, a mask processing unit may be provided in the front stage of the comparators 107 and 108 to fix the sense voltage Vcs at a zero value for a predetermined mask period after the output switch 129 is turned on. good. With such a configuration, the ringing noise of the sense voltage Vcs generated when the transistor N1 is turned on can be avoided.

The starter 109 activates the external terminal T8 when the power supply voltage Vcc drops below a predetermined threshold voltage immediately after starting the insulated switching power supply 1 or in the light load mode or no load mode of the power supply IC 100 (details will be described later). The power supply voltage Vcc is raised by charging or recharging the capacitor C2 externally attached to the external terminal T6 using the voltage VH.

The controller 110 centrally controls the operation of each part of the power supply IC 100 . For example, focusing on the on-duty control of the transistor N1, the controller 110 controls the drive clock signal CLK (=on-timing signal) input from the oscillator 116, the off-timing signal S6 input from the comparator 106, and the maximum duty cycle. Based on the maximum duty setting signal Dmax input from the setting section 117, pulses of the set signal S9 and the reset signal S10 are generated.

Focusing on the abnormality protection function of the power supply IC 100, the controller 110 performs resetting to forcibly turn off the transistor N1 based on the overvoltage detection signal S1, the overload detection signal S7, and the overcurrent detection signal S8. The signal S10 is fixed to the off logic level.

Focusing on the operation mode switching function (details will be described later) of the power supply IC 100, the controller 110 detects a plurality of power consumption different power based on the light load detection signal S2, the no load detection signal S3, and the immediate return detection signal S4. operating modes (= normal mode and at least one power saving mode).

Further, the controller 110 also has a function of determining whether or not to perform burst control (=intermittent control) of the transistor N1 based on the burst detection signal S5. More specifically, the controller 110 basically keeps the transistor N1 off while the burst detection signal S5 is at high level.

The RS flip-flop 111 outputs PWM [pulse width modulation ] Switches the logic level of the signal S11. Specifically, the RS flip-flop 111 sets the PWM signal S11 to high level when the set signal S9 rises to high level, and sets the PWM signal S11 to low level when the reset signal S10 rises to high level. reset to

The driver 112 receives the PWM signal S11 to generate the gate signal G1 and outputs it to the external terminal T5. More specifically, the driver 112 sets the gate signal G1 to high level when the PWM signal S11 is at high level, and sets the gate signal G1 to low level when the PWM signal S11 is at low level.

The gain adjustment unit 113 divides the feedback voltage Vfb input from the external terminal T2 by a predetermined gain α (=voltage dividing ratio α) to generate a divided feedback voltage Vfb2 (=α×Vfb). The gain adjustment unit 113 has a function of switching the gain α according to the operation mode of the power supply IC 100 (details will be described later).

The slope compensator 114 generates a slope voltage Vslp having a triangular wave, a sawtooth wave, or an n-order slope wave (for example, n=2) in synchronization with the drive clock signal CLK.

Addition unit 115 adds sense voltage Vcs (=voltage signal simulating the behavior of primary current Ip) input from external terminal T3 and slope voltage Vslp input from slope compensation unit 114 to generate reference voltage Vref. do. By adopting such a configuration, output feedback control of the current mode system is performed, so that it is possible to improve the stability of the output feedback loop and improve the transient response characteristics when the load fluctuates. However, if voltage-mode output feedback control is sufficient, the adder 115 can be omitted.

The oscillator 116 generates a drive clock signal CLK for the controller 110 and outputs it to the controller 110 . Note that the oscillator 116 has a function of monitoring the divided feedback voltage Vfb2 and raising the oscillation frequency of the drive clock signal CLK for a certain period of time during peak load (=when the load becomes heavier than during normal operation). Good. With such a function, it is possible to reduce the cost of the transistor N1 and reduce the size of the transformer TR.

The maximum duty setting unit 117 generates a maximum duty setting signal Dmax for limiting the on-duty Don of the transistor N1 (=ratio of the on-period Ton in the switching period T) to a predetermined upper limit value or less, and outputs the signal Dmax to the controller 110. do.

A resistor 118 (resistance value: R118) is connected between the application end of the constant voltage Vreg and the external terminal T2, and converts the feedback current Ifb flowing through the external terminal T2 to the feedback voltage Vfb (=Vreg−Ifb×R118). It is a current/voltage conversion element that converts. Therefore, the feedback voltage Vfb decreases as the feedback current Ifb increases, and increases as the feedback current Ifb decreases.

The source and backgate of the transistor 119 are connected to the constant voltage Vreg application terminal. The drain of transistor 119 is connected to one end of resistor 118 . The gate of transistor 119 is connected to the input terminal of power save signal PS. The transistor 119 connected in this manner conducts/disconnects the current path through which the feedback current Ifb flows according to the power save signal PS. More specifically, the transistor 119 turns on when the power save signal PS is at low level and turns off when the power save signal PS is at high level.

In addition to the components described above, the power supply IC 100 also includes a constant voltage generation circuit, a charge pump circuit, a brownout circuit, a soft start circuit, an AC input compensation circuit, a frequency hopping circuit, and a , various protection circuits (UVLO [under voltage lock out] circuit, etc.) may be integrated.

<On-duty control>
Next, the on-duty control of the transistor N1 will be briefly described. As described above, when Vod>VoREF, the larger the difference between the two (=|Vod−VoREF|), the larger the driving current ILED and therefore the feedback current Ifb. When the feedback current Ifb increases, the feedback voltage Vfb decreases and the crossing timing with the reference voltage Vref is advanced. Therefore, the rise timing of the off-timing signal S6 is advanced, and the rise timing of the reset signal S10 is advanced. As a result, the fall timing of the PWM signal S11 (and thus the gate signal G1) is advanced, and the on-duty Don of the transistor N1 is reduced, thereby reducing the DC output voltage Vo.

Conversely, when Vod<VoREF, the drive current ILED decreases as the difference between the two (=|Vod−VoREF|) increases, so the feedback current Ifb also decreases. When the feedback current Ifb decreases, the feedback voltage Vfb increases, delaying the crossing timing with the reference voltage Vref. Therefore, the rise timing of the off-timing signal S6 is delayed, and the rise timing of the reset signal S10 is delayed. As a result, the fall timing of the PWM signal S11 (and thus the gate signal G1) is delayed, and the on-duty Don of the transistor N1 is increased, thereby increasing the DC output voltage Vo.

Through such on-duty control, the DC output voltage Vo can be maintained at its target value (={(R7+R8)/R8}×VoREF).

Among various components integrated in the power supply IC 100, the comparator 106, the controller 110, the RS flip-flop 111, the driver 112, the gain adjustment section 113, the slope compensation section 114, and the resistor 118 are the feedback current Ifb (= It functions as an on-duty control section that controls the on-duty Don of the transistor N1 based on the second output detection signal).

<Operation mode switching>
Next, operation mode switching of the power supply IC 100 will be described. As described above, the controller 110 has a function of switching between a plurality of operation modes with different power consumption based on the light load detection signal S2, the no-load detection signal S3, and the immediate return detection signal S4. .

In the following, the explanation will be continued taking as an example the case where the normal mode (MODE 1), the light load mode (MODE 2) and the no-load mode (MODE 3) are provided as the plurality of operation modes. Note that the light load mode (MODE2) is a first power saving mode that consumes less power than the normal mode (MODE2), and the no-load mode (MODE3) consumes even more power than the light load mode (MODE2). A second low power saving mode (details of each are provided below).

FIG. 3 is a diagram showing conditions for switching operation modes in the power supply IC 100. As shown in FIG. When the power supply IC 100 is in the normal mode (MODE1), the monitor voltage Vm of the transistor N1 (more precisely, the monitor voltage Vm during the off period of the transistor N1, the same shall apply hereinafter) is lower than the threshold voltage Vth2, that is, the light When the period in which the pulse edge of the load detection signal S2 is not detected continues over the determination time Tc1, the power supply IC 100 shifts from the normal mode (MODE1) to the light load mode (MODE2). Conversely, when the power supply IC 100 is in the light load mode (MODE2), the monitor voltage Vm is higher than the threshold voltage Vth2, that is, the pulse edges of the light load detection signal S2 are periodically detected. When the period continues over the determination time Tc1, the power supply IC 100 returns from the light load mode (MODE2) to the normal mode (MODE1).

Further, when the power supply IC 100 is in the light load mode (MODE2), the state in which the monitor voltage Vm is lower than the threshold voltage Vth3, that is, the period in which the pulse edge of the no-load detection signal S3 is not detected continues over the determination time Tc1. Then, the power supply IC 100 shifts from the light load mode (MODE2) to the no-load mode (MODE3). Conversely, when the power supply IC 100 is in the no-load mode (MODE3), the monitor voltage Vm is higher than the threshold voltage Vth3, that is, the pulse edge of the no-load detection signal S3 is periodically detected. When the period continues over the determination time Tc1, the power supply IC 100 returns from the no-load mode (MODE3) to the light-load mode (MODE2).

Thus, the controller 110 switches between the normal mode (MODE1) and the light load mode (MODE2), or The operation mode of the power supply IC 100 is switched between the light load mode (MODE2) and the no-load mode (MODE3).

As described above, the monitor voltage Vm during the OFF period of the transistor N1 fluctuates depending on the DC output voltage Vo. Therefore, according to the above operation mode switching, for example, when the DC output voltage Vo is lowered in the secondary circuit system 1s, this can be detected and the power consumption of the power supply IC 100 can also be lowered. It is possible to achieve further reduction in standby power consumption of the entire system.

In the power supply IC 100, the monitor voltage Vm for overvoltage detection is also used for operation mode switching, so the number of external terminals does not need to be increased.

Further, even if the power supply IC 100 is in the light load mode (MODE2) or the no-load mode (MODE3), the feedback voltage Vfb is higher than the threshold voltage Vth4, that is, the immediate return detection signal S4 is at high level. If this continues over the predetermined determination time Tc2, the power supply IC 100 immediately returns to the normal mode (MODE1).

It should be noted that the term "immediate return" in this specification means that even in the no-load mode (MODE 3), the normal mode (MODE 1) is restored without going through the light load mode (MODE 2), regardless of the monitoring result of the monitor voltage Vm. not only when the immediate return detection signal S4 rises to the high level, the normal mode (MODE1) is immediately restored, but also when the normal mode is restored after the predetermined determination time Tc2 as described above. It also includes the case of returning to (MODE 1).

In this manner, the controller 110 immediately returns to the normal mode (MODE1) according to the monitoring result (=immediate return detection signal S4) of the feedback current Ifb (and thus the feedback voltage Vfb). Therefore, when the target value of the DC output voltage Vo is increased in the secondary circuit system 1s, the power supply IC 100 can be returned to the normal mode (MODE 1) without delay and the power supplied to the load 2 can be increased. 2 is heavy, the DC output voltage Vo can be raised without any trouble.

FIG. 4 is a timing chart showing an example of operation mode switching in the power supply IC 100. From the top, gate signal G1, switch voltage Vsw (=drain voltage of transistor N1), monitor voltage Vm, mask signal MASK (=controller 110). internal signal), a light load detection signal S2, a no-load detection signal S3, and an operation mode (MODE) of the power supply IC 100 are depicted.

The mask signal MASK is a binary signal for masking the light load detection signal S2 and the no-load detection signal S3 (=signal processing for extracting only the logic level during the OFF period of the transistor N1). , the gate signal G1 becomes high level (=the logic level when the mask is released) for a predetermined monitoring period after the gate signal G1 is lowered to low level. Therefore, in this figure, as the light load detection signal S2 and the no-load detection signal S3, not the output signals of the comparators 102 and 103 as they are, but masked signals are depicted.

When the target value of the DC output voltage Vo is set to the normal value in the secondary circuit system 1s, Vm>Vth2 during the OFF period of the transistor N1 (=low level period of the gate signal G1). At this time, periodic pulses appear in the light load detection signal S2 and the no-load detection signal S3. Controller 110 maintains power supply IC 100 in normal mode (MODE 1) while these pulses are being detected.

On the other hand, when the target value of the DC output voltage Vo is lowered by one step in the secondary circuit system 1s, Vth3<Vm<Vth2 during the OFF period of the transistor N1. At this time, periodic pulses appear in the no-load detection signal S3 as before, but the light-load detection signal S2 stays low. The controller 110 shifts the power supply IC 100 from the normal mode (MODE1) to the light load mode (MODE2) when this state continues for a predetermined determination time Tc1.

Further, when the target value of the DC output voltage Vo is lowered by one step in the secondary circuit system 1s, Vm<Vth3 during the OFF period of the transistor N1. At this time, not only the light load detection signal S2 but also the no-load detection signal S3 are stuck at the low level. The controller 110 shifts the power supply IC 100 from the light load mode (MODE2) to the no-load mode (MODE3) when this state continues for the predetermined determination time Tc1.

<Controller (first configuration example)>
FIG. 5 is a diagram showing a first configuration example of the controller 110. As shown in FIG. The controller 110 of this configuration example includes an edge detection unit a, a first timer unit b, a second timer unit c, and an operation mode switching unit d as functional blocks related to switching the operation mode of the power supply IC 100. .

The edge detector a is a circuit block that detects pulse edges (for example, rising edges) of the light load detection signal S2 and the no-load detection signal S3, and includes an inverter a1 and D flip-flops a2 to a5.

The inverter a1 logically inverts the output state signal Nout to generate an inverted output state signal NoutB. Therefore, the inverted output state signal NoutB becomes low level when the output state signal Nout is high level, and becomes high level when the output state signal Nout is low level. The output state signal Nout is a signal indicating the ON/OFF state of the transistor N1, and for example, becomes high level during the ON period of the transistor N1 and becomes low level during the OFF period of the transistor N1. Note that the output state signal Nout may be generated by level-shifting the gate signal G1, for example.

The D flip-flop a2 latches the high level signal input to the data input terminal (D) when the light load detection signal S2 input to the clock input terminal rises to a high level, and outputs the result as an edge signal. It is output from the output terminal (Q) as the detection signal Sa2.

The D flip-flop a3 latches the high level signal input to the data input terminal (D) when the no-load detection signal S3 input to the clock input terminal rises to a high level, and outputs the result as an edge signal. It is output from the output terminal (Q) as the detection signal Sa3.

Also, the D flip-flops a2 and a3 are reset by an inverted output state signal NoutB input to their respective reset input terminals. Specifically, the D flip-flops a2 and a3 are in the reset state (Sa2=Sa3=L) during the low level period of the inverted output state signal NoutB (=on period of the transistor N1), and the high level of the inverted output state signal NoutB. During the level period (=off period of the transistor N1), the reset release state is established.

The D flip-flop a4 latches the edge detection signal Sa2 input to the data input terminal (D) when the output state signal Nout input to the clock input terminal rises to a high level, and outputs the result as an edge detection signal. It is output from the output terminal (Q) as the detection signal Sa4.

The D flip-flop a5 latches the edge detection signal Sa3 input to the data input terminal (D) when the output state signal Nout input to the clock input terminal rises to a high level, and outputs the result as an edge detection signal. It is output from the output terminal (Q) as the detection signal Sa5.

Also, the D flip-flops a4 and a5 are reset by an enable signal EN input to their respective reset input terminals. Specifically, the D flip-flops a4 and a5 are reset (Sa4=Sa5=L) during the low level period of the enable signal EN (=disable period of the power supply IC 100), and during the high level period of the enable signal EN ( = enable period of the power supply IC 100).

The first timer section b is a circuit block that counts a predetermined judgment time Tc1, and includes timers b1 to b4, RS flip-flops b5 and b6, and inverters b7 to b10.

The timer b1 is for judging transition from the normal mode (MODE1) to the light load mode (MODE2). (corresponding to the determination time Tc1), the set signal Sb1 rises to a high level. However, the timer b1 is reset by the inverted edge detection signal Sa4B input to the reset input terminal. More specifically, the timer b1 is reset during the low level period of the inverted edge detection signal Sa4B (=the period during which the pulse edge of the light load detection signal S2 is periodically detected), and the inverted edge detection signal Sa4B (=a period during which the pulse edge of the light load detection signal S2 is not detected), the reset is released. Therefore, the set signal Sb1 rises to high level when the inverted edge detection signal Sa4B is maintained at high level over the determination time Tc1.

The timer b2 is for judging return from the light load mode (MODE2) to the normal mode (MODE1). (corresponding to the determination time Tc1), the reset signal Sb2 rises to a high level. However, the timer b2 is reset by the edge detection signal Sa4 input to the reset input terminal. Specifically, the timer b2 is reset during the low level period of the edge detection signal Sa4 (=the period during which the pulse edge of the light load detection signal S2 is not detected), and during the high level period of the edge detection signal Sa4 (=the light load period). During the period in which the pulse edge of the detection signal S2 is periodically detected, the reset is released. Therefore, the reset signal Sb2 rises to high level when the edge detection signal Sa4 is maintained at high level over the determination time Tc1.

The timer b3 is for judging transition from the light load mode (MODE2) to the no-load mode (MODE3), counts the number of clock pulses CK input to the clock input terminal, and the count value reaches a predetermined value ( (corresponding to the judgment time Tc1), the set signal Sb3 rises to a high level. However, the timer b3 is reset by the inverted edge detection signal Sa5B input to the reset input terminal. More specifically, the timer b3 is reset during the low level period of the inverted edge detection signal Sa5B (=the period during which the pulse edge of the no-load detection signal S3 is periodically detected), and the inverted edge detection signal Sa5B (=a period during which the pulse edge of the no-load detection signal S3 is not detected), the reset is released. Therefore, the set signal Sb3 rises to high level when the inverted edge detection signal Sa5B is maintained at high level over the determination time Tc1.

The timer b4 is used to determine return from the no-load mode (MODE3) to the light-load mode (MODE2). (corresponding to the judgment time Tc1), the reset signal Sb4 rises to a high level. However, the timer b4 is reset by the edge detection signal Sa5 input to the reset input terminal. More specifically, the timer b4 is reset during the low level period of the edge detection signal Sa5 (=the period during which the pulse edge of the no-load detection signal S3 is not detected), and is reset during the high level period (=no load detection signal S3) of the edge detection signal Sa5. During the period in which the pulse edge of the load detection signal S3 is periodically detected, the reset is released. Therefore, the reset signal Sb4 rises to high level when the edge detection signal Sa5 is maintained at high level over the determination time Tc1.

The RS flip-flop b5 converts the transition return signal Sb5 output from the output terminal (Q) according to the set signal Sb1 input to the set terminal (S) and the reset signal Sb2 input to the reset terminal (R). Switch logic levels. Specifically, the RS flip-flop b5 sets the transition return signal Sb5 to a high level when the set signal Sb1 rises to a high level, and sets the transition return signal Sb5 to a high level when the reset signal Sb2 rises to a high level. Reset to low level. That is, the transition return signal Sb5 rises to a high level at the timing of transition from the normal mode (MODE1) to the light load mode (MODE2), and goes low at the timing to return from the light load mode (MODE2) to the normal mode (MODE1). fall to the level.

The RS flip-flop b6 outputs a transition return signal Sb6 output from its output terminal (Q) according to a set signal Sb3 input to its set terminal (S) and a reset signal Sb4 input to its reset terminal (R). Switch logic levels. More specifically, the RS flip-flop b6 sets the transition restoration signal Sb6 to a high level when the set signal Sb3 rises to a high level, and sets the transition restoration signal Sb6 to a high level when the reset signal Sb4 rises to a high level. reset to low level. That is, the transition return signal Sb6 rises to a high level at the timing of transition from the light load mode (MODE2) to the no-load mode (MODE3), and the timing at which the no-load mode (MODE3) should return to the light load mode (MODE2). to a low level.

The inverter b7 logically inverts the edge detection signal Sa4 to generate an inverted edge detection signal Sa4B. Therefore, the inverted edge detection signal Sa4B becomes low level when the edge detection signal Sa4 is high level, and becomes high level when the edge detection signal Sa4 is low level.

The inverter b8 logically inverts the edge detection signal Sa5 to generate an inverted edge detection signal Sa5B. Therefore, the inverted edge detection signal Sa5B becomes low level when the edge detection signal Sa5 is high level, and becomes high level when the edge detection signal Sa5 is low level.

Inverter b9 logically inverts transition return signal Sb5 to generate inverted transition return signal Sb5B. The inverted transition return signal Sb5B becomes low level when the transition return signal Sb5 is at high level, and becomes high level when the transition return signal Sb5 is at low level.

Inverter b10 logically inverts transition return signal Sb6 to generate inverted transition return signal Sb6B. The inverted transition return signal Sb6B becomes low level when the transition return signal Sb6 is at high level, and becomes high level when the transition return signal Sb6 is at low level.

The second timer section c is a circuit block that counts a predetermined determination time Tc2, and includes a timer c1.

The timer c1 is for judging immediate return from the light load mode (MODE2) and no-load mode (MODE3) to the normal mode (MODE1), and counts the number of clock pulses CK input to the clock input end. When the count value reaches a predetermined value (=determination time Tc2), the immediate return signal Sc1 is raised to high level. However, the timer c1 is reset by the immediate return detection signal S4 input to the reset input terminal. Specifically, the timer c1 is reset during the low level period of the immediate return detection signal S4 (=the period when the feedback voltage Vfb is lower than the threshold voltage Vth4), and during the high level period of the immediate return detection signal S4 (=the feedback voltage). During the period when the voltage Vfb is higher than the threshold voltage Vth4, the reset is released. Therefore, the immediate return signal Sc1 rises to a high level when the immediate return detection signal S4 is maintained at a high level over the determination time Tc2.

In this figure, an example of configuration using pulse counters (=digital timers) is given as timers b1 to b4 and timer c1, but analog timers may also be used.

The operation mode switching unit d is a circuit block that generates mode signals M1 to M3 based on the inverted transition return signals Sb5B and Sb6B and the immediate return signal Sc1, and includes D flip-flops d1 to d3 and an up/down counter d4.

The D flip-flop d1 latches the inverted transition return signal Sb5B input to the data input terminal (D) when the driving clock signal CLK input to the clock input terminal rises to a high level, and outputs the result. It is output from the output terminal (Q) as an up-down signal Sd1.

The D flip-flop d2 latches the inverted transition return signal Sb6B input to the data input terminal (D) when the driving clock signal CLK input to the clock input terminal rises to a high level, and outputs the result. It is output from the output terminal (Q) as an up-down signal Sd2.

The D flip-flop d3 latches the immediate return signal Sc1 input to the data input terminal (D) when the driving clock signal CLK input to the clock input terminal rises to a high level, and resets the result. It is output from the output terminal (Q) as a signal Sd3.

Also, the D flip-flops d1 to d3 are reset by an enable signal EN input to their respective reset input terminals. More specifically, the D flip-flops d1 to d3 are reset (Sd1=Sd2=Sd3=L) during the low level period of the enable signal EN (=disable period of the power supply IC 100), and when the enable signal EN is high. During the level period (=enable period of the power supply IC 100), the reset release state is entered.

The up/down counter d4 switches the logic levels of the mode signals M1 to M3 when the rising edge and falling edge of the up/down signals Sd1 and Sd2 occur.

As a premise of the following description, the mode signal M1 is at high level when the power supply IC 100 is in the normal mode (MODE1), and is at low level in other operation modes. On the other hand, the mode signal M2 is assumed to be high level when the power supply IC 100 is in the light load mode (MODE2), and to be low level in other operation modes. Also, the mode signal M3 is assumed to be high level when the power supply IC 100 is in the no-load mode (MODE3), and to be low level in other operation modes.

In other words, if the mode signals M1 to M3 are understood as 3-bit signals of "M1M2M3", the output value of the up/down counter d4 can take three values of "100b", "010b", and "001b". Each output value corresponds to normal mode (MODE1), light load mode (MODE2), and no load mode (MODE3).

For example, when the output value of the up/down counter d4 is "100b", the pulse edge of the light load detection signal S2 is not detected for the determination time Tc1, and the up/down signal Sd1 falls to a low level. The output value of the down counter d4 is counted down to "010b". This countdown causes the operation mode of the power supply IC 100 to shift from the normal mode (MODE1) to the light load mode (MODE2).

On the other hand, when the output value of the up/down counter d4 is "010b", the pulse edge of the light load detection signal S2 is periodically detected over the determination time Tc1, and when the up/down signal Sd1 rises to a high level, The output value of the up/down counter d4 is counted up to "100b". By this count-up, the operation mode of the power supply IC 100 is returned from the light load mode (MODE2) to the normal mode (MODE1).

Further, for example, when the output value of the up/down counter d4 is "010b", the pulse edge of the no-load detection signal S3 is not detected for the determination time Tc1, and the up/down signal Sd2 falls to a low level. , the output value of the up/down counter d4 is counted down to "001b". This countdown causes the operation mode of the power supply IC 100 to shift from the light load mode (MODE2) to the no-load mode (MODE3).

On the other hand, when the output value of the up/down counter d4 is "001b", the pulse edge of the no-load detection signal S3 is periodically detected over the determination time Tc1, and when the up/down signal Sd2 rises to a high level, The output value of the up/down counter d4 is counted up to "010b". By this count-up, the operation mode of the power supply IC 100 is returned from the no-load mode (MODE3) to the light-load mode (MODE2).

Also, the up-down counter d4 is reset by a reset signal Sd3 input from the D flip-flop d3. More specifically, when the output value of the up/down counter d4 is "010b" or "001b", the feedback voltage Vfb continuously exceeds the threshold voltage Vth4 over the determination time Tc2, and the reset signal Sd3 is When it rises to high level, the output value of the up/down counter d4 is reset to "100b". With this reset, the operation mode of the power supply IC 100 is immediately returned from the light load mode (MODE2) or no load mode (MODE3) to the normal mode (MODE1).

The up/down counter d4 is also reset by the enable signal EN input to the reset input terminal. More specifically, the up-down counter d4 is reset during the low level period of the enable signal EN (=disable period of the power supply IC 100), and is reset during the high level period of the enable signal EN (=enable period of the power supply IC 100). A reset release state is entered.

<Light load mode>
FIG. 6 is a diagram showing the internal operation state of the power supply IC 100 in the light load mode (MODE2). In the light load mode (MODE 2), the comparators 101 and 107 and a part of the controller 110 (=the functional part related to the signal processing of the overvoltage detection signal S1 and the overload detection signal S7) are indicated by x marks in the figure. ) stops operating and their current consumption is reduced.

FIG. 7 is a timing chart showing an example of peak current control in the light load mode (MODE2). The feedback voltage Vfb is drawn in the upper part, and the sense voltage Vcs is drawn in the lower part.

As shown in the figure, in the light load mode (MODE2), the peak current value of the primary current Ip flowing through the transistor N1 (=corresponding to the peak value Vcsp of the sense voltage Vcs) is lower than in the normal mode (MODE1), for example It is raised by 1.5 times.

According to such peak current control, a larger amount of primary current Ip can flow by turning on the transistor N1 only once. Therefore, for example, as shown in this figure, in the case where the feedback voltage Vfb is lower than the threshold voltage Vth5 and the burst control of the transistor N1 is performed, the number of times of switching at the time of canceling the burst can be reduced, thereby reducing the switching loss. It becomes possible to

As described above, in the light load mode (MODE 2), the current consumption of the power supply IC 100 is lower than in the normal mode (MODE 1), and the peak current value at the time of canceling the burst is raised, thereby reducing the standby power of the power supply IC 100. transformation has been realized.

<No load mode>
FIG. 8 is a diagram showing the internal operation state of power supply IC 100 in the no-load mode (MODE3). As indicated by x marks in the figure, in the no-load mode (MODE3), the current consumption is reduced in the same manner as in the light-load mode (MODE2). 103, comparators 106 to 108, oscillator 116, maximum duty setting unit 117, and almost all parts of controller 110 (= function parts other than those related to signal processing of immediate return detection signal S4 and burst detection signal S5) operate. are stopped, and the current consumption of each is reduced.

In the no-load mode (MODE3), the transistor 119 is turned off during the burst stop period of the transistor N1. Therefore, the current path through which the feedback current Ifb flows is cut off, so that the current consumption of the power supply IC 100 is greatly reduced.

FIG. 9 is a timing chart showing an example of peak current control in the no-load mode (MODE3). As in FIG. 7, the feedback voltage Vfb is shown in the upper part, and the sense voltage Vcs is shown in the lower part.

As shown in the figure, in the no-load mode (MODE3), the peak current value of the primary current Ip flowing through the transistor N1 (=corresponding to the peak value Vcsp of the sense voltage Vcs) is higher than in the normal mode (MODE1), for example be raised twice. Therefore, it is possible to further reduce the number of times of switching when the burst is released, compared to the light load mode (MODE2), so that the switching loss can be further reduced.

Even if the peak current value of the primary current Ip is doubled, the peak value (=2Vcsp) of the sense voltage Vcs is set to be sufficiently lower than the overcurrent detection value Vocp. Therefore, unintended overcurrent protection is not applied in the no-load mode (MODE3).

Furthermore, in the no-load mode (MODE 3), the burst stop time is controlled to always be a predetermined value (for example, 10 ms) or longer (details will be described later).

As described above, in the no-load mode (MODE 3), the burst stop time is controlled to be a predetermined value or more, and the current consumption at the time of burst stop is reduced more than in the light load mode (MODE 2). Further reduction of the standby power consumption of the power supply IC 100 is realized by further raising the peak current value during the period.

<Controller (second configuration example)>
FIG. 10 is a diagram showing a second configuration example of the controller 110. As shown in FIG. The controller 110 of this configuration example includes a burst control unit e as a functional block related to burst control in the no-load mode (MODE 3).

The burst control unit e is a circuit block that generates a burst stop signal STOP and a power save signal PS so that the burst stop time is always a predetermined value (for example, 10 ms) or more in the no-load mode (MODE 3). It includes a pulse generator e1, timers e2 and e3, and a logical sum operator e4.

The one-shot pulse generator e1 generates a one-shot pulse in the reset signal Se1 when the burst detection signal S5 rises to high level.

The timer e2 is for measuring the burst stop time Tc3 (for example, 10 ms), counts the number of clock pulses CK input to the clock input terminal, and the count value corresponds to a predetermined value (=burst stop time Tc3). ), the timer signal Se2 falls from high level to low level. The timer e2 is reset by a one-shot pulse of the reset signal Se1 input to the reset input terminal. Therefore, the timer signal Se2 rises to high level when the burst detection signal S5 rises to high level, and falls to low level when the burst stop time Tc3 elapses. The timer signal Se2 is output to the timer e3, and is also output to each part of the power supply IC 100 as the power save signal PS.

The timer e3 is for generating a circuit recovery time Tc4 (for example, 150 μs). As the simplest circuit configuration, for example, a delay timer that generates the delay timer signal Se3 by delaying the timer signal Se2 by the circuit recovery time Tc4 is used. be able to. It should be noted that the circuit recovery time Tc4 is the required standby time from when the current supply to each part of the power supply IC 100 is restarted until the operation of each part is stabilized.

A logical sum calculator e4 generates a logical sum signal Se4 of the timer signal Se2 and the delay timer signal Se3. Therefore, the OR signal Se4 becomes high level when at least one of the timer signal Se2 and the delay timer signal Se3 is high level, and becomes low level when both the timer signal Se2 and the delay timer signal Se3 are low level. Become. The OR signal Se4 is used as a burst stop signal STOP.

<Burst control>
FIG. 11 is a timing chart showing an example of burst control in the no-load mode (MODE3). From the top, feedback voltage Vfb, power save signal PS, burst stop signal STOP, gate signal G1, sense voltage Vcs, feedback current. Ifb and power supply voltage Vcc are depicted.

At time t1, when the feedback voltage Vfb falls below the threshold voltage Vth5, the power save signal PS and the burst stop signal STOP rise to high level. As a result, the gate signal G1 is fixed at the low level, the switching of the transistor N1 is stopped, and the feedback current Ifb is interrupted.

When the burst stop time Tc3 elapses from time t1, the power save signal PS falls to low level at time t2. As a result, the feedback current Ifb starts to flow. In this figure, the feedback voltage Vfb exceeds the threshold voltage Vth5 before the burst stop time Tc3 elapses from time t1. It is never lowered to a low level.

When the circuit recovery time Tc4 elapses from time t2, the burst stop signal STOP falls to low level at time t3. As a result, the low-level fixation of the gate signal G1 is released, and switching of the transistor N1 is resumed.

After that, at time t4, when the feedback voltage Vfb falls below the threshold voltage Vth5 again, burst control similar to the above is repeated.

As described above, in the burst control in the no-load mode (MODE 3), when the burst is stopped (see times t1 to t3, etc.), not only is switching of the transistor N1 stopped, but also the feedback current Ifb flowing through the phototransistor PT is cut off, the standby power of the power supply IC 100 (=the power consumed by the switching operation of the transistor N1+the power consumed by the self-operation of the power supply IC 100) can be greatly reduced.

In particular, when the DC output voltage Vo is lowered in the secondary circuit system 1s, the power supply voltage Vcc generated from the induced voltage Vp of the auxiliary winding L3 is also lowered. Therefore, in the power supply IC 100, the capacitor C2 is recharged by the starter 109. However, if burst control is performed in the no-load mode (MODE 3), the power consumption of the power supply IC 100 can be greatly reduced and the recharge can be performed. Since the frequency of this can be minimized, it is possible to prevent deterioration of standby power consumption.

In this figure, it can be seen that while the feedback current Ifb is interrupted (see times t1 to t2, etc.), the power supply voltage Vcc falls slowly and the frequency of recharging by the starter 109 is suppressed. .

<Gain adjustment section (peak current switching section)>
FIG. 12 is a diagram showing a configuration example of the gain adjustment section 113. As shown in FIG. The gain adjustment unit 113 of this configuration example is a circuit block that functions as a peak current switching unit that switches the peak current value of the primary current Ip flowing through the transistor N1 for each of a plurality of operation modes. It includes MOS field effect transistors N2 and N3, a NOR operator NOR and an inverter INV.

In the following description, it is assumed that the resistance value of the resistor R9 is 3R, the resistance value of the resistor R10 is R, the resistance value of the resistor R11 is 0.5R, and the resistance value of the resistor R12 is 1.5R.

A first end of the resistor R9 is connected to the input end (=external terminal T2) of the feedback voltage Vfb. A second end of the resistor R9 and a first end of the resistor R10 are connected to the output end of the divided feedback voltage Vfb2. A second end of the resistor R10 and a first end of the resistor R11 are connected to the drain of the transistor N2. A first end of the resistor R11 and a second end of the resistor R12 are connected to the source and back gate of the transistor N2 and the drain of the transistor N3, respectively. A second end of the resistor R12 is connected to the source and back gate of the transistor N3 and the ground terminal GND1, respectively.

The gate of the transistor N2 is connected to the output end of the NOR operator NOR (=corresponding to the output end of the gate signal GN2). Therefore, the transistor N2 turns on when the gate signal GN2 is at high level, and turns off when the gate signal GN2 is at low level.

The gate of the transistor N3 is connected to the output end of the inverter INV (=corresponding to the output end of the gate signal GN3). Therefore, the transistor N3 is turned on when the gate signal GN3 is at high level and turned off when the gate signal GN3 is at low level.

The NOR operator NOR generates a NOR operation signal of the mode signals M2 and M3 and outputs it as the gate signal GN2. Therefore, the gate signal GN2 becomes low level when at least one of the mode signals M2 and M3 is high level, and becomes high level when both of the mode signals M2 and M3 are low level.

The inverter INV generates a logically inverted signal of the mode signal M3 and outputs it as the gate signal GN3. Therefore, the gate signal GN3 becomes low level when the mode signal M3 is high level, and becomes high level when the mode signal M3 is low level.

In the gain adjustment unit 113 having the above configuration, when the power supply IC 100 is in the normal mode (MODE 1), M2=M3=L and GN2=GN3=H, so that N2=N3=ON. Therefore, the gain α is "1/4 (=R/(3R+R))".

On the other hand, when the power supply IC 100 is in the light load mode (MODE2), M2=H, M3=L, GN2=L, and GN3=H, so that N2=OFF and N3=ON. Therefore, the gain α is "1/3 (=(R+0.5R)/(3R+R+0.5R))".

When the power supply IC 100 is in the no-load mode (MODE3), M2=L, M3=H, and GN2=GN3=L, so that N2=N3=OFF. Therefore, the gain α is "1/2 (=(R+0.5R+1.5R)/(3R+R+0.5R+1.5R))".

From the following equation (1), it can be seen that the peak current value of the primary current Ip is also switched by switching the gain α.

Ip=Vcs/Rs=α×Vfb/Rs (1)

That is, in the light load mode (MODE 2), switching to α=1/3 increases the peak current value of the primary current Ip by 1.33 times compared to the normal mode (MODE 1, α=1/4). Therefore, it is possible to improve the efficiency at light load.

In the no-load mode (MODE 3), by switching to α=1/2, the peak current value of the primary current Ip can be doubled compared to the normal mode (MODE 1, α=1/4). Therefore, it is possible to improve the efficiency at no load.

<Peak current switching>
In the above, the configuration for switching the peak current value of the primary current Ip for each operation mode of the power supply IC 100 is taken as an example, but the peak current switching (gain adjustment) does not necessarily have to be performed in combination with the operation mode switching of the power supply IC 100. However, by increasing the peak current value of the primary current Ip when a light load is detected, it is possible to achieve high efficiency during a light load (during standby).

As a light load detection method, for example, when the feedback voltage Vfb falls below the threshold voltage Vth5, the burst detection signal S5 rises to a high level, and burst control of the transistor N1 by the controller 110 is started, the light load is detected. is detected and the peak current value of the primary current Ip is increased.

Further, for example, after the burst control of the transistor N1 by the controller 110 is started, when the burst stop period of the transistor N1 (=the period during which the feedback voltage Vfb is lower than the threshold voltage Vth5) becomes longer than a predetermined value, The peak current value of the primary current Ip may be increased by detecting that the load is light.

Further, for example, it is possible to increase the peak current value of the primary current Ip by detecting that the peak voltage value of the sense voltage Vcs has decreased or that the ON period Ton of the transistor N1 has become shorter.

On the other hand, as a method of switching the peak current, as described above, the peak current value of the primary current Ip may be raised by adjusting the gain α (=voltage division ratio) of the feedback voltage Vfb.

<Package layout>
FIG. 13 is a diagram (XZ plan view) showing an example of a package layout. In the power supply IC 100 of this figure, a first chip 100a and a second chip 100b are mounted on an island 100c.

The first chip 100a is integrated with a circuit block (for example, a starter 109 that receives an input of a high voltage VH) that requires a high withstand voltage. The first chip 100a is connected to the external terminal T8 via wires W1 and W2. Also, the first chip 100a is connected to the second chip 100b through wires W3 to W6.

Circuit blocks (101 to 108 and 110 to 119) other than the above are integrated in the second chip 100b. The second chip 100b is connected to external terminals T1-T6 via wires W7-W12, respectively.

In the package layout of this figure, on the island 100c, the first chip 100a is arranged near the second side (=the side close to pins 5 to 7), and the second chip 100b is arranged near the first side ( = side close to pins 1 to 4). By adopting such a package layout, the wires W1 to W12 can be laid as short as possible.

Next, the reason why the power supply IC 100 has a two-chip configuration instead of a one-chip configuration will be described. If a circuit block requiring a high breakdown voltage and other circuit blocks are formed on a single chip, it is necessary to provide a buffer region between the high breakdown voltage process area and the low breakdown voltage process area. As a result, the chip size becomes very large, resulting in a significant cost increase.

On the other hand, if the power supply IC 100 has a two-chip structure, there is no need to provide a buffer region in either the first chip 100a or the second chip 100b, so the size of each chip can be reduced, resulting in cost reduction. It becomes possible to plan Also, since the first chip 100a and the second chip 100b are separated, it is very advantageous in terms of withstand voltage.

<Summary>
The following is a general discussion of various embodiments disclosed herein.

The power supply control device disclosed in this specification is a main control unit for an isolated switching power supply, and includes a first output detection signal corresponding to a DC output voltage to a load, the DC output voltage and its The configuration (first configuration) includes a controller that monitors the second output detection signal according to the difference value from the target value and switches between a plurality of operation modes with different power consumption according to the results of both monitoring.

In addition, the power supply control device having the first configuration has a normal mode and at least one power saving mode as the plurality of operation modes, and the controller controls the A configuration for switching the operation mode between the normal mode and the power saving mode or between a plurality of the power saving modes, and returning to the normal mode according to the monitoring result of the second output detection signal (second configuration).

Further, in the power control device having the second configuration, the controller determines whether or not to perform burst control of the output switch according to the monitoring result of the second output detection signal (third configuration). should be

Further, the power supply control device having the third configuration has a configuration (fourth configuration) further including a peak current switching unit that switches a peak current value of the primary current flowing through the output switch for each of the plurality of operation modes. good.

In the power supply control device having the fourth configuration, the power saving mode includes a light load mode in which current consumption is reduced more than in the normal mode and the peak current value at the time of burst cancellation is increased; and burst stop. a no-load mode in which the time is controlled to be equal to or greater than a predetermined value, and in which current consumption during burst stop is reduced more than in the light load mode and the peak current value during burst release is further increased; A configuration (fifth configuration) is preferable.

Further, the isolated switching power supply disclosed in this specification has a power control device having any one of the first to fifth configurations, and a switching output stage controlled by the power control device. (sixth configuration).

In the isolated switching power supply having the sixth configuration, the switching output stage uses a transformer to electrically insulate the primary circuit system and the secondary circuit system, and supplies DC input to the primary circuit system. A configuration (seventh configuration) that functions as a component of a DC/DC conversion unit that generates the DC output voltage from the voltage and supplies it to the load of the secondary circuit system is preferably employed.

Further, the insulated switching power supply having the seventh configuration may preferably have a configuration (eighth configuration) in which variable control of the DC output voltage is performed in the secondary circuit system.

The isolated switching power supply having the eighth configuration may further include a rectifying section for generating the DC input voltage from the AC input voltage (the ninth configuration).

Further, an electronic device disclosed in this specification includes an insulated switching power supply having any one of the sixth to ninth configurations, and a load that operates by receiving power supply from the insulated switching power supply. (tenth configuration).

Further, the power supply control device disclosed in this specification is a control main body of the isolated switching power supply, and is a peak current switching unit that raises the peak current value of the primary current flowing through the output switch when a light load is detected. (eleventh configuration).

The power supply control device having the eleventh configuration has an on-duty control section that controls the on-duty of the output switch based on the output detection signal corresponding to the difference between the DC output voltage to the load and its target value. and the peak current switching unit adjusts the gain of the output detection signal to raise the peak current value when a light load is detected (a twelfth configuration).

In the power supply control device having the twelfth configuration, the output detection signal may be a voltage signal, and the gain may be a voltage division ratio (thirteenth configuration).

Further, the power control apparatus having the 12th or 13th configuration further includes a controller for determining whether or not to perform burst control of the output switch according to the monitoring result of the output detection signal (14th configuration).

In the power supply control device having the fourteenth configuration, the peak current switching unit may increase the peak current value when the controller performs burst control of the output switch (fifteenth configuration). .

Further, in the power supply control device having the fourteenth or fifteenth configuration, the peak current switching unit increases the peak current value when the burst stop period of the output switch becomes longer than a predetermined value (the 16 configuration).

Further, the isolated switching power supply disclosed in this specification has a power control device having any one of the eleventh to sixteenth configurations, and a switching output stage controlled by the power control device. (17th configuration).

In the isolated switching power supply having the seventeenth configuration, the switching output stage uses a transformer to electrically insulate the primary circuit system and the secondary circuit system, and supplies direct current to the primary circuit system. A configuration (eighteenth configuration) that functions as a component of a DC/DC converter that generates the DC output voltage from the input voltage and supplies it to the load of the secondary circuit system is preferably employed.

The isolated switching power supply having the eighteenth configuration may further include a rectifying section for generating the DC input voltage from the AC input voltage (the nineteenth configuration).

Further, an electronic device disclosed in this specification includes an insulated switching power supply having any one of the seventeenth to nineteenth configurations, and a load that operates by receiving power supplied from the insulated switching power supply. (twentieth configuration).

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalence to the claims are included.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be applied to isolated switching power supplies used in all fields (home appliance field, automobile field, industrial machinery field, etc.).

1 Insulated switching power supply 1p Primary circuit system (GND1 system)
1s Secondary circuit system (GND2 system)
2 load 10 rectifier 11 filter 12 diode bridge 13, 14 capacitor 20 DC/DC converter 100 power supply IC (power supply control device)
100a first chip 100b second chip 100c island 101 to 108 comparator 109 starter 110 controller 111 RS flip-flop 112 driver 113 gain adjustment section (peak current switching section)
114 slope compensator 115 adder 116 oscillator 117 maximum duty setting unit 118 resistor 119 P-channel MOS field effect transistor a edge detector a1 inverter a2-a5 D flip-flop b first timer b1-b4 timer b5, b6 RS flip-flop b7 to b10 inverter c second timer c1 timer d operation mode switching unit d1 to d3 D flip-flop d4 up/down counter e burst control unit e1 one-shot pulse generation unit e2, e3 timer e4 OR operator PW commercial AC power supply X Electronic equipment TR Transformer L1 Primary winding L2 Secondary winding L3 Auxiliary winding R1-R12 Resistors C1-C4 Capacitors D1-D4 Diodes N1-N3 N-channel MOS field effect transistors LED Light-emitting diodes PT Phototransistors REG Shunt regulators NOR NOR operator INV Inverter T1~T8 External terminal W1~W12 Wire

Claims (20)

A power supply control device that controls an isolated switching power supply,
A first output detection signal corresponding to the DC output voltage to the load and a second output detection signal corresponding to the difference value between the DC output voltage and its target value are monitored, and power consumption is reduced according to the results of both monitoring. A power control device comprising a controller for switching between a plurality of different operation modes. A normal mode and at least one power saving mode are provided as the plurality of operation modes,
The controller switches an operation mode between the normal mode and the power saving mode or between a plurality of power saving modes according to the monitoring result of the first output detection signal, and switches the operation mode of the second output detection signal. 2. The power supply control device according to claim 1, wherein the return to the normal mode is performed according to the monitoring result. 3. The power supply control device according to claim 2, wherein said controller determines whether or not to perform burst control of the output switch according to the monitoring result of said second output detection signal. 4. The power supply control device according to claim 3, further comprising a peak current switching unit that switches a peak current value of the primary current flowing through the output switch for each of the plurality of operation modes. As the power saving mode,
a light load mode in which current consumption is reduced more than in the normal mode and the peak current value at the time of burst release is raised;
a no-load mode in which the burst stop time is controlled to be equal to or greater than a predetermined value, current consumption during burst stop is reduced more than in the light load mode, and the peak current value at burst release is further increased;
5. The power control device according to claim 4, comprising: A power supply control device according to any one of claims 1 to 5;
a switching output stage controlled by the power control device;
An isolated switching power supply characterized by comprising: The switching output stage generates the DC output voltage from the DC input voltage supplied to the primary circuit system while electrically insulating the primary circuit system and the secondary circuit system using a transformer. 7. The isolated switching power supply according to claim 6, functioning as a component of a DC/DC converter that supplies the load of the system. 8. The insulated switching power supply according to claim 7, wherein said secondary circuit system performs variable control of said DC output voltage. 9. The isolated switching power supply according to claim 8, further comprising a rectifying section that generates the DC input voltage from an AC input voltage. The insulated switching power supply according to any one of claims 6 to 9,
a load that operates by being supplied with power from the isolated switching power supply;
An electronic device comprising: A power supply control device that controls an isolated switching power supply,
A power supply control device comprising a peak current switching section for increasing a peak current value of a primary current flowing through an output switch when a light load is detected. further comprising an on-duty control unit for controlling the on-duty of the output switch based on an output detection signal corresponding to a difference value between the DC output voltage to the load and its target value;
12. The power supply control device according to claim 11, wherein the peak current switching unit raises the peak current value by adjusting the gain of the output detection signal when a light load is detected. 13. The power control device according to claim 12, wherein said output detection signal is a voltage signal, and said gain is a voltage dividing ratio. 14. The power supply control device according to claim 12, further comprising a controller that determines whether or not to perform burst control of said output switch according to a monitoring result of said output detection signal. 15. The power supply control device according to claim 14, wherein the peak current switching unit raises the peak current value when the controller performs burst control of the output switch. 16. The power supply control device according to claim 14, wherein the peak current switching unit raises the peak current value when a burst stop period of the output switch becomes longer than a predetermined value. A power supply control device according to any one of claims 11 to 16;
a switching output stage controlled by the power control device;
An isolated switching power supply characterized by comprising: a power supply control device according to any one of claims 12 to 16;
a switching output stage controlled by the power control device;
has
The switching output stage generates the DC output voltage from the DC input voltage supplied to the primary circuit system while electrically insulating the primary circuit system and the secondary circuit system using a transformer. An isolated switching power supply functioning as a component of the DC/DC conversion section that supplies the load of the system. 19. The isolated switching power supply according to claim 18, further comprising a rectifying section that generates the DC input voltage from an AC input voltage. The insulated switching power supply according to any one of claims 17 to 19,
a load that operates by being supplied with power from the isolated switching power supply;
An electronic device comprising:

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