WO2021083076A1 - 电路原理图生成方法及生成系统 - Google Patents

电路原理图生成方法及生成系统 Download PDF

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Publication number
WO2021083076A1
WO2021083076A1 PCT/CN2020/123661 CN2020123661W WO2021083076A1 WO 2021083076 A1 WO2021083076 A1 WO 2021083076A1 CN 2020123661 W CN2020123661 W CN 2020123661W WO 2021083076 A1 WO2021083076 A1 WO 2021083076A1
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netlist
value
generating
circuit diagram
schematic circuit
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PCT/CN2020/123661
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English (en)
French (fr)
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王钦克
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上海安路信息科技股份有限公司
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Publication of WO2021083076A1 publication Critical patent/WO2021083076A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Definitions

  • the present invention relates to the field of integrated circuit technology, and in particular to a method and system for generating circuit schematic diagrams.
  • Circuit schematic diagram also known as circuit diagram, uses graphics to intuitively reflect the components and electrical connections in the circuit, directly reflects the structure and working principle of the circuit, and is widely used in the design and analysis of circuits.
  • circuit schematic diagram also known as circuit diagram, uses graphics to intuitively reflect the components and electrical connections in the circuit, directly reflects the structure and working principle of the circuit, and is widely used in the design and analysis of circuits.
  • automatically generating circuit schematics from the logic circuit netlist to graphically display is an indispensable tool for assisted design software to improve the designer's interactive experience.
  • the automatically generated circuit diagrams need to be regular, symmetrical, readable, easy to understand, and as close as possible to the common cognitive habits of humans, and to reduce the graphical display response of complex circuits
  • the algorithm complexity used in the automatic generation of circuit diagrams is generally low.
  • FPGA integrated circuits usually include BRAM, DSP, IP and other devices that are much larger than general logic devices.
  • the size of the hierarchical modules in the circuit varies greatly.
  • grid-based automatic circuit diagram generation methods are adopted, and a device is placed in each grid interval, which is more suitable for graphical display of circuits with small differences in device size. Therefore, it is not suitable for FPGA integrated circuits or in graphics. It is used when displaying hierarchical integrated circuit design.
  • the purpose of the present invention is to provide a method and system for generating a schematic diagram of a circuit, which avoids the use of grids and reduces the complexity of the connection algorithm and the crossing and bending of the connection.
  • the method for generating a schematic circuit diagram of the present invention includes the following steps:
  • S1 Provide a wire netting netlist, and calculate the level value of the netlist device according to the wire netting netlist to determine the column of the netlist device;
  • S3 Generate a constraint graph according to the sorting graph, and then traverse the constraint graph in a forward direction to calculate the value of the first longitudinal position of the netlist device;
  • the beneficial effects of the present invention are: the device layout does not need to be based on a grid, and the graphical display effect is better; the pseudo device with the same order value as the driving device is generated according to the connected line or the feedback line, and the connected line and the feedback line are processed by the pseudo device.
  • the wiring algorithm needs to be simplified for the signal connection between adjacent devices; the netlist devices and the pseudo devices on the same column are sorted according to the sorting value, with fewer wiring crossings, and more signal connection relationships between devices Clear: Constraint diagrams are used, with less wire bending, and the signal connection relationship between devices is clearer.
  • the step S1 includes the following steps:
  • S11 Initialize the netlist device, and then establish a breadth priority search queue and a feedback device priority queue according to the wire netlist;
  • S12 Calculate and update the tier value of the netlist device through the breadth-first search queue and the feedback device priority queue, until the tier value of the netlist device cannot be updated.
  • the beneficial effect is that the breadth-first search queue and the feedback device priority queue are established to calculate and update the level value of the netlist device, and the algorithm complexity is low.
  • the input pin devices in the netlist device are added to the breadth-first search queue.
  • the beneficial effect is that the network netlist is used to establish the breadth priority search queue and the feedback device priority queue to calculate the level value of the netlist device.
  • the algorithm is simple and the calculation efficiency is high.
  • the feedback device priority queue established is empty.
  • the beneficial effect lies in: simplifying the difficulty of initial calculation.
  • the initialization includes setting the level value of the netlist device to 1.
  • the beneficial effect is that: setting the level value of the netlist device to 1 facilitates subsequent calculations and reduces the complexity of the algorithm.
  • the step S12 includes judging that the breadth-first search queue is not empty, then selecting the first-ranked netlist device in the breadth-first search queue as the priority device; judging that the in-degree of the priority device is greater than 0 , The priority device is added to the feedback device priority queue; if it is judged that the in-degree of the priority device is equal to 0 and has not been processed, the fan-out device with the in-degree of the priority device greater than 0 is performed first deal with.
  • the beneficial effect is that it is convenient to accurately calculate the level value of the netlist device.
  • the first processing includes updating the gradation value of the fan-out device of the priority device; subtracting 1 from the in-degree of the fan-out device of the priority device; adding the fan-out device of the priority device to all Describe the last position in the breadth-first search queue.
  • the beneficial effect is that it is convenient to continuously update the gradation value of the device to obtain the final accurate gradation value.
  • the gradation value of the fan-out device is the maximum value of the gradation value of the priority device plus 1 and the gradation value before the fan-out device is updated.
  • the beneficial effect is that the accurate gradation value of the fan-out device can be obtained.
  • the step S12 further includes judging that the feedback device priority queue is not empty, then selecting the first-ranked netlist device in the feedback device priority queue as the feedback device; judging that the in-degree of the feedback device is greater than 0 and in the loop, the in-degree of the feedback device is set to 0, and the feedback device is added to the breadth-first search queue.
  • the beneficial effect is that it is convenient to repeatedly calculate and update the level value of the netlist device to obtain an accurate level value.
  • the hierarchical values of the netlist devices in the feedback device priority queue are sorted from small to large.
  • the beneficial effect is that the hierarchy value of the netlist device is clearly arranged, and the algorithm is simplified to facilitate calculation.
  • the circuit schematic diagram is from column 1 to column n from left to right, the input pin device in the netlist device is placed in the first column, and the output pin device in the netlist device Placed in the nth column, and the remaining netlist devices are placed in the second to n-1th columns, where n is a natural number greater than 1.
  • the beneficial effect is that it is convenient to make the circuit schematic diagram more regular and symmetrical.
  • the input pin devices are sorted according to the codes of the input pin devices, and then the value of the current sort position of the input pin device is multiplied by a threshold value to obtain the input pin The sort value of the device.
  • the beneficial effect is that it is convenient to obtain the accurate sorting value of the input pin device.
  • the threshold value is 100.
  • the beneficial effect is that it is convenient to calculate the sort value of the netlist device, which makes the calculation clearer and simpler, and avoids the appearance of decimals.
  • the ranking values of the netlist devices in the second column to the nth column are the average of the ranking values of the respective fan-in devices of the netlist devices.
  • the beneficial effect is that it is convenient to calculate the ranking value of the netlist device in the second column to the nth column.
  • the sorting is performed according to the average value of the value of the device fan-in to the sorting position of the device.
  • the beneficial effect is to prevent different devices from being located at the same longitudinal position.
  • the devices are sorted according to their codes in the netlist.
  • the beneficial effect is to prevent different devices from being located at the same longitudinal position.
  • each time the connecting line or the feedback line passes through a column a dummy device is generated on the column.
  • the beneficial effect is that the connection line and the feedback line are completely eliminated, which is beneficial to optimize the layout.
  • the height of the dummy device is the height of the horizontal line rail in the schematic circuit diagram.
  • the beneficial effect is to prevent the pseudo device from occupying too much space, and to ensure the regularity of the overall circuit schematic diagram.
  • generating a constraint map according to the ranking map in step S3 includes: generating a position constraint for two adjacent devices in each column of the device in the ranking map; each connected line or each feedback Two adjacent devices on the line generate a position constraint; the device on the m-th column forms a position constraint with the highest fan-in device and the lowest fan-in device of the device on the m-1 column, and m is greater than 1 and less than Or a natural number equal to n.
  • the beneficial effects are: establishing a constraint diagram, reducing the length of signal connection lines, reducing the number of short discounts, and increasing the readability of the circuit schematic diagram.
  • the position constraint is a directed edge.
  • the beneficial effect is that it is convenient to determine the transmission direction of the signal.
  • the value of the first longitudinal position of the device with an in-degree of 0 in the constraint map is 0.
  • the beneficial effect is that the value of the first longitudinal position of a type of device is determined preferentially, which facilitates the calculation of the value of the first longitudinal position of other devices.
  • the value of the first longitudinal position of the device with an in-degree greater than 0 in the constraint map is equal to the value of the first longitudinal position of the fan-in device of the device plus the minimum value of the relative position difference of the corresponding in-edge of the device .
  • the beneficial effect is that the appearance of short bending lines is initially reduced.
  • the value of the second longitudinal position of the device whose number of sides is 0 in the constraint graph is equal to the value of the first longitudinal position.
  • the beneficial effect is that it is convenient to adjust the value of the second longitudinal position and reduce the complexity of the algorithm calculation.
  • the value of the second longitudinal position of the device whose number of edges is greater than 0 in the constraint graph is equal to the value of the second longitudinal position of the fan-out device of the device minus the value of the device corresponding to the edge
  • the maximum value of the relative position difference is that the appearance of short bending lines is further reduced.
  • the signal connection line includes a first type signal connection line, a second type signal connection line, and a third type signal connection line.
  • the signal connection line of the second type is the signal connection line with the output pin and the input pin located on both sides of the tunnel
  • the signal connection line of the third type is the output pin and the input pin are both in the tunnel The signal connection line on the other side.
  • the step S5 includes: allocating the signal connecting lines of the first type to the corresponding longitudinal track through a second process, and then allocating the signal connecting lines of the second type to the corresponding longitudinal track through the second process. Finally, the third type of signal connection line is allocated to the corresponding longitudinal line track through the second processing, so as to allocate the signal connection line to the corresponding longitudinal line track.
  • the beneficial effect is that: only the signal connection between two adjacent columns of netlist devices needs to be processed, the connection line and the feedback line do not need to be considered, and the wiring is simpler.
  • the second processing includes: sorting the signal connection lines of the first type, the signal connection lines of the second type or the signal connection lines of the third type according to the smallest longitudinal coordinate of the pin from small to large ; According to the order of the signal connection lines, they are assigned to the leftmost longitudinal track. If the two signal connection lines overlap, the next longitudinal track is selected until the signal connection lines are allocated.
  • the beneficial effects are: avoid overlapping of signal connection lines, avoid waste of longitudinal line rails, and improve the compactness of the overall layout.
  • the present invention also provides a circuit schematic diagram generation system, which includes a hierarchy value calculation module, a ranking value calculation module, a pseudo device generation module, a ranking diagram generation module, a constraint diagram generation module, and a first calculation module ,
  • the second calculation module, the longitudinal line distribution module, the third calculation module and the signal line connection module, the level value calculation module is used to calculate the level value of the netlist device according to the wire net netlist to determine the netlist device
  • the ranking value calculation module is used to calculate the ranking value of the netlist device according to the wire net list;
  • the pseudo device generation module is used to generate a pseudo device with the same ranking value as the driving device according to the connecting line or the feedback line
  • the sequence diagram generation module is used to sequence the netlist devices and the pseudo devices on the same column according to the sequence value to generate a sequence diagram;
  • the constraint diagram generation module is used to generate a constraint diagram according to the sequence diagram;
  • the first calculation module is used to traverse the constraint graph in the forward direction to calculate the value of
  • the beneficial effects of the circuit principle diagram generating system of the present invention are: the device layout does not need to be based on grids, and the graphical display effect is better; the pseudo device generating module generates pseudo devices with the same order value as the driving device according to the connecting lines or feedback lines.
  • the device processes the connection line and the feedback line through the pseudo device, and only needs to deal with the signal connection between the adjacent devices, which simplifies the connection algorithm;
  • the sorting graph generation module compares the netlist device and the netlist device on the same column according to the sorting value.
  • the pseudo devices are sorted, with fewer wires crossing, and the signal connection relationship between the devices is clearer; the sequence diagram generating module generates a constraint map, with fewer wires being bent, and the signal connection relationship between the devices is clearer.
  • Fig. 1 is a flowchart of a method for generating a schematic circuit diagram of the present invention
  • Fig. 2 is a structural block diagram of the circuit principle diagram generating system of the present invention.
  • an embodiment of the present invention provides a method for generating a schematic circuit diagram.
  • the method for generating a schematic circuit diagram includes the following steps:
  • S1 Provide a wire netting netlist, and calculate the level value of the netlist device according to the wire netting netlist to determine the column of the netlist device;
  • S3 Generate a constraint graph according to the sorting graph, and then traverse the constraint graph in a forward direction to calculate the value of the first longitudinal position of the netlist device;
  • the netlist devices with the same level value are a column.
  • the step S1 includes the following steps:
  • S11 Initialize the netlist device to set the level value of the netlist device to 1, and then establish a breadth-first search queue and a feedback device priority queue according to the netlist The input pin device of is added to the breadth-first search queue, and the feedback device priority queue is empty;
  • S12 Calculate and update the tier value of the netlist device through the breadth-first search queue and the feedback device priority queue, until the tier value of the netlist device cannot be updated.
  • the step S12 includes step a, and the step a includes determining that the breadth-first search queue is not empty, and then selecting the first-ranked netlist device in the breadth-first search queue as the priority Device; judging that the in-degree of the priority device is greater than 0, then add the priority device to the feedback device priority queue; judging that the in-degree of the priority device is equal to 0 and has not been processed, then the priority device Fan-out devices whose in-degree is greater than 0 undergo the first processing.
  • the step a further includes determining that the in-degree of the priority device is equal to 0 and has been processed, and then the next netlist device is selected as the priority device according to the order in the breadth-first search queue.
  • the step a is repeated until the in-degrees of the netlist devices in the breadth-first search queue are all 0 and have been processed.
  • the first processing includes updating the gradation value of the fan-out device of the priority device; reducing the in-degree of the fan-out device of the priority device by 1; and reducing the fan-out of the priority device The device is added to the last position in the breadth-first search queue.
  • the gradation value of the fan-out device is the maximum value of the gradation value of the priority device plus 1 and the gradation value before the fan-out device is updated.
  • the step S12 further includes step b.
  • the step b includes determining that the feedback device priority queue is not empty, and then selecting the first-ranked netlist device in the feedback device priority queue as Feedback device; judging that the in-degree of the feedback device is greater than 0 and is in the loop, then the in-degree of the feedback device is set to 0, and the feedback device is added to the breadth-first search queue, and then all Mentioned step a.
  • the step b further includes determining that the in-degree of the feedback device is equal to 0 or the feedback device is located in the loop, then the step a is executed.
  • the netlist device whose current in-degree is 0 is ignored, and the information of the netlist device that does not belong to the loop is saved for the next time
  • a negative result is returned directly.
  • the hierarchical values of the netlist devices in the feedback device priority queue are sorted from small to large.
  • the circuit schematic diagram is from the first column to the nth column from left to right, the input pin devices in the netlist device are placed in the first column, and the netlist device is The output pin devices of is placed in the nth column, and the remaining netlist devices are placed in the second column to the n-1th column, and n is a natural number greater than 1.
  • the input pin devices are sorted according to the codes of the input pin devices, and then the value of the current sort position of the input pin device is multiplied by a threshold to Obtain the sort value of the input pin device.
  • the threshold value is 100, so as to facilitate the subsequent calculation of the sort value of the netlist device, avoid the occurrence of decimals, and simplify the algorithm.
  • the rank values of the netlist devices in the second column to the nth column are the average values of the rank values of the respective fan-in devices of the netlist devices.
  • the ranking is performed according to the average value of the fan-in device ranking positions of the device, and the devices include the network. Between the watch device and the dummy device, between the two netlist devices, and between the two dummy devices.
  • the devices are sorted according to their codes in the wire net list, and the devices include the net list device and the pseudo device.
  • each time the connecting line or the feedback line passes through a column the dummy device is generated on the column, and the height of the dummy device is a circuit principle.
  • the height of the horizontal rail in the picture is a circuit principle.
  • generating the constraint map according to the ranking map in step S3 includes: generating a position constraint for two adjacent devices in each column of the ranking map, and the first relative position difference is the height of the previous device;
  • Each connected line or two adjacent devices on each feedback line generates a position constraint, wherein the height of the position of the dummy device on the same connecting line is higher than or equal to the position of the previous column of dummy devices or driving devices Height, the height of the dummy device on the same feedback line is higher than or equal to the position height of the dummy device or the driving device in the next column, the second relative position difference is 0; the device on the mth column is different from that on the m-1th column
  • the highest position fan-in device and the lowest position fan-in device of the device form a position constraint, where the position height of the lowest position fan-in device is lower than or equal to the position height of the device, and the position height of the highest position fan-in device is higher than or equal to the device.
  • the driving device is a device that sends information.
  • the highest position fan-in device and the lowest position fan-in device are both a fan-in device and a dummy device.
  • the position constraint is a directed edge
  • the directed edge has a direction
  • the direction of the directed edge between the two adjacent devices in each column is directed from the front device to the rear device
  • the direction of the directed edge and the signal transmission direction between the two adjacent devices on the connecting line or the feedback line are the same.
  • the device on the mth column and the highest position of the device on the m-1 column are fanned into the devices.
  • the directed edge and signal transmission direction between the fan-in device and the lowest position are the same.
  • the value of the first longitudinal position of the device with an in-degree of 0 in the constraint map is 0.
  • the value of the first longitudinal position of the device with an in-degree greater than 0 in the constraint map is equal to the value of the first longitudinal position of the fan-in device of the device plus the relative position of the device corresponding to the in-edge The minimum value among the results obtained by the difference, where the relative position difference includes at least one of the first relative position difference, the second relative position difference, and the third relative position difference.
  • the value of the second longitudinal position of the device whose number of sides is 0 in the constraint graph is equal to the value of the first longitudinal position.
  • the value of the second longitudinal position of the device whose number of edges is greater than 0 in the constraint graph is equal to the value of the second longitudinal position of the fan-out device of the device minus the device
  • the relative position difference includes at least one of the first relative position difference, the second relative position difference, and the third relative position difference.
  • the signal connection line includes a first type signal connection line, a second type signal connection line, and a third type signal connection line.
  • the first type of signal connection line is a signal connection line whose output pins and input pins are on one side of the tunnel, specifically, it is the left side of the tunnel;
  • the second type of signal connection line is that the output pins and input pins are located on the left side of the tunnel.
  • the third type of signal connection line is a signal connection line whose output pins and input pins are on the other side of the tunnel, specifically, it is the right side of the tunnel.
  • the tunnel includes at least one longitudinal rail.
  • the step S5 includes: assigning the first type of signal connection line to the corresponding longitudinal track through a second process, and then passing the second type of signal connection line through the second The processing is allocated to the corresponding longitudinal line track, and finally the third type of signal connection line is allocated to the corresponding longitudinal line track through the second processing, so as to allocate the signal connection line to the corresponding longitudinal line track.
  • the second processing includes: arranging the first type signal connection line, the second type signal connection line, or the third type signal connection line from a small value according to the minimum longitudinal coordinate of the pin. Sort to the largest; according to the order of the signal connection lines, they are assigned to the leftmost longitudinal track. If two signal connection lines overlap, the next longitudinal track is selected until the signal connection lines are allocated.
  • the pins include output pins and input pins.
  • the maximum longitudinal coordinate and the minimum longitudinal coordinate of the signal connection line are calculated according to the numerical value of the second longitudinal position of the netlist device and the dummy device.
  • the maximum longitudinal coordinate and the minimum longitudinal coordinate of the signal connection line are used to determine whether two signal connection lines on the same longitudinal line track overlap. If the maximum longitudinal coordinate of the first signal connection line is less than or Equal to the minimum longitudinal coordinate of the second signal connection line, then the first signal connection line and the second signal connection line overlap.
  • the netlist device and the dummy device have the same width.
  • the device width is multiplied by the column number of the device in the column to obtain the first value, and the first value is added to the width of all channels in front of the device in the column to obtain the value of the lateral position of the device in the column.
  • the signal connection line includes a first line segment, a second line segment, and a third line segment that are sequentially connected, the second line segment is located in a longitudinal line track, and the first line segment is connected to the signal output The netlist device or the dummy device is connected, and the third line segment is connected with the netlist device or the dummy device received by the signal.
  • the width of the net list device, the width of the longitudinal wire rail and the height of the horizontal wire rail are all set with thresholds, and the value of the first longitudinal position and the value of the second longitudinal position are set. Represents distance.
  • the connecting line is a connecting line between the netlist devices that are not in adjacent columns, and the signal is transmitted from left to right.
  • the feedback line is a connection line between the netlist devices that are not in adjacent columns, and the signal is transmitted from left to right.
  • the signal connection line is a connection line between the netlist devices in adjacent columns.
  • Fig. 2 is a structural block diagram of a circuit schematic diagram generating system in some embodiments of the present invention.
  • the circuit schematic diagram generation system 10 includes a hierarchy value calculation module 101, a ranking value calculation module 102, a pseudo device generation module 103, a ranking diagram generation module 104, a constraint diagram generation module 105, a first calculation module 106, and a first calculation module.
  • the level value calculation module 101 is used for calculating the level value of the netlist device according to the netlist to determine the column of the netlist device; the ranking value calculation module 102 is used for calculating the netlist according to the netlist Table device ranking value; the pseudo device generating module 103 is used to generate pseudo devices with the same ranking value as the driving device according to the connecting line or the feedback line; the ranking map generating module 104 is used to compare all the devices on the same column according to the ranking value The netlist device and the pseudo device are sorted to generate a ranking graph; the constraint graph generating module 105 is used to generate a constraint graph according to the ranking graph; the first calculation module 106 is used to traverse the constraint graph in the forward direction to calculate The value of the first longitudinal position of the netlist device; the second calculation module 107 is used to reversely traverse the constraint graph to adjust the value of the first longitudinal position of the netlist device and generate a second longitudinal position The value of the longitudinal line rail allocation module 108 is used to allocate the signal connection line to the corresponding longitudinal

Abstract

本发明提供了一种电路原理图生成方法，包括计算网表器件的层次值，以决定网表器件的列，计算网表器件的排序值，并根据连通线或反馈线生成伪器件，只需要针对相邻器件之间的信号连接，简化了连线算法，根据排序值对网表器件和伪器件进行排序生成排序图，根据排序图生成约束图，连线弯折少，正向遍历约束图，计算第一纵向位置的数值，反向遍历约束图，对第一纵向位置的数值进行调整生成第二纵向位置的数值，将信号连接线分配到纵向线轨，计算横向位置的数值，连接信号连接线，以生成电路原理图，器件布局不需要基于网格，图形化显示效果更好。本发明还提供了一种用于实现电路原理图生成方法的电路原理图生成系统。

Description

电路原理图生成方法及生成系统 技术领域
本发明涉及集成电路技术领域，尤其涉及一种电路原理图生成方法及生成系统。
背景技术
电路原理图又称电路图，用图形的方式直观的反映电路中各器件及其电气连接情况，直接体现了电路的结构和工作原理，广泛应用于设计、分析电路中。对于复杂的FPGA集成电路，从逻辑电路线网网表自动生成电路原理图来图形化显示是辅助设计软件不可或缺的提高设计者交互体验的重要工具。
为了增强集成电路设计人员对复杂电路原理图的理解，自动生成的电路图需要规整、对称、可读、易理解，并且尽可能贴近人类普遍的认知习惯，同时为了减少复杂电路的图形化显示反应时间，电路图的自动生成所采用的算法复杂度一般较低。
FPGA集成电路中通常包含BRAM、DSP、IP等比一般逻辑器件大很多的器件，在图形化显示层次化的集成电路设计时，电路中的层次模块的大小相差很大。而现有技术中均采用基于网格的电路图自动生成方法，每个网格区间中放置一个器件，比较适合图形化显示器件大小相差不大的电路，因此并不适合FPGA集成电路或在图形化显示层次化的集成电路设计时使用。
因此，有必要提供一种新型的电路原理图生成方法及生成系统以解决现有技术中存在的上述问题。
发明内容
本发明的目的在于提供一种电路原理图生成方法及生成系统，避免网格的使用，减少连线算法的复杂度以及连线的交叉和弯折。
为实现上述目的，本发明的所述电路原理图生成方法，包括以下步骤：
S1：提供线网网表，根据所述线网网表计算网表器件的层次值，以决定所述网表器件的列；
S2：根据所述线网网表计算所述网表器件的排序值，并根据连通线或反馈线生成与驱动器件相同排序值的伪器件，然后根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；
S3：根据所述排序图生成约束图，然后正向遍历所述约束图，以计算所述网表器件的第一纵向位置的数值；
S4：反向遍历所述约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；
S5：将所述信号连接线分配到相应的纵向线轨，然后计算所述网表器件和所述伪器件的横向位置的数值，将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
本发明的有益效果在于：器件布局不需要基于网格，图形化显示效果更好；根据连通线或反馈线生成与驱动器件相同排序值的伪器件，通过伪器件处理连通线和反馈线，只需要针对相邻器件之间的信号连接，简化了连线算法；根据排序值对同一列上的所述网表器件和所述伪器件进行排序，连线交叉少，器件间的信号连接关系更加清晰；采用了约束图，连线弯折少，器件间的信号连接关系更加清晰。
优选地，所述步骤S1包括以下步骤：
S11：对所述网表器件进行初始化，然后根据所述线网网表建立广度优先搜索队列和反馈器件优先队列；
S12：通过所述广度优先搜索队列和所述反馈器件优先队列计算并更新所述网表器件的层次值，直至所述网表器件的层次值无法得到更新。其有益效果在于：建立所述广度优先搜索队列和所述反馈器件优先队列来计算并更新所述网表器件的层次值，算法复杂度低。
进一步优选地，所述步骤S11中，建立所述广度优先搜索队列时，将所述网表器件中的输入管脚器件添加到所述广度优先搜索队列中。其有益效果在于：采用线网网表建立广度优先搜索队列和反馈器件优先队列来计算网表器件的层次值算法简单，计算效率高。
进一步优选地，所述步骤S11中，建立的所述反馈器件优先队列为空。其有益效果在于：简化初始计算的难度。
进一步优选地，所述步骤S11中，所述初始化包括将所述网表器件的层次值设为1。其有益效果在于：将所述网表器件的层次值设为1便于后续的计算，减少算法的复杂度。
进一步优选地，所述步骤S12包括判断所述广度优先搜索队列不为空，则选取所述广度优先搜索队列中排序第一的网表器件作为优先器件；判断所述优先器件的入度大于0，则将所述优先器件添加到所述反馈器件优先队列中；判断所述优先器件的入度等于0且未处理过，则对所述优先器件的入度大于0的扇出器件进行第一处理。其有益效果在于：便于准确计算网表器件的层次值。
进一步优选地，所述第一处理包括更新所述优先器件的扇出器件的层次值；将所述优先器件的扇出器件的入度减1；将所述优先器件的扇出器件添加到所述广度优先搜索队列中排序最后的位置。其有益效果在于：便于不断更新器件的层次值，以得到最后准确的层次值。
进一步优选地，所述扇出器件的层次值为所述优先器件的层次值加1和所述扇出器件更新前的层次值中的最大值。其有益效果在于：可以得到扇出器件准确的层次值。
进一步优选地，所述步骤S12还包括判断所述反馈器件优先队列不为空，则选取所述反馈器件优先队列中排序第一的网表器件作为反馈器件；判断所述反馈器件的入度大于0且位于回路中，则将所述反馈器件的入度设为0，并将所述反馈器件添加到所述广度优先搜索队列中。其有益效果在于：便于重复计算并更新网表器件的层次值，以得到准确的层次值。
进一步优选地，所述反馈器件优先队列中所述网表器件的层次值由小到大排序。其有益效果在于：使得网表器件的层次值排列清晰，简化算法便于进行计算。
优选地，所述电路原理图自左向右依次为第1列至第n列，所述网表器件中的输入管脚器件放置于第1列，所述网表器件中的输出管脚器件放置于第n列，剩余的所述网表器件放置于第2列至第n-1列，n为大于1的自然数。其有益效果在于：便于使电路原理图更加规整和对称。
进一步优选地，所述步骤S2中，根据输入管脚器件的编码对所述输入管脚器件进行排序，然后将所述输入管脚器件当前排序位置的数值乘阈值，以得到所述输入管脚器件的排序值。其有益效果在于：便于得到输入管脚器件准确的排序值。
进一步优选地，所述阈值为100。其有益效果在于：便于计算网表器件的排序值，使得计算更加清晰简单，避免了小数的出现。
进一步优选地，所述步骤S2中，第2列至第n列的所述网表器件的排序值为所述网表器件各自的扇入器件的排序值的平均值。其有益效果在于：便于计算第2列至第n列的网表器件的排序值。
进一步优选地，所述步骤S2中，若器件之间的排序值相同，则按照该器件扇入器件排序位置的数值的平均值进行排序。其有益效果在于：避免不同器件位于同一纵向位置。
进一步优选地，若平均值相同，按照器件在所述线网网表中的编码进行排 序。其有益效果在于：避免不同器件位于同一纵向位置。
优选地，所述步骤S2中，所述连通线或所述反馈线每穿过一列则在该列上生成一个伪器件。其有益效果在于：完全取消了连通线和反馈线，有利于优化布局。
进一步优选地，所述伪器件的高度为所述电路原理图中横向线轨的高度。其有益效果在于：避免伪器件占用过多的空间，保证整体电路原理图的规整。
进一步优选地，所述步骤S3中根据所述排序图生成约束图包括：所述排序图每列器件中相邻的两个器件生成一个位置约束；每个所述连通线或每个所述反馈线上相邻的两个器件生成一个位置约束；第m列上的器件分别与第m-1列上该器件最高位置扇入器件和最低位置扇入器件形成位置约束，m为大于1且小于或等于n的自然数。其有益效果在于：建立约束图，减少信号连接线的长度，以减少短折现的数量，以增加电路原理图的可读性。
进一步优选地，所述位置约束为一个有向边。其有益效果在于：便于确定信号的传递方向。
进一步优选地，所述约束图中入度为0的器件的第一纵向位置的数值为0。其有益效果在于：优先确定一类器件的第一纵向位置的数值，便于其他器件第一纵向位置的数值的计算。
进一步优选地，所述约束图中入度大于0的器件的第一纵向位置的数值等于该器件的扇入器件的第一纵向位置的数值加上该器件对应入边的相对位置差的最小值。其有益效果在于：初步减少了短弯折线的出现。
优选地，所述步骤S4中，所述约束图中出边数为0的器件的第二纵向位置的数值等于第一纵向位置的数值。其有益效果在于：便于对第二纵向位置的数值进行调整，减少算法计算的复杂度。
进一步优选地，所述步骤S4中，所述约束图中出边数大于0的器件的第二纵向位置的数值等于该器件的扇出器件的第二纵向位置的数值减该器件对应出 边的相对位置差的最大值。其有益效果在于：进一步减少了短弯折线的出现。
优选地，所述信号连接线包括第一类信号连接线、第二类信号连接线和第三类信号连接线，所述第一类信号连接线为输出引脚和输入引脚均在甬道一侧的信号连接线，所述第二类信号连接线为输出引脚和输入引脚位于甬道两侧的信号连接线，所述第三类信号连接线为输出引脚和输入引脚均在甬道另一侧的信号连接线。其有益效果在于：减少了信号连接线的交叉。
进一步优选地，所述步骤S5包括：将所述第一类信号连接线通过第二处理分配到相应的纵向线轨，然后将所述第二类信号连接线通过所述第二处理分配到相应的纵向线轨，最后将所述第三类信号连接线通过所述第二处理分配到相应的纵向线轨，以将所述信号连接线分配到相应的纵向线轨。其有益效果在于：只需要处理相邻两列网表器件之间的信号连接，无需考虑连通线和反馈线，布线更加更简单。
进一步优选地，所述第二处理包括：将所述第一类信号连接线、所述第二类信号连接线或所述第三类信号连接线按照引脚的最小纵向坐标从小到大进行排序；按照所述信号连接线的排序顺序依次分配到最左边的纵向线轨，若两条所述信号连接线重叠，则选择下一条纵向线轨，直至所述信号连接线分配完毕。其有益效果在于：避免信号连接线出现重叠，且能避免纵向线轨的浪费，提高了整体布局的紧凑性。
本发明还提供了一种电路原理图生成系统，所述电路原理图生成系统包括层次值计算模块、排序值计算模块、伪器件生成模块、排序图生成模块、约束图生成模块、第一计算模块、第二计算模块、纵向线轨分配模块、第三计算模块和信号线连接模块，所述层次值计算模块用于根据线网网表计算网表器件的层次值，以决定所述网表器件的列；所述排序值计算模块用于根据线网网表计算所述网表器件的排序值；所述伪器件生成模块用于根据连通线或反馈线生成与驱动器件相同排序值的伪器件；所述排序图生成模块用于根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；所述约束图生成 模块用于根据排序图生成约束图；所述第一计算模块用于正向遍历约束图，以计算所述网表器件的第一纵向位置的数值；所述第二计算模块用于反向遍历约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；所述纵向线轨分配模块用于将所述信号连接线分配到相应的纵向线轨；所述第三计算模块用于计算所述网表器件和所述伪器件的横向位置的数值；所述信号线连接模块用于将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
本发明所述电路原理图生成系统的有益效果在于：器件布局不需要基于网格，图形化显示效果更好；所述伪器件生成模块根据连通线或反馈线生成与驱动器件相同排序值的伪器件，通过伪器件处理连通线和反馈线，只需要针对相邻器件之间的信号连接，简化了连线算法；所述排序图生成模块根据排序值对同一列上的所述网表器件和所述伪器件进行排序，连线交叉少，器件间的信号连接关系更加清晰；所述排序图生成模块生成约束图，连线弯折少，器件间的信号连接关系更加清晰。
附图说明
图1为本发明电路原理图生成方法的流程图；
图2为本发明电路原理图生成系统的结构框图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本文中使用的 “包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
针对现有技术存在的问题，本发明的实施例提供了一种电路原理图生成方法，参照图1，所述电路原理图生成方法包括以下步骤：
S1：提供线网网表，根据所述线网网表计算网表器件的层次值，以决定所述网表器件的列；
S2：根据所述线网网表计算所述网表器件的排序值，并根据连通线或反馈线生成与驱动器件相同排序值的伪器件，然后根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；
S3：根据所述排序图生成约束图，然后正向遍历所述约束图，以计算所述网表器件的第一纵向位置的数值；
S4：反向遍历所述约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；
S5：将信号连接线分配到相应的纵向线轨，然后计算所述网表器件和所述伪器件的横向位置的数值，将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
本发明的一些实施例中，所述层次值相同的网表器件为一列。
本发明的一些实施例中，所述步骤S1包括以下步骤：
S11：对所述网表器件进行初始化，以将所述网表器件的层次值设为1，然后根据线网网表建立广度优先搜索队列和反馈器件优先队列，其中将所述网表器件中的输入管脚器件添加到所述广度优先搜索队列中，且所述反馈器件优先队列为空；
S12：通过所述广度优先搜索队列和所述反馈器件优先队列计算并更新所述网表器件的层次值，直至所述网表器件的层次值无法得到更新。
本发明的一些实施例中，所述步骤S12包括步骤a，所述步骤a包括判断所述广度优先搜索队列不为空，则选取所述广度优先搜索队列中排序第一的网表器件作为优先器件；判断所述优先器件的入度大于0，则将所述优先器件添加到所述反馈器件优先队列中；判断所述优先器件的入度等于0且未处理过，则对所述优先器件的入度大于0的扇出器件进行第一处理。
本发明的一些实施例中，所述步骤a还包括判断所述优先器件的入度等于0且处理过，则按所述广度优先搜索队列中的排序选取下一个网表器件作为优先器件。
本发明的一些实施例中，重复执行所述步骤a，直至所述广度优先搜索队列中所述网表器件的入度均为0且被处理过。
本发明的一些实施例中，所述第一处理包括更新所述优先器件的扇出器件的层次值；将所述优先器件的扇出器件的入度减1；将所述优先器件的扇出器件添加到所述广度优先搜索队列中排序最后的位置。
本发明的一些实施例中，所述扇出器件的层次值为优先器件的层次值加1和所述扇出器件更新前的层次值中的最大值。
本发明的一些实施例中，所述步骤S12还包括步骤b，所述步骤b包括判断所述反馈器件优先队列不为空，则选取所述反馈器件优先队列中排序第一的网表器件作为反馈器件；判断所述反馈器件的入度大于0且位于回路中，则将所述反馈器件的入度设为0，并将所述反馈器件添加到所述广度优先搜索队列中，然后执行所述步骤a。
本发明的一些实施例中，所述步骤b还包括判断所述反馈器件的入度等于0或所述反馈器件位于回路中，则执行所述步骤a。
本发明的一些实施例中，判断所述反馈器件是否位于回路中时，忽略当前入度为0的所述网表器件，并保存不属于回路的所述网表器件的信息，以便于下次检查该网表器件是否位于回路中时直接返回否定结果。
本发明的一些实施例中，所述所述反馈器件优先队列中所述网表器件的层次值由小到大排序。
本发明的一些实施例中，所述电路原理图自左向右依次为第1列至第n列，所述网表器件中的输入管脚器件放置于第1列，所述网表器件中的输出管脚器件放置于第n列，剩余的所述网表器件放置于第2列至第n-1列，n为大于1的自然数。
本发明的一些实施例中，所述步骤S2中，根据所述输入管脚器件的编码对所述输入管脚器件进行排序，然后将所述输入管脚器件当前排序位置的数值乘阈值，以得到所述输入管脚器件的排序值。
本发明的一些实施例中，所述阈值为100，以便于后续所述网表器件的排序值的计算，避免小数的出现，简化算法。
本发明的一些实施例中，所述步骤S2中，第2列至第n列的所述网表器件的排序值为所述网表器件各自的扇入器件的排序值的平均值。
本发明的一些实施例中，所述步骤S2中，若器件之间的排序值相同，则按照该器件的扇入器件排序位置的数值的平均值进行排序，所述器件之间包括所述网表器件和所述伪器件之间、两个所述网表器件之间和两个所述伪器件之间。
本发明的一些实施例中，若平均值相同，按照器件在所述线网网表中的编码进行排序，所述器件包括所述网表器件和所述伪器件。
本发明的一些实施例中，所述步骤S2中，所述连通线或所述反馈线每穿过一列则在该列上生成一个所述伪器件，所述所述伪器件的高度为电路原理图中横向线轨的高度。
本发明的一些实施例中，所述步骤S3中根据排序图生成约束图包括：排序图每列器件中相邻的两个器件生成一个位置约束，第一相对位置差为前一个器件的高度；每个所述连通线或每个所述反馈线上相邻的两个器件生成一个位置约束，其中同一所述连通线上伪器件的位置高度高于或等于前一列伪器件或驱 动器件的位置高度，同一所述反馈线上伪器件的高度高于或等于后一列的伪器件或驱动器件的位置高度，第二相对位置差为0；第m列上的器件分别与第m-1列上该器件最高位置扇入器件和最低位置扇入器件形成位置约束，其中最低位置扇入器件的位置高度低于或等于该器件的位置高度，最高位置扇入器件的位置高度高于或等于该器件的位置高度，第三相对位置差为信号连接线连接的输出引脚和输入引脚在器件上的相对位置高度差，m为大于1且小于或等于n的自然数。
本发明的一些实施例中，所述驱动器件为发送信息的器件。
本发明的一些实施例中，所述最高位置扇入器件和所述最低位置扇入器件均为扇入器件和伪器件中的一种。
本发明的一些实施例中，所述位置约束为一个有向边，所述有向边具有方向，每列器件相邻的两个器件之间有向边的方向由在前器件指向在后器件，连通线或反馈线上相邻的两个器件之间有向边的方向和信号的传递方向相同，第m列上的器件分别与第m-1列上该器件最高位置扇入器件之间和最低位置扇入器件之间的有向边和信号的传递方向相同。
本发明的一些实施例中，所述约束图中入度为0的器件的第一纵向位置的数值为0。
本发明的一些实施例中，所述约束图中入度大于0的器件的第一纵向位置的数值等于该器件的扇入器件的第一纵向位置的数值加上该器件对应入边的相对位置差得到的结果中的最小值，其中相对位置差包括第一相对位置差、第二相对位置差和第三相对位置差中的至少一种。
本发明的一些实施例中，所述步骤S4中，所述约束图中出边数为0的器件的第二纵向位置的数值等于第一纵向位置的数值。
本发明的一些实施例中，所述步骤S4中，所述约束图中出边数大于0的器件的第二纵向位置的数值等于该器件的扇出器件的第二纵向位置的数值减该器 件对应出边的相对位置差得到的结果中的最大值，其中相对位置差包括第一相对位置差、第二相对位置差和第三相对位置差中的至少一种。
本发明的一些实施例中，所述信号连接线包括第一类信号连接线、第二类信号连接线和第三类信号连接线。第一类信号连接线为输出引脚和输入引脚均在甬道一侧的信号连接线，具体地，为所述甬道的左侧；第二类信号连接线为输出引脚和输入引脚位于甬道两侧的信号连接线；第三类信号连接线为输出引脚和输入引脚均在甬道另一侧的信号连接线，具体地，为所述甬道的右侧。其中，甬道包括至少包括一条纵向线轨。
本发明的一些实施例中，所述步骤S5包括：将所述第一类信号连接线通过第二处理分配到相应的纵向线轨，然后将所述第二类信号连接线通过所述第二处理分配到相应的纵向线轨，最后将所述第三类信号连接线通过所述第二处理分配到相应的纵向线轨，以将所述信号连接线分配到相应的纵向线轨。
本发明的一些实施例中，所述第二处理包括：将所述第一类信号连接线、所述第二类信号连接线或所述第三类信号连接线按照引脚的最小纵向坐标从小到大进行排序；按照所述信号连接线的排序顺序依次分配到最左边的纵向线轨，若两条信号连接线重叠，则选择下一条纵向线轨，直至所述信号连接线分配完毕。其中，引脚包括输出引脚和输入引脚。
本发明的一些实施例中，根据所述网表器件和所述伪器件的第二纵向位置的数值计算信号连接线的最大纵向坐标和最小纵向坐标。
本发明的一些实施例中，通过所述信号连接线的最大纵向坐标和最小纵向坐标判断同一纵向线轨上的两条信号连接线是否重叠，若第一条信号连接线的最大纵向坐标小于或等于第二条信号连接线的最小纵向坐标，则第一条信号连接线和第二条信号连接线重叠。
本发明的一些实施例中，所述网表器件和所述伪器件的宽度相同。
本发明的一些实施例中，器件宽度乘该列器件的列数以得到第一数值，第 一数值加该列器件前所有甬道的宽度以得到一列器件的横向位置的数值。
本发明的一些实施例中，所述信号连接线包括依次连接的第一线段、第二线段和第三线段，所述第二线段位于纵向线轨内，所述第一线段与信号输出所述网表器件或所述伪器件连接，所述第三线段与信号接收的所述网表器件或所述伪器件连接。
本发明的一些实施例中，所述网表器件的宽度、所述纵向线轨的宽度和所述横向线轨的高度均设有阈值，且第一纵向位置的数值和第二纵向位置的数值代表距离。
本发明的一些实施例中，所述连通线为不在相邻列的所述网表器件之间的连接线，且信号自左向右传递。
本发明的一些实施例中，所述反馈线为不在相邻列的所述网表器件之间的连接线，且信号自左向右传递。
本发明的一些实施例中，所述信号连接线为相邻列的所述网表器件之间的连接线。
图2为本发明一些实施例中电路原理图生成系统的结构框图。参照图2，所述电路原理图生成系统10包括层次值计算模块101、排序值计算模块102、伪器件生成模块103、排序图生成模块104、约束图生成模块105、第一计算模块106、第二计算模块107、纵向线轨分配模块108、第三计算模块109和信号线连接模块110。所述层次值计算模块101用于根据线网网表计算网表器件的层次值，以决定所述网表器件的列；所述排序值计算模块102用于根据线网网表计算所述网表器件的排序值；所述伪器件生成模块103用于根据连通线或反馈线生成与驱动器件相同排序值的伪器件；所述排序图生成模块104用于根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；所述约束图生成模块105用于根据排序图生成约束图；所述第一计算模块106用于正向遍历约束图，以计算所述网表器件的第一纵向位置的数值；所述第二计算模 块107用于反向遍历约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；所述纵向线轨分配模块108用于将所述信号连接线分配到相应的纵向线轨；所述第三计算模块109用于计算所述网表器件和所述伪器件的横向位置的数值；所述信号线连接模块110用于将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
虽然在上文中详细说明了本发明的实施方式，但是对于本领域的技术人员来说显而易见的是，能够对这些实施方式进行各种修改和变化。但是，应理解，这种修改和变化都属于权利要求书中所述的本发明的范围和精神之内。而且，在此说明的本发明可有其它的实施方式，并且可通过多种方式实施或实现。

Claims (28)

  1. 一种电路原理图生成方法，其特征在于，包括以下步骤：
    S1：提供线网网表，根据所述线网网表计算网表器件的层次值，以决定所述网表器件的列；
    S2：根据所述线网网表计算所述网表器件的排序值，并根据连通线或反馈线生成与驱动器件相同排序值的伪器件，然后根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；
    S3：根据所述排序图生成约束图，然后正向遍历所述约束图，以计算所述网表器件的第一纵向位置的数值；
    S4：反向遍历所述约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；
    S5：将信号连接线分配到相应的纵向线轨，然后计算所述网表器件和所述伪器件的横向位置的数值，将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
  2. 根据权利要求1所述的电路原理图生成方法，其特征在于，所述步骤S1包括以下步骤：
    S11：对所述网表器件进行初始化，然后根据所述线网网表建立广度优先搜索队列和反馈器件优先队列；
    S12：通过所述广度优先搜索队列和所述反馈器件优先队列计算并更新所述网表器件的层次值，直至所述网表器件的层次值无法得到更新。
  3. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述步骤S11中，建立所述广度优先搜索队列时，将所述网表器件中的输入管脚器件添加到所述广度优先搜索队列中。
  4. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述步骤S11中，建立的所述反馈器件优先队列为空。
  5. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述步骤S11中，所述初始化包括将所述网表器件的层次值设为1。
  6. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述步骤S12包括判断所述广度优先搜索队列不为空，则选取所述广度优先搜索队列中排序第一的网表器件作为优先器件；判断所述优先器件的入度大于0，则将所述优先器件添加到所述反馈器件优先队列中；判断所述优先器件的入度等于0且未处理过，则对所述优先器件的入度大于0的扇出器件进行第一处理。
  7. 根据权利要求6所述的电路原理图生成方法，其特征在于，所述第一处理包括更新所述优先器件的扇出器件的层次值；将所述优先器件的扇出器件的入度减1；将所述优先器件的扇出器件添加到所述广度优先搜索队列中排序最后的位置。
  8. 根据权利要求7所述的电路原理图生成方法，其特征在于，所述扇出器件的层次值为所述优先器件的层次值加1和所述扇出器件更新前的层次值中的最大值。
  9. 根据权利要求6所述的电路原理图生成方法，其特征在于，所述步骤S12还包括判断所述反馈器件优先队列不为空，则选取所述反馈器件优先队列中排序第一的网表器件作为反馈器件；判断所述反馈器件的入度大于0且位于回路中，则将所述反馈器件的入度设为0，并将所述反馈器件添加到所述广度优先搜索队列中。
  10. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述反馈器件优先队列中所述网表器件的层次值由小到大排序。
  11. 根据权利要求1所述的电路原理图生成方法，其特征在于，所述电路原理图自左向右依次为第1列至第n列，所述网表器件中的输入管脚器件放置 于第1列，所述网表器件中的输出管脚器件放置于第n列，剩余的所述网表器件放置于第2列至第n-1列，n为大于1的自然数。
  12. 根据权利要求11所述的电路原理图生成方法，其特征在于，所述步骤S2中，根据输入管脚器件的编码对所述输入管脚器件进行排序，然后将所述输入管脚器件当前排序位置的数值乘阈值，以得到所述输入管脚器件的排序值。
  13. 根据权利要求12所述的电路原理图生成方法，其特征在于，所述阈值为100。
  14. 根据权利要求12所述的电路原理图生成方法，其特征在于，所述步骤S2中，第2列至第n列的网表器件的排序值为网表器件各自的扇入器件的排序值的平均值。
  15. 根据权利要求2所述的电路原理图生成方法，其特征在于，所述步骤S2中，若器件之间的排序值相同，则按照该器件扇入器件的排序位置数值的平均值进行排序。
  16. 根据权利要求15所述的电路原理图生成方法，其特征在于，若平均值相同，按照器件在线网网表中的编码进行排序。
  17. 根据权利要求1所述的电路原理图生成方法，其特征在于，所述步骤S2中，所述连通线或所述反馈线每穿过一列则在该列上生成一个所述伪器件。
  18. 根据权利要求17所述的电路原理图生成方法，其特征在于，所述伪器件的高度为所述电路原理图中横向线轨的高度。
  19. 根据权利要求11所述的电路原理图生成方法，其特征在于，所述步骤S3中根据所述排序图生成约束图包括：所述排序图每列器件中相邻的两个器件生成一个位置约束；每个所述连通线或每个所述反馈线上相邻的两个器件生成一个位置约束；第m列上的器件分别与第m-1列上该器件最高位置扇入器件和最低位置扇入器件形成位置约束，m为大于1且小于或等于n的自然数。
  20. 根据权利要求19所述的电路原理图生成方法，其特征在于，所述位置约束为一个有向边。
  21. 根据权利要求19所述的电路原理图生成方法，其特征在于，所述约束图中入度为0的器件的第一纵向位置的数值为0。
  22. 根据权利要求19所述的电路原理图生成方法，其特征在于，所述约束图中入度大于0的器件的第一纵向位置的数值等于该器件的扇入器件的第一纵向位置的数值加上该器件对应入边的相对位置差的最小值。
  23. 根据权利要求1所述的电路原理图生成方法，其特征在于，所述步骤S4中，所述约束图中出边数为0的器件的第二纵向位置的数值等于第一纵向位置的数值。
  24. 根据权利要求23所述的电路原理图生成方法，其特征在于，所述步骤S4中，所述约束图中出边数大于0的器件的第二纵向位置的数值等于该器件的扇出器件的第二纵向位置的数值减该器件对应出边的相对位置差的最大值。
  25. 根据权利要求1所述的电路原理图生成方法，其特征在于，所述信号连接线包括第一类信号连接线、第二类信号连接线和第三类信号连接线，所述第一类信号连接线为输出引脚和输入引脚均在甬道一侧的信号连接线，所述第二类信号连接线为输出引脚和输入引脚位于甬道两侧的信号连接线，所述第三类信号连接线为输出引脚和输入引脚均在甬道另一侧的信号连接线。
  26. 根据权利要求25所述的电路原理图生成方法，其特征在于，所述步骤S5包括：将所述第一类信号连接线通过第二处理分配到相应的纵向线轨，然后将所述第二类信号连接线通过所述第二处理分配到相应的纵向线轨，最后将所述第三类信号连接线通过所述第二处理分配到相应的纵向线轨，以将所述信号连接线分配到相应的纵向线轨。
  27. 根据权利要求26所述的电路原理图生成方法，其特征在于，所述第二处理包括：将所述第一类信号连接线、所述第二类信号连接线或所述第三类信 号连接线按照引脚的最小纵向坐标从小到大进行排序；按照信号连接线的排序顺序依次分配到最左边的纵向线轨，若两条信号连接线重叠，则选择下一条纵向线轨，直至所述信号连接线分配完毕。
  28. 一种电路原理图生成系统，其特征在于，用于实现权利要求1-27中任意一项所述的电路原理图生成方法，所述电路原理图生成系统包括层次值计算模块、排序值计算模块、伪器件生成模块、排序图生成模块、约束图生成模块、第一计算模块、第二计算模块、纵向线轨分配模块、第三计算模块和信号线连接模块，
    所述层次值计算模块用于根据线网网表计算网表器件的层次值，以决定所述网表器件的列；
    所述排序值计算模块用于根据线网网表计算所述网表器件的排序值；
    所述伪器件生成模块用于根据连通线或反馈线生成与驱动器件相同排序值的伪器件；
    所述排序图生成模块用于根据排序值对同一列上的所述网表器件和所述伪器件进行排序，以生成排序图；
    所述约束图生成模块用于根据排序图生成约束图；
    所述第一计算模块用于正向遍历约束图，以计算所述网表器件的第一纵向位置的数值；
    所述第二计算模块用于反向遍历约束图，以对所述网表器件的第一纵向位置的数值进行调整并生成第二纵向位置的数值；
    所述纵向线轨分配模块用于将所述信号连接线分配到相应的纵向线轨；
    所述第三计算模块用于计算所述网表器件和所述伪器件的横向位置的数值；
    所述信号线连接模块用于将所述网表器件或所述伪器件与相应的信号连接线连接，以生成电路原理图。
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