WO2021082510A1 - Semiconductor package structure having micro-isolation cavity - Google Patents

Semiconductor package structure having micro-isolation cavity Download PDF

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Publication number
WO2021082510A1
WO2021082510A1 PCT/CN2020/100509 CN2020100509W WO2021082510A1 WO 2021082510 A1 WO2021082510 A1 WO 2021082510A1 CN 2020100509 W CN2020100509 W CN 2020100509W WO 2021082510 A1 WO2021082510 A1 WO 2021082510A1
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chip
dielectric
metal wiring
circuit board
laminated circuit
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PCT/CN2020/100509
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French (fr)
Chinese (zh)
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徐志伟
高会言
厉敏
李娜雨
张梓江
王绍刚
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浙江大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to the technical field of integrated circuit packaging, in particular to a semiconductor packaging structure with micro-cavities.
  • Phased array technology is a key technology in the communication field to improve spectrum efficiency, increase transmission rate, and improve reliability.
  • the RF transceiver chip integrates multiple channels, and each RF transceiver channel will be affected by electromagnetic interference from other channels on the same chip.
  • the receiving circuit of the radio frequency integrated circuit is susceptible to interference from external electromagnetic signals.
  • the low-noise amplifier is very sensitive to external electromagnetic waves and substrate crosstalk; the transmitting circuit will generate electromagnetic interference signals, such as the power driver, which does not need to be emitted.
  • the electromagnetic wave of the electromagnetic wave and injects the crosstalk signal into the substrate some radio frequency circuits are sensitive to the external electromagnetic crosstalk signal, but also generate electromagnetic interference signals, such as voltage-controlled oscillators.
  • electromagnetic shielding covers were usually used to increase the isolation, but this was only suitable for isolation between chips and could not increase the isolation between channels within the chips. At the same time, this solution also increased the complexity and weight of the system.
  • the isolation between channels in the semiconductor chip is also affected by the packaging process.
  • high-performance chip packaging processes include wire bond packaging, ball grid array packaging, and so on.
  • Wire bonding packaging technology connects the chip pad and the package substrate through a metal rod wire, but a longer rod wire will increase signal attenuation and reduce system integration. The parasitic effect introduced will greatly reduce the performance of the chip.
  • the electromagnetic coupling effect between adjacent channel RF signal bars will reduce the isolation between channels and degrade system performance.
  • Another common packaging technology, ball grid array packaging has the advantages of small size, high pin density, and good electrical performance. It is mainly used in digital and analog integrated circuits with dense input and output pins.
  • the number of pins of the radio frequency transceiver chip has gradually increased, but it is difficult to ensure the isolation between channels on the chip using traditional packaging technology.
  • the need to improve the existing packaging process to improve isolation is particularly urgent.
  • the present invention proposes a semiconductor package structure with micro-cavities, which has high pin density, low package parasitics, and high isolation between channels.
  • a semiconductor packaging structure with micro-cavities characterized in that the semiconductor packaging structure includes a multi-channel or multi-module semiconductor chip, a thermally conductive substrate, a fixed filler, a metal solder ball, and a laminated circuit board.
  • a rectangular groove slightly larger than the chip is formed on the thermally conductive substrate, and fixed fillers are added to the sidewall and top surface of the thermally conductive substrate for the bonding of the semiconductor chip and the thermally conductive substrate.
  • the semiconductor chip pad direction is downwardly connected to the metal solder ball, and the other side of the metal solder ball is connected to the laminated circuit board, and the laminated circuit board Including metal wiring layers M1, M2,..., Mn, dielectric layers IMD1, IMD2,..., IMD(n-1), vias connecting different metal wiring layers, adjacent metal wiring layers are separated by dielectric layers, Any two or more metal wiring layers are connected by vias;
  • the pads of the multi-channel or multi-module chip are connected to metal solder balls and connected to the metal wiring layer M1 on the top layer of the laminated circuit; the chip is divided into different areas according to the channel or module to form a channel or module 1 , Channel or module 2,..., channel or module n, etc.; metal solder balls are arranged tightly on the peripheral boundary of each area, so that the chip, metal solder ball and laminated circuit board form an effective reduction of electromagnetic waves between channels or modules Coupled micro-cavity structure.
  • the said dielectric layer is composed of two different materials of dielectric layers, the dielectric layer formed by medium one and the medium layer formed by medium two are arranged alternately, and the material of the top and bottom layers of the laminated circuit board is medium one, A metal wiring layer is formed inside or on the surface of the dielectric layer formed by the first medium, and no metal wiring layer is formed inside the dielectric layer formed by the second medium.
  • the material of the metal wiring layer is copper
  • the material of the metal solder ball is a copper-tin-silver alloy.
  • the invention connects the inverted chip to the laminated circuit board through metal solder balls, improves pin density, reduces package size, reduces overall weight, reduces interconnection line transmission loss, and improves the performance of the radio frequency system.
  • the metal solder balls, chips, and laminated circuit boards closely arranged at the channel or module boundary form a micro-compartment structure, which limits the electrical and magnetic interference signals generated by the channel circuit within the micro-compartment, thereby reducing the gap between the modules of the chip.
  • the coupling and crosstalk improve the isolation between channels.
  • FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor package structure with micro-cavities according to the present invention.
  • Fig. 2 is a bottom view of a chip of a semiconductor package structure with micro-cavities according to the present invention.
  • FIG. 1 a cross-sectional structure diagram of a semiconductor package structure with micro-cavities according to the present invention.
  • the flip-chip package micro-cavity structure includes a thermally conductive substrate, a fixed filler, an integrated circuit chip, and a metal solder ball. , Metal wiring layers M1, M2, ..., Mn, dielectric layers IMD1, IMD2, ..., IMD(n-1), and vias connecting different metal wiring layers.
  • a rectangular groove slightly larger than the chip is formed under the thermally conductive substrate, and fixed fillers are added to the sidewall and top surface to bond the chip and the substrate.
  • the integrated circuit chip is bonded to the thermally conductive substrate by flipping the chip. In the cavity.
  • the die pad direction is connected to the metal solder ball downwards, and the other side of the metal solder ball is connected to the metal wiring layer M1 of the laminated circuit board.
  • the n-1 dielectric layer is laminated under the chip, and the upper and lower sides of each dielectric layer are connected with The metal wiring layer forms a total of n metal wiring layers. Any two or more metal wiring layers are connected through vias.
  • the dielectric layer of the laminated circuit board is composed of two dielectric layers of different materials, and the dielectric layer formed by the first medium and the dielectric layer formed by the second medium are arranged alternately.
  • the material of the top and bottom layers of the laminated circuit board is dielectric one, and a metal wiring layer is formed inside or on the surface of the dielectric layer formed by dielectric one; no metal wiring layer is formed inside the dielectric layer formed by dielectric two.
  • Fig. 2 is a bottom view of a chip of a semiconductor package structure with micro-cavities according to the present invention.
  • Metal solder balls are connected to the pads of the multi-channel or multi-module chip and connected to the metal wiring layer M1 on the top layer of the laminated circuit.
  • the chip is divided into different areas according to different channels or modules, forming channel or module 1, channel or module 2,..., channel or module n, etc.
  • Metal solder balls are tightly arranged on the peripheral boundary of each area, so that the chip, the metal solder balls and the laminated circuit board form a micro-cavity structure that can effectively reduce the electromagnetic coupling between channels or between modules.
  • the material of the metal wiring layer is copper
  • the material of the metal solder ball is a copper-tin-silver alloy.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

Disclosed in the present invention is a semiconductor package structure having a micro-isolation cavity, comprising a multi-channel or multi-module semiconductor chip, a heat conductive substrate, a fixing filler, metal solder balls, metal wiring layers, dielectric layers, and via holes. A groove slightly larger than the chip is formed on the heat conductive substrate, the chip is placed in the groove in a flip-chip manner and bonded with the heat conductive substrate, and a chip pad is connected to a laminated circuit board below the chip pad by means of the metal solder balls. The laminated circuit board is provided with multiple metal wiring layers, the metal wiring layers are isolated by the dielectric layers, and different metal wiring layers are interconnected using the via holes. The chip is divided into different areas depending on channels or modules, the metal solder balls are closely arranged on the peripheral boundary of each area, and the chip, the metal solder balls, and the laminated circuit board form a micro-isolation cavity structure capable of effectively reducing electromagnetic coupling between the channels or modules. According to the present invention, the package volume is reduced, the transmission loss of a signal on an interconnection line is reduced, the degree of isolation between the channels or modules of the chip is effectively improved, and the system performance is improved.

Description

一种带有微隔腔的半导体封装结构Semiconductor packaging structure with micro-cavity 技术领域Technical field
本发明涉及集成电路封装技术领域，具体涉及一种带有微隔腔的半导体封装结构。The invention relates to the technical field of integrated circuit packaging, in particular to a semiconductor packaging structure with micro-cavities.
背景技术Background technique
相控阵列技术是通信领域中提升频谱效率、增加传输速率、提高可靠性的关键技术。为了支持阵列化天线应用，射频收发芯片集成了多个通道，每个射频收发通道会受到同一芯片上其他通道电磁干扰的影响。具体而言，射频集成电路的接收电路容易受到外界电磁信号的干扰，如低噪声放大器对外部电磁波和衬底串扰非常敏感；发射电路则会产生电磁干扰信号，如功率驱动器会向外发射不需要的电磁波并向衬底注入串扰信号；部分射频电路既对外界的电磁串扰信号敏感，又会产生电磁干扰信号，如压控振荡器。过去的系统通常采用电磁屏蔽罩增加隔离度，但这只适用于芯片间的隔离，无法增加芯片内通道间的隔离度，同时这种方案也增加了系统的复杂度和重量。Phased array technology is a key technology in the communication field to improve spectrum efficiency, increase transmission rate, and improve reliability. In order to support the application of arrayed antennas, the RF transceiver chip integrates multiple channels, and each RF transceiver channel will be affected by electromagnetic interference from other channels on the same chip. Specifically, the receiving circuit of the radio frequency integrated circuit is susceptible to interference from external electromagnetic signals. For example, the low-noise amplifier is very sensitive to external electromagnetic waves and substrate crosstalk; the transmitting circuit will generate electromagnetic interference signals, such as the power driver, which does not need to be emitted. The electromagnetic wave of the electromagnetic wave and injects the crosstalk signal into the substrate; some radio frequency circuits are sensitive to the external electromagnetic crosstalk signal, but also generate electromagnetic interference signals, such as voltage-controlled oscillators. In the past systems, electromagnetic shielding covers were usually used to increase the isolation, but this was only suitable for isolation between chips and could not increase the isolation between channels within the chips. At the same time, this solution also increased the complexity and weight of the system.
半导体芯片内通道间隔离度还会受到封装工艺的影响。目前常用的高性能芯片封装工艺包括引线键合封装、球栅阵列封装等。引线键合封装技术通过金属棒线连接芯片焊盘和封装基板，但是较长的棒线会增加信号的衰减，降低系统集成度，引入的寄生效应会使芯片的性能大打折扣。在多通道射频收发芯片中，相邻通道射频信号棒线之间的电磁耦合效应会降低通道间隔离度，恶化系统性能。另一种常见封装技术，球栅阵列封装，具有体积小、引脚密度高、电性能好的优点，主要应用于输入输出引脚密集的数字和模拟集成电路。随着集成度的提高，射频收发芯片的引脚数量也逐渐增加，但采用传统封装技术难以保证片内通道间隔离度。针对高集成度多通道或多模块射频芯片，改进现有封装工艺改善隔离度的需求显的尤为迫切。The isolation between channels in the semiconductor chip is also affected by the packaging process. Currently commonly used high-performance chip packaging processes include wire bond packaging, ball grid array packaging, and so on. Wire bonding packaging technology connects the chip pad and the package substrate through a metal rod wire, but a longer rod wire will increase signal attenuation and reduce system integration. The parasitic effect introduced will greatly reduce the performance of the chip. In a multi-channel RF transceiver chip, the electromagnetic coupling effect between adjacent channel RF signal bars will reduce the isolation between channels and degrade system performance. Another common packaging technology, ball grid array packaging, has the advantages of small size, high pin density, and good electrical performance. It is mainly used in digital and analog integrated circuits with dense input and output pins. With the improvement of integration, the number of pins of the radio frequency transceiver chip has gradually increased, but it is difficult to ensure the isolation between channels on the chip using traditional packaging technology. For highly integrated multi-channel or multi-module radio frequency chips, the need to improve the existing packaging process to improve isolation is particularly urgent.
发明内容Summary of the invention
针对现有技术的不足，本发明提出一种带有微隔腔的半导体封装结构，该结构引脚密度高、封装寄生小、通道间隔离度高。In view of the shortcomings of the prior art, the present invention proposes a semiconductor package structure with micro-cavities, which has high pin density, low package parasitics, and high isolation between channels.
本发明的目的通过如下技术方案来实现：The purpose of the present invention is achieved through the following technical solutions:
一种带有微隔腔的半导体封装结构，其特征在于，所述的半导体封装结构包括多通道或多模块的半导体芯片、导热基板、固定填充物、金属焊球、层压电路板，所述的导热基板上形成略大于芯片的长方形凹槽，在其侧壁和顶面加入固定填充物用于半导体芯片和导热基板的粘接，所述的半导体芯片采用倒片摆放的方式粘接在所述的导热基板的腔体中，所 述的半导体芯片焊盘方向向下连接所述的金属焊球，所述的金属焊球另一侧连接层压电路板，所述的层压电路板包括金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔，相邻的金属布线层由介质层隔开，任意两层或多层金属布线层之间均通过过孔相连；A semiconductor packaging structure with micro-cavities, characterized in that the semiconductor packaging structure includes a multi-channel or multi-module semiconductor chip, a thermally conductive substrate, a fixed filler, a metal solder ball, and a laminated circuit board. A rectangular groove slightly larger than the chip is formed on the thermally conductive substrate, and fixed fillers are added to the sidewall and top surface of the thermally conductive substrate for the bonding of the semiconductor chip and the thermally conductive substrate. In the cavity of the thermally conductive substrate, the semiconductor chip pad direction is downwardly connected to the metal solder ball, and the other side of the metal solder ball is connected to the laminated circuit board, and the laminated circuit board Including metal wiring layers M1, M2,..., Mn, dielectric layers IMD1, IMD2,..., IMD(n-1), vias connecting different metal wiring layers, adjacent metal wiring layers are separated by dielectric layers, Any two or more metal wiring layers are connected by vias;
所述的多通道或多模块芯片的焊盘连接金属焊球，并与层压电路顶层的金属布线层M1相连；在芯片上按照通道或模块的不同划分成不同的区域，形成通道或模块1、通道或模块2、……、通道或模块n等；在每个区域的周围边界上紧密排布金属焊球，由此芯片、金属焊球和层压电路板形成有效降低通道间或模块间电磁耦合的微隔腔结构。The pads of the multi-channel or multi-module chip are connected to metal solder balls and connected to the metal wiring layer M1 on the top layer of the laminated circuit; the chip is divided into different areas according to the channel or module to form a channel or module 1 , Channel or module 2,..., channel or module n, etc.; metal solder balls are arranged tightly on the peripheral boundary of each area, so that the chip, metal solder ball and laminated circuit board form an effective reduction of electromagnetic waves between channels or modules Coupled micro-cavity structure.
进一步地，所述的介质层由两种不同材料的介质层组成，由介质一形成的介质层和由介质二形成的介质层相间排列，层压电路板的顶层和底层的材料为介质一，在由介质一形成的介质层内部或表面形成金属布线层，在由介质二形成的介质层内部不形成金属布线层。Further, the said dielectric layer is composed of two different materials of dielectric layers, the dielectric layer formed by medium one and the medium layer formed by medium two are arranged alternately, and the material of the top and bottom layers of the laminated circuit board is medium one, A metal wiring layer is formed inside or on the surface of the dielectric layer formed by the first medium, and no metal wiring layer is formed inside the dielectric layer formed by the second medium.
进一步地，所述的金属布线层材料为铜，所述的金属焊球材料为铜锡银合金。Further, the material of the metal wiring layer is copper, and the material of the metal solder ball is a copper-tin-silver alloy.
本发明的有益效果如下：The beneficial effects of the present invention are as follows:
本发明将倒放芯片通过金属焊球与层压电路板连接，提高引脚密度，缩小封装尺寸，减轻整体重量，降低互连线的传输损耗，改善射频系统的性能。在通道或模块边界紧密排列的金属焊球、芯片和层压电路板形成了微隔腔结构，将所述通道电路产生的电、磁干扰信号限制在微隔腔内部，从而减少芯片各模块间的耦合和串扰，提高了通道间隔离度。The invention connects the inverted chip to the laminated circuit board through metal solder balls, improves pin density, reduces package size, reduces overall weight, reduces interconnection line transmission loss, and improves the performance of the radio frequency system. The metal solder balls, chips, and laminated circuit boards closely arranged at the channel or module boundary form a micro-compartment structure, which limits the electrical and magnetic interference signals generated by the channel circuit within the micro-compartment, thereby reducing the gap between the modules of the chip. The coupling and crosstalk improve the isolation between channels.
附图说明Description of the drawings
图1为本发明的一种带有微隔腔的半导体封装结构的剖面结构示意图。FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor package structure with micro-cavities according to the present invention.
图2为本发明的一种带有微隔腔的半导体封装结构的芯片仰视图。Fig. 2 is a bottom view of a chip of a semiconductor package structure with micro-cavities according to the present invention.
具体实施方式Detailed ways
下面根据附图和优选实施例详细描述本发明，本发明的目的和效果将变得更加明白，通过结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。Hereinafter, the present invention will be described in detail based on the drawings and preferred embodiments. The purpose and effects of the present invention will become more apparent. The present invention will be further described in detail by combining the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention.
如图1所示，本发明的一种带有微隔腔的半导体封装结构的剖面结构示意图，所述的倒片封装微隔腔结构包括导热基板、固定填充物、集成电路芯片、金属焊球、金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔。在导热基板下面形成大小略大于芯片的长方形凹槽，在其侧壁和顶面加入固定填充物用于芯片和基板的粘接，集成电路芯片采用倒片摆放的方式粘接在导热基板的腔体中。芯片焊盘方向向下连接金属焊球，金属焊球另一侧连接层压电路板的金属布线层M1，芯片下方层压了n-1层介质层，每层介质层上下两侧均连接有金属布线层，形成了总共n层金属布 线层。任意两层或多层金属布线层之间均通过过孔相连。As shown in FIG. 1, a cross-sectional structure diagram of a semiconductor package structure with micro-cavities according to the present invention. The flip-chip package micro-cavity structure includes a thermally conductive substrate, a fixed filler, an integrated circuit chip, and a metal solder ball. , Metal wiring layers M1, M2, ..., Mn, dielectric layers IMD1, IMD2, ..., IMD(n-1), and vias connecting different metal wiring layers. A rectangular groove slightly larger than the chip is formed under the thermally conductive substrate, and fixed fillers are added to the sidewall and top surface to bond the chip and the substrate. The integrated circuit chip is bonded to the thermally conductive substrate by flipping the chip. In the cavity. The die pad direction is connected to the metal solder ball downwards, and the other side of the metal solder ball is connected to the metal wiring layer M1 of the laminated circuit board. The n-1 dielectric layer is laminated under the chip, and the upper and lower sides of each dielectric layer are connected with The metal wiring layer forms a total of n metal wiring layers. Any two or more metal wiring layers are connected through vias.
优选地，层压电路板的介质层由两种不同材料的介质层组成，由介质一形成的介质层和由介质二形成的介质层相间排列。层压电路板的顶层和底层的材料为介质一，在由介质一形成的介质层内部或表面形成金属布线层；在由介质二形成的介质层内部不形成金属布线层。Preferably, the dielectric layer of the laminated circuit board is composed of two dielectric layers of different materials, and the dielectric layer formed by the first medium and the dielectric layer formed by the second medium are arranged alternately. The material of the top and bottom layers of the laminated circuit board is dielectric one, and a metal wiring layer is formed inside or on the surface of the dielectric layer formed by dielectric one; no metal wiring layer is formed inside the dielectric layer formed by dielectric two.
图2为本发明的一种带有微隔腔的半导体封装结构的芯片仰视图。多通道或多模块芯片的焊盘上连接金属焊球，并与层压电路顶层的金属布线层M1相连。在芯片上按照通道或模块的不同划分成不同的区域，形成通道或模块1、通道或模块2、……、通道或模块n等。在每个区域的周围边界上紧密排布金属焊球，由此芯片、金属焊球和层压电路板形成了可以有效降低通道间或模块间电磁耦合的微隔腔结构。Fig. 2 is a bottom view of a chip of a semiconductor package structure with micro-cavities according to the present invention. Metal solder balls are connected to the pads of the multi-channel or multi-module chip and connected to the metal wiring layer M1 on the top layer of the laminated circuit. The chip is divided into different areas according to different channels or modules, forming channel or module 1, channel or module 2,..., channel or module n, etc. Metal solder balls are tightly arranged on the peripheral boundary of each area, so that the chip, the metal solder balls and the laminated circuit board form a micro-cavity structure that can effectively reduce the electromagnetic coupling between channels or between modules.
优选地，所述的金属布线层材料为铜，所述的金属焊球材料为铜锡银合金。Preferably, the material of the metal wiring layer is copper, and the material of the metal solder ball is a copper-tin-silver alloy.
本领域普通技术人员可以理解，以上所述仅为发明的优选实例而已，并不用于限制发明，尽管参照前述实例对发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实例记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内，所做的修改、等同替换等均应包含在发明的保护范围之内。Those of ordinary skill in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, for those skilled in the art, they can still The technical solutions recorded in the foregoing examples are modified, or some of the technical features are equivalently replaced. All modifications and equivalent substitutions made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims (3)

  1. 一种带有微隔腔的半导体封装结构，其特征在于，所述的半导体封装结构包括多通道或多模块的半导体芯片、导热基板、固定填充物、金属焊球、层压电路板，所述的导热基板上形成略大于芯片的长方形凹槽，在其侧壁和顶面加入固定填充物用于半导体芯片和导热基板的粘接，所述的半导体芯片采用倒片摆放的方式粘接在所述的导热基板的腔体中，所述的半导体芯片焊盘方向向下连接所述的金属焊球，所述的金属焊球另一侧连接层压电路板，所述的层压电路板包括金属布线层M1、M2、……、Mn、介质层IMD1、IMD2、……、IMD(n-1)、连接不同金属布线层的过孔，相邻的金属布线层由介质层隔开，任意两层或多层金属布线层之间均通过过孔相连。A semiconductor packaging structure with micro-cavities, characterized in that the semiconductor packaging structure includes a multi-channel or multi-module semiconductor chip, a thermally conductive substrate, a fixed filler, a metal solder ball, and a laminated circuit board. A rectangular groove slightly larger than the chip is formed on the thermally conductive substrate, and fixed fillers are added to the sidewall and top surface of the thermally conductive substrate for the bonding of the semiconductor chip and the thermally conductive substrate. In the cavity of the thermally conductive substrate, the semiconductor chip pad direction is downwardly connected to the metal solder ball, and the other side of the metal solder ball is connected to the laminated circuit board, and the laminated circuit board Including metal wiring layers M1, M2,..., Mn, dielectric layers IMD1, IMD2,..., IMD(n-1), vias connecting different metal wiring layers, adjacent metal wiring layers are separated by dielectric layers, Any two or more metal wiring layers are connected through vias.
    所述的多通道或多模块芯片的焊盘连接金属焊球，并与层压电路顶层的金属布线层M1相连；在芯片上按照通道或模块的不同划分成不同的区域，形成通道或模块1、通道或模块2、……、通道或模块n等；在每个区域的周围边界上紧密排布金属焊球，由此芯片、金属焊球和层压电路板形成有效降低通道间或模块间电磁耦合的微隔腔结构。The pads of the multi-channel or multi-module chip are connected to metal solder balls and connected to the metal wiring layer M1 on the top layer of the laminated circuit; the chip is divided into different areas according to the channel or module to form a channel or module 1 , Channel or module 2,..., channel or module n, etc.; metal solder balls are arranged tightly on the peripheral boundary of each area, so that the chip, metal solder ball and laminated circuit board form an effective reduction of electromagnetic waves between channels or modules Coupled micro-cavity structure.
  2. 根据权利要求1所述的一种带有微隔腔的半导体封装结构，其特征在于，所述的介质层由两种不同材料的介质层组成，由介质一形成的介质层和由介质二形成的介质层相间排列，层压电路板的顶层和底层的材料为介质一，在由介质一形成的介质层内部或表面形成金属布线层，在由介质二形成的介质层内部不形成金属布线层。The semiconductor packaging structure with micro-cavities according to claim 1, wherein the dielectric layer is composed of two different materials of dielectric layers, a dielectric layer formed by dielectric one and a dielectric layer formed by dielectric two. The dielectric layers are arranged alternately. The material of the top and bottom layers of the laminated circuit board is dielectric one. A metal wiring layer is formed inside or on the dielectric layer formed by dielectric one, and no metal wiring layer is formed inside the dielectric layer formed by dielectric two. .
  3. 根据权利要求1所述的一种带有微隔腔的半导体封装结构，其特征在于，所述的金属布线层材料为铜，所述的金属焊球材料为铜锡银合金。The semiconductor package structure with micro-cavities according to claim 1, wherein the material of the metal wiring layer is copper, and the material of the metal solder balls is a copper-tin-silver alloy.
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