JP4504204B2 - High frequency chip package with connecting elements - Google Patents

Description

  The present application relates to a microelectronic element, for example, a technique for packaging a semiconductor chip.

  The semiconductor chip is usually provided as a package. The package facilitates handling of the chip during manufacture and during mounting of the chip on an external substrate, such as a circuit board or other circuit panel. For example, many semiconductor chips are provided as packages suitable for surface mounting. These packages typically have an external structure with terminals exposed on the bottom surface of the external structure. The terminals are exposed on the bottom surface of the chip carrier. In a surface mount operation, the package is placed on a circuit board such that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be permanently bonded in place by melting or “reflowing” the solder or otherwise heating the assembly to activate the bonding material. Many packages of this general type have been proposed for various applications. Most commonly, such packages include dielectric elements commonly referred to as “chip carriers”. A “chip carrier” has terminals formed as metal structures plated or etched on a dielectric element. These terminals are typically connected to the chip's own contacts by features such as thin traces extending along the chip carrier itself, and fine leads or wires extending between the chip contacts and the terminals or traces. Is done. These packages may further include an overmolding or encapsulant that covers the chip and covers the top of the chip carrier.

  Chips used to generate or process radio frequency (“RF”) signals are commonly referred to as “RF chips” and are used in wireless devices such as mobile phones and wireless data communication devices. As the adoption of wireless devices increases, the need for packages that are particularly suitable for use with RF chips has increased. RF chips typically generate a significant amount of heat during operation. Furthermore, the RF chip requires a low impedance connection to external circuitry and in some cases a connection that can handle significant current. In addition, the RF chip package desirably incorporates an electrical shield that prevents unwanted propagation of electromagnetic fields from occurring between the RF chip and the environment. For example, radio frequency power amplifier chips used in transmitters can produce significant spurious RF emissions. Other elements of the circuit must be protected from these emissions. Conversely, radio frequency amplifiers used in receivers should be isolated from RF emissions generated by other components.

  It is desirable to package the RF chip as a unit that includes other components separate from the RF chip itself, such as inductors, couplers, chokes, capacitors, and resistors. In order to facilitate miniaturization of the entire wireless device, the entire package must be made as small as possible. Furthermore, such a package must be manufacturable at low cost and high reliability. Considering all these factors has traditionally posed significant challenges.

  One aspect of the invention provides a microelectronic package that includes at least one lower chip, most preferably a radio frequency chip, and a connecting element extending over the lower chip. The package desirably further includes at least one upper chip disposed over the connecting element. The connecting element extends outward in the horizontal direction beyond the lower tip. Most preferably, the connecting element includes one or more dielectric layers and one or more trace layers extending along the dielectric layers. For example, the connecting element may be a single layer or multilayer rigid circuit board, or may be a flexible circuit panel commonly referred to as a “tape”.

  The package most preferably further includes an assembly of components. This assembly, referred to herein as the bottom planar element, includes a plurality of terminals and a thermal conductor. Preferably, the thermal conductor is an element having an area substantially larger than the area of each terminal. The thermal conductor is most desirably aligned at least partially with the at least one lower tip, the lower tip being on the thermal conductor and in heat transfer relationship with the thermal conductor. The terminals are most preferably substantially coplanar with the thermal conductor, and all of these components are at a lower vertical level than the lower chip. Terminals and thermal conductors are exposed on the bottom surface of the package, and when the package is attached, these elements can be coupled to corresponding elements on a circuit board or other external substrate.

  In a particularly preferred arrangement, the lower chip is an active semiconductor chip, most preferably an RF chip, such as an RF power amplifier chip, and the upper chip includes one or more integrated passive chips. Such integrated passive chips incorporate a number of passive components, such as resistors, capacitors, and inductors. In a preferred structure according to this aspect of the invention, the terminals are located adjacent to the periphery of the package, outside the area occupied by the lower semiconductor chip. Leads extend upward from these terminals to the connecting element. Thus, the connecting element carries signals horizontally in the plane above the lower chip, and the leads carry signals down to the terminals. In other words, the chip carrier handles the horizontal movement or “fan-out” of the signal traces from the lower chip contacts to the periphery of the connecting element. The upper tip may be any size. Typically, all of the passive components incorporated in an integrated passive chip may be provided as a relatively small size integrated passive chip. In a particularly preferred arrangement, the thermal conductors, terminals, and leads are manufactured as elements of a unitary lead frame. Thus, the lead can be a robust and thick structure that provides a low impedance connection between the terminal and the connecting element. Furthermore, the path design on the connecting elements is less complex and can provide room for relatively large and wide traces. As described further below, the upper chip can be mounted directly above the lower chip, so communication between the upper and lower chips is a very short line, for example a direct vertical connection between the alignment contacts of the upper and lower chips Can be processed. A preferred connection element has a cost per unit area that is substantially less expensive than the chip itself. Thus, providing the horizontal movement of the signal using connecting elements in addition to the chip itself substantially reduces the cost of the package.

  A package according to a further embodiment of the invention includes a connecting element incorporating a dielectric element and traces extending along the dielectric element, the connecting element having a top surface and a bottom surface. The package includes at least one lower chip attached to the bottom surface of the connecting element, the at least one lower chip having a surface remote from the connector, the surface defining a low reference plane at a level below the connector. A package according to this aspect of the invention includes a plurality of active terminals disposed below a low reference plane and further includes a plurality of active leads in the form of an elongated strip extending between the active terminals and the connecting element. Active leads are connected to at least some of the traces. Most desirably, at least some of the active leads are thicker than the traces on the connecting element. Such a structure can be manufactured by providing active leads as elements of the lead frame. The package according to this aspect of the invention further includes one or more upper chips attached to the top surface of the connection element, and preferably further includes an encapsulant surrounding the active lead and the at least one lower chip.

  Yet another aspect of the present invention provides a unitary metal lead frame incorporating a plate having a top surface and a bottom surface and having an edge. The lead frame according to this aspect of the invention further includes one or more temporary elements and a plurality of active terminals. The plurality of active terminals are horizontally spaced from the plate, for example, as rows along one or more edges of the plate. Most preferably, the active terminal is connected to the plate only via a temporary element. The lead frame desirably further includes a plurality of active leads. These active leads protrude upward from the active terminals and protrude above the top surface of the plate. Most preferably, these active leads further extend inward toward the plate. Desirably, the temporary element extends outwardly relative to the plate beyond the active terminal. For example, if the active terminals are arranged as rows extending along the edge of the plate, the temporary element may include strips extending beside the row of active terminals, each row of active terminals being one such strip. Between the plate and the plate. As described below, these structures facilitate disconnecting the active terminals and active leads from the plate after assembly of other components. The lead frame according to this aspect of the invention can be used in the manufacture of packages as described above.

  A further aspect of the invention provides a method of making a microelectronic package. The method according to this aspect of the invention desirably includes assembling a subassembly incorporating a connecting element having a top surface and a bottom surface, wherein the one or more lower tips are a thermal conductor, and a thermal conductor. Attached to a bottom surface having a bottom planar assembly that includes a substantially coplanar active terminal. The assembly step is preferably such that the lower chip is between the connecting element and the thermal conductor, so that the connecting element is disposed on the thermal conductor and also on one or more lower chips. Executed. The method further includes electrically connecting the connection element to the active terminal. Most preferably, the bottom planar assembly includes active leads projecting upward from the active terminals so that the connecting elements are juxtaposed with the active leads in the assembly step. In other words, the bottom planar assembly desirably includes a structure such as the lead frame described above having active leads protruding upward from the plane of the thermal conductor, and the assembly step lowers the lower chip between the active leads. Is performed in close proximity to the heat conductor. The subassembly used in this process may further include one or more upper tips attached to the top surface.

  According to one aspect of the invention, a packaged chip is provided that includes a bottom package element and a top package element. Each of the package elements has an upper surface facing upward and a bottom surface facing downward. Each package element further includes one or more dielectric layers and a plurality of conductive elements.

  The top package element exists above the bottom package element and defines an internal space between the top package element and the bottom package element. The conductive element of the bottom package element includes a bottom terminal exposed on the bottom surface of the bottom package element. The conductive element of the upper package element includes an upper terminal exposed on the upper surface of the upper package element.

  One or more chips are disposed in the interior space and connected to at least some terminals of at least one package element. The conductive element of the upper package element substantially blocks radio frequency energy from radiating between one or more chips and the space above the upper package element.

  According to a preferred embodiment of the present invention, at least some terminals of the top and bottom package elements are electrically connected to each other. Desirably, at least one chip is configured to process a radio frequency analog signal and may be, for example, a radio frequency power amplifier.

  In accordance with certain preferred aspects of the present invention, a first chip and a second chip are included in a packaged chip, each chip having a front surface with contacts, a back surface, and between the front and back surfaces. The first and second chips are stacked in an opposing arrangement, with the back surface of the second chip facing one of the package elements.

  According to a preferred arrangement, the surface of the second chip is larger than the surface of the first chip, and the second chip extends beyond the first chip in at least one horizontal direction.

  According to another aspect of the invention, a packaged chip is provided that includes at least one chip having at least one edge, a bottom package element, and a top package element. Each of the package elements has an upper surface facing upward and a bottom surface facing downward. The top package element resides above the chip and the bottom package element, and the package element defines an internal space between which the chip is placed.

  According to such an aspect of the present invention, the conductive element of the bottom package element includes a bottom terminal exposed on the bottom surface of the bottom package element. The conductive element of the upper package element includes an upper terminal exposed on the upper surface of the upper package element.

  The chip is connected to at least some terminals of at least one package element. Leads extend from one or both of the package elements into the interior space. According to such an aspect of the invention, at least some conductive elements of the top and bottom package elements are connected to each other via leads.

  In a preferred arrangement according to this aspect of the invention, the conductive elements on the at least one package element include traces and at least some of the leads are integrally formed with the traces. Alternatively or additionally, at least some of the leads include wire bonds. In one embodiment, the leads include a bottom lead that extends between the chip and the bottom package element, and a top lead that extends between the chip and the top package element. Desirably, the leads further include interconnect leads that directly connect at least some of the conductive elements of one package element to at least some of the conductive elements of the other package element.

  In accordance with a preferred aspect of the present invention, the packaged chip further includes interconnect pillars. The interconnect post extends between the top package element and the bottom package element to interconnect at least some of the conductive elements on the package element.

  According to another aspect, the packaged chip further includes a ball interconnect structure. The ball interconnect structure extends between the top package element and the bottom package element to interconnect at least some of the conductive elements on the package element.

  Desirably, according to certain preferred embodiments, the one or more chips are disposed on the upper package element and connected to at least some terminals of the upper package element, wherein the conductive element of the upper package element comprises: Radio frequency energy is substantially prevented from radiating between one or more chips disposed in the interior space and one or more chips disposed on the upper package element.

  According to a preferred embodiment of the present invention, a cap panel is provided. The cap panel is over the upper package element and defines an upper space between the cap panel and the upper package element. The cap panel includes a conductive element that defines at least a portion of the antenna. Desirably, the conductive element of the cap panel defines a shield disposed between the antenna and the headspace.

  According to another preferred aspect of the invention, the top and bottom package elements and the cap panel comprise an integral part of the unitary sheet having at least two folded parts.

  According to another aspect of the invention, an electronic assembly is provided that includes a first chip that includes a radio frequency power amplifier (RFPA) and at least one other chip disposed in a vertically stacked relationship to the first chip. Is done. The package is used to hold a chip. The package substantially has bottom terminals configured to be attached to the circuit panel, chip-to-chip interconnections, and radio frequency energy radiated and propagated between the first chip of the assembly and at least one other chip. Including a shield configured to interfere with the operation. The shield is desirably provided between the first chip and the external space of the assembly. The package desirably includes at least a portion of the antenna. The shield is desirably configured to shield at least one other chip from RF energy emitted from the first chip.

  According to certain preferred aspects, the electronic assembly forms part of a portable electronic communication device, a handset, and a cellular mobile communication device including the handset.

  According to yet another aspect of the invention, an electronic assembly is provided that includes a first chip having a radio frequency power amplifier (RFPA) configured to generate at least 10 milliwatts of RF power. A second tip including a surface acoustic wave tip is also provided in the assembly. The first and second chips are held by a package that includes a bottom terminal configured to attach to the circuit panel and a shield between the first chip and the second chip. The shield is preferably configured to shield the second chip from RF energy emitted from the first chip.

Desirably, the package occupies a volume of less than about 0.5 cm ³ .

  In accordance with yet another preferred aspect of the present invention, a packaged chip is provided that includes at least one lower chip. An upper package element is provided that extends above the lower chip and extends horizontally beyond the lower chip. At least one lower chip is attached to the upper package element. A plurality of leads extend downward from the upper package element. In such an arrangement, the upper package element and leads substantially impede radio frequency energy from radiating between the lower chip and the space above the upper package element.

  A further preferred variation of this embodiment includes an enclosure that extends around the edge of the lower chip. The lead substantially blocks radio frequency energy from radiating between the lower chip and the outer space of the enclosure. According to a preferred aspect of the present invention, the leads are selected from the group consisting of, for example, preformed solder features, posts, wire bonds, and leads integrally formed with the chip carrier.

  In particularly preferred embodiments, the at least one lower chip includes a functional element selected from the group consisting of, for example, a radio frequency (RF) transmitter, an RF power amplifier, an RF energy switch, and a filter. The filter may be a surface acoustic wave type filter, for example.

  According to yet another particularly preferred aspect of the invention, one or more upper chips are arranged on the package element. The one or more upper chips include one or more functional elements selected from the group consisting of, for example, an RF receiver, a low noise amplifier, an RF mixer, an IF mixer, a sampler, an oscillator, and a signal processor.

  These and other objects, features and advantages of the present invention will become readily apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings.

  The lead frame 20 (FIG. 1) according to one embodiment of the present invention is formed as a unitary structure from a metal such as copper, for example, about 50 to 500 microns thick. The lead frame according to this embodiment includes a central thermal conductor or plate 22. Plate 22 is generally rectangular and has a pair of opposing edges 24, referred to herein as the active edges of the plate, and a further pair of opposing edges 26, referred to as ground edges. The plate has a top surface 28 and a bottom surface 30. The lead frame further includes a pair of small rectangular plates called ground buses 32. The ground bus 32 extends parallel to the ground edge 26 of the center plate. One or both of the ground buses 32 can be used as a ground connection in the completed assembly or can be used as a power bus that supplies power. From now on, the term ground bus refers to the structure in which it is used in any way. The ground bus is connected to the central plate 22 by a set of ground posts 34 that project outward from the central plate 22. A temporary element or rail 36 extends along each active edge 24. Each temporary element is connected to the ground bus 32 by an additional temporary element or rail 38. The central plate 22, ground bus 32, struts 34, and temporary elements 36 and 38 are all in a common plane.

  As used in this disclosure with reference to such a leadframe or generally other planar structure, the term “horizontal” refers to the planar direction of the structure, ie along the drawing sheet of FIG. Used to mean direction and direction to the left and right in FIG. The terms “vertical” and the corresponding “upper” and “lower” mean directions across this plane. Further, the term “horizontal outward” refers to the direction away from the central plate 22 and the term “inward” refers to the horizontal direction toward the center of the plate.

  A set of ground leads 40 protrudes upward from each ground bus 32. The ground lead associated with each ground bus further protrudes inward in the horizontal direction from the ground bus to the plate 22. As best seen in FIG. 1, the ground leads 40 associated with each ground bus 32 alternate with ground posts 34 connecting the ground bus to the central plate 22. As best seen in FIG. 2, each ground lead 40 defines an upper land 41 at its inner end.

  Along each active edge 24 of the central plate 22 is a row of active leads 42. The active lead of each row is integrated with a temporary element 36 that extends along the active edge adjacent to such row. Each active lead protrudes inward from the temporary element and further protrudes upward onto a plane above the temporary element. As best seen in FIG. 3, each active lead defines an upper land 43 at the inner end of the lead above the plane of the plate 22 and far from the plate and adjacent to the temporary element 36, the outer end of the lead. To define the lower land 45 or active terminal. The upper land 43 of the active lead is preferably coplanar with the upper land 41 of the ground lead, and the lower land 45 is preferably coplanar with the bottom surface 30 of the plate 22.

  The lead frame 20 is desirably provided in the form of a continuous or semi-continuous tape, strip, or sheet incorporating a number of lead frames as previously described. For example, in FIG. 1, the above-described lead frame 20 is shown connected to a portion of the adjacent lead frame 20a. The lead frames are interconnected along temporary element 36 and along the outer end of ground bus 34 and adjacent temporary element 38.

  The subassembly 50 (FIGS. 4-6) incorporates a connection element 52 in the form of a circuit panel. The circuit panel has a dielectric layer 54 that defines a top surface 56 and a bottom surface 58. The circuit panel is generally rectangular and defines an edge 53, referred to herein as a ground edge, and an edge 55, referred to herein as an active edge. The dielectric element 54 has a conductive element or trace 60 on the top surface 56 and a conductive element or trace 62 on the bottom surface 58 (FIG. 5). The conductive features on the connecting element are typically formed from a metal layer as thin as 5-50 μm, as is commonly used in flexible circuits. These features can be formed by known etching or plating processes used in the manufacture of flexible circuits or circuit boards. The circuit panel defines a mounting pad 64 on its top surface and a mounting pad 65 on its bottom surface. As can be further seen in FIG. 5, the circuit panel includes a conductive through via 66 extending between its top and bottom surfaces. Some of the vias 65 interconnect the top pad 64 directly to the corresponding pad 66 on the bottom surface. Another via, such as via 65 (FIG. 6) interconnects top trace 60a to bottom trace 62a. Subassembly 50 is desirably provided in the form of a continuous strip or tape (not shown) that incorporates multiple connecting elements formed on the same dielectric layer. The features of these connecting elements are provided at a repeat distance equal to the repeat distance between adjacent lead frames in the lead frame strip or tape described above.

  The circuit panel can have a commonly used type of dielectric layer. For example, the circuit panel can include a dielectric layer 54 of FR-4 or FR-5 epoxy reinforced fiberglass board, BT resin and / or polyimide. BT resin and / or polyimide can be used in reinforced or non-reinforced circuit panels. Alternatively, the circuit panel can be formed as a tape having a flexible dielectric layer.

  The connecting element 52 is provided with a relatively large set of pads or lands 70. These pads or lands 70 are on the bottom surface 58 of the periphery of the connecting element and are adjacent to the edges 53 and 55. Traces and other metal features interconnect these lands with some or all of the pads 64 and 66 described above. The conductive features on the bottom surface 58 include a large, generally rectangular ground plane 62b. The ground plane 62b extends between the ground edges 53, and several lands 70 are incorporated in the ground edges. The ground plane 62b may have openings 63 (FIGS. 5 and 6) that provide electrical isolation from several pads 66 at the bottom. The bottom conductive feature or trace further includes a pair of large RF pads 62c (FIG. 6) and a wide RF trace 62d. RF trace 62 d is connected to these pads and extends to land 70 adjacent to active edge 55. Only a few traces 60 on the top surface are shown. These traces may be provided as needed to interconnect the pads and vias required for circuit path design.

  The subassembly further includes a pair of lower tips 72. Each lower chip has a front surface 74 and contacts 76 are exposed on such front surface. Each lower chip further has a back surface 78 and an edge 80 extending between the front surface and the back surface. The lower chip is attached to the bottom surface 58 of the connecting element and connected to the bottom surface pad 66 by a solder ball 82 or other conductive bonding material. As one example, a fluxless solder process can be used to couple the chip to the connecting element. Such a fluxless process can be performed, for example, under a nitrogen atmosphere or other inert atmosphere or under vacuum. In other examples, stud bumps or balls having gold on the surface or formed of gold can be diffusion bonded to corresponding lands 66 or other features of the connecting element 52 having a tin contact surface. Desirably, gold stud bumps are formed on the chip by wire bonders when the chip is still in wafer form before being diced. Such a process allows gold stud bumps to be applied at the desired high rate and the pitch and height of the bumps to be well controlled. An inverse variant in which gold stud bumps are provided on the lands and compatible bonding surfaces are provided on the chip may also be used.

  The lower tip 72 is mounted side by side adjacent to the center of the connecting element and is thus separated from the edges 53 and 55. In other words, the connecting element extends outward in the horizontal direction beyond the lower tip, so that the land 70 protrudes outward beyond the lower tip. The subassembly further includes an upper tip 84. Upper chip 84 has a front surface 86 with contacts 88, a back or upward surface 90, and an edge 92 extending between the front and back surfaces. The upper chip is attached to the upper surface 56 of the connection element in substantially the same manner as the lower chip, so that the upper chip contacts 88 are connected to pads 64 on the upper surface of the connection element, for example by solder balls or other conductive bonding material 94. Combined with The chip may be assembled to the connecting element by conventional bonding techniques, such as those commonly used in flip chip bonding. When the chips are mounted in this way, the chips are connected to each other and to the lands 70 of the connection elements. Since the upper chip 84 is mounted on the lower chip 72, some or all of the upper and lower chip contacts can be aligned with each other. Some or all of the interconnections between the upper and lower chips can be short straight through connections, each such straight through connection having a lower chip contact 82 and an upper chip contact 88 aligned therewith. Defined by a single conductive via 65 extending between the two.

  In this embodiment, lower chip 72 is an active radio frequency chip, such as a radio frequency power amplifier chip, and upper chip 84 is an integrated passive chip that has passive components, such as resistors and capacitors, but no active components. . In the illustrated state, the subassembly can be tested for proper functioning, for example, by engaging the lands 70 with the contacts of the test fixture. In addition, additional contact points or test lands (not shown) can be provided on the connecting element 52. Furthermore, the connection element itself may include passive components such as resistors, capacitors, and in particular inductors. As described in certain embodiments of the aforementioned international application PCT / US02 / 27509, inductors can be formed by circuit panel traces and other conductive elements, and for example, circuit panel traces and chips. Can be formed by interconnecting elements by interconnecting conductive elements in one of the two. For example, the inductor may be defined by the conductive element of the panel or connection element 52 combined with the conductive element of the upper or passive chip 84.

  In the assembly method according to the embodiment of the present invention, the subassembly 50 is assembled to the lead frame 20 described above. As best seen in FIGS. 4 and 6, the subassembly 50 is aligned over the lead frame and the land 70 adjacent to the ground edge 53 of the connecting element is above the upper land 41 of the ground lead and is the active edge. Land 70 adjacent to 55 is above the upper land 43 of the active lead. By moving the sub-assembly downward or moving the lead frame upward, the sub-assembly is advanced downward relative to the lead frame to engage the lands of the connecting element with the upper lands of the lead frame. Prior to engaging the lands together, a solder ball or other conductive bonding material 96 is provided on the lands 70 of the connecting elements or on the lands of the lead frame. For example, the solder ball 96 may be applied in the same process used to apply the solder ball to attach the lower chip 72. Alternatively, the lead frame may be “tin-plated” or a thin coating of solder or other bonding material may be provided on the upper lands 41 and 43 prior to assembling the lead frame and subassembly. A set of diffusion bonding materials may be used, for example, a tin layer on the lands 70 of the connecting elements and a gold layer on the lands 41 and 43 of the lead frame, or vice versa. The connecting element lands 70 are coupled to the lead frame lands, thereby electrically connecting the conductive elements of the connecting element to the active and ground leads of the lead frame. The lower chip back surface 78 may be in direct contact with the center plate or thermal conductor 22 of the lead frame. Alternatively, a relatively thin and thermally conductive die attach layer may be provided between the back surface of the lower chip and the center plate. The die attach may be a metal die attach, for example, solder may be used. Alternatively, an intermetallic bond may be used. For example, the leadframe thermal conductor 22 may be formed of copper and provided with a thin layer of tin, solder, or other metal bonding material that provides a cooperating bonding surface to the metallized surface of the lower chip 72. The back surface of the lower chip 72 is preferably metallized with a gold coating, and when the lower chip 72 is connected to the tin plated surface of the thermal conductor 22, a tin-gold or solder-gold contact is formed. The reverse arrangement can also be used: the back side of the lower chip is metallized with a tin coating and the thermal conductor is coated with gold, for example plated. Desirably, this process is performed while the lead frame is still in the form of a continuous strip or tape with other adjacent lead frames, and the connector 50 is also in the form of a continuous strip or tape, thus In operation, a plurality of subassemblies are coupled together with a plurality of lead frames or bottom planar elements.

  After the subassembly is coupled to the lead frame, the resulting assembly is sealed by overmolding with a protective resin, such as epoxy, polyimide, or other dielectric composite. This process may be performed in a normal mold. Desirably, the bottom surface of the lead frame is protected during this process by a membrane or other temporary cover (not shown) or by one of the surfaces of a mold (not shown), in the molding process. In order to prevent the resin from adhering to these bottom surfaces.

  In a variation of the above embodiment shown in FIG. 9A, some or all of the ground leads 40a are attached to the heat conductor 22 and extend horizontally outward therefrom and coupled to the corresponding leads of the connecting element 52. A lead 41a is defined. In such cases, one or more ground buses 32 of leadframe 20 can be removed when connected to a thermal conductor, and a conductive interconnect to ground is further provided via the thermal conductor.

  After sealing, the sealing assemblies formed on the various lead frames in the strip or tape are separated or “single” from each other. During the singulation process, the temporary elements 36 and 38 and the outer margin of the ground bus 32 are cut from the remainder of the lead frame. Since these temporary elements and outer margins are present at the outboard edge of the assembly, they can be removed without damaging other components during the singulation process. In addition, when these elements are removed, the other elements of the assembly are supported and retained by the sealant. The resulting assembly (FIGS. 7-9) has a connecting element 52 and chips 84 and 72 embedded in a sealant assembly 100. The assembly has a bottom surface 120 near the plane of the thermal conductor, a ground edge surface 122 projecting upward from the bottom surface adjacent to the ground bus 32, and an active edge surface 124 projecting upward from the bottom surface in the row of active terminals 45. In this state, each active lead 42 and active terminal 45 are electrically isolated from other active leads and active terminals, but are maintained in place by the encapsulant assembly 100. The upper portions of the ground lead 40 and the active lead 42 (FIG. 9) are also embedded in the encapsulant, and these leads are fixed in place with respect to the connecting element 52. However, the lower land 45 defined by the ground bus 32 and the active lead remains exposed at the bottom surface 120 of the assembly. Similarly, the bottom surface of the central plate or thermal conductor 22 remains exposed at the bottom surface of the assembly. The thermal conductor, ground bus, and terminal are present below the lower reference surface 91 defined by the back surface of the lower chip 72. Depending on the actual conditions used for the molding, these surfaces may be recessed with respect to the surrounding bottom surface of the encapsulant assembly, or protrude slightly below the surrounding encapsulant, in FIGS. As can be seen, it may be the same height as the bottom of the encapsulant. However, the surface of the ground bus, the center plate, and the lower land of the active leads remain accessible, so that they are applied to the bottom of the package, ie, the surface facing downward in FIGS. Can be touched by. As best seen in FIGS. 7 and 9, the lower land or active terminal 45 is located adjacent to the edge 124 of the encapsulant assembly 100 and thus adjacent to the edge of the package. The ground bus 32 is also disposed adjacent to the other edge 122 of the sealing material assembly 100.

  The resulting package can be surface mounted to the circuit board 102 or other circuit panel. Desirably, the circuit board includes a ground bus 104, a lower land or active terminal 45, and ground contacts 104 arranged in a pattern corresponding to the pattern of the central plate 22, active contact pads 106 (FIG. 9), and large thermal contact pads. (108) (FIG. 8). The package can be coupled to the circuit board by solder bonding. Desirably, a layer of solder 110 or other bonding material is provided between the central plate or thermal conductor 22 and the thermal pad 108, and a small collection of bonding material 112 is formed between the ground contact pad 104 and the ground bus 32. Between. Another assembly of bonding material 114 is provided between other contact pads 106 and active terminals 45. Here again, the bonding material may be provided as a pre-tin plating or coating on the lead frame. The circuit board has appropriate signal connections to each of the contact pads 106 associated with the active terminals 45. Thus, the active terminal 45 serves as an active signal contact for the packaged assembly. The ground bus 32 and the center plate 22 serve as ground contacts. In addition, the bonded plate 22 serves as a thermal conductor that conducts heat from the lower chip 72 and other elements of the package to the circuit board. The plate or thermal conductor 22 has a large surface area and high thermal conductivity. The large collection 110 of bonding material provides a similar low resistance thermal path from the plate to the thermal pad 108 on the circuit board. Active leads 42 and ground leads 40 provide a robust connection between the conductive elements of connection element 52 and the circuit board. The central plate or thermal conductor 22 provides an electromagnetic shield under the lower chip 72. In addition, the large ground plane 62B (FIG. 6) and other metal components on the connecting element 52 provide additional shielding on top of the lower chip.

  The assembly of FIG. 10 is substantially the same as the assembly previously described with respect to FIGS. However, the assembly of FIG. 10 includes two lower tips 172 and two upper tips 184. The lower or active chip 172 includes radio frequency chips, such as high performance chips manufactured with gallium arsenide technology, and complementary metal oxide semiconductor (CMOS) chips, such as power control chips. Upper chip 184 desirably includes an integrated passive device. One upper chip 184 is associated with each of the lower chips 172. The associated chip contacts are aligned with each other to provide a straight through connection between the upper and lower chips similar to the connections previously described with reference to FIGS. The connecting element 152 may comprise a multilayer laminated substrate (MLC) comprising several metal layers, for example four metal layers. Upper chip 184 and lower chip 172 are flip chips attached to connecting element 152 in the same manner as described above.

  The assembly of connecting element 152 and chips 172 and 184 is achieved by coupling leads 140 to pads 170 and abutting the back surface of the lower chip against the thermal conductor 123 of the lead frame or coupling the back surface of the lower chip to the thermal conductor. It is attached to the lead frame in the same manner as described above.

  Sealing and singulation of the coupled assemblies is desirably performed in much the same manner as previously described with respect to FIGS. However, in this embodiment, the edge surface 121 exists inside the ground bus 32, that is, the ground bus 32 forming the terminal of the ground lead 140 extends beyond the adjacent edge surface of the encapsulant assembly. The sealing material 100 is applied so as to protrude outward. A ground lead 140 connected to the ground bus protrudes outwardly above the encapsulant and extends into the encapsulant above the bottom plane of the assembly. Active leads (not shown) have a similar configuration, and the terminals associated with these leads also protrude outward beyond the edge of the encapsulant assembly. When the assembly is attached to the circuit panel, a solder fillet 177 may be formed on the top surface of the terminals, that is, the top surface of the ground bus 32 and the top surface of the terminals associated with the active leads. The solder fillet may be integrated with the solder connecting the terminals to the circuit panel. The solder fillet provides improved heat dissipation from the package, including improved heat conduction to the circuit panel.

  In the embodiment of FIG. 11, the bottom planar element of the package is defined by a chip carrier rather than a lead frame. The chip carrier 200 includes a bottom planar dielectric layer 202 having a central thermal conductor 204 and terminals 206. The terminals and thermal conductors in this embodiment are exposed to the bottom surface 208 of the dielectric layer by holes 210 extending through the dielectric layer. The dielectric layer further has a bond window 212 extending therethrough. A lead 214 associated with the terminal 206 may be integrally formed with the terminal. Lead 214 may extend across the bond window in the plane of terminal 206 and thermal conductor 210. In this state, the inner end 216 of the lead may be temporarily connected to the thermal conductor 204 by, for example, a brittle element (not shown) prior to assembly. A subassembly 250 similar to subassembly 50 may be assembled with such a carrier, and leads 214 may be bent upward and coupled to lands 270 around connecting element 252. For example, a bonding tool is advanced through the bond window to bend and bond the leads. The lead bonding operation is substantially the same as the operation disclosed in US Pat. No. 5,915,752, for example. The disclosure of this US patent is hereby incorporated herein by reference. The resulting assembly is sealed to form a sealant assembly 218 that covers the bottom planar element terminals 206 and the top surface of the dielectric element 202. The sealing process is performed to leave the terminal 206 and the thermal conductor 204 exposed, for example, by covering the bond window 212 before introducing the sealant over the top surface of the dielectric element 206. In this embodiment as well, conductive elements (not shown) on the connecting element 252 serve as a connection between the chip and the land 270 of the connecting element. Here again, the connecting element 252 extends horizontally outwards beyond the lower tip 272.

  A package according to yet another embodiment (FIG. 12) uses a bottom planar element 300. The bottom planar element 300 incorporates a dielectric layer 302, terminals 306, and thermal conductors 308 similar to the corresponding elements previously described with reference to FIG. However, in this embodiment, the lead 314 that connects the conductive feature of the connecting element 352 to the terminal 306 is provided as a strip formed integrally with the conductive element of the connecting element 352. The lead 314 may protrude outward from the edge of the connecting element 352. Alternatively, the lead 314 may initially extend across the bond window 312 in the dielectric layer of the connection element and is displaced downward from the plane of the connection element by a bonding tool using a process similar to that described above. May be. Other methods of providing a lead extending upward and downward between the connecting element and the terminal may be used. For example, wire bonds or other leads formed separately from the connecting element and separately from the bottom planar element may be used. As shown in FIG. 12, the encapsulant assembly 318 and other components may be covered by a conductive electrical shield or container 320. In a further variation, a heat sink may be provided only on the top surface of the encapsulant assembly. A heat sink, shield, or container 320 may be placed directly on the back surface of the upper chip 84 or connected thereto by a layer of thermally conductive grease or other flowable material 322. In a further variation, when the assembly is attached to the panel, the bottom edge of the container 320 may be soldered to the circuit panel to provide a ground connection and improve heat conduction to the panel. Such a container may be provided with a solder fillet similar to the fillet previously described with reference to FIG. The solder fillet extends upward along the side of the container.

  Any number of lower tips and any number of upper tips may be used. In addition, chips other than active RF chips and integrated passive chips may be used. For example, a chip such as a logic chip or a memory chip may be provided in addition to or instead of the integrated passive chip. Further, the package may include discrete electrical components attached to the connecting element or the bottom planar element. In the embodiment described above, the chip is mounted with the front or contact holding surface facing the connecting element. However, one or more chips may not have their front side facing the connection element, and the contacts of such chips are electrically connected to the connection element by leads, for example wire bonds.

  The connecting element may include any number of dielectric layers and any number of conductive feature layers. For example, the connecting element may be a multilayer structure having layers on the inner conductive layer and its upper and lower surfaces. Merely by way of example, the internal conductive layer may include a trace layer or one or more ground planes, or other conductive planes. Alternatively, as can be seen in FIG. 13, the connection element 450 may incorporate a single dielectric layer and a single conductive feature layer on its top surface. A single layer defines pads 464 and traces 460 on the top surface. Some or all of the conductive features may be exposed through holes 465 in the dielectric layer to define additional pads 466 exposed on the bottom surface 458 of the dielectric layer. Similarly, lands 470 adjacent to the edge of the dielectric layer may be exposed through holes 471 in the dielectric layer to connect to the bottom planar assembly as described above. Similar structures may have conductive elements located only on the bottom surface and may similarly define the pads exposed on both surfaces.

  A lead frame according to a further embodiment of the present invention (FIG. 14) includes a plurality of terminal leads 542. Each terminal lead 542 has a lower land or terminal 545 and an upper land 543 similar to the corresponding features of the active lead 42 previously described with reference to FIG. The lead frame in FIG. 14 further includes an inductor 501. Each inductor includes a series of strips 503 that cooperatively define a turn or partial turn about an axis perpendicular to the plane of the drawing of FIG. A pair of inductor leads 505 is provided for each inductor. Each inductor lead has a lower end 507 connected to one of the strips and an upper end 509 forming an upper land. The upper land of the inductor lead is coplanar with the upper end of the terminal lead. In the process-in-progress state of FIG. 14, the lead frame elements are physically connected to each other by temporary elements 536. A lead frame according to this embodiment can be assembled to a connecting element or subassembly (not shown) in a manner similar to that previously described with reference to FIGS. The connecting element has a land corresponding to the terminal lead and an additional land corresponding to the inductor lead. Thus, assembling the connection element to the lead frame serves to connect the inductor in the circuit to the trace on the connection element. Here again, after assembly, the temporary elements 536 are removed, leaving terminals isolated from each other and from the inductor. The use of an inductor formed integrally with the lead frame provides an inductor formed from the relatively thick metal of the lead frame, so the inductor has a very low internal resistance and correspondingly high Q value. The spiral inductor shown in FIG. 14 is merely an example, and the leadframe conductive elements can be used as inductor components to make other types of inductors, such as those described in the aforementioned international application. Furthermore, the inductor leads can be connected to one or more chips rather than to a connection element or circuit panel.

  In the embodiment of FIG. 14, the terminals and leads used as ground connections to the circuit board are interposed between the other terminals and leads. In other words, it is not essential to provide ground features that are concentrated on a particular edge of the structure. Further, the embodiment of FIG. 14 omits the thermal conductor or center plate used in the embodiment of FIG. The thermal conductor may be further omitted in other embodiments, such as the embodiment of FIGS. If the thermal conductor is omitted, the bottom surface of the lower chip may optionally be exposed at the bottom surface of the package, so that when the package is mounted on the circuit panel, the bottom surface of the lower chip can be coupled to the elements of the circuit panel. . In other words, the bottom surface of the lower chip may be coplanar with the terminals that serve to connect the package to the circuit panel. In such an arrangement, the bottom surface of the lower chip may be metallized by tin plating or other methods to facilitate bonding during surface mounting operations or other operations used to attach the package to the panel.

  In the embodiment shown in FIGS. 15 and 16, the connecting element 652 is a chip carrier. The chip carrier is exposed to the dielectric layer 658, the upper patterned metal layer defining the land 654 exposed above the chip carrier, and the land 656 exposed below, and also below the connecting element or chip carrier. A lower patterned metal layer defining an interconnect terminal 670. The lower patterned metal layer further defines a ground bus 691 (FIG. 16), which is exposed on the bottom surface of the connecting element 652. One or both of the metal layers further define a trace 653. Trace 653 connects interconnect terminal 672 to a land and via, which interconnects some or all of land 656 with land 654. Here again, the connecting element may comprise two or more dielectric layers and may comprise three or more metal layers. Alternatively, as previously described with reference to FIG. 13, the connecting element may include only one metal layer defining lands exposed on both sides of the chip carrier.

  The bottom planar element 660 is provided as a lower chip carrier that is substantially the same as the bottom planar element 200 previously described with reference to FIG. Accordingly, the bottom planar element 660 includes a dielectric layer 662 and a patterned metal layer 664 overlying the dielectric layer. This patterned metal layer defines active terminals 672, interconnect terminals 671, traces 692 connecting the active terminals to the interconnect terminals, and additional component attachment terminals 676. Additional component mounting terminals are connected to some of the interconnect terminals 671 by additional traces (not shown). The active terminal 672 is exposed to the bottom surface of the bottom planar element through a hole in the dielectric layer 662. Some or all of the additional component mounting terminals 676 may be exposed to the bottom surface through holes in the dielectric layer. The same patterned metal layer may further define a thermal conductor 620. The thermal conductor 620 is further exposed to the bottom surface of the chip carrier through a large opening in the dielectric layer. As best seen in FIG. 16, the metal layer may be in the form of a continuous metal layer. This continuous metal layer defines the thermal conductor 620 and extends over substantially all of the top surface of the dielectric layer except for the area occupied by the terminals and traces. A continuous metal layer surrounds the terminals and traces but is electrically isolated from these features by small gaps in the metal layer. The continuous metal layer provides an effective RF shield.

  One or more lower chips 611, eg, active radio frequency chips, are disposed below the connecting element 652 and are conductively attached to the lands 656 below the connecting element 652, as described above. One or more upper chips 613, eg, a passive chip that includes one or more integrated passive components, is conductively attached to lands 654 of the upper patterned metal layer 654.

  As best seen in FIG. 15, a large solder ball 622 extends between the interconnect terminals 671 and 672, thereby providing an active terminal 672 and an additional component mounting terminal 676 on the bottom planar element or lower chip carrier 660. Connect to connection element 652 and chips 611 and 613. Some or all of the active terminals 672 may be directly connected to the interconnect terminals 670 on the connecting elements by solder balls 622a. In other words, some or all of the active terminals also serve as interconnect terminals. Some of the large solder balls 622b (FIG. 16) also connect the continuous metal layer and thermal conductor 620 to the ground bus 691 of the connecting element or upper chip carrier 652. Large solder balls 622 are placed outside the area where the lower chip 613 is attached to the upper chip carrier 652, but are preferably placed on the sides of the peripheral edges of the lower chip 613. One or more discrete devices 686, such as passive electronic components, such as capacitors, resistors, and inductors, are coupled to additional element mounting terminals 676 of the lower chip carrier 660, interconnect terminals 670 and 671 and large solder balls. Connected to one or both of chips 611 and 613 via some of 622. In this embodiment, the discrete device 686 is located outside the area covered by the connecting element or upper chip carrier 652 and protrudes up to or beyond the level of the connecting element 652. This arrangement allows the package to accommodate relatively thick discrete devices while keeping the overall package height relatively small.

  Using solder balls that form a connection between the bottom planar element or lower chip carrier and the connecting element or upper chip carrier eliminates the need for bond windows in the connecting element or in the bottom planar element. Thereby, the cost of these elements is reduced. Furthermore, such a connection is desirable. This is because the need to selectively metallize connection elements is eliminated.

  The package of FIGS. 15 and 16 is assembled by first coupling the chips 611 and 613 to the connecting element 652 and then using the solder balls 622 to couple the connecting element 652 to the lower chip carrier 660. Can do. The back surface of the lower chip 611 is desirably coupled to the thermal conductor 620 of the lower chip carrier 660 at the same time when the connecting element 652 is coupled to the lower chip carrier 660. Thereafter, the resulting assembly may be sealed to form a sealant assembly 618 that covers the surface of the connection element 652 and extends between the lower chip carrier 660 and the connection element 652. Discrete component 686 can be coupled to terminal 676 at any time prior to sealing. An alternative assembly process aligns the upper and lower chips, the connecting element 652, and the lower chip carrier or bottom planar element 660, and then reflows the aligned elements to bond the elements between the assemblies in one step. Forming a connection.

  In use, the active terminals 672, the thermal conductor 620, and optionally the additional element terminals 676 of the lower chip carrier 660 are in the same manner as described above for the solder or other bonding material that forms the land grid array. Thin assemblies or layers are coupled to corresponding terminals on a circuit board or other circuit panel. Here again, the thermal conductor or continuous layer 620 is desirably attached to a large grounded pad on the circuit panel so that the thermal conductor acts as both a ground connection and an RF shield element. In a variation of this embodiment, when the package is attached to the panel, the thermal conductor may be omitted so that the back surface of the lower chip is directly coupled to the circuit panel, and the back surface of the lower chip is exposed on the bottom surface of the package. Good.

  The embodiment of FIG. 17 is similar to the embodiment shown in FIGS. 15 and 16 except that instead of the large solder balls 622 shown in FIGS. 15 and 16, a column 722 protruding from the upper chip carrier 752 The difference is that the carrier 752 is interconnected with the lower chip carrier 760. The pillars 722 are preferably formed from copper or other metal material by etching. This etching is performed, for example, in a manner as described in US Pat. No. 6,177,636 and commonly assigned US provisional application entitled “Creating Feature Height Modified Circuits”. This US provisional application was identified as Attorney Docket No. Tessera 3.8-358, filed October 6, 2003, and has not yet been assigned a serial number. The disclosures of these US patents and US provisional applications are hereby incorporated herein by reference. The lands 730 used to interconnect with the lower chip 711 may be formed by the process disclosed in such a provisional application in order to reduce the height of the initially formed metal pillar.

  Desirably, the copper post 722 is plated with an adhesion promoting metal, such as nickel, and then gold for corrosion resistance. The gold plated pillars 722 are then coupled to the terminals 772 of the lower chip carrier 760 by a bonding material 732, eg, an assembly 732 of solder, tin, eutectic composition, or the like. The embodiment of FIG. 18 is similar to the embodiment shown in FIG. 17, but the through posts 822 are formed to extend upward from the lower chip carrier 860 rather than downward from the upper chip carrier 852. Different. The pillars 822 are coupled to corresponding terminals 870 of the upper chip carrier 852 by bonding material 832.

  FIG. 19 shows an assembly 1400 according to another embodiment of the present invention. In this embodiment, one or more chips 1414 and 1415 are disposed in the internal space between the lower package element or bottom planar element 1418 and the upper package element or connection element 1430. In the particular embodiment illustrated, the lower package element 1418 may be a chip carrier that includes a sheet-like dielectric element 1419. A patterned metal conductive layer 1420 is disposed on the top surface of such a dielectric element. This metal layer defines a lower terminal 1422 that is exposed through a hole in the dielectric layer 1419 at the bottom surface 1424 of the lower chip carrier 1418 for interconnection to the underlying element. The metal layer 1420 further includes a heat conductor, such as the heat conductor previously described with reference to FIG. The thermal conductor is exposed to the bottom surface of the lower chip carrier by a hole in the dielectric layer 1418. Here again, the thermal conductor may optionally be in the form of a substantially continuous layer. The continuous layer extends around the other components of the metal layer and provides a large ground plane as described above. In other variations, other package elements, such as lead frames, sheet-like dielectric elements having one or more metal layers on the bottom, or having multiple dielectric layers and also having one or more conductive layers Multilayer circuit panels having layers, such as those previously described and those described in the '509 application, may be used as the lower package element.

  The one or more chips are passive chips 1415 with integrated passive devices as previously described. Furthermore, the passive chip can be provided with one or more discrete passive devices 1441, which are attached to the front contact holding surface 1417 of the passive chip. The one or more chips are “active chips” 1414 having one or more integrated active devices. The passive chip 1415 is preferably a flip chip that is attached to the active chip 1414 via surface mount means such as solder balls or solder bump arrays, land grid arrays, and the like. The active chip 1414 has an upward front contact holding surface 1435 and a downward back surface 1437 arranged in contact with the lower chip carrier 1418.

  The downwardly facing back surface 1437 of the active chip 1414 is desirably attached to the metal layer 1420 of the lower chip carrier 1418 by a bonding material having a high thermal conductivity, such as a metal bonding material. The passive chip 1415 has a back surface 1416 that is attached to the upper chip carrier 1430. The upper chip carrier 1430 is disposed on the passive chip 1415. In FIG. 19, the upper chip carrier 1430 is shown as a multilayer panel. This multilayer panel has multiple layers of metal features 1438 including traces, bond pads 1429 on the bottom of the panel, terminals 1431 on the top of the panel, and vias 1434. Vias 1434 extend through the panel and traces and vias conductively interconnect at least some of the bond pads 1429 to at least some of the terminals 1431. The metal features 1438 of the upper chip carrier desirably include a substantially continuous conductive plane, such as a heat spreader 1403 or other features sufficient to form a barrier to operating frequency electromagnetic radiation used in the assembly. . Other forms of package elements can be used, such as a lead frame or a sheet-like dielectric element having one or more metal layers. Preferably, these other forms include similar features.

  Preferably, it has a larger area than the upper tip 1418 and protrudes from the upper tip 1418 with respect to at least one edge. In order to attach the passive chip 1418 to the upper chip carrier 1430, a high thermal conductivity material 1432 is preferably disposed between the passive chip 1418 and the upper chip carrier 1430 so that the upper chip 1415 is in heat transfer with the spreader 1403. To be done.

  As shown in FIG. 19, some or all of contacts 1401 on passive chip 1415 are electrically connected to lower chip carrier 1418 by bottom leads 1426. Bottom lead 1426 may include leads formed integrally with wire bonds and / or traces of lower chip carrier 1418. For example, the bottom lead 1426 may be integrally formed with the terminal 1422 as part of the metal layer 1420. These leads may be deformable leads and may have ends that are temporarily held in place relative to the dielectric element 1419 by a brittle element. An example of such a brittle lead was previously described with reference to FIG. A bond window 1440 can be provided in the dielectric element of the lower chip carrier in a manner similar to that previously described with reference to FIG. During assembly, a tool inserted through the bond window disconnects the lead 1426 from the brittle connection to the dielectric element of the chip carrier 1418, bends the lead and attaches the lead to the contact pad on the passive chip 1415.

  As further shown in FIG. 19, passive chip 1415 is interconnected to upper chip carrier 1430 by upper leads 1428 in the form of wire bonds. Upper lead 1428 is connected between contact 1401 on upper or passive chip 1415 and bond pad 1429 on the upper chip carrier. The bond pads are conductively interconnected to terminals 1431 on the top surface of chip carrier 1430.

  The top lead 1428 and bottom lead 1428 may be arranged to connect some or all of the upper chip carrier terminals 1431 with some or all of the lower chip carrier terminals 1422. Some or all of such connections may be “straight through” connections that do not pass through the functional elements of chips 1414 and 1415. For example, if both the top and bottom leads are connected to the common contact 1401 of the passive chip or to two contacts 1401 connected by a low resistance conductor on the passive chip, a straight through connection is made. . Other interconnects can be arranged so that signals passing between the conductive elements of the upper and lower interposers are routed through one or more functional elements of the chip.

  An encapsulant 1436 is desirably provided between the upper chip carrier 1430 and the lower chip carrier. The provided sealing material has the characteristics as described above. The assembly of FIG. 19 first creates a subassembly including chips 1414 and 1415, then couples the subassembly to an upper chip carrier 1430 having a bonding material layer 1432, and connects some or all of the contacts 1401 of the chip 1415. , May be formed by wire bonding to contact pads 1428 of the upper chip carrier having upper leads 1428. After the wire bonding step, the lower chip carrier is placed on the back surface 1437 of the lower chip 1414 and the bottom leads 1426 are connected to some or all of the upper or passive chip contact pads 1401. Next, an encapsulant is introduced between the upper and lower chip carriers. Some or all of these steps may be performed while the upper chip carrier, the lower chip carrier, or both are part of a large tape or sheet. The tape or sheet is cut during or after assembly to provide individual units that include one or more assemblies 1400.

  Assembly 1400 may be attached to a circuit panel having contact pads 1481 and thermal conductor attachment elements 1482 disposed on contact surface 1480 using a solder bonding process or other metal bonding process similar to the process described above. This is to form a metal connection between the terminal 1422 of the lower chip carrier 1418 and the contact pad 1481 and a large connection between the thermal conductor of the lower chip carrier and the thermal conductor mounting element 1482 of the panel. As previously described, the thermal conductor and panel mounting element 1482 provides thermal conduction to the assembly over a large area on the backside of the active chip 1414 and diffuses heat transferred from the active chip into the circuit panel.

  One or more additional chips or other microelectronic elements 1490 may be attached to the terminals 1431 of the upper chip carrier. Typically, the additional elements are arranged to interact with the chip in the assembly. As shown, the chip 1490 is a flip chip attached to the upper chip carrier 1830 via a surface mount technique such as a solder ball grid array or land grid. Alternatively, the chip 1490 can be mounted upward on the upper chip carrier and interconnected to the upper chip carrier terminal 1431 via wire bonds or the like.

  In a particularly preferred arrangement, the chips 1414 and 1415 disposed in the space between the upper and lower chip carriers include one or more emitting chips that emit or emit energy at radio frequencies. A radio frequency power amplifier (“RFPA”) is one example of an emission tip. RFPA amplifies radio frequency analog signals and generally provides signals to an antenna for transmitting signals as radio waves over air or other generally non-conductive media. Nearly all of the amplified output of RFPA is generally intended to be coupled to such antennas by conductors, but some radio frequency energy is still emitted or radiated as radio waves from the chip or conductor. There is a case. In this case, the additional microelectronic element 1490 desirably includes one or more functional elements associated with signal reception or processing. Such functional elements include, but are not limited to, RF receivers, low noise amplifiers, filters, RF mixers, IF mixers, samplers, oscillators, and signal processors. If the upper chip carrier 1430 includes a ground plane, such as a heat conductor 1403 or other shielding element, stray RF emissions that occur from the chips 1414 and 1415 disposed between the chip carriers to the space above the upper chip carrier are substantially reduced. The additional microelectronic element 1490 is obstructed and thus protected from such stray emission. The thermal conductors and other conductive components of the lower chip carrier 1418 also substantially interfere with stray RF emissions that occur downward from the space between the chip carriers as well. Leads 1426 and 1428 substantially interfere with RF emission toward the edge of the assembly, for example when the space between grounded leads is smaller than the wavelength of RF emission. In some cases, additional grounded leads extending between the upper and lower chip carriers, or other conductive elements, such as continuous or nearly continuous conductivity extending from the vicinity of the upper chip carrier to the vicinity of the lower chip carrier. It may be desirable to provide a wall structure to prevent RF emission towards the edge. In other cases where the vertical distance between the conductive elements of the upper and lower chip carriers is less than the wavelength of the RF radiation, these elements alone will interfere with edge direction emission. It should be understood that in FIG. 19, as with the other drawings, the size of the assembly, particularly the vertical dimension of the assembly, is greatly exaggerated for purposes of illustration. By way of example only, the actual vertical distance between chip carriers may be about 1-2 millimeters or less.

  Additional microelectronic elements 1490 may be attached to assembly 1400 to form a larger preassembled module. The preassembled module can be processed and assembled into a circuit panel. In further variations, additional elements mounted on the upper chip carrier 1430 may include other multi-chip assemblies. For example, in the particular embodiment of FIG. 19, the upper chip carrier terminals 1431 include terminals 1431a provided in a pattern corresponding to the pattern of the lower chip carrier terminals 1422, and thus in addition to the microelectronic element 1490, Alternatively, other complete assemblies equal to assembly 1400 can be mounted over these terminals. For example, large solder balls 1433 can be used to support other assemblies (not shown) on element 1490. Multiple assemblies 1400 can be stacked on top of each other as a preassembled unit or during assembly into a circuit panel.

  The assembly 1500 of FIG. 20 is the same as the assembly 1400 of FIG. 19 except as described below. In the assembly 1500 of FIG. 20, a plurality of upper chips 1515, eg, passive chips, are disposed on a plurality of lower chips, eg, active chips 1514. Chips 1515 and 1514 are connected to each other. A portion of the front surface of the upper tip 1515 protrudes from the edge of the lower tip 1514 and extends beyond the edge. Also in this embodiment, multiple leads interconnect lower chip carrier 1518 to passive chip 1515 and connect the passive chip to upper chip carrier 1530. Here again, the leads are interconnected to the bottom lead 1542 that interconnects the terminal 1522 on the lower chip carrier 1518 to the contact 1523 of the passive chip 1515, and the contact 1523 of the passive chip to the bonding pad 1529 of the upper chip carrier, and thus to the terminal 1531. It includes an upper lead 1544 for connection. In this embodiment, some or all of the top leads 1544 are integrally formed with the bottom leads 1542. As described above, bottom lead 1542 can be integrally formed with metal layer features on the lower chip carrier, such as traces or terminals 1522, and can be coupled to terminals 1523 by a bonding tool. In such a case, the upper lead 1544 can be a continuation of the lead 1542 and is coupled to the terminal 1529 by a bonding tool. The bonding window 1540 of the lower chip carrier 1518 is made large enough to accommodate the required lead length. This type of lead necessarily provides a straight through that is connected between the lower chip carrier and the upper chip carrier. The lead formation technique previously described with reference to FIG. 19 may be used to form other leads.

  FIG. 21 shows another variation of the assembly shown and described in FIGS. 19 and 20. In the assembly of FIG. 21, the bottom lead 1642 extends again between the conductive features of the lower chip carrier and the contacts of the upper chip. However, some or all of the upper leads used in the embodiments of FIGS. 19 and 20 are replaced by interconnect leads 1644 that extend directly from the lower chip carrier 1630 to the upper chip carrier. Again, leads 1642 and 1644 can be integrally formed with the conductive features of lower chip carrier 1618 and can be coupled by a tool that is pressed to the leads through bond window 1640. Alternatively, the leads may be discrete leads, such as wire bonds, or a combination of discrete leads and leads formed integrally with the lower chip carrier. When the leads are integrally formed with the lower chip carrier, the leads may be placed at different locations along an axis perpendicular to the cross section shown in FIG. In such a method, the bonding tool can select one of the leads and couple it to the upper chip 1615 to form the bottom lead 1642. Next, at different times, the bonding tool can select another lead and couple it to the upper chip carrier 1630 to form the interconnect lead 1644. If the assembly includes only bottom and interconnect leads as shown in FIG. 21, the connection between the top chip carrier 1630 and the chip can be made by providing a set of leads. Each set includes a bottom lead 1642 and an interconnect lead 1644, each set of leads being interconnected by conductive features on the lower chip carrier 1618. For example, both leads of such a set may be connected to the same terminal 1622 of the lower chip carrier. Alternatively, both leads may be connected by a trace (not shown) but are isolated from terminal 1622.

  FIG. 22 shows another variation in which the upper or passive chip 1715 is placed in the recess of the upper chip carrier 1730. The contact pad 1729 of the upper chip carrier is substantially coplanar with the contact 1701 of the upper chip 1715. In this embodiment, the upper chip carrier is desirably a substrate type element, such as a ceramic substrate. The depressions are formed in the upper chip carrier 1730, for example by molding a precursor material into a substrate having a desired shape according to a known process. Alternatively, the substrate is formed first, then the material is removed, for example by etching or mechanical processing, to form the depressions 1702. In a further alternative, an upper chip carrier is formed by bonding a ring-shaped substrate having conductive features defining contact pads 1729 of the upper chip carrier with a substantially flat substrate, the ring-shaped substrate defining a recess, and flat Substrate conductive features 1710 can be connected to contact pads 1729.

  Bottom lead 1742 and top lead 1744 interconnect lower chip carrier 1718 to upper chip 1715 and upper chip carrier 1730. The leads are formed integrally with the lower chip carrier and can be coupled by lead deformation as described above. The lower and upper leads 1742 and 1744 may be individual leads or may be a continuous strip configuration, for example, as previously described with reference to FIG. The generally coplanar configuration of upper chip contact 1701 and upper chip carrier contact pad 1729 facilitates the bonding operation. Alternatively, leads 1742 and 1744 may be wire bonds or any of the other lead configurations described above. In a further variation (FIG. 24), a flat upper chip carrier substrate 1830 can be provided with contact pads 1829 in the form of pillars protruding from the bottom surface of the substrate. When the upper chip 1815 is placed on the bottom surface of such a substrate, the pillar is placed adjacent to one or more edges of the upper chip, and the tip of the pillar is substantially coplanar with the upper chip contact 1801. .

  Another variation is shown in FIG. As shown in FIG. 24, the upper chip carrier 1930 and the lower chip carrier 1918 are part of a folded dielectric sheet 1919 having a patterned metal layer 1920, such as the tape described above. In other words, a single sheet having the patterned metal layer 1920 is folded to provide a lower chip carrier 1918 and an upper chip carrier 1930. Thus, the boundary between the upper and lower chip carriers is a folded portion 1921 in the sheet. Microelectronic packages that include folded sheets and methods of making the same are described, for example, in co-pending commonly assigned U.S. Patent Application Nos. 10 / 077,388, 10 / 281,550, 10 / 654,375, This is described in detail in the embodiments of 60 / 408,644, 60 / 443,438, and PCT International Application PCT / US03 / 25256. The disclosures of all such applications are hereby incorporated herein by reference. It is also described in the embodiment of US Pat. No. 6,225,688. The disclosure of this US patent is also incorporated herein by reference.

  In the embodiment of FIG. 24, the upper or passive chip 1915 has a back surface 1932 attached to the inner or downward facing surface of the upper chip carrier 1930, and a front surface having contacts to which the active chip 1914 is flip-chip attached as described above. 1917. The lower chip carrier 1918 has a bottom surface from which a plurality of terminals 1922 are exposed. Similarly, the upper chip carrier 1930 has an upper surface from which a plurality of terminals 1924 are exposed.

  In one manufacturing process, the active chip 1914 is attached to the passive chip 1915. The attached chip is then attached to a thermal conductor or ground plate included in the metal layer 1920 on the dielectric sheet portion forming the lower chip carrier 1918, for example, by an encapsulant or a thermally conductive bonding material 1938, Thereafter, the dielectric sheet is folded and the upper or back surface 1932 of the passive chip 1915 is attached to the upper chip carrier 1930. Alternatively, it is assembled by first attaching the back side 1932 of the passive chip 1915 to the upper chip carrier 1930, then folding the sheet 1919, and then attaching the back side 1934 of the active chip to the metal layer 1920 of the lower chip carrier 1918. Chips 1914 and 1915 can be attached.

  A plurality of bottom leads 1942 interconnect the lower chip carrier 1918 to the passive chip 1915. As shown, the leads 1942 are integrally formed with the lower chip carrier, and a bonding tool that deforms each lead through a bond window 1940 after the sheet 1919 is folded to form the upper and lower chip carriers. Can be coupled to the passive chip 1915. As in the embodiment previously described with reference to FIG. 19, chips 1914 and 1915 desirably include one or more emission chips, such as RFPA. As in the embodiment previously described with reference to FIG. 19, the conductive features on the upper and lower chip carriers and other features such as leads 1942 extending between the lower chip carrier 1918 and the passive chip 1915. The combination provides a shield that prevents radio frequency radiation from substantially passing between the interior and exterior spaces between the upper and lower chip carriers 1918 and 1930. To provide additional RF shielding, the tape can include shielding features, such as a generally continuous ground plane that extends between the chip carriers and thus extends along the folded portion 1921. The tape can include one or more additional conductive layers as described below in connection with FIG. 26 to provide shielding features. Here again, additional conductive elements, such as additional leads extending between the upper and lower chip carriers remote from the folded portion, may be provided to provide additional RF shielding.

  Electrical interconnection between the active chip 1914 and the passive chip 1915 is made through contacts provided on the front and back surfaces 1917 and 1935 of the passive and active chips. Interconnection between the lower chip carrier 1918 and the passive chip 1915 is made through bottom leads 1942 extending from terminals 1922. In this embodiment, separately formed leads are not required to interconnect the terminals 1922 of the lower chip carrier 1918 to the terminals 1924 of the upper chip carrier 1930. This is because the folded sheets that make up the upper and lower chip carriers have a patterned metal layer 1920. The metal layer 1920 provides an interconnect in the form of traces that extend along the sheet and around the folded portion 1921. Desirably, a selected one of terminals 1922 is selectively interconnected to only a selected one of terminals 1924 by a patterned metal layer 1919, and a signal is transmitted between the upper chip carrier and the lower chip carrier. Passages are provided and common interconnects are provided, such as power and ground passages.

  FIG. 25 is a plan view illustrating an embodiment in which a plurality of carriers, including chip carriers, are provided as a set of foldable dielectric sheet 2000 flaps having a patterned metal layer (not shown). Such dielectric sheets and patterned metal layers are generally described above with reference to FIG. Carriers 2001, 2002, 2003, 2004, and 2005 support a plurality of functional blocks, each functional block having an attached chip or other electronic element, such as an antenna. Each carrier of the sheet 2000 has a structure and function, such as a lower chip carrier or an upper chip carrier of a multi-layer folded stack package as previously described with respect to FIG. Each of the carriers is patterned to support functional blocks. The functional block may be unique within a particular dielectric sheet 2000 or the same as other chip carriers. In an embodiment, a portion of the dielectric sheet 2000 can be patterned to support a power amplifier (PA) 2001, a receiver (RX) 2002, an antenna (ANT) 2004, and a transmitter (TX) 2005. Block “ANT” on carrier 304 represents an antenna. The antenna can desirably be formed integrally with the carrier, for example in the pattern of conductive traces on a dielectric sheet. Although not specifically shown in FIG. 25, portions of dielectric sheet 2000 are interconnected by wiring patterns in the metal layer as previously described with reference to FIG. The dielectric sheet 2000 has a generally cruciform pattern and is intended to be folded at the folded portion 2021 to form a multi-layer folded layered chip package having five stacked layers. Cross-shaped folding packages are described, for example, in co-pending commonly assigned US patent application Ser. No. 10 / 077,388. The disclosure of this US patent application is hereby incorporated herein by reference.

  To reduce interference from the power amplifier, the receiver carrier 2002 is desirably folded to be shielded from the radiation emitted by the power amplifier and / or antenna carriers 2001, 2003, and 2004 of the package. For example, the receiver chip carrier 2002 is folded so that the chip attached to the carrier 2002 does not face the chip attached to the carrier 2001 of the power amplifier. The transmitter carrier 2005 is preferably folded over the folded receiver carrier 2002 so that the chip of the transmitter carrier does not face the chip on the receiver carrier. Thereafter, the antenna carrier 2025 can be folded over a three-level stack of power amplifier, receiver, and transmitter such that the antenna is present on the upward face of the folded package. In each case, a conductive shield element incorporated in at least one carrier is present between the emission source, eg PA 2001 or antenna 2003, and a chip or other component that is protected from emission.

  FIGS. 26-28 illustrate other variations in a folded stacked package according to an embodiment of the present invention. As shown in FIG. 26, the two-layer folded stacked package 2100 is composed of a dielectric element 2102 having two metal layers 2120 and 2121. The package includes an upper chip carrier 2130, a lower chip carrier 2118 formed integrally with the upper chip carrier, one or more upper chips 2116 disposed on the upper chip carrier, and an upper chip carrier and a lower chip carrier. One or more lower tips 2114 disposed between the two. Desirably, the lower tip 2114 includes RFPA or other emission source. Upper chip 2116 desirably includes one or more functional elements associated with receiving or signal processing functions, as previously described in connection with FIG.

  The first metal layer 2120 of the sheet is patterned and serves to interconnect the chips and / or other elements. The second metal layer 2121 is substantially continuous over a large area of the sheet and acts as a ground plane or alternatively as a conductive backplane. The second metal layer 2121 acts as an electromagnetic shield for the lower chip 2114 and components in the internal space between the upper chip carrier 2130 and the lower chip carrier 2118 because of its continuity. As shown in FIG. 26, the chip is mounted in an upward position and interconnected to the respective portions of the metal layer of the folded sheet by wire bonds.

  In a further variation shown in FIG. 27, a three level folded stacked package 2200 is provided. In this variation, it has a pattern formed in a first metal layer 2210, a dielectric layer 2215 adhered thereto, and a second metal layer 2220 adhered to the dielectric layer on the opposite side of the first metal layer 2210. A unitary metal sheet element 2200 is provided. The unitary metal sheet element is folded twice to provide the structure shown in FIG. The antenna is provided as a set of patterns 2202 in the cap panel 2210 of the package, and is exposed and facing outward. The antenna may incorporate a spiral coil, dipole, or other conductor pattern. Alternatively, the antenna may be as described in the '509 application. As previously described with respect to FIG. 26, the substantially continuous portion 2221 of the metal layer 2220 also functions as a shield element and preferably a ground plane, substantially hindering the emission of radio frequency energy. In particular, the radio frequency energy emitted from the antenna pattern 2202 is blocked from reaching the upper chip 2216 disposed between the metal layer 2221 and the upper chip carrier 2230. In addition, leads 2244 extending between the terminals of upper chip carrier 2230 and upper chip 2216 also help prevent radiation from reaching chip 2216. In addition, the metal layer 2221 and the lead 2244 also prevent radiation emitted by the upper tip 2216 from reaching substantially the area above the metal layer 2221.

  In one embodiment, the lower chip 2214 includes a functional element having a radio frequency transmitter function, eg, a radio frequency transmitter, a radio frequency power amplifier (RFPA), and / or a transmit filter. Upper chip 2216 desirably includes one or more functional elements associated with receiving and / or signal processing functions. Such functional elements include, but are not limited to, RF receivers, low noise amplifiers, filters, RF mixers, IF mixers, one or more analog-to-digital converter elements such as samplers (sample and hold circuits), quantum A generator, an oscillator, and a signal processor. Alternatively or in addition, the upper chip 2216 includes RFPA control circuitry, eg, transmitter control circuitry. The transmitter control circuit may be a digital chip provided as a complementary metal oxide semiconductor (CMOS) technology or “biCMOS” chip, including, for example, both bipolar and CMOS transistors.

  Preferably, the RFPA outputs sufficient energy to the antenna so that communication signals are transmitted over commonly available wireless interfaces. Accordingly, the RFPA is configured to output at least 10 milliwatts of radio frequency power, more preferably 100 milliwatts or more, and most preferably 500 milliwatts or more.

  In one embodiment, upper chip 2216 includes one or more surface acoustic wave (SAW) filter devices configured to be used in a radio frequency signal receiver. Such a SAW filter device is desirably attached to a chip carrier as described in co-pending US Provisional Patent Application No. 60 / 449,673, which is incorporated herein by reference.

The package including the lower chip 2214, the upper chip 2216, and the antenna can desirably be made thin. For example, each chip carrier and cap panel has a thickness of about 200 μm or less, each chip has a thickness of less than about 200 μm, and the area of each chip is in a range of less than about 0.5 cm ^2. is there. Accordingly, packages containing these elements are in the range of about [(3 × 0.2) + (2 × 0.2)] × 0.5 (cm ³ ) = 0.5 cm ³ .

  FIG. 28 shows a variation of the package structure 2300 shown in FIG. In FIG. 28, the upper chip is flip-chip attached by a surface mount technique to the patterned metal layer of the upper chip carrier 2330 instead of the wire bonds shown in FIGS.

  Desirably, the package structure according to the variation illustrated in FIGS. 25-28 is incorporated into a portable electronic communication device, such as a handset. For example, the package structure can be incorporated into a cellular mobile communications device, such as a cellular phone, or alternatively, a cellular mobile data terminal, such as a portable digital assistant handset having a wireless communications interface.

  29 and 30 illustrate a variation of the embodiment previously illustrated and described with reference to FIGS. However, in FIGS. 29 and 30, a larger passive chip 2415 is attached to the lower chip carrier 2418. In this embodiment, the active chip 2414 is flip chip attached to the passive chip. As shown in FIG. 29, the upper lead 2444 is integrally formed with the trace 2422 on the bottom surface of the upper chip carrier 2430. The upper leads are interconnected to the passive chip 2415, for example, by deformation with a bonding tool through a bond window 2440 provided in the upper chip carrier 2430. Bottom lead 2442 is provided as a wire bond. As shown in FIG. 30, a plurality of passive chips 2515 are provided. The upper leads extend from the upper surface 2532 of the upper chip carrier 2530, and the upper chip carrier 2530 is provided as a multilayer substrate type carrier. In such a case, the top lead 2544 is interconnected to the passive chip 2515 by wire bonds, similar to the bottom lead 2542 that interconnects the passive chip 2515 to the lower chip carrier 2518. FIG. 31 shows a further variation where the upper chip carrier 2630 also has a plurality of chips 2614 attached.

  32 and 33 show an embodiment in which a plurality of chip carriers having attached chips are provided. The chip carrier is conductively connected by large solder balls 2702. Solder balls 2702 extend between the upper metal layer 2720 of the lower chip carrier 2718 and the lower metal layer of the intermediate chip carrier 2730. Similarly, conductive interconnects are provided by large solder balls 2704. Solder balls 2704 extend between the upper metal layer of intermediate chip carrier 2730 and the lower metal layer of upper chip carrier 2750. The assembly is attached to a circuit board 2712 having a pattern 2708. The conductive interconnect provided by the large solder balls 2702 and 2704 is simply to support the ground plane or common plane, or alternatively to transmit signals between devices on the lower, middle, and upper chip carriers. It may be. As further shown in FIG. 32, conductive interconnects are provided in the form of wire bonds between the upper chip carrier 2750 and the intermediate chip carrier 2730. A bond window 2740 in the upper chip carrier 2750 is provided for that purpose.

  Large solder balls 2702 and 2704 also substantially assist in hindering radio frequency energy from radiating from devices present between the respective chip carrier and external space. Furthermore, the middle and upper chip carriers may be provided with ground planes that assist in the interference of radiation. With particular reference to FIG. 33, a ground plane is provided under the antenna formed by the conductive pattern 2806 of the upper chip carrier 2850. In such embodiments, additional solder balls 2801 are provided on the underside of the lower chip carrier, for example to interconnect with a circuit panel.

  In other embodiments, instead of large solder balls 2702, 2704, 2802, 2804, conductive pillars for interconnecting respective chip carriers may be provided (not shown). In such embodiments, the column has a generally cylindrical or truncated cone shape, or alternatively a polygonal cross section.

  In the embodiments described above, the use of connection elements in the form of circuit panels separate from the integrated passive chip provides significant economic advantages. The circuit panel has a low cost per unit area. However, in a further variation, the features and methods described so far can be used in an arrangement in which the passive chip acts as a connecting element. For example, in such an embodiment, the lead frame described above can be used.

  Since these and other variations and combinations of the features described so far can be utilized without departing from the invention, the foregoing description of the preferred embodiments is considered as an example and not as a limitation of the invention. It should be.

  The present invention can be used in the manufacture of electronic devices.

1 is a plan view of a lead frame according to one embodiment of the present invention. FIG. FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. FIG. 3 is a partial cross-sectional view taken along line 3-3 of FIG. FIG. 3 is a view similar to FIG. 2 but showing a lead frame in combination with a subassembly of a manufacturing process step. FIG. 5 is a partial cross-sectional view of the subassembly shown in FIG. 4. FIG. 4 is a plan view of an assembly formed from the subassembly and lead frame of FIG. 3. It is a top view which shows the assembly in the latter half stage of manufacture. FIG. 8 is a cross-sectional view of the assembly of FIG. 7 in combination with a circuit board. FIG. 9 is a partial cross-sectional view of the assembly and circuit board of FIG. 8 taken along line 9-8 of FIG. FIG. 6 is a cross-sectional view illustrating a package according to a further embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a package according to a further embodiment of the present invention. FIG. 11 is a view similar to FIG. 10 but showing a package according to yet another embodiment of the present invention. It is a fragmentary sectional view of the connection element used in other embodiment of this invention. FIG. 2 is a view similar to FIG. 1 but showing a lead frame according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 16 is a partially cut perspective view of a packaged chip according to the embodiment of the present invention shown in FIG. 15. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. 2 is a high level schematic plan view of a packaged chip according to an embodiment of the invention. FIG. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to a further embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a packaged chip according to yet another embodiment of the present invention.

Claims (24)

(A) at least one lower tip;
(B) a connecting element extending over the at least one lower tip and extending beyond the at least one lower tip in at least one horizontal direction;
(C) define at least a portion of the bottom surface of the package under the at least one lower chip, a plurality of terminals exposed from the bottom surface, a bottom planar element including a heat conductor exposed to the bottom surface, the heat A conductor has an area greater than the area of each of the terminals, the thermal conductor is at least partially aligned with the at least one lower tip, and at least some of the terminals are connected to the at least one by the connecting element; A bottom planar element electrically connected to at least some of the contacts of the lower chip, the terminals having a plurality of active terminals and a plurality of active leads projecting upward from the active terminals to the connecting element ;
And (d) at least one upper chip mounted to said top surface of said connecting element, microelectronic packages. It said connecting element is a conductive trace extending along at least one conductive layer and the at least one conductive layer, at least some of said terminals, at least some of said contacts of said at least one lower chip by the trace The package according to claim 1, wherein the package is connected to   The package of claim 1, wherein the active lead is formed integrally with the active terminal.   The package of claim 2, wherein the active lead is thicker than the trace. The package of claim 1, wherein the bottom planar element includes one or more ground buses coplanar with the thermal conductor.   The package of claim 1, wherein the bottom planar element further comprises a bottom planar dielectric layer, and the terminals are attached to the bottom planar dielectric layer. The package of claim 6 , wherein the at least one upper chip is an integrated passive chip that includes one or more passive components, the passive chip having a horizontal dimension that is less than a horizontal dimension of a connecting element. The package of claim 7 , wherein the at least one lower chip is an active RF chip.   The package according to claim 2, further comprising a ground lead formed integrally with the ground bus, the ground lead protruding upward from the ground bus to the connection element.   The package of claim 5, wherein the ground bus is laterally spaced from the thermal conductor, and the bottom planar element includes a ground post that extends between the thermal conductor and the ground bus.   The thermal conductor has a plurality of edges, the one or more ground buses extend along one or more edges of the thermal conductor, and the active contact is one or more other of the thermal conductors The package of claim 3 arranged as one or more rows along an edge. (A) a connecting element having a top surface and a bottom surface and including a dielectric layer and traces extending along the dielectric layer;
(B) at least one lower tip attached to the bottom surface of the connecting element having a surface remote from the connecting element, the surface defining a lower reference plane at a level below the connecting element;
(C) a plurality of active terminals arranged below the lower reference plane;
(D) a plurality of active leads connected to at least some of the traces, at least some of which are thicker than the traces, in the form of elongated strips extending between the active terminals and the connecting elements; An active lead ;
(E) and at least one upper chip mounted to said top surface of said connecting element, microelectronic packages. The package of claim 12 , further comprising an assembly of encapsulant covering the connecting element and the at least one lower chip, wherein the active leads are embedded in the encapsulant. The package according to claim 13 , wherein the assembly of the sealing materials defines a bottom surface below the lower reference surface, and the active terminals are exposed on the bottom surface of the assembly. The package according to claim 14 , wherein the assembly of the sealing materials defines an edge surface extending upward from the bottom surface, and the active terminals are disposed on the edge surface. The package of claim 12 wherein the trace is less than 40 μm thick and the active lead is at least 50 μm thick. (A) (i) a subassembly incorporating a connecting element having a top surface and a bottom surface and incorporating one or more lower tips attached to said bottom surface; and (ii) a bottom planar element including a thermal conductor; The one or more lower chips are present on the thermal conductor, the connecting element is disposed on the thermal conductor and the one or more lower chips, and the upper chip There the fit these to the top surface of the connecting element, the assembly steps are performed, the steps,
And (b) of the connection element, and a step of electrically connecting to the active terminal of the thermal conductor and coplanar, making microelectronic package. The bottom planar element includes an active lead projecting upward from the active terminal, whereby the connection element is juxtaposed with the active lead in the assembly step, and the electrical connection step causes the conductive element of the connection element to be active. The method of claim 17 , comprising electrically connecting to the lead. The step of providing the bottom planar element includes providing a lead frame including the active lead, the active terminal, and the thermal conductor, and after the assembly step, the active terminal and the active lead are removed from the thermal conductor. The method of claim 18 further comprising the step of detaching. Encapsulating the active leads, connecting elements, and chips to leave the active terminals and the thermal conductor exposed, wherein the separating step is a temporary element of the lead frame after the encapsulating step. 20. The method of claim 19 , comprising removing. (A) (i) one or more lower chips having a surface remote from the connecting element and defining a lower reference plane, the upper surface, the bottom surface, and the one or more lower chips attached to the bottom surface And (ii) a separate bottom planar element including active terminals present below the lower reference plane , wherein the one or more lower tips are on the bottom planar element present in a bottom planar element, a step of assembling at least one upper chip attached to the top surface of the (iii) said connecting elements,
(B) including the step of electrically connecting the connecting element to the terminal, a method of making a microelectronic package. The bottom planar element has a terminal lead protruding upward from the terminal, the terminal lead has a top end, the connecting element includes a conductive layer having a trace, and the trace extends to a land exposed at the bottom surface. The method of claim 21 , wherein the assembly step is performed to engage the land with the upper end of the terminal lead. The method of claim 21 , wherein the bottom planar element comprises an inductor, and further comprising connecting the inductor to the connection element. The method of claim 21 , wherein the bottom planar element comprises a lead frame.

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