WO2021079666A1 - Chip temperature sensor for semiconductor chip, and flow rate measurement device - Google Patents

Chip temperature sensor for semiconductor chip, and flow rate measurement device Download PDF

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Publication number
WO2021079666A1
WO2021079666A1 PCT/JP2020/035391 JP2020035391W WO2021079666A1 WO 2021079666 A1 WO2021079666 A1 WO 2021079666A1 JP 2020035391 W JP2020035391 W JP 2020035391W WO 2021079666 A1 WO2021079666 A1 WO 2021079666A1
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Prior art keywords
resistance element
semiconductor chip
type diffusion
chip
temperature sensor
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PCT/JP2020/035391
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French (fr)
Japanese (ja)
Inventor
松本　昌大
晃 小田部
尭生 佐藤
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日立Astemo株式会社
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Publication of WO2021079666A1 publication Critical patent/WO2021079666A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
    • G01F1/00—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow
    • G01F1/68—Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using thermal effects
    • G01F1/684—Structural arrangements; Mounting of elements, e.g. in relation to fluid flow
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/22—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor
    • G01K7/24—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit
    • G01K7/25—Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a non-linear resistance, e.g. thermistor in a specially-adapted circuit, e.g. bridge circuit for modifying the output characteristic, e.g. linearising

Definitions

  • the present invention relates to the structure of a semiconductor device, and particularly relates to a technique that is effective when applied to a chip temperature sensor that measures the chip temperature of a semiconductor chip.
  • the in-vehicle air flow sensor measures the flow rate of intake air to the engine to optimize the fuel injection amount of the engine, improve fuel efficiency, and contribute to the reduction of carbon dioxide (CO 2) and exhaust gas. It is positioned as a key component.
  • a chip temperature sensor is formed by forming two resistance elements with different resistance temperature coefficients with different impurity concentrations on a semiconductor chip such as silicon (Si) in series to form a heater resistance.
  • a semiconductor chip such as silicon (Si)
  • a current is supplied to the heater resistor to control heating to a constant temperature, and the flow rate and flow direction of air are controlled by utilizing the fact that the amount of heat transfer to air is distributed to the chip temperature sensors on both sides depending on the air flow velocity.
  • Patent Document 1 As an example of detecting the chip temperature of a semiconductor chip by connecting two resistance elements having different resistance temperature coefficients in series, for example, there is a technique described in Patent Document 1.
  • an N-type diffusion resistance element having a positive temperature coefficient and a polycrystalline silicon resistance element having a negative temperature coefficient are connected in series, and the voltage at the connection point of these resistance elements changes according to the chip temperature.
  • the chip temperature of the semiconductor chip is measured by utilizing the above.
  • Patent Document 2 states that "an N-type resistor portion and a P-type resistor portion electrically connected in series with each other are provided, and the N-type resistor portions are arranged so as to be perpendicular to each other and electrically. It has a first N-type diffusion layer resistance element and a second N-type diffusion layer resistance element connected in series, and the P-type resistance portions are arranged so as to be perpendicular to each other and are electrically connected in series. It has a first P type diffusion layer resistance element and a second P type diffusion layer resistance element, the first N type diffusion layer resistance element is arranged along the ⁇ 110> direction, and the first P type diffusion layer resistance element is in the ⁇ 100> direction. "Resistance circuits arranged along the line" are disclosed.
  • Patent Document 1 Since the method of Patent Document 1 uses a resistance element having a positive temperature coefficient and a negative temperature coefficient, there is an advantage that the sensitivity to temperature is increased.
  • the mounting stress due to the resin mold and the mounting stress generated by fixing the semiconductor chip to the printed circuit board act on the semiconductor chip. Due to this mounting stress, the N-type diffusion resistance element having a positive temperature coefficient greatly changes the resistance value. Also, although the polycrystalline silicon resistance element having a negative temperature coefficient is not as high as that of the N-type diffusion resistance element, the resistance value is changed by the mounting stress.
  • this mounting stress changes due to the difference in the coefficient of linear expansion of the printed circuit board, the coefficient of linear expansion of the molded resin, the coefficient of linear expansion of the semiconductor chip, and the change in ambient temperature. It also changes depending on the heat treatment applied at the time of mounting on the printed circuit board and the temperature at which the molding resin is molded. Further, it changes when the mold resin or the printed circuit board absorbs moisture.
  • Patent Document 1 lacks consideration for mounting stress generated in a semiconductor chip.
  • Patent Document 2 has a circuit configuration in consideration of the stress of the semiconductor chip received from the package material or the like, but the resistance values of the N-type resistor portion and the P-type resistor portion when the semiconductor chip is stressed. The amount of change is not always equal, which may cause an error in the measurement of chip temperature.
  • an object of the present invention is to provide a chip temperature sensor for a semiconductor chip, which is less affected by mounting stress.
  • the present invention relates to the same semiconductor chip with a first resistance element having a first impurity concentration and a first resistance element connected in series to the first impurity concentration.
  • a second resistance element having a different second impurity concentration, and an angle in the chip surface of the semiconductor chip in which the current energization direction of the first resistance element and the piezo resistance coefficient of the semiconductor chip are minimized.
  • the angle with the direction is larger than the angle between the current energizing direction of the second resistance element and the angular direction in the chip surface of the semiconductor chip at which the piezo resistance coefficient of the semiconductor chip is minimized. ..
  • the present invention is a flow rate measuring device including a heater resistance and an upstream temperature sensor and a downstream temperature sensor on both sides of the heater resistance on a semiconductor chip, wherein the upstream temperature sensor and the downstream temperature sensor are provided.
  • the temperature sensor is a chip temperature sensor of the above-mentioned semiconductor chip.
  • the detection accuracy of the chip temperature sensor of the semiconductor chip and the flow rate measuring device (air flow sensor) using the sensor can be improved.
  • FIG. 1 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment
  • FIG. 2 is a layout diagram of the N-type diffusion resistance elements 1 and 2 on the semiconductor chip
  • FIG. 3 is a relationship between the impurity concentration and the temperature coefficient of resistance
  • FIG. 4 is a diagram showing the relationship between the impurity concentration and the piezo resistance coefficient
  • FIG. 5 is a diagram showing the relationship between the angle ⁇ between the current energizing direction of the N-type diffusion resistance element and the ⁇ 110> direction and the piezo resistance coefficient. is there.
  • the chip temperature sensor of the semiconductor chip of this embodiment includes an N-type diffusion resistance element 1 having a high impurity concentration, an N-type diffusion resistance element 2 having a low impurity concentration, and an N-type diffusion resistance element 1. It is composed of an amplifier 3 that amplifies the voltage at the connection point of the N-type diffusion resistance element 2. One end of the N-type diffusion resistance element 1 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2. One end of the N-type diffusion resistance element 2 is connected to the ground, and the other end is connected to the N-type diffusion resistance element 1.
  • the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 are arranged on the same semiconductor chip 4 made of silicon (Si), and the longitudinal direction of the N-type diffusion resistance element 1 is ⁇ 110.
  • the N-type diffusion resistance element 2 is arranged so as to be offset by an angle of ⁇ p from the crystal axis direction of ⁇ 110>, and the longitudinal direction of the N-type diffusion resistance element 2 is arranged in the crystal axis direction of ⁇ 110>.
  • the current energizing direction of the N-type diffusion resistance elements 1 and 2 is the longitudinal direction of the N-type diffusion resistance elements 1 and 2 so as to be the longitudinal direction of the N-type diffusion resistance elements 1 and 2, respectively. There are contacts on both ends of the. Further, in the N-type diffusion resistance elements 1 and 2, the angular direction in the chip surface of the semiconductor chip 4 in which the piezoresistive coefficient is extremely small is ⁇ 110>.
  • crystal structure of silicon constituting the semiconductor chip 4 is a simple cubic crystal, [110], [101], [011] and the like are equivalent, so these are described as ⁇ 110>.
  • the change in the resistance value of the N-type diffusion resistance element 2 becomes larger than the change in the resistance value of the N-type diffusion resistance element 1.
  • the voltage at the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 changes according to the chip temperature of the semiconductor chip 4. Therefore, by amplifying this voltage with the amplifier 3, the chip of the semiconductor chip 4 An output voltage Vout corresponding to the temperature can be obtained.
  • the piezoresistive coefficient of the diffusion resistance element changes according to the impurity concentration, and the piezoresistive coefficient is different between the N-type diffusion resistance element 1 having a high impurity concentration and the N-type diffusion resistance element 2 having a low impurity concentration.
  • the N-type diffusion resistance element 1 having a high impurity concentration has a small piezoresistive coefficient
  • the N-type diffusion resistance element 2 having a low impurity concentration has a large piezoresistive coefficient.
  • the resistance value of the N-type diffusion resistance element 2 changes more than the change of the resistance value of the N-type diffusion resistance element 1, and the N-type diffusion resistance element 1 and the N-type diffusion resistance element 1 change.
  • the voltage at the connection point of the N-type diffusion resistance element 2 changes. This causes an error in the measurement of the chip temperature.
  • the piezoresistive coefficient changes according to the impurity concentration, the current energization direction, and the angle ⁇ between the ⁇ 110> direction. Therefore, even if the N-type diffusion resistance elements 1 and 2 have different impurity concentrations, the piezoresistive coefficients of the N-type diffusion resistance elements 1 and 2 can be made equal by appropriately selecting the angle ⁇ .
  • the angle ⁇ between the current energizing direction of the N-type diffusion resistance element 1 and the ⁇ 110> direction is set to ⁇ p, and the current energization direction and the ⁇ 110> direction of the N-type diffusion resistance element 2 are set.
  • the angle ⁇ is set to zero, the piezo resistance coefficients of the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 are made equal.
  • the resistance values of the N-type diffusion resistance elements 1 and 2 change by the same amount, so that the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 4, the measurement error of the chip temperature can be eliminated.
  • the current energizing direction in which the piezoresistive coefficient of the N-type diffusion resistance element is minimized exists every 90 °, but since these are all in the ⁇ 110> direction, the N-type diffusion resistance element Even if the current-carrying directions of the currents 1 and 2 are rotated by 90 ° and 180 ° 270 °, they are equivalent when the mounting stress is uniform (a state in which tensile or compressive stress is applied in all directions).
  • N-type diffusion resistors are used for both the N-type diffusion resistance elements 1 and 2. This is because the polarity of the piezoresistive coefficient differs between the N-type diffusion resistance and the P-type diffusion resistance, so only the magnitude of the piezoresistive coefficient can be changed by the method of changing the direction of the current flowing through the resistance element as in this embodiment. N-type diffusion resistors are used for both the resistance elements 1 and 2.
  • FIG. 6 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment
  • FIG. 7 is a layout diagram of the P-type diffusion resistance elements 5 and 6 on the semiconductor chip
  • FIG. 8 is energization of the current of the P-type diffusion resistance element. It is a figure which shows the relationship between the angle ⁇ of a direction and a ⁇ 100> direction, and a piezo resistance coefficient.
  • the chip temperature sensor of the semiconductor chip of this embodiment includes a P-type diffusion resistance element 5 having a high impurity concentration, a P-type diffusion resistance element 6 having a low impurity concentration, and a P-type diffusion resistance element 5. It is composed of an amplifier 7 that amplifies the voltage at the connection point of the P-type diffusion resistance element 6. One end of the P-type diffusion resistance element 5 is connected to the power supply voltage Vcc, and the other end is connected to the P-type diffusion resistance element 6. One end of the P-type diffusion resistance element 6 is connected to the ground, and the other end is connected to the P-type diffusion resistance element 5.
  • the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 are arranged on the same semiconductor chip 8 made of silicon (Si), and the longitudinal direction of the P-type diffusion resistance element 5 is ⁇ 100.
  • the P-type diffusion resistance element 6 is arranged so as to be offset by an angle of ⁇ p from the crystal axis direction of ⁇ 100>, and the longitudinal direction of the P-type diffusion resistance element 6 is arranged in the crystal axis direction of ⁇ 100>.
  • the current energizing direction of the P-type diffusion resistance elements 5 and 6 is the longitudinal direction of the P-type diffusion resistance elements 5 and 6 so as to be the longitudinal direction of the P-type diffusion resistance elements 5 and 6, respectively. There are contacts on both ends of the. Further, in the P-type diffusion resistance elements 5 and 6, the angular direction in the chip surface of the semiconductor chip 8 in which the piezoresistive coefficient is extremely small is ⁇ 100>.
  • crystal structure of silicon constituting the semiconductor chip 8 is a simple cubic crystal, [100], [010], [001], etc. are equivalent, so these are described as ⁇ 100>.
  • the change in the resistance value of the P-type diffusion resistance element 6 becomes larger than the change in the resistance value of the P-type diffusion resistance element 5.
  • the voltage at the connection point between the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 changes according to the chip temperature of the semiconductor chip 8. Therefore, by amplifying this voltage with the amplifier 7, the chip of the semiconductor chip 8 is used. An output voltage Vout corresponding to the temperature can be obtained.
  • the piezoresistive coefficient of a P-type diffusion resistance element changes according to the impurity concentration, the piezoresistive effect of the P-type diffusion resistance element 5 having a high impurity concentration and the P-type diffusion resistance element 6 having a low impurity concentration The resistance coefficient is different, the piezoresistive coefficient of the P-type diffusion resistance element 5 having a high impurity concentration is small, and the piezoresistive coefficient of the P-type diffusion resistance element 6 having a low impurity concentration is large.
  • the resistance value of the P-type diffusion resistance element 6 changes more than the change of the resistance value of the P-type diffusion resistance element 5, and the P-type diffusion resistance element 5 and the P-type diffusion resistance element 5 change.
  • the voltage at the connection point of the P-type diffusion resistance element 6 changes. This causes an error in the measurement of the chip temperature.
  • the piezoresistive coefficient changes according to the impurity concentration, the current energization direction, and the angle ⁇ between the ⁇ 100> direction. Therefore, even if the P-type diffusion resistance elements 5 and 6 have different impurity concentrations, the piezoresistive coefficients of the P-type diffusion resistance elements 5 and 6 can be made equal by appropriately selecting the angle ⁇ .
  • the angle ⁇ between the current energizing direction of the P-type diffusion resistance element 5 and the ⁇ 100> direction is set to ⁇ p, and the current energization direction and the ⁇ 100> direction of the P-type diffusion resistance element 6 are set.
  • the angle ⁇ is set to zero, the piezo resistance coefficients of the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 are made equal.
  • the resistance values of the P-type diffusion resistance elements 5 and 6 change by the same amount, so that the connection point between the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 8, it is possible to eliminate the measurement error of the chip temperature.
  • the first resistance element (P-type diffusion resistance element 5) and the second resistance element (P-type diffusion resistance element 6) are both P-type diffusion resistance elements.
  • the angle ( ⁇ p) formed between the current energizing direction of the first resistance element (P-type diffusion resistance element 5) and the ⁇ 100> direction of the semiconductor chip 8 is the second resistance element (P-type diffusion). It is configured to be larger than the angle formed between the current energizing direction of the resistance element 6) and the ⁇ 100> direction of the semiconductor chip 8.
  • the angle between the current energizing direction of the second resistance element (P-type diffusion resistance element 6) and the angular direction in the chip surface of the semiconductor chip 8 in which the piezo resistance coefficient of the semiconductor chip 8 is minimized is equal. It is configured.
  • the current energizing direction in which the piezoresistive coefficient of the P-type diffusion resistance element is minimized exists every 90 °, but since these are all in the ⁇ 100> direction, the P-type diffusion resistance element Even if the current energization directions of 5 and 6 are rotated by 90 ° and 180 ° 270 °, they are equivalent when the mounting stress is uniform (a state in which tensile or compressive stress is applied in all directions).
  • the P-type diffusion resistance elements 5 and 6 are both described using the P-type diffusion resistance. This is because the polarity of the piezoresistive coefficient differs between the N-type diffusion resistance and the P-type diffusion resistance, so only the magnitude of the piezoresistive coefficient can be changed by the method of changing the direction of the current flowing through the resistance element as in this embodiment.
  • a P-type diffusion resistor is used for both the resistance elements 5 and 6.
  • FIGS. 9 to 11 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment
  • FIG. 10 is a layout diagram of the N-type diffusion resistance elements 1 and 2 on the semiconductor chip
  • FIG. 11 is energization of the current of the N-type diffusion resistance element. It is a figure which shows the relationship between the angle ⁇ of a direction and a ⁇ 110> direction, and a piezo resistance coefficient.
  • the chip temperature sensor of the semiconductor chip of this embodiment is arranged by shifting the longitudinal direction of the N-type diffusion resistance element 1 from the crystal axis direction of ⁇ 110> by an angle of ⁇ p2, and N-type diffusion resistance.
  • the longitudinal direction of the element 2 is different from that of the chip temperature sensor of the semiconductor chip of the first embodiment in that the element 2 is arranged so as to be offset by an angle of ⁇ p1 from the crystal axis direction of ⁇ 110>.
  • other configurations such as the connection relationship between the N-type diffusion resistance element 1, the N-type diffusion resistance element 2, and the amplifier 3 are basically the same as those in the first embodiment.
  • the resistance values of the N-type diffusion resistance elements 1 and 2 change by the same amount, so that the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 4, the measurement error of the chip temperature can be eliminated.
  • the angle ⁇ p2 between the current energizing direction of the N-type diffusion resistance element 1, which is the resistance element having the higher impurity concentration, and the ⁇ 110> direction, which is the direction in which the piezoresistive coefficient is minimized, is the resistance having the lower impurity concentration.
  • the chip temperature sensor of the semiconductor chip of this embodiment is a first resistance element (N-type diffusion resistance element 1) having a first impurity concentration on the same semiconductor chip 4. And a second resistance element (N-type diffusion resistance element 2) connected in series to the first resistance element (N-type diffusion resistance element 1) and having a second impurity concentration different from the first impurity concentration.
  • the first impurity concentration is formed to be higher than the second impurity concentration.
  • the angle formed between the current energizing direction of the first resistance element (N-type diffusion resistance element 1) and the ⁇ 110> direction of the semiconductor chip 4. ( ⁇ p2) is configured to be larger than the angle ( ⁇ p1) formed between the current energizing direction of the second resistance element (N-type diffusion resistance element 2) and the ⁇ 110> direction of the semiconductor chip 4.
  • the current energizing direction of the N-type diffusion resistance element 1 is shifted by the angle of ⁇ p2 from the crystal axis direction of ⁇ 110>, and the current energization direction of the N-type diffusion resistance element 2 is ⁇ 110>.
  • > Is arranged so as to be offset by an angle of ⁇ p1 from the crystal axis direction, but the effect of mounting stress can be reduced by reducing the piezo resistance coefficient itself of each of the N-type diffusion resistance elements 1 and 2, so N-type diffusion It is more preferable that the current energizing direction of the resistance element 2 is the crystal axis direction of ⁇ 110>.
  • the current energizing direction of the P-type diffusion resistance element should be the crystal axis direction of ⁇ 100>.
  • FIG. 12 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment
  • FIG. 13 is a layout diagram of the N-type diffusion resistance elements 9, 10, 11, and 12 on the semiconductor chip.
  • the chip temperature sensor of the semiconductor chip of this embodiment has N-type diffusion resistance elements 9 and 10 instead of the N-type diffusion resistance element 1 of Example 1 (FIGS. 1 and 2). Is arranged, and N-type diffusion resistance elements 11 and 12 are arranged instead of the N-type diffusion resistance element 2, which is different from the chip temperature sensor of the semiconductor chip of the first embodiment.
  • One end of the N-type diffusion resistance element 9 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 10.
  • One end of the N-type diffusion resistance element 10 is connected to the N-type diffusion resistance element 9, and the other end is connected to the N-type diffusion resistance element 11.
  • One end of the N-type diffusion resistance element 11 is connected to the N-type diffusion resistance element 10, and the other end is connected to the N-type diffusion resistance element 12.
  • One end of the N-type diffusion resistance element 12 is connected to the ground, and the other end is connected to the N-type diffusion resistance element 11.
  • the other configurations such as the point that the amplifier 3 is connected to the connection point between the N-type diffusion resistance element 10 and the N-type diffusion resistance element 11, are basically the same as those in the first embodiment.
  • the N-type diffusion resistance elements 9 and 10 are arranged in place of the N-type diffusion resistance element 1, and the longitudinal direction of the N-type diffusion resistance element 10 is set to the crystal axis direction of ⁇ 110>.
  • the N-type diffusion resistance element 9 is arranged so as to be offset by the angle of ⁇ p from, and the N-type diffusion resistance element 9 is arranged so as to be displaced by the angle of ⁇ p from the crystal axis direction of ⁇ 110>, which is displaced by 90 °, instead of the N-type diffusion resistance element 2.
  • the N-type diffusion resistance elements 11 and 12 are arranged, the longitudinal direction of the N-type diffusion resistance element 12 is arranged in the crystal axis direction of ⁇ 110>, and the longitudinal direction of the N-type diffusion resistance element 11 is deviated by 90 ° ⁇ 110>. It is arranged in the crystal axis direction of.
  • the second resistance element is a third resistance element (N-type diffusion resistance element 11) and a fourth resistance element (N-type diffusion resistance element 12). It is configured by series connection, and the current energizing direction of the third resistance element (N-type diffusion resistance element 11) and the current energization direction of the fourth resistance element (N-type diffusion resistance element 12) are perpendicular to each other. It is configured to be.
  • the first resistance element is composed of a fifth resistance element (N-type diffusion resistance element 9) and a sixth resistance element (N-type diffusion resistance element 10) connected in series, and the fifth resistance element.
  • the current energizing direction of the (N-type diffusion resistance element 9) and the current energization direction of the sixth resistance element (N-type diffusion resistance element 10) are configured to be perpendicular to each other.
  • the N-type diffusion resistance elements 9, 10, 12 so that the current energization directions of the N-type diffusion resistance elements 9, 10, 11, and 12 are in the longitudinal directions of the N-type diffusion resistance elements 9, 10, 11, 12, respectively. Contacts are provided at both ends of 11 and 12 in the longitudinal direction.
  • the mounting stress is not uniform.
  • the effect of the combined stress of the N-type diffusion resistance elements 9 and 10 and the combined stress of the N-type diffusion resistance elements 11 and 12 is affected. Can be equal. This is described in detail in Patent Document 2 above.
  • the combined resistance of the N-type diffusion resistance elements 9 and 10 and the N are N, regardless of how the mounting stress works from any angle direction, even if the stress is uniformly as a tensile stress as a whole.
  • the influence of the mounting stress of the combined resistance of the type diffusion resistance elements 11 and 12 can be made equal.
  • the N-type diffusion resistance elements 9 and 10 having the higher impurity concentration are connected in series, and the currents of the N-type diffusion resistance elements 9 and 10 are arranged so as to be perpendicular to each other, and the impurity concentration is low.
  • FIG. 14 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment
  • FIG. 15 is a layout diagram of the N-type diffusion resistance elements 1, 2, 13 and 14 on the semiconductor chip.
  • the chip temperature sensor of the semiconductor chip of this embodiment has the N-type diffusion resistance elements 13 and 14 and the switching means 15 in addition to the configuration of the first embodiment (FIGS. 1 and 2). , 16 and 17 are arranged, which is different from the chip temperature sensor of the semiconductor chip of the first embodiment.
  • One end of the N-type diffusion resistance element 1 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 16.
  • One end of the N-type diffusion resistance element 13 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 15.
  • One end of the N-type diffusion resistance element 14 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 17.
  • the longitudinal direction of the N-type diffusion resistance element 13 is arranged so as to be offset by an angle of ⁇ p ⁇ from the crystal axis direction of ⁇ 110>, and the longitudinal direction of the N-type diffusion resistance element 14 is arranged. Is arranged so as to be offset by an angle of ⁇ p + ⁇ from the crystal axis direction of ⁇ 110>. Further, switching means 15, 16 and 17 are arranged to select an N-type diffusion resistance element to be connected to the N-type diffusion resistance element 2.
  • the switching means 15, 16 and 17 may have a configuration capable of switching the presence / absence of a switch, wiring, and the presence / absence of a connection such as a fuse. Further, the N-type diffusion resistance elements 1, 2, 13, 14 so that the current energization direction of the N-type diffusion resistance elements 1, 2, 13, 14 is in the longitudinal direction of the N-type diffusion resistance elements 1, 2, 13, 14, Contacts are provided at both ends of the 14 in the longitudinal direction.
  • the first resistance element is composed of a plurality of resistance elements (N-type diffusion resistance elements 1, 13, 14) having different angles in the current energizing direction. It has switching means 15, 16 and 17 for switching the connection between each of the plurality of resistance elements (N-type diffusion resistance elements 1, 13 and 14) and the second resistance element (N-type diffusion resistance element 2).
  • the N-type diffusion resistance elements 13 and 14 are provided, and the N-type diffusion resistance elements 13 and 14 are switched instead of the N-type diffusion resistance element 1 by using the switching means 15, 15 and 17. It is possible to connect to 2. As a result, even if the impurity concentrations of the N-type diffusion resistance elements 1, 2, 13 and 14 change, the current energization direction and the piezo resistance coefficient of the appropriate N-type diffusion resistance element are minimized ⁇ 110>. You will be able to select the angle with the direction.
  • the accuracy of detecting the air flow rate can be improved.
  • the flow rate measuring device is configured to include a heater resistance and an upstream temperature sensor and a downstream temperature sensor on both sides of the heater resistance on the semiconductor chip, and the upstream temperature sensor and the downstream temperature sensor are provided.
  • the temperature sensor the chip temperature sensor of the semiconductor chip described in any one of Examples 1 to 5 is used.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations.
  • it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.
  • N-type diffusion resistance element 1 ... N-type diffusion resistance element (high impurity concentration), 2 ... N-type diffusion resistance element (low impurity concentration), 3 ... amplifier, 4 ... semiconductor chip, 5 ... P-type diffusion resistance element (high impurity concentration), 6 ... P-type diffusion resistance element (low impurity concentration), 7 ... amplifier, 8 ... semiconductor chip, 9 ... N-type diffusion resistance element, 10 ... N-type diffusion resistance element, 11 ... N-type diffusion resistance element, 12 ... N-type diffusion resistance Element, 13 ... N-type diffusion resistance element, 14 ... N-type diffusion resistance element, 15 ... switching means, 16 ... switching means, 17 ... switching means.

Abstract

This invention addresses the problem of providing a chip temperature sensor that is for a semiconductor chip and is less susceptible to the influence of mounting stress.　Provided on a single semiconductor chip are a first resistance element that has a first impurity concentration and a second resistance element that is connected in series with the first resistance element and has a second impurity concentration different from the first impurity concentration. The angle between the direction in which current flows through the first resistance element and the angular direction within the chip surface of the semiconductor chip in which the piezoresistive coefficient of the semiconductor chip is minimized is larger than the angle between the direction in which current flows through the second resistance element and the angular direction within the chip surface of the semiconductor chip in which the piezoresistive coefficient of the semiconductor chip is minimized.

Description

半導体チップのチップ温度センサ、流量測定装置Semiconductor chip chip temperature sensor, flow rate measuring device
　本発明は、半導体装置の構造に係り、特に、半導体チップのチップ温度を計測するチップ温度センサに適用して有効な技術に関する。 The present invention relates to the structure of a semiconductor device, and particularly relates to a technique that is effective when applied to a chip temperature sensor that measures the chip temperature of a semiconductor chip.
　車載用エアフローセンサは、エンジンへの吸入空気の流量を測定することで、エンジンの燃料噴射量を適正化し、燃費の向上とともに、二酸化炭素（ＣＯ２）や排出ガスの低減に貢献する内燃機関の基幹部品として位置づけられている。 The in-vehicle air flow sensor measures the flow rate of intake air to the engine to optimize the fuel injection amount of the engine, improve fuel efficiency, and contribute to the reduction of carbon dioxide (CO 2) and exhaust gas. It is positioned as a key component.
　代表的なエアフローセンサとして、シリコン（Ｓｉ）などの半導体チップ上に不純物濃度を変えた抵抗温度係数の異なる２個の抵抗素子を直列接続した形で形成してチップ温度センサを構成し、ヒータ抵抗とその両隣に上流側温度センサと下流側温度センサとして２つのチップ温度センサを配置したものがある。 As a typical airflow sensor, a chip temperature sensor is formed by forming two resistance elements with different resistance temperature coefficients with different impurity concentrations on a semiconductor chip such as silicon (Si) in series to form a heater resistance. There are two chip temperature sensors arranged on both sides of it as an upstream temperature sensor and a downstream temperature sensor.
　ヒータ抵抗に電流を供給して一定温度に加熱制御し、空気への熱伝達量が空気流速に依存して両隣のチップ温度センサに分配されることを利用して空気の流量と流れの方向を求める。 A current is supplied to the heater resistor to control heating to a constant temperature, and the flow rate and flow direction of air are controlled by utilizing the fact that the amount of heat transfer to air is distributed to the chip temperature sensors on both sides depending on the air flow velocity. Ask.
　異なる抵抗温度係数を有する２個の抵抗素子を直列接続することで半導体チップのチップ温度を検出する例として、例えば、特許文献１に記載された技術がある。 As an example of detecting the chip temperature of a semiconductor chip by connecting two resistance elements having different resistance temperature coefficients in series, for example, there is a technique described in Patent Document 1.
　特許文献１では、正の温度係数を有するＮ型拡散抵抗素子と負の温度係数を有する多結晶シリコン抵抗素子を直列接続して、これらの抵抗素子の接続点の電圧がチップ温度に応じて変化することを利用して半導体チップのチップ温度を計測する。 In Patent Document 1, an N-type diffusion resistance element having a positive temperature coefficient and a polycrystalline silicon resistance element having a negative temperature coefficient are connected in series, and the voltage at the connection point of these resistance elements changes according to the chip temperature. The chip temperature of the semiconductor chip is measured by utilizing the above.
　また、特許文献２には「互いに電気的に直列に接続されたＮ型抵抗部とＰ型抵抗部とを備え、Ｎ型抵抗部は、互いに直角をなすように配置され、かつ、電気的に直列に接続された第１Ｎ型拡散層抵抗素子と第２Ｎ型拡散層抵抗素子とを有し、Ｐ型抵抗部は、互いに直角をなすように配置され、かつ、電気的に直列に接続された第１Ｐ型拡散層抵抗素子と第２Ｐ型拡散層抵抗素子とを有し、第１Ｎ型拡散層抵抗素子は＜１１０＞方向に沿って配置され、第１Ｐ型拡散層抵抗素子は＜１００＞方向に沿って配置される抵抗回路」が開示されている。 Further, Patent Document 2 states that "an N-type resistor portion and a P-type resistor portion electrically connected in series with each other are provided, and the N-type resistor portions are arranged so as to be perpendicular to each other and electrically. It has a first N-type diffusion layer resistance element and a second N-type diffusion layer resistance element connected in series, and the P-type resistance portions are arranged so as to be perpendicular to each other and are electrically connected in series. It has a first P type diffusion layer resistance element and a second P type diffusion layer resistance element, the first N type diffusion layer resistance element is arranged along the <110> direction, and the first P type diffusion layer resistance element is in the <100> direction. "Resistance circuits arranged along the line" are disclosed.
特開平５－１２１７３６号公報Japanese Unexamined Patent Publication No. 5-121736 特開２０１８－１６０５２３号公報JP-A-2018-160523
　上記特許文献１の方式では正の温度係数と負の温度係数を有する抵抗素子を使用しているため、温度に対する感度が大きくなる利点がある。 Since the method of Patent Document 1 uses a resistance element having a positive temperature coefficient and a negative temperature coefficient, there is an advantage that the sensitivity to temperature is increased.
　しかしながら、実際の半導体チップでは樹脂モールドによる実装応力や半導体チップをプリント基板に固定することによって生じる実装応力が半導体チップに働く。この実装応力により、正の温度係数を有するＮ型拡散抵抗素子は大きく抵抗値を変化させる。また、負の温度係数を有する多結晶シリコン抵抗素子もＮ型拡散抵抗素子程では無いが、実装応力により抵抗値を変化させる。 However, in an actual semiconductor chip, the mounting stress due to the resin mold and the mounting stress generated by fixing the semiconductor chip to the printed circuit board act on the semiconductor chip. Due to this mounting stress, the N-type diffusion resistance element having a positive temperature coefficient greatly changes the resistance value. Also, although the polycrystalline silicon resistance element having a negative temperature coefficient is not as high as that of the N-type diffusion resistance element, the resistance value is changed by the mounting stress.
　また、この実装応力はプリント基板の線膨張係数やモールド樹脂の線膨張係数、半導体チップの線膨張係数の差と周囲温度の変化により変化する。また、プリント基板への取り付け時に与える熱処理やモールド樹脂を成型する温度によっても変化する。更に、モールド樹脂やプリント基板が吸湿することでも変化する。 In addition, this mounting stress changes due to the difference in the coefficient of linear expansion of the printed circuit board, the coefficient of linear expansion of the molded resin, the coefficient of linear expansion of the semiconductor chip, and the change in ambient temperature. It also changes depending on the heat treatment applied at the time of mounting on the printed circuit board and the temperature at which the molding resin is molded. Further, it changes when the mold resin or the printed circuit board absorbs moisture.
　これらによって生じる実装応力の変化はＮ型拡散抵抗素子や多結晶シリコン抵抗素子の抵抗値を変化させるため、チップ温度の計測に誤差を生じさせる。つまり、上記特許文献１では半導体チップに生じる実装応力に対する配慮が欠けていた。 The change in mounting stress caused by these changes the resistance value of the N-type diffusion resistance element and the polycrystalline silicon resistance element, which causes an error in the measurement of the chip temperature. That is, Patent Document 1 lacks consideration for mounting stress generated in a semiconductor chip.
　一方、上記特許文献２は、パッケージ材料などから受ける半導体チップの応力を考慮した回路構成ではあるが、半導体チップが応力を受けた際にＮ型抵抗部とＰ型抵抗部のそれぞれの抵抗値の変化量が必ずしも等しくなるとは限らず、チップ温度の計測に誤差を生じさせる可能性がある。 On the other hand, Patent Document 2 has a circuit configuration in consideration of the stress of the semiconductor chip received from the package material or the like, but the resistance values of the N-type resistor portion and the P-type resistor portion when the semiconductor chip is stressed. The amount of change is not always equal, which may cause an error in the measurement of chip temperature.
　そこで、本発明の目的は、実装応力の影響が小さい半導体チップのチップ温度センサを提供することにある。 Therefore, an object of the present invention is to provide a chip temperature sensor for a semiconductor chip, which is less affected by mounting stress.
　上記課題を解決するために、本発明は、同一の半導体チップに、第１の不純物濃度を有する第１の抵抗素子と、前記第１の抵抗素子に直列接続され、前記第１の不純物濃度と異なる第２の不純物濃度を有する第２の抵抗素子と、を備え、前記第１の抵抗素子の電流の通電方向と前記半導体チップのピエゾ抵抗係数が極小となる前記半導体チップのチップ表面内の角度方向との角度が、前記第２の抵抗素子の電流の通電方向と前記半導体チップのピエゾ抵抗係数が極小となる前記半導体チップのチップ表面内の角度方向との角度よりも大きいことを特徴とする。 In order to solve the above problems, the present invention relates to the same semiconductor chip with a first resistance element having a first impurity concentration and a first resistance element connected in series to the first impurity concentration. A second resistance element having a different second impurity concentration, and an angle in the chip surface of the semiconductor chip in which the current energization direction of the first resistance element and the piezo resistance coefficient of the semiconductor chip are minimized. The angle with the direction is larger than the angle between the current energizing direction of the second resistance element and the angular direction in the chip surface of the semiconductor chip at which the piezo resistance coefficient of the semiconductor chip is minimized. ..
　また、本発明は、半導体チップ上に、ヒータ抵抗と、前記ヒータ抵抗の両隣に上流側温度センサと下流側温度センサと、を備える流量測定装置であって、前記上流側温度センサ及び前記下流側温度センサは、上記の半導体チップのチップ温度センサであることを特徴とする。 Further, the present invention is a flow rate measuring device including a heater resistance and an upstream temperature sensor and a downstream temperature sensor on both sides of the heater resistance on a semiconductor chip, wherein the upstream temperature sensor and the downstream temperature sensor are provided. The temperature sensor is a chip temperature sensor of the above-mentioned semiconductor chip.
　本発明によれば、実装応力の影響が小さい半導体チップのチップ温度センサを提供することが可能となる。 According to the present invention, it is possible to provide a chip temperature sensor for a semiconductor chip that is less affected by mounting stress.
　これにより、半導体チップのチップ温度センサ、及びそれを用いた流量測定装置（エアフローセンサ）の検出精度の向上が図れる。 As a result, the detection accuracy of the chip temperature sensor of the semiconductor chip and the flow rate measuring device (air flow sensor) using the sensor can be improved.
　上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。 Issues, configurations and effects other than those described above will be clarified by the explanation of the following embodiments.
本発明の実施例１の半導体チップのチップ温度センサの回路図である。It is a circuit diagram of the chip temperature sensor of the semiconductor chip of Example 1 of this invention. 図１のＮ型拡散抵抗素子１，２の半導体チップ上の配置を示す図である。It is a figure which shows the arrangement on the semiconductor chip of the N-type diffusion resistance elements 1 and 2 of FIG. 不純物濃度と抵抗温度係数の関係を示す図である。It is a figure which shows the relationship between the impurity concentration and the temperature coefficient of resistance. 不純物濃度とピエゾ抵抗係数の関係を示す図である。It is a figure which shows the relationship between the impurity concentration and the piezoresistive coefficient. Ｎ型拡散抵抗素子の電流の通電方向と＜１１０＞方向との角度θとピエゾ抵抗係数の関係を示す図である。It is a figure which shows the relationship between the angle θ and the piezoresistive coefficient between the current energization direction of the N-type diffusion resistance element, and the <110> direction. 本発明の実施例２の半導体チップのチップ温度センサの回路図である。It is a circuit diagram of the chip temperature sensor of the semiconductor chip of Example 2 of this invention. 図６のＰ型拡散抵抗素子５，６の半導体チップ上の配置を示す図である。It is a figure which shows the arrangement on the semiconductor chip of the P-type diffusion resistance elements 5 and 6 of FIG. Ｐ型拡散抵抗素子の電流の通電方向と＜１００＞方向との角度θとピエゾ抵抗係数の関係を示す図である。It is a figure which shows the relationship between the angle θ and the piezoresistive coefficient between the current energization direction of a P-type diffusion resistance element, and the <100> direction. 本発明の実施例３の半導体チップのチップ温度センサの回路図である。It is a circuit diagram of the chip temperature sensor of the semiconductor chip of Example 3 of this invention. 図９のＮ型拡散抵抗素子１，２の半導体チップ上の配置を示す図である。9 is a diagram showing the arrangement of the N-type diffusion resistance elements 1 and 2 in FIG. 9 on a semiconductor chip. Ｎ型拡散抵抗素子の電流の通電方向と＜１１０＞方向との角度θとピエゾ抵抗係数の関係を示す図である。It is a figure which shows the relationship between the angle θ and the piezoresistive coefficient of the current energization direction of an N type diffusion resistance element, and the <110> direction. 本発明の実施例４の半導体チップのチップ温度センサの回路図である。It is a circuit diagram of the chip temperature sensor of the semiconductor chip of Example 4 of this invention. 図１２のＮ型拡散抵抗素子９，１０，１１，１２の半導体チップ上の配置を示す図である。It is a figure which shows the arrangement on the semiconductor chip of the N-type diffusion resistance element 9, 10, 11, 12 of FIG. 本発明の実施例５の半導体チップのチップ温度センサの回路図である。It is a circuit diagram of the chip temperature sensor of the semiconductor chip of Example 5 of this invention. 図１４のＮ型拡散抵抗素子１，２、１３，１４の半導体チップ上の配置を示す図である。It is a figure which shows the arrangement on the semiconductor chip of the N-type diffusion resistance element 1, 2, 13, 14 of FIG.
　以下、図面を用いて本発明の実施例を説明する。なお、各図面において同一の構成については同一の符号を付し、重複する部分についてはその詳細な説明は省略する。 Hereinafter, examples of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of overlapping portions will be omitted.
　先ず、図１から図５を参照して、本発明の第１の実施例である半導体チップのチップ温度センサについて説明する。なお、図１は本実施例の半導体チップのチップ温度センサの回路図、図２はＮ型拡散抵抗素子１，２の半導体チップ上の配置図、図３は不純物濃度と抵抗温度係数の関係を示す図、図４は不純物濃度とピエゾ抵抗係数の関係を示す図、図５はＮ型拡散抵抗素子の電流の通電方向と＜１１０＞方向との角度θとピエゾ抵抗係数の関係を示す図である。 First, the chip temperature sensor of the semiconductor chip, which is the first embodiment of the present invention, will be described with reference to FIGS. 1 to 5. FIG. 1 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment, FIG. 2 is a layout diagram of the N-type diffusion resistance elements 1 and 2 on the semiconductor chip, and FIG. 3 is a relationship between the impurity concentration and the temperature coefficient of resistance. FIG. 4 is a diagram showing the relationship between the impurity concentration and the piezo resistance coefficient, and FIG. 5 is a diagram showing the relationship between the angle θ between the current energizing direction of the N-type diffusion resistance element and the <110> direction and the piezo resistance coefficient. is there.
　本実施例の半導体チップのチップ温度センサは、図１に示すように、不純物濃度の高いＮ型拡散抵抗素子１と、不純物濃度の低いＮ型拡散抵抗素子２と、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２の接続点の電圧を増幅する増幅器３により構成される。Ｎ型拡散抵抗素子１は、一端が電源電圧Ｖｃｃに接続され、他端がＮ型拡散抵抗素子２に接続されている。Ｎ型拡散抵抗素子２は、一端がグランドに接続され、他端がＮ型拡散抵抗素子１に接続されている。 As shown in FIG. 1, the chip temperature sensor of the semiconductor chip of this embodiment includes an N-type diffusion resistance element 1 having a high impurity concentration, an N-type diffusion resistance element 2 having a low impurity concentration, and an N-type diffusion resistance element 1. It is composed of an amplifier 3 that amplifies the voltage at the connection point of the N-type diffusion resistance element 2. One end of the N-type diffusion resistance element 1 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2. One end of the N-type diffusion resistance element 2 is connected to the ground, and the other end is connected to the N-type diffusion resistance element 1.
　また、図２に示すように、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２はシリコン（Ｓｉ）からなる同一の半導体チップ４に配置され、Ｎ型拡散抵抗素子１の長手方向を＜１１０＞の結晶軸方向からθｐの角度だけずらして配置し、Ｎ型拡散抵抗素子２の長手方向は＜１１０＞の結晶軸方向に配置している。 Further, as shown in FIG. 2, the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 are arranged on the same semiconductor chip 4 made of silicon (Si), and the longitudinal direction of the N-type diffusion resistance element 1 is <110. The N-type diffusion resistance element 2 is arranged so as to be offset by an angle of θp from the crystal axis direction of <110>, and the longitudinal direction of the N-type diffusion resistance element 2 is arranged in the crystal axis direction of <110>.
　なお、図示していないが、Ｎ型拡散抵抗素子１，２の電流の通電方向は、それぞれＮ型拡散抵抗素子１，２の長手方向になるようにＮ型拡散抵抗素子１，２の長手方向の両端にコンタクトを設けている。また、Ｎ型拡散抵抗素子１，２ではピエゾ抵抗係数が極小となる半導体チップ４のチップ表面内の角度方向は＜１１０＞になる。 Although not shown, the current energizing direction of the N-type diffusion resistance elements 1 and 2 is the longitudinal direction of the N-type diffusion resistance elements 1 and 2 so as to be the longitudinal direction of the N-type diffusion resistance elements 1 and 2, respectively. There are contacts on both ends of the. Further, in the N-type diffusion resistance elements 1 and 2, the angular direction in the chip surface of the semiconductor chip 4 in which the piezoresistive coefficient is extremely small is <110>.
　また、半導体チップ４を構成するシリコンの結晶構造は単純立方晶なので［１１０］、［１０１］、［０１１］などは等価であるため、これらを＜１１０＞と記載した。 Further, since the crystal structure of silicon constituting the semiconductor chip 4 is a simple cubic crystal, [110], [101], [011] and the like are equivalent, so these are described as <110>.
　次に、本実施例のチップ温度検出の動作について説明する。図３に示すように、拡散抵抗素子の抵抗温度係数は不純物濃度に応じて変化するので、不純物濃度の高いＮ型拡散抵抗素子１と不純物濃度の低いＮ型拡散抵抗素子２とでは抵抗温度係数が異なり、不純物濃度の高いＮ型拡散抵抗素子１の抵抗温度係数は小さく、不純物濃度の低いＮ型拡散抵抗素子２の抵抗温度係数は大きくなる。 Next, the operation of chip temperature detection in this embodiment will be described. As shown in FIG. 3, since the temperature coefficient of resistance of the diffusion resistance element changes according to the concentration of impurities, the temperature coefficient of resistance between the N-type diffusion resistance element 1 having a high impurity concentration and the N-type diffusion resistance element 2 having a low impurity concentration However, the temperature coefficient of resistance of the N-type diffusion resistance element 1 having a high impurity concentration is small, and the temperature coefficient of resistance of the N-type diffusion resistance element 2 having a low impurity concentration is large.
　ここで、半導体チップ４のチップ温度が変化すると、Ｎ型拡散抵抗素子１の抵抗値の変化よりも、Ｎ型拡散抵抗素子２の抵抗値の変化の方が大きくなる。この結果、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２の接続点の電圧は半導体チップ４のチップ温度に応じて変化するので、この電圧を増幅器３で増幅することで半導体チップ４のチップ温度に応じた出力電圧Ｖｏｕｔを得ることができる。 Here, when the chip temperature of the semiconductor chip 4 changes, the change in the resistance value of the N-type diffusion resistance element 2 becomes larger than the change in the resistance value of the N-type diffusion resistance element 1. As a result, the voltage at the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 changes according to the chip temperature of the semiconductor chip 4. Therefore, by amplifying this voltage with the amplifier 3, the chip of the semiconductor chip 4 An output voltage Vout corresponding to the temperature can be obtained.
　次に、本実施例の実装応力影響について説明する。図４に示すように、拡散抵抗素子のピエゾ抵抗係数は不純物濃度に応じて変化し、不純物濃度の高いＮ型拡散抵抗素子１と不純物濃度の低いＮ型拡散抵抗素子２とではピエゾ抵抗係数が異なり、不純物濃度の高いＮ型拡散抵抗素子１のピエゾ抵抗係数は小さく、不純物濃度の低いＮ型拡散抵抗素子２のピエゾ抵抗係数は大きくなる。 Next, the effect of mounting stress in this embodiment will be described. As shown in FIG. 4, the piezoresistive coefficient of the diffusion resistance element changes according to the impurity concentration, and the piezoresistive coefficient is different between the N-type diffusion resistance element 1 having a high impurity concentration and the N-type diffusion resistance element 2 having a low impurity concentration. Unlike this, the N-type diffusion resistance element 1 having a high impurity concentration has a small piezoresistive coefficient, and the N-type diffusion resistance element 2 having a low impurity concentration has a large piezoresistive coefficient.
　この結果、半導体チップ４に実装応力が働くと、Ｎ型拡散抵抗素子１の抵抗値の変化よりも、Ｎ型拡散抵抗素子２の抵抗値の方が大きく変化し、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２の接続点の電圧が変化する。このことでチップ温度の計測に誤差を生じさせる。 As a result, when the mounting stress acts on the semiconductor chip 4, the resistance value of the N-type diffusion resistance element 2 changes more than the change of the resistance value of the N-type diffusion resistance element 1, and the N-type diffusion resistance element 1 and the N-type diffusion resistance element 1 change. The voltage at the connection point of the N-type diffusion resistance element 2 changes. This causes an error in the measurement of the chip temperature.
　Ｎ型拡散抵抗素子の場合、図５に示すように、ピエゾ抵抗係数は不純物濃度と電流の通電方向と＜１１０＞方向との角度θに応じて変化する。そこで、異なる不純物濃度のＮ型拡散抵抗素子１，２であっても角度θを適切に選択することでＮ型拡散抵抗素子１，２のピエゾ抵抗係数を等しくできる。 In the case of an N-type diffusion resistance element, as shown in FIG. 5, the piezoresistive coefficient changes according to the impurity concentration, the current energization direction, and the angle θ between the <110> direction. Therefore, even if the N-type diffusion resistance elements 1 and 2 have different impurity concentrations, the piezoresistive coefficients of the N-type diffusion resistance elements 1 and 2 can be made equal by appropriately selecting the angle θ.
　本実施例においては、Ｎ型拡散抵抗素子１の電流の通電方向と＜１１０＞方向との角度θをθｐに設定し、Ｎ型拡散抵抗素子２の電流の通電方向と＜１１０＞方向との角度θをゼロに設定することでＮ型拡散抵抗素子１とＮ型拡散抵抗素子２のピエゾ抵抗係数を等しくしている。 In this embodiment, the angle θ between the current energizing direction of the N-type diffusion resistance element 1 and the <110> direction is set to θp, and the current energization direction and the <110> direction of the N-type diffusion resistance element 2 are set. By setting the angle θ to zero, the piezo resistance coefficients of the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 are made equal.
　こうすることで、半導体チップ４に実装応力が働いたとしてもＮ型拡散抵抗素子１，２の抵抗値は同じだけ変化するので、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２の接続点の電圧は変化しない。つまり、半導体チップ４に実装応力が働いたとしてもチップ温度の計測誤差を無くすことができる。 By doing so, even if the mounting stress acts on the semiconductor chip 4, the resistance values of the N-type diffusion resistance elements 1 and 2 change by the same amount, so that the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 4, the measurement error of the chip temperature can be eliminated.
　なお、Ｎ型拡散抵抗素子のピエゾ抵抗係数が極小になる電流の通電方向は図５からも明らかなように９０°毎に存在するが、これらは全て＜１１０＞方向なので、Ｎ型拡散抵抗素子１，２の電流の通電方向を９０°、１８０°２７０°回転させても実装応力が一様（全方向に引っ張りあるいは圧縮の応力が掛かった状態）である場合は等価である。 As is clear from FIG. 5, the current energizing direction in which the piezoresistive coefficient of the N-type diffusion resistance element is minimized exists every 90 °, but since these are all in the <110> direction, the N-type diffusion resistance element Even if the current-carrying directions of the currents 1 and 2 are rotated by 90 ° and 180 ° 270 °, they are equivalent when the mounting stress is uniform (a state in which tensile or compressive stress is applied in all directions).
　また、本実施例では、Ｎ型拡散抵抗素子１，２には共にＮ型拡散抵抗を用いて説明した。これはＮ型拡散抵抗とＰ型拡散抵抗ではピエゾ抵抗係数の極性が異なるので本実施例のように抵抗素子に流れる電流方向を変える方法ではピエゾ抵抗係数の大きさしか変更できないため、Ｎ型拡散抵抗素子１，２には共にＮ型拡散抵抗を用いている。 Further, in this embodiment, N-type diffusion resistors are used for both the N-type diffusion resistance elements 1 and 2. This is because the polarity of the piezoresistive coefficient differs between the N-type diffusion resistance and the P-type diffusion resistance, so only the magnitude of the piezoresistive coefficient can be changed by the method of changing the direction of the current flowing through the resistance element as in this embodiment. N-type diffusion resistors are used for both the resistance elements 1 and 2.
　次に、図６から図８を参照して、本発明の第２の実施例である半導体チップのチップ温度センサについて説明する。なお、図６は本実施例の半導体チップのチップ温度センサの回路図、図７はＰ型拡散抵抗素子５，６の半導体チップ上の配置図、図８はＰ型拡散抵抗素子の電流の通電方向と＜１００＞方向との角度θとピエゾ抵抗係数の関係を示す図である。 Next, the chip temperature sensor of the semiconductor chip, which is the second embodiment of the present invention, will be described with reference to FIGS. 6 to 8. FIG. 6 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment, FIG. 7 is a layout diagram of the P-type diffusion resistance elements 5 and 6 on the semiconductor chip, and FIG. 8 is energization of the current of the P-type diffusion resistance element. It is a figure which shows the relationship between the angle θ of a direction and a <100> direction, and a piezo resistance coefficient.
　本実施例の半導体チップのチップ温度センサは、図６に示すように、不純物濃度の高いＰ型拡散抵抗素子５と、不純物濃度の低いＰ型拡散抵抗素子６と、Ｐ型拡散抵抗素子５とＰ型拡散抵抗素子６の接続点の電圧を増幅する増幅器７により構成される。Ｐ型拡散抵抗素子５は、一端が電源電圧Ｖｃｃに接続され、他端がＰ型拡散抵抗素子６に接続されている。Ｐ型拡散抵抗素子６は、一端がグランドに接続され、他端がＰ型拡散抵抗素子５に接続されている。 As shown in FIG. 6, the chip temperature sensor of the semiconductor chip of this embodiment includes a P-type diffusion resistance element 5 having a high impurity concentration, a P-type diffusion resistance element 6 having a low impurity concentration, and a P-type diffusion resistance element 5. It is composed of an amplifier 7 that amplifies the voltage at the connection point of the P-type diffusion resistance element 6. One end of the P-type diffusion resistance element 5 is connected to the power supply voltage Vcc, and the other end is connected to the P-type diffusion resistance element 6. One end of the P-type diffusion resistance element 6 is connected to the ground, and the other end is connected to the P-type diffusion resistance element 5.
　また、図７に示すように、Ｐ型拡散抵抗素子５とＰ型拡散抵抗素子６はシリコン（Ｓｉ）からなる同一の半導体チップ８に配置され、Ｐ型拡散抵抗素子５の長手方向を＜１００＞の結晶軸方向からθｐの角度だけずらして配置し、Ｐ型拡散抵抗素子６の長手方向は＜１００＞の結晶軸方向に配置している。 Further, as shown in FIG. 7, the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 are arranged on the same semiconductor chip 8 made of silicon (Si), and the longitudinal direction of the P-type diffusion resistance element 5 is <100. The P-type diffusion resistance element 6 is arranged so as to be offset by an angle of θp from the crystal axis direction of <100>, and the longitudinal direction of the P-type diffusion resistance element 6 is arranged in the crystal axis direction of <100>.
　なお、図示していないが、Ｐ型拡散抵抗素子５，６の電流の通電方向は、それぞれＰ型拡散抵抗素子５，６の長手方向になるようにＰ型拡散抵抗素子５，６の長手方向の両端にコンタクトを設けている。また、Ｐ型拡散抵抗素子５，６ではピエゾ抵抗係数が極小となる半導体チップ８のチップ表面内の角度方向は＜１００＞になる。 Although not shown, the current energizing direction of the P-type diffusion resistance elements 5 and 6 is the longitudinal direction of the P-type diffusion resistance elements 5 and 6 so as to be the longitudinal direction of the P-type diffusion resistance elements 5 and 6, respectively. There are contacts on both ends of the. Further, in the P-type diffusion resistance elements 5 and 6, the angular direction in the chip surface of the semiconductor chip 8 in which the piezoresistive coefficient is extremely small is <100>.
　また、半導体チップ８を構成するシリコンの結晶構造は単純立方晶なので［１００］、［０１０］、［００１］などは等価であるため、これらは＜１００＞と記載した。 Further, since the crystal structure of silicon constituting the semiconductor chip 8 is a simple cubic crystal, [100], [010], [001], etc. are equivalent, so these are described as <100>.
　次に、本実施例のチップ温度検出の動作について説明する。図３に示すように、Ｐ型拡散抵抗素子でも抵抗温度係数は不純物濃度に応じて変化するので、不純物濃度の高いＰ型拡散抵抗素子５と不純物濃度の低いＰ型拡散抵抗素子６とでは抵抗温度係数が異なり、不純物濃度の高いＰ型拡散抵抗素子５の抵抗温度係数は小さく、不純物濃度の低いＰ型拡散抵抗素子６の抵抗温度係数は大きくなる。 Next, the operation of chip temperature detection in this embodiment will be described. As shown in FIG. 3, since the temperature coefficient of resistance of a P-type diffusion resistance element changes according to the impurity concentration, the resistance between the P-type diffusion resistance element 5 having a high impurity concentration and the P-type diffusion resistance element 6 having a low impurity concentration The temperature coefficient is different, the resistance temperature coefficient of the P-type diffusion resistance element 5 having a high impurity concentration is small, and the resistance temperature coefficient of the P-type diffusion resistance element 6 having a low impurity concentration is large.
　ここで、半導体チップ８のチップ温度が変化すると、Ｐ型拡散抵抗素子５の抵抗値の変化よりも、Ｐ型拡散抵抗素子６の抵抗値の変化の方が大きくなる。この結果、Ｐ型拡散抵抗素子５とＰ型拡散抵抗素子６の接続点の電圧は半導体チップ８のチップ温度に応じて変化するので、この電圧を増幅器７で増幅することで半導体チップ８のチップ温度に応じた出力電圧Ｖｏｕｔを得ることができる。 Here, when the chip temperature of the semiconductor chip 8 changes, the change in the resistance value of the P-type diffusion resistance element 6 becomes larger than the change in the resistance value of the P-type diffusion resistance element 5. As a result, the voltage at the connection point between the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 changes according to the chip temperature of the semiconductor chip 8. Therefore, by amplifying this voltage with the amplifier 7, the chip of the semiconductor chip 8 is used. An output voltage Vout corresponding to the temperature can be obtained.
　次に、本実施例の実装応力影響について説明する。図４に示すように、Ｐ型拡散抵抗素子でもピエゾ抵抗係数は不純物濃度に応じて変化するので、不純物濃度の高いＰ型拡散抵抗素子５と不純物濃度の低いＰ型拡散抵抗素子６とではピエゾ抵抗係数が異なり、不純物濃度の高いＰ型拡散抵抗素子５のピエゾ抵抗係数は小さく、不純物濃度の低いＰ型拡散抵抗素子６のピエゾ抵抗係数は大きくなる。 Next, the effect of mounting stress in this embodiment will be described. As shown in FIG. 4, since the piezoresistive coefficient of a P-type diffusion resistance element changes according to the impurity concentration, the piezoresistive effect of the P-type diffusion resistance element 5 having a high impurity concentration and the P-type diffusion resistance element 6 having a low impurity concentration The resistance coefficient is different, the piezoresistive coefficient of the P-type diffusion resistance element 5 having a high impurity concentration is small, and the piezoresistive coefficient of the P-type diffusion resistance element 6 having a low impurity concentration is large.
　この結果、半導体チップ８に実装応力が働くと、Ｐ型拡散抵抗素子５の抵抗値の変化よりも、Ｐ型拡散抵抗素子６の抵抗値の方が大きく変化し、Ｐ型拡散抵抗素子５とＰ型拡散抵抗素子６の接続点の電圧が変化する。このことでチップ温度の計測に誤差を生じさせる。 As a result, when the mounting stress acts on the semiconductor chip 8, the resistance value of the P-type diffusion resistance element 6 changes more than the change of the resistance value of the P-type diffusion resistance element 5, and the P-type diffusion resistance element 5 and the P-type diffusion resistance element 5 change. The voltage at the connection point of the P-type diffusion resistance element 6 changes. This causes an error in the measurement of the chip temperature.
　Ｐ型拡散抵抗素子の場合、図８に示すように、ピエゾ抵抗係数は不純物濃度と電流の通電方向と＜１００＞方向との角度θに応じて変化する。そこで、異なる不純物濃度のＰ型拡散抵抗素子５，６であっても角度θを適切に選択することでＰ型拡散抵抗素子５，６のピエゾ抵抗係数を等しくできる。 In the case of the P-type diffusion resistance element, as shown in FIG. 8, the piezoresistive coefficient changes according to the impurity concentration, the current energization direction, and the angle θ between the <100> direction. Therefore, even if the P-type diffusion resistance elements 5 and 6 have different impurity concentrations, the piezoresistive coefficients of the P-type diffusion resistance elements 5 and 6 can be made equal by appropriately selecting the angle θ.
　本実施例においては、Ｐ型拡散抵抗素子５の電流の通電方向と＜１００＞方向との角度θをθｐに設定し、Ｐ型拡散抵抗素子６の電流の通電方向と＜１００＞方向との角度θをゼロに設定することでＰ型拡散抵抗素子５とＰ型拡散抵抗素子６のピエゾ抵抗係数を等しくしている。 In this embodiment, the angle θ between the current energizing direction of the P-type diffusion resistance element 5 and the <100> direction is set to θp, and the current energization direction and the <100> direction of the P-type diffusion resistance element 6 are set. By setting the angle θ to zero, the piezo resistance coefficients of the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 are made equal.
　こうすることで、半導体チップ８に実装応力が働いたとしてもＰ型拡散抵抗素子５，６の抵抗値は同じだけ変化するので、Ｐ型拡散抵抗素子５とＰ型拡散抵抗素子６の接続点の電圧は変化しない。つまり、半導体チップ８に実装応力が働いたとしてもチップ温度の計測誤差を無くすことができる。 By doing so, even if the mounting stress acts on the semiconductor chip 8, the resistance values of the P-type diffusion resistance elements 5 and 6 change by the same amount, so that the connection point between the P-type diffusion resistance element 5 and the P-type diffusion resistance element 6 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 8, it is possible to eliminate the measurement error of the chip temperature.
　本実施例の半導体チップのチップ温度センサは、言い換えると、第１の抵抗素子（Ｐ型拡散抵抗素子５）および第２の抵抗素子（Ｐ型拡散抵抗素子６）は、共にＰ型拡散抵抗素子であり、第１の抵抗素子（Ｐ型拡散抵抗素子５）の電流の通電方向と半導体チップ８の＜１００＞方向との間に成す角度（θｐ）が、第２の抵抗素子（Ｐ型拡散抵抗素子６）の電流の通電方向と半導体チップ８の＜１００＞方向との間に成す角度よりも大きくなるように構成されている。 In other words, in the chip temperature sensor of the semiconductor chip of this embodiment, the first resistance element (P-type diffusion resistance element 5) and the second resistance element (P-type diffusion resistance element 6) are both P-type diffusion resistance elements. The angle (θp) formed between the current energizing direction of the first resistance element (P-type diffusion resistance element 5) and the <100> direction of the semiconductor chip 8 is the second resistance element (P-type diffusion). It is configured to be larger than the angle formed between the current energizing direction of the resistance element 6) and the <100> direction of the semiconductor chip 8.
　また、第２の抵抗素子（Ｐ型拡散抵抗素子６）の電流の通電方向と半導体チップ８のピエゾ抵抗係数が極小となる半導体チップ８のチップ表面内の角度方向との角度が等しくなるように構成されている。 Further, the angle between the current energizing direction of the second resistance element (P-type diffusion resistance element 6) and the angular direction in the chip surface of the semiconductor chip 8 in which the piezo resistance coefficient of the semiconductor chip 8 is minimized is equal. It is configured.
　なお、Ｐ型拡散抵抗素子のピエゾ抵抗係数が極小になる電流の通電方向は図８からも明らかなように９０°毎に存在するが、これらは全て＜１００＞方向なので、Ｐ型拡散抵抗素子５，６の電流の通電方向を９０°、１８０°２７０°回転させても実装応力が一様（全方向に引っ張りあるいは圧縮の応力が掛かった状態）である場合は等価である。 As is clear from FIG. 8, the current energizing direction in which the piezoresistive coefficient of the P-type diffusion resistance element is minimized exists every 90 °, but since these are all in the <100> direction, the P-type diffusion resistance element Even if the current energization directions of 5 and 6 are rotated by 90 ° and 180 ° 270 °, they are equivalent when the mounting stress is uniform (a state in which tensile or compressive stress is applied in all directions).
　また、本実施例では、Ｐ型拡散抵抗素子５，６には共にＰ型拡散抵抗を用いて説明した。これはＮ型拡散抵抗とＰ型拡散抵抗ではピエゾ抵抗係数の極性が異なるので本実施例のように抵抗素子に流れる電流方向を変える方法ではピエゾ抵抗係数の大きさしか変更できないため、Ｐ型拡散抵抗素子５，６には共にＰ型拡散抵抗を用いている。 Further, in this embodiment, the P-type diffusion resistance elements 5 and 6 are both described using the P-type diffusion resistance. This is because the polarity of the piezoresistive coefficient differs between the N-type diffusion resistance and the P-type diffusion resistance, so only the magnitude of the piezoresistive coefficient can be changed by the method of changing the direction of the current flowing through the resistance element as in this embodiment. A P-type diffusion resistor is used for both the resistance elements 5 and 6.
　次に、図９から図１１を参照して、本発明の第３の実施例である半導体チップのチップ温度センサについて説明する。なお、図９は本実施例の半導体チップのチップ温度センサの回路図、図１０はＮ型拡散抵抗素子１，２の半導体チップ上の配置図、図１１はＮ型拡散抵抗素子の電流の通電方向と＜１１０＞方向との角度θとピエゾ抵抗係数の関係を示す図である。 Next, the chip temperature sensor of the semiconductor chip, which is the third embodiment of the present invention, will be described with reference to FIGS. 9 to 11. 9 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment, FIG. 10 is a layout diagram of the N-type diffusion resistance elements 1 and 2 on the semiconductor chip, and FIG. 11 is energization of the current of the N-type diffusion resistance element. It is a figure which shows the relationship between the angle θ of a direction and a <110> direction, and a piezo resistance coefficient.
　本実施例の半導体チップのチップ温度センサは、図１０に示すように、Ｎ型拡散抵抗素子１の長手方向を＜１１０＞の結晶軸方向からθｐ２の角度だけずらして配置し、Ｎ型拡散抵抗素子２の長手方向は＜１１０＞の結晶軸方向からθｐ１の角度だけずらして配置している点において、実施例１の半導体チップのチップ温度センサとは異なる。図９に示すように、Ｎ型拡散抵抗素子１やＮ型拡散抵抗素子２、増幅器３の接続関係など、その他の構成は、基本的に実施例１と同様である。 As shown in FIG. 10, the chip temperature sensor of the semiconductor chip of this embodiment is arranged by shifting the longitudinal direction of the N-type diffusion resistance element 1 from the crystal axis direction of <110> by an angle of θp2, and N-type diffusion resistance. The longitudinal direction of the element 2 is different from that of the chip temperature sensor of the semiconductor chip of the first embodiment in that the element 2 is arranged so as to be offset by an angle of θp1 from the crystal axis direction of <110>. As shown in FIG. 9, other configurations such as the connection relationship between the N-type diffusion resistance element 1, the N-type diffusion resistance element 2, and the amplifier 3 are basically the same as those in the first embodiment.
　＜１１０＞の結晶軸方向に対し、Ｎ型拡散抵抗素子１の長手方向及びＮ型拡散抵抗素子２の長手方向を、それぞれθｐ２，θｐ１の角度だけずらして配置することで、図１１に示すように不純物濃度の異なるＮ型拡散抵抗素子１，２のピエゾ抵抗係数を等しくしている。 As shown in FIG. 11, by arranging the longitudinal direction of the N-type diffusion resistance element 1 and the longitudinal direction of the N-type diffusion resistance element 2 with respect to the crystal axis direction of <110> by the angles of θp2 and θp1, respectively. The piezoresistive coefficients of the N-type diffusion resistance elements 1 and 2 having different impurity concentrations are made equal to each other.
　こうすることで、半導体チップ４に実装応力が働いたとしてもＮ型拡散抵抗素子１，２の抵抗値は同じだけ変化するので、Ｎ型拡散抵抗素子１とＮ型拡散抵抗素子２の接続点の電圧は変化しない。つまり、半導体チップ４に実装応力が働いたとしてもチップ温度の計測誤差を無くすことができる。 By doing so, even if the mounting stress acts on the semiconductor chip 4, the resistance values of the N-type diffusion resistance elements 1 and 2 change by the same amount, so that the connection point between the N-type diffusion resistance element 1 and the N-type diffusion resistance element 2 Voltage does not change. That is, even if the mounting stress acts on the semiconductor chip 4, the measurement error of the chip temperature can be eliminated.
　なお、不純物濃度の高い方の抵抗素子であるＮ型拡散抵抗素子１の電流の通電方向とピエゾ抵抗係数が極小となる方向である＜１１０＞方向との角度θｐ２を不純物濃度の低い方の抵抗素子であるＮ型拡散抵抗素子２の電流の通電方向とピエゾ抵抗係数が極小となる方向である＜１１０＞方向との角度θｐ１よりも大きくすることで、Ｎ型拡散抵抗素子１，２のピエゾ抵抗係数を近づけることができ、実装応力の影響を確実に低減することができる。（θｐ２＞θｐ１）　以上説明したように、本実施例の半導体チップのチップ温度センサは、同一の半導体チップ４に、第１の不純物濃度を有する第１の抵抗素子（Ｎ型拡散抵抗素子１）と、第１の抵抗素子（Ｎ型拡散抵抗素子１）に直列接続され、第１の不純物濃度と異なる第２の不純物濃度を有する第２の抵抗素子（Ｎ型拡散抵抗素子２）と、を備えており、第１の抵抗素子（Ｎ型拡散抵抗素子１）の電流の通電方向と半導体チップ４のピエゾ抵抗係数が極小となる半導体チップ４のチップ表面内の角度方向との角度（θｐ２）が、第２の抵抗素子（Ｎ型拡散抵抗素子２）の電流の通電方向と半導体チップ４のピエゾ抵抗係数が極小となる半導体チップ４のチップ表面内の角度方向との角度（θｐ１）よりも大きくなるように構成されている。 The angle θp2 between the current energizing direction of the N-type diffusion resistance element 1, which is the resistance element having the higher impurity concentration, and the <110> direction, which is the direction in which the piezoresistive coefficient is minimized, is the resistance having the lower impurity concentration. By making the angle θp1 between the current energizing direction of the N-type diffusion resistance element 2 and the <110> direction in which the piezoresistive coefficient becomes the minimum, the piezos of the N-type diffusion resistance elements 1 and 2 are made larger than the angle θp1. The resistance coefficient can be brought close to each other, and the influence of mounting stress can be surely reduced. (Θp2> θp1) As described above, the chip temperature sensor of the semiconductor chip of this embodiment is a first resistance element (N-type diffusion resistance element 1) having a first impurity concentration on the same semiconductor chip 4. And a second resistance element (N-type diffusion resistance element 2) connected in series to the first resistance element (N-type diffusion resistance element 1) and having a second impurity concentration different from the first impurity concentration. The angle (θp2) between the current energizing direction of the first resistance element (N-type diffusion resistance element 1) and the angular direction in the chip surface of the semiconductor chip 4 at which the piezo resistance coefficient of the semiconductor chip 4 is minimized. However, it is larger than the angle (θp1) between the current energizing direction of the second resistance element (N-type diffusion resistance element 2) and the angular direction in the chip surface of the semiconductor chip 4 in which the piezo resistance coefficient of the semiconductor chip 4 is minimized. It is configured to be large.
　そして、第１の不純物濃度は、第２の不純物濃度よりも高くなるように形成されている。 Then, the first impurity concentration is formed to be higher than the second impurity concentration.
　また、本実施例の半導体チップのチップ温度センサは、言い換えると、第１の抵抗素子（Ｎ型拡散抵抗素子１）の電流の通電方向と半導体チップ４の＜１１０＞方向との間に成す角度（θｐ２）が、第２の抵抗素子（Ｎ型拡散抵抗素子２）の電流の通電方向と半導体チップ４の＜１１０＞方向との間に成す角度（θｐ１）よりも大きくなるように構成されている。 Further, in the chip temperature sensor of the semiconductor chip of this embodiment, in other words, the angle formed between the current energizing direction of the first resistance element (N-type diffusion resistance element 1) and the <110> direction of the semiconductor chip 4. (Θp2) is configured to be larger than the angle (θp1) formed between the current energizing direction of the second resistance element (N-type diffusion resistance element 2) and the <110> direction of the semiconductor chip 4. There is.
　なお、本実施例では、Ｎ型拡散抵抗素子１の電流の通電方向を＜１１０＞の結晶軸方向からθｐ２の角度だけずらして配置し、Ｎ型拡散抵抗素子２の電流の通電方向は＜１１０＞の結晶軸方向からθｐ１の角度だけずらして配置しているが、Ｎ型拡散抵抗素子１，２の各々のピエゾ抵抗係数自体を小さくした方が実装応力の影響を小さくできるので、Ｎ型拡散抵抗素子２の電流の通電方向は＜１１０＞の結晶軸方向にした方がより好適である。 In this embodiment, the current energizing direction of the N-type diffusion resistance element 1 is shifted by the angle of θp2 from the crystal axis direction of <110>, and the current energization direction of the N-type diffusion resistance element 2 is <110>. > Is arranged so as to be offset by an angle of θp1 from the crystal axis direction, but the effect of mounting stress can be reduced by reducing the piezo resistance coefficient itself of each of the N-type diffusion resistance elements 1 and 2, so N-type diffusion It is more preferable that the current energizing direction of the resistance element 2 is the crystal axis direction of <110>.
　また、実施例２のように、Ｐ型の拡散抵抗素子を用いた場合はＰ型拡散抵抗素子の電流の通電方向は＜１００＞の結晶軸方向にした方が良い。 Further, when a P-type diffusion resistance element is used as in Example 2, the current energizing direction of the P-type diffusion resistance element should be the crystal axis direction of <100>.
　次に、図１２及び図１３を参照して、本発明の第４の実施例である半導体チップのチップ温度センサについて説明する。なお、図１２は本実施例の半導体チップのチップ温度センサの回路図、図１３はＮ型拡散抵抗素子９，１０，１１，１２の半導体チップ上の配置図である。 Next, the chip temperature sensor of the semiconductor chip, which is the fourth embodiment of the present invention, will be described with reference to FIGS. 12 and 13. FIG. 12 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment, and FIG. 13 is a layout diagram of the N-type diffusion resistance elements 9, 10, 11, and 12 on the semiconductor chip.
　本実施例の半導体チップのチップ温度センサは、図１２及び図１３に示すように、実施例１（図１及び図２）のＮ型拡散抵抗素子１の代わりにＮ型拡散抵抗素子９，１０を配置し、Ｎ型拡散抵抗素子２の代わりにＮ型拡散抵抗素子１１，１２を配置している点において、実施例１の半導体チップのチップ温度センサとは異なる。 As shown in FIGS. 12 and 13, the chip temperature sensor of the semiconductor chip of this embodiment has N-type diffusion resistance elements 9 and 10 instead of the N-type diffusion resistance element 1 of Example 1 (FIGS. 1 and 2). Is arranged, and N-type diffusion resistance elements 11 and 12 are arranged instead of the N-type diffusion resistance element 2, which is different from the chip temperature sensor of the semiconductor chip of the first embodiment.
　Ｎ型拡散抵抗素子９は、一端が電源電圧Ｖｃｃに接続され、他端がＮ型拡散抵抗素子１０に接続されている。Ｎ型拡散抵抗素子１０は、一端がＮ型拡散抵抗素子９に接続され、他端がＮ型拡散抵抗素子１１に接続されている。Ｎ型拡散抵抗素子１１は、一端がＮ型拡散抵抗素子１０に接続され、他端がＮ型拡散抵抗素子１２に接続されている。Ｎ型拡散抵抗素子１２は、一端がグランドに接続され、他端がＮ型拡散抵抗素子１１に接続されている。 One end of the N-type diffusion resistance element 9 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 10. One end of the N-type diffusion resistance element 10 is connected to the N-type diffusion resistance element 9, and the other end is connected to the N-type diffusion resistance element 11. One end of the N-type diffusion resistance element 11 is connected to the N-type diffusion resistance element 10, and the other end is connected to the N-type diffusion resistance element 12. One end of the N-type diffusion resistance element 12 is connected to the ground, and the other end is connected to the N-type diffusion resistance element 11.
　なお、Ｎ型拡散抵抗素子１０とＮ型拡散抵抗素子１１の接続点に増幅器３が接続されている点など、その他の構成は、基本的に実施例１と同様である。 The other configurations, such as the point that the amplifier 3 is connected to the connection point between the N-type diffusion resistance element 10 and the N-type diffusion resistance element 11, are basically the same as those in the first embodiment.
　図１３に示すように、本実施例では、Ｎ型拡散抵抗素子１の代わりにＮ型拡散抵抗素子９，１０を配置し、Ｎ型拡散抵抗素子１０の長手方向を＜１１０＞の結晶軸方向からθｐの角度だけずらして配置し、Ｎ型拡散抵抗素子９の長手方向は９０°ずれた＜１１０＞の結晶軸方向からθｐの角度だけずらして配置し、Ｎ型拡散抵抗素子２の代わりにＮ型拡散抵抗素子１１，１２を配置し、Ｎ型拡散抵抗素子１２の長手方向を＜１１０＞の結晶軸方向に配置し、Ｎ型拡散抵抗素子１１の長手方向を９０°ずれた＜１１０＞の結晶軸方向に配置している。 As shown in FIG. 13, in this embodiment, the N-type diffusion resistance elements 9 and 10 are arranged in place of the N-type diffusion resistance element 1, and the longitudinal direction of the N-type diffusion resistance element 10 is set to the crystal axis direction of <110>. The N-type diffusion resistance element 9 is arranged so as to be offset by the angle of θp from, and the N-type diffusion resistance element 9 is arranged so as to be displaced by the angle of θp from the crystal axis direction of <110>, which is displaced by 90 °, instead of the N-type diffusion resistance element 2. The N-type diffusion resistance elements 11 and 12 are arranged, the longitudinal direction of the N-type diffusion resistance element 12 is arranged in the crystal axis direction of <110>, and the longitudinal direction of the N-type diffusion resistance element 11 is deviated by 90 ° <110>. It is arranged in the crystal axis direction of.
　本実施例の半導体チップのチップ温度センサは、言い換えると、第２の抵抗素子は、第３の抵抗素子（Ｎ型拡散抵抗素子１１）と第４の抵抗素子（Ｎ型拡散抵抗素子１２）の直列接続で構成されており、第３の抵抗素子（Ｎ型拡散抵抗素子１１）の電流の通電方向と第４の抵抗素子（Ｎ型拡散抵抗素子１２）の電流の通電方向は、互いに直角となるように構成されている。 In the chip temperature sensor of the semiconductor chip of this embodiment, in other words, the second resistance element is a third resistance element (N-type diffusion resistance element 11) and a fourth resistance element (N-type diffusion resistance element 12). It is configured by series connection, and the current energizing direction of the third resistance element (N-type diffusion resistance element 11) and the current energization direction of the fourth resistance element (N-type diffusion resistance element 12) are perpendicular to each other. It is configured to be.
　また、第１の抵抗素子は、第５の抵抗素子（Ｎ型拡散抵抗素子９）と第６の抵抗素子（Ｎ型拡散抵抗素子１０）の直列接続で構成されており、第５の抵抗素子（Ｎ型拡散抵抗素子９）の電流の通電方向と第６の抵抗素子（Ｎ型拡散抵抗素子１０）の電流の通電方向は、互いに直角となるように構成されている。 Further, the first resistance element is composed of a fifth resistance element (N-type diffusion resistance element 9) and a sixth resistance element (N-type diffusion resistance element 10) connected in series, and the fifth resistance element. The current energizing direction of the (N-type diffusion resistance element 9) and the current energization direction of the sixth resistance element (N-type diffusion resistance element 10) are configured to be perpendicular to each other.
　なお、Ｎ型拡散抵抗素子９，１０，１１，１２の電流の通電方向が、それぞれＮ型拡散抵抗素子９，１０，１１，１２の長手方向になるようにＮ型拡散抵抗素子９，１０，１１，１２の長手方向の両端にコンタクトを設けている。 The N-type diffusion resistance elements 9, 10, 12 so that the current energization directions of the N-type diffusion resistance elements 9, 10, 11, and 12 are in the longitudinal directions of the N-type diffusion resistance elements 9, 10, 11, 12, respectively. Contacts are provided at both ends of 11 and 12 in the longitudinal direction.
　本実施例では、Ｎ型拡散抵抗素子１の代わりにＮ型拡散抵抗素子９と９０°回転したＮ型拡散抵抗素子１０を配置することで、実装応力が一様でなく、例えば、図１３に示したＸ軸方向に引っ張り応力、Ｙ向に圧縮応力が働いたような状態でもＮ型拡散抵抗素子９，１０の合成抵抗とＮ型拡散抵抗素子１１，１２の合成抵抗の実装応力による影響を等しくすることができる。このことは上記特許文献２に詳しく記載されている。 In this embodiment, by arranging the N-type diffusion resistance element 9 and the N-type diffusion resistance element 10 rotated by 90 ° instead of the N-type diffusion resistance element 1, the mounting stress is not uniform. For example, in FIG. Even when tensile stress is applied in the X-axis direction and compressive stress is applied in the Y direction, the effect of the combined stress of the N-type diffusion resistance elements 9 and 10 and the combined stress of the N-type diffusion resistance elements 11 and 12 is affected. Can be equal. This is described in detail in Patent Document 2 above.
　つまり、実装応力の働き方が如何なる角度方向からの応力であっても、一様に全体的に引っ張り応力の様な状態であったとしても、Ｎ型拡散抵抗素子９，１０の合成抵抗とＮ型拡散抵抗素子１１，１２の合成抵抗の実装応力による影響を等しくできる。 That is, the combined resistance of the N-type diffusion resistance elements 9 and 10 and the N are N, regardless of how the mounting stress works from any angle direction, even if the stress is uniformly as a tensile stress as a whole. The influence of the mounting stress of the combined resistance of the type diffusion resistance elements 11 and 12 can be made equal.
　この結果、実装応力の働き方がいかようになっても、実装応力によるチップ温度の計測の誤差を無くすことができる。 As a result, no matter how the mounting stress works, it is possible to eliminate the error in measuring the chip temperature due to the mounting stress.
　つまり、不純物濃度の高い方のＮ型拡散抵抗素子９，１０を直列接続で構成し、Ｎ型拡散抵抗素子９，１０の電流の通電方向は互いに直角になるように配置し、不純物濃度の低い方のＮ型拡散抵抗素子１１，１２を直列接続で構成し、Ｎ型拡散抵抗素子１１，１２の電流の通電方向は互いに直角になるように配置することで、実装応力の働き方がいかようになっても、実装応力によるチップ温度の計測の誤差を無くすことができる。 That is, the N-type diffusion resistance elements 9 and 10 having the higher impurity concentration are connected in series, and the currents of the N-type diffusion resistance elements 9 and 10 are arranged so as to be perpendicular to each other, and the impurity concentration is low. By connecting the N-type diffusion resistance elements 11 and 12 in series and arranging the currents of the N-type diffusion resistance elements 11 and 12 so that they are perpendicular to each other, how the mounting stress works. Even if this happens, it is possible to eliminate the error in measuring the chip temperature due to the mounting stress.
　次に、図１４及び図１５を参照して、本発明の第５の実施例である半導体チップのチップ温度センサについて説明する。なお、図１４は本実施例の半導体チップのチップ温度センサの回路図、図１５はＮ型拡散抵抗素子１，２，１３，１４の半導体チップ上の配置図である。 Next, the chip temperature sensor of the semiconductor chip, which is the fifth embodiment of the present invention, will be described with reference to FIGS. 14 and 15. FIG. 14 is a circuit diagram of the chip temperature sensor of the semiconductor chip of this embodiment, and FIG. 15 is a layout diagram of the N-type diffusion resistance elements 1, 2, 13 and 14 on the semiconductor chip.
　本実施例の半導体チップのチップ温度センサは、図１４及び図１５に示すように、実施例１（図１及び図２）の構成に加えて、Ｎ型拡散抵抗素子１３，１４と切り換え手段１５，１６，１７を配置している点において、実施例１の半導体チップのチップ温度センサとは異なる。 As shown in FIGS. 14 and 15, the chip temperature sensor of the semiconductor chip of this embodiment has the N-type diffusion resistance elements 13 and 14 and the switching means 15 in addition to the configuration of the first embodiment (FIGS. 1 and 2). , 16 and 17 are arranged, which is different from the chip temperature sensor of the semiconductor chip of the first embodiment.
　Ｎ型拡散抵抗素子１は、一端が電源電圧Ｖｃｃに接続され、他端が切り換え手段１６を介してＮ型拡散抵抗素子２に接続されている。Ｎ型拡散抵抗素子１３は、一端が電源電圧Ｖｃｃに接続され、他端が切り換え手段１５を介してＮ型拡散抵抗素子２に接続されている。Ｎ型拡散抵抗素子１４は、一端が電源電圧Ｖｃｃに接続され、他端が切り換え手段１７を介してＮ型拡散抵抗素子２に接続されている。 One end of the N-type diffusion resistance element 1 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 16. One end of the N-type diffusion resistance element 13 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 15. One end of the N-type diffusion resistance element 14 is connected to the power supply voltage Vcc, and the other end is connected to the N-type diffusion resistance element 2 via the switching means 17.
　なお、Ｎ型拡散抵抗素子１，１３，１４とＮ型拡散抵抗素子２の接続点に増幅器３が接続されている点など、その他の構成は、基本的に実施例１と同様である。 Other configurations, such as the point that the amplifier 3 is connected to the connection point between the N-type diffusion resistance elements 1, 13 and 14 and the N-type diffusion resistance element 2, are basically the same as those in the first embodiment.
　図１５に示すように、本実施例では、Ｎ型拡散抵抗素子１３の長手方向を＜１１０＞の結晶軸方向からθｐ―αの角度だけずらして配置し、Ｎ型拡散抵抗素子１４の長手方向を＜１１０＞の結晶軸方向からθｐ＋αの角度だけずらして配置している。また、Ｎ型拡散抵抗素子２と接続するＮ型拡散抵抗素子を選択するために切り換え手段１５，１６，１７を配置している。 As shown in FIG. 15, in this embodiment, the longitudinal direction of the N-type diffusion resistance element 13 is arranged so as to be offset by an angle of θp−α from the crystal axis direction of <110>, and the longitudinal direction of the N-type diffusion resistance element 14 is arranged. Is arranged so as to be offset by an angle of θp + α from the crystal axis direction of <110>. Further, switching means 15, 16 and 17 are arranged to select an N-type diffusion resistance element to be connected to the N-type diffusion resistance element 2.
　切り換え手段１５，１６，１７は、スイッチや配線の有無、ヒューズなどの接続の有無を切り換えることができる構成であれば良い。また、Ｎ型拡散抵抗素子１，２，１３，１４の電流の通電方向がＮ型拡散抵抗素子１，２，１３，１４の長手方向になるようにＮ型拡散抵抗素子１，２，１３，１４の長手方向の両端にコンタクトを設けている。 The switching means 15, 16 and 17 may have a configuration capable of switching the presence / absence of a switch, wiring, and the presence / absence of a connection such as a fuse. Further, the N-type diffusion resistance elements 1, 2, 13, 14 so that the current energization direction of the N-type diffusion resistance elements 1, 2, 13, 14 is in the longitudinal direction of the N-type diffusion resistance elements 1, 2, 13, 14, Contacts are provided at both ends of the 14 in the longitudinal direction.
　本実施例の半導体チップのチップ温度センサは、言い換えると、第１の抵抗素子は、電流の通電方向の角度が異なる複数の抵抗素子（Ｎ型拡散抵抗素子１，１３，１４）で構成され、複数の抵抗素子（Ｎ型拡散抵抗素子１，１３，１４）の各々と第２の抵抗素子（Ｎ型拡散抵抗素子２）との接続を切り換える切り換え手段１５，１６，１７を有している。 In other words, in the chip temperature sensor of the semiconductor chip of this embodiment, the first resistance element is composed of a plurality of resistance elements (N-type diffusion resistance elements 1, 13, 14) having different angles in the current energizing direction. It has switching means 15, 16 and 17 for switching the connection between each of the plurality of resistance elements (N-type diffusion resistance elements 1, 13 and 14) and the second resistance element (N-type diffusion resistance element 2).
　本実施例では、Ｎ型拡散抵抗素子１３，１４を設けて、Ｎ型拡散抵抗素子１の代わりにＮ型拡散抵抗素子１３，１４を切り換え手段１５，１５，１７を用いてＮ型拡散抵抗素子２に接続できるようにしている。このことによって、Ｎ型拡散抵抗素子１，２，１３，１４の不純物濃度が変化しても適切なＮ型拡散抵抗素子の電流の通電方向とピエゾ抵抗係数が極小となる方向である＜１１０＞方向との角度を選択できるようになる。 In this embodiment, the N-type diffusion resistance elements 13 and 14 are provided, and the N-type diffusion resistance elements 13 and 14 are switched instead of the N-type diffusion resistance element 1 by using the switching means 15, 15 and 17. It is possible to connect to 2. As a result, even if the impurity concentrations of the N-type diffusion resistance elements 1, 2, 13 and 14 change, the current energization direction and the piezo resistance coefficient of the appropriate N-type diffusion resistance element are minimized <110>. You will be able to select the angle with the direction.
　なお、以上の各実施例において説明した半導体チップのチップ温度センサを流量測定装置（エアフローセンサ）に搭載することで、空気流量の検出精度の向上を図ることができる。 By mounting the chip temperature sensor of the semiconductor chip described in each of the above embodiments on the flow rate measuring device (air flow sensor), the accuracy of detecting the air flow rate can be improved.
　この場合、流量測定装置（エアフローセンサ）は、半導体チップ上に、ヒータ抵抗と、ヒータ抵抗の両隣に上流側温度センサと下流側温度センサと、を備えて構成され、上流側温度センサ及び下流側温度センサに、実施例１から５のいずれかで説明した半導体チップのチップ温度センサを用いる。 In this case, the flow rate measuring device (air flow sensor) is configured to include a heater resistance and an upstream temperature sensor and a downstream temperature sensor on both sides of the heater resistance on the semiconductor chip, and the upstream temperature sensor and the downstream temperature sensor are provided. As the temperature sensor, the chip temperature sensor of the semiconductor chip described in any one of Examples 1 to 5 is used.
　また、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施例は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 Further, the present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.
　１…Ｎ型拡散抵抗素子（高不純物濃度）、２…Ｎ型拡散抵抗素子（低不純物濃度）、３…増幅器、４…半導体チップ、５…Ｐ型拡散抵抗素子（高不純物濃度）、６…Ｐ型拡散抵抗素子（低不純物濃度）、７…増幅器、８…半導体チップ、９…Ｎ型拡散抵抗素子、１０…Ｎ型拡散抵抗素子、１１…Ｎ型拡散抵抗素子、１２…Ｎ型拡散抵抗素子、１３…Ｎ型拡散抵抗素子、１４…Ｎ型拡散抵抗素子、１５…切り換え手段、１６…切り換え手段、１７…切り換え手段。 1 ... N-type diffusion resistance element (high impurity concentration), 2 ... N-type diffusion resistance element (low impurity concentration), 3 ... amplifier, 4 ... semiconductor chip, 5 ... P-type diffusion resistance element (high impurity concentration), 6 ... P-type diffusion resistance element (low impurity concentration), 7 ... amplifier, 8 ... semiconductor chip, 9 ... N-type diffusion resistance element, 10 ... N-type diffusion resistance element, 11 ... N-type diffusion resistance element, 12 ... N-type diffusion resistance Element, 13 ... N-type diffusion resistance element, 14 ... N-type diffusion resistance element, 15 ... switching means, 16 ... switching means, 17 ... switching means.

Claims (12)

  1. 　同一の半導体チップに、第１の不純物濃度を有する第１の抵抗素子と、
    　前記第１の抵抗素子に直列接続され、前記第１の不純物濃度と異なる第２の不純物濃度を有する第２の抵抗素子と、を備え、
    　前記第１の抵抗素子の電流の通電方向と前記半導体チップのピエゾ抵抗係数が極小となる前記半導体チップのチップ表面内の角度方向との角度が、前記第２の抵抗素子の電流の通電方向と前記半導体チップのピエゾ抵抗係数が極小となる前記半導体チップのチップ表面内の角度方向との角度よりも大きい半導体チップのチップ温度センサ。     The first resistance element having the first impurity concentration and the same semiconductor chip,
    A second resistance element, which is connected in series to the first resistance element and has a second impurity concentration different from the first impurity concentration, is provided.
    The angle between the current energizing direction of the first resistance element and the angular direction in the chip surface of the semiconductor chip at which the piezoresistive coefficient of the semiconductor chip is minimized is the current energizing direction of the second resistance element. A chip temperature sensor for a semiconductor chip in which the piezoresistive coefficient of the semiconductor chip is minimal and is larger than the angle with respect to the angular direction in the chip surface of the semiconductor chip.
  2. 　請求項１に記載の半導体チップのチップ温度センサであって、
    　前記第１の不純物濃度は、前記第２の不純物濃度よりも高い半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 1.
    The first impurity concentration is a chip temperature sensor of a semiconductor chip higher than the second impurity concentration.
  3. 　請求項１に記載の半導体チップのチップ温度センサであって、
    　前記第１の抵抗素子および前記第２の抵抗素子は、共にＮ型拡散抵抗素子、或いは、共にＰ型拡散抵抗素子である半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 1.
    The first resistance element and the second resistance element are both N-type diffusion resistance elements or P-type diffusion resistance elements, and are chip temperature sensors for semiconductor chips.
  4. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第１の抵抗素子および前記第２の抵抗素子は、共にＮ型拡散抵抗素子であり、
    　前記第１の抵抗素子の電流の通電方向と前記半導体チップの＜１１０＞方向との間に成す角度が、前記第２の抵抗素子の電流の通電方向と前記半導体チップの＜１１０＞方向との間に成す角度よりも大きい半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    The first resistance element and the second resistance element are both N-type diffusion resistance elements.
    The angle formed between the current energizing direction of the first resistance element and the <110> direction of the semiconductor chip is the energizing direction of the current of the second resistance element and the <110> direction of the semiconductor chip. A chip temperature sensor for a semiconductor chip that is larger than the angle formed between them.
  5. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第１の抵抗素子および前記第２の抵抗素子は、共にＰ型拡散抵抗素子であり、
    　前記第１の抵抗素子の電流の通電方向と前記半導体チップの＜１００＞方向との間に成す角度が、前記第２の抵抗素子の電流の通電方向と前記半導体チップの＜１００＞方向との間に成す角度よりも大きい半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    The first resistance element and the second resistance element are both P-type diffusion resistance elements.
    The angle formed between the current energizing direction of the first resistance element and the <100> direction of the semiconductor chip is the energizing direction of the current of the second resistance element and the <100> direction of the semiconductor chip. A chip temperature sensor for a semiconductor chip that is larger than the angle formed between them.
  6. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第２の抵抗素子の電流の通電方向と前記半導体チップのピエゾ抵抗係数が極小となる前記半導体チップのチップ表面内の角度方向との角度が等しい半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    A chip temperature sensor for a semiconductor chip in which the angle between the current energizing direction of the second resistance element and the angular direction in the chip surface of the semiconductor chip at which the piezoresistive coefficient of the semiconductor chip is minimized is equal.
  7. 　請求項４に記載の半導体チップのチップ温度センサであって、
    　前記第２の抵抗素子の電流の通電方向と前記半導体チップの＜１１０＞方向が等しい半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 4.
    A chip temperature sensor for a semiconductor chip in which the current energizing direction of the second resistance element and the <110> direction of the semiconductor chip are equal to each other.
  8. 　請求項５に記載の半導体チップのチップ温度センサであって、
    　前記第２の抵抗素子の電流の通電方向と前記半導体チップの＜１００＞方向が等しい半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 5.
    A chip temperature sensor for a semiconductor chip in which the current energizing direction of the second resistance element and the <100> direction of the semiconductor chip are equal to each other.
  9. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第２の抵抗素子は、第３の抵抗素子と第４の抵抗素子の直列接続で構成され、
    　前記第３の抵抗素子の電流の通電方向と前記第４の抵抗素子の電流の通電方向は、互いに直角である半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    The second resistance element is composed of a third resistance element and a fourth resistance element connected in series.
    A chip temperature sensor for a semiconductor chip in which the current energizing direction of the third resistance element and the current energizing direction of the fourth resistance element are at right angles to each other.
  10. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第１の抵抗素子は、第５の抵抗素子と第６の抵抗素子の直列接続で構成され、
    　前記第５の抵抗素子の電流の通電方向と前記第６の抵抗素子の電流の通電方向は、互いに直角である半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    The first resistance element is composed of a fifth resistance element and a sixth resistance element connected in series.
    A chip temperature sensor for a semiconductor chip in which the current energizing direction of the fifth resistance element and the current energizing direction of the sixth resistance element are at right angles to each other.
  11. 　請求項２に記載の半導体チップのチップ温度センサであって、
    　前記第１の抵抗素子は、電流の通電方向の角度が異なる複数の抵抗素子で構成され、
    　前記複数の抵抗素子の各々と前記第２の抵抗素子との接続を切り換える切り換え手段を有する半導体チップのチップ温度センサ。     The chip temperature sensor for a semiconductor chip according to claim 2.
    The first resistance element is composed of a plurality of resistance elements having different angles in the current energizing direction.
    A chip temperature sensor of a semiconductor chip having a switching means for switching the connection between each of the plurality of resistance elements and the second resistance element.
  12. 　半導体チップ上に、ヒータ抵抗と、
    　前記ヒータ抵抗の両隣に上流側温度センサと下流側温度センサと、を備える流量測定装置であって、
    　前記上流側温度センサ及び前記下流側温度センサは、請求項１から１１のいずれか１項に記載の半導体チップのチップ温度センサである流量測定装置。     On the semiconductor chip, the heater resistance and
    A flow rate measuring device including an upstream temperature sensor and a downstream temperature sensor on both sides of the heater resistor.
    The upstream temperature sensor and the downstream temperature sensor are flow rate measuring devices that are chip temperature sensors for semiconductor chips according to any one of claims 1 to 11.
PCT/JP2020/035391 2019-10-25 2020-09-18 Chip temperature sensor for semiconductor chip, and flow rate measurement device WO2021079666A1 (en)

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