JP2014225610A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having various sorts of built-in circuits including an oscillation circuit, which ensures characteristics of the built-in circuits with high accuracy regardless of a package structure.SOLUTION: A semiconductor device is a packaged and resin-sealed semiconductor device in which a semiconductor chip having various sorts of built-in circuits including an oscillation circuit is sealed with a resin material. The semiconductor device comprises a plurality of circuits formed on a principal surface of a semiconductor substrate; and stress sensors 10 formed on the principal surface of the semiconductor substrate, for detecting a stress acting on the plurality of circuits. The stress sensor 10 includes a first conductivity type first semiconductor resistance which is formed on the principal surface of the semiconductor substrate and has a first impurity concentration and a first conductivity type second semiconductor resistance which is formed on the principal surface of the semiconductor substrate and has a second impurity concentration lower than the first impurity concentration, and outputs an electric signal depending on a ratio or a difference between resistance values of the first and second semiconductor resistances.

Description

  The present invention relates to a semiconductor device, and is suitably used for a semiconductor device incorporating various circuits including an oscillation circuit, for example.

  As an example of a semiconductor device incorporating various circuits including an oscillation circuit, International Publication No. 2012 / 073007A1 (Patent Document 1) encapsulates a semiconductor chip incorporating an oscillation circuit and the like with a resin material and is packaged. A resin-encapsulated semiconductor device is disclosed.

  In this type of semiconductor device, stress is generated in the semiconductor chip due to the difference in thermal expansion coefficient between the resin material and the semiconductor substrate. When stress is applied to the semiconductor chip, the resistance value of the reference resistor varies due to deformation of the reference resistor included in the oscillation circuit in response to the stress. As a result, the oscillation frequency of the oscillation circuit varies. In Patent Document 1, an extension direction of a conductor pattern is generated on the main surface of the semiconductor chip so that the conductor pattern constituting the reference resistance is not affected by the stress generated in the semiconductor chip as much as possible. It is disclosed that the stress is set in a decreasing direction.

International Publication No. 2012/073307 JP-A-2005-291978 JP-A-62-252152

  The semiconductor device described in Patent Document 1 stabilizes the oscillation frequency of the oscillation circuit by suppressing fluctuations in the resistance value of the reference resistor as much as possible. However, the fluctuation of the resistance value of the reference resistor depends on the package structure (resin material properties, package shape and dimensions, etc.) that encapsulates the semiconductor chip, so the oscillation frequency accuracy varies depending on the package structure. turn into. Therefore, in the semiconductor device disclosed in Patent Document 1, the guaranteed accuracy value of the circuit characteristics such as the oscillation frequency is regulated by the package whose accuracy is most deteriorated in a series of package lineups. Since the package structure greatly affects the accuracy of the circuit characteristics, it is not easy to change the package characteristics. Therefore, in a semiconductor device, it becomes a big problem to guarantee the characteristics of a built-in circuit with high accuracy regardless of the package structure. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device according to an embodiment includes a plurality of circuits formed on a main surface of a semiconductor substrate and a stress sensor that is formed on the main surface of the semiconductor substrate and detects stress acting on the plurality of circuits. The stress sensor is formed on the main surface of the semiconductor substrate and has a first conductivity type first semiconductor resistor having a first impurity concentration, and is formed on the main surface of the semiconductor substrate and has a first impurity concentration lower than the first impurity concentration. And a second semiconductor resistor of the first conductivity type having an impurity concentration of 2.

  According to the above-described embodiment, the characteristics of the circuit built in the semiconductor chip can be ensured with high accuracy regardless of the structure of the package for sealing the semiconductor chip.

2 is a plan layout diagram of a semiconductor chip constituting the semiconductor device according to the first embodiment. FIG. It is a circuit diagram which shows an example of the oscillation circuit formed in a semiconductor chip. It is explanatory drawing which shows typically the relationship between the oscillation signal of an oscillation part, switching of ON / OFF of a switch, and the voltage of a capacity | capacitance. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 3 is a perspective view of the inside of a semiconductor device as viewed from the upper surface side of the semiconductor device according to the first embodiment. It is a figure explaining the change of the resistance value of resistance wiring by stress. It is a circuit diagram for demonstrating one structural example of a stress sensor. It is a circuit diagram for demonstrating the other structural example of a stress sensor. It is a circuit diagram for demonstrating the other structural example of a stress sensor. It is sectional drawing of P-type diffused resistance used for the resistive element of a stress sensor. It is a figure which shows the relationship between the impurity concentration in a diffusion resistance, and a piezoresistance coefficient. It is sectional drawing of N type diffused resistance used for the resistive element of a stress sensor. It is sectional drawing of the polysilicon resistance used for the resistive element of a stress sensor. It is a figure which shows the crystal axis dependence of the piezoresistance coefficient in a P-type silicon substrate. It is a figure which shows the resistive element formed in a P-type silicon substrate. It is a figure for demonstrating the mode of the change of the resistance value with respect to stress in a P-type polysilicon resistance and an N-type polysilicon resistance. 6 is a diagram for explaining correction of circuit characteristics in the semiconductor device according to the first embodiment; FIG. It is a circuit diagram of an oscillation circuit. It is a circuit diagram of a temperature sensor. 1 is a plan view of a semiconductor chip according to a first embodiment. It is a figure which shows the result of having simulated the stress which generate | occur | produces in a semiconductor chip. It is a plane layout figure which shows an example of arrangement | positioning of a stress sensor and a circuit block. It is a plane layout figure which shows the other example of arrangement | positioning of a stress sensor and a circuit block. It is a plane layout figure which shows the other example of arrangement | positioning of a stress sensor and a circuit block. FIG. 6 is a circuit diagram of a semiconductor chip constituting a semiconductor device according to a second embodiment. It is a circuit diagram for demonstrating the structural example of a stress sensor. It is a figure which shows the structure of the resistive element which comprises a stress sensor.

  Hereinafter, an embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Embodiment 1]
(Circuit configuration of semiconductor device)
FIG. 1 is a plan layout diagram of a semiconductor chip constituting the semiconductor device according to the first embodiment. In the figure, an example of a layout of circuit blocks and the like built in the semiconductor chip CP is shown.

  Referring to FIG. 1, an oscillation circuit and other circuits are formed on the main surface of semiconductor chip CP. Specifically, the semiconductor chip CP has a rectangular planar shape, and includes an oscillation circuit region OSC in which an oscillation circuit is formed and a region in which a circuit other than the oscillation circuit is formed. For example, the semiconductor chip CP includes a RAM area RAM in which a RAM (Random Access Memory) is formed, a logic circuit area LOG in which a logic circuit is formed, and a flash memory area FLA in which a flash memory (nonvolatile memory) is formed. have. The semiconductor chip CP further includes an AD / DA area AD in which A / D (analog / digital) converters and D / A converters are formed, an I / F circuit area IF in which I / F circuits are formed, and a power supply circuit. And a formed power supply circuit area PC.

  On the outer periphery of the main surface of the semiconductor chip CP, a plurality of pad electrodes PD are arranged along the four sides of the main surface of the semiconductor chip CP. Each pad electrode PD is connected to an oscillation circuit area OSC, a RAM area RAM, a logic circuit area LOG, a flash memory area FLA, an AD / DA area AD, an I / F circuit area IF, a power supply via an internal wiring layer of the semiconductor chip CP. It is electrically connected to the circuit area PC or the like.

(Configuration of oscillation circuit)
FIG. 2 is a circuit diagram showing an example of an oscillation circuit formed in the semiconductor chip CP. FIG. 3 is an explanatory diagram schematically showing the relationship between the oscillation signal (frequency F) of the oscillating unit 13, the on / off switching of the switch SW1, and the voltage of the capacitor C1.

  With reference to FIG. 2, the oscillation circuit includes a voltage-current conversion unit 11, a voltage generation unit 12, and an oscillation unit 13.

  The voltage-current converter 11 converts the reference voltage VrefI, which is an input voltage, into a current (reference current) Iref using the reference resistor Rst. Specifically, when the reference voltage VrefI is input to the operational amplifier OP1 of the voltage / current converter 11, the reference current Iref is generated by applying the reference voltage VrefI to the reference resistor Rst. When the resistance value of the reference resistor Rst is R, the reference current Iref is Iref = VrefI / R. That is, the reference resistor Rst can be regarded as a resistor for converting the reference voltage VrefI into the reference current Iref. The reference current Iref is copied by a current mirror circuit composed of transistors T1 and T2 and supplied to the voltage generator 12.

  The voltage generator 12 generates a voltage Vo corresponding to the oscillation frequency F of the oscillator 13 using the input current Iref from the voltage-current converter 11. Specifically, the current Iref supplied from the voltage / current converter 11 is input to the switch SW <b> 1 of the voltage generator 12. The switch SW1 is connected to the capacitor C1 and the switch SW2, and the switch SW1 is turned on (conductive) for a time 1 / F with respect to the oscillation frequency F of the oscillation unit 13. Immediately before the switch SW1 is turned on, the switch SW2 is turned off (non-conducting) and the capacitor C1 is discharged, and the charge voltage of the capacitor C1 is 0V. By turning on the switch SW1 with the switch SW2 turned off, charging of the capacitor C1 is started in response to a current (reference current Iref) flowing into the capacitor C1 via the switch SW1. That is, during the time when the switch SW1 is turned on (1 / F time), the capacitor C1 is charged by the reference current Iref. At this time, when the charge stored in the capacitor C1 is Q, Q = Iref × (1 / F). Therefore, when the capacitance value of the capacitor C1 is C and the voltage is V, the voltage V is expressed by the following formula (1) using the charge Q and the capacitor C.

  Here, since the reference current Iref is determined by the reference voltage VrefI and the reference resistance Rst as described above (Iref = VrefI / Rst), the above equation (1) can be transformed into the following equation (2).

  The voltage V of the capacitor C1 is input to the inverting input terminal (− terminal) of the operational amplifier OP2. The reference voltage Vrefc is input to the non-inverting input terminal (+ terminal) of the operational amplifier OP2. The operational amplifier OP2 outputs a voltage Vo obtained by amplifying the voltage difference between the input voltage V and the reference voltage Vrefc.

  The oscillator 13 oscillates at a frequency corresponding to the input voltage Vo from the voltage generator 12. Specifically, the voltage Vo output from the voltage generator 12 is input to a VCO (Voltage Control Oscillator) 20. The VCO 20 outputs an oscillation signal at a frequency F corresponding to the input voltage Vo. The VCO 20 is an oscillator that controls the oscillation frequency with a voltage. When the voltage Vo input to the VCO 20 changes, the frequency F of the oscillation signal output from the VCO 20 changes accordingly.

  The oscillation unit 13 outputs an oscillation signal having a frequency F and outputs a frequency feedback signal to the control signal generator 30. The control signal generator 30 converts the frequency feedback signal into a switching control signal for controlling on / off of the switches SW1 and SW2. Specifically, the control signal generator 30 generates a switching control signal for the switch SW1 according to the oscillation frequency F of the oscillating unit 13 so that the time for which the switch SW1 is turned on becomes 1 / F. Further, a switching control signal for the switch SW2 is generated so that the switches SW1 and SW2 are turned on and off in a complementary manner.

  As described above, in the voltage generation unit 12, the oscillation circuit generates the voltage Vo according to the input current Iref from the voltage-current conversion unit 11 and the oscillation frequency F of the oscillation unit 13, and the generated voltage Vo is generated by the oscillation unit 13. , And the oscillation unit 13 is configured to oscillate at a frequency corresponding thereto. The voltage Vo generated by the voltage generation unit 12 is controlled according to the oscillation frequency F of the oscillation unit 13, and the oscillation frequency F is controlled according to the controlled voltage Vo, so that the oscillation frequency F varies. Even so, the fluctuation can be fed back to control the oscillation frequency F of the oscillation unit 13. Thereby, the fluctuation | variation of the oscillation frequency F of the oscillation part 13 can be suppressed, and the oscillation part 13 can be oscillated with the stable frequency.

  Here, the oscillation frequency F of the oscillation unit 13 is stabilized when the voltage V of the capacitor C1 and the reference voltage Vrefc match. That is, when the oscillation frequency F is stable, the relationship shown in the following formula (3) is established. Using this relationship, the oscillation frequency F of the oscillating unit 13 can be expressed by the following equation (4).

  As can be seen from the above equation (4), the oscillation frequency F changes according to the reference voltages VrefI and Vrefc, the capacitance value C of the capacitor C1, and the resistance value R of the reference resistor R. Therefore, if any of these values changes, the oscillation frequency F also changes. It should be noted that fluctuations caused by the reference voltages VrefI and Vrefc can be canceled out by designing the circuit. On the other hand, when the capacitance value of the capacitor C1 and the resistance value of the reference resistor Rst vary, the voltage Vo generated by the voltage generation unit 12 varies, and thus the oscillation frequency F of the oscillation unit 13 varies. In particular, when the resistance value of the reference resistor Rst varies, the reference current Iref generated by the voltage-current converter 11 varies, so the current Iref input to the voltage generator 12 also varies. As a result, the voltage The voltage Vo output from the generation unit 12 is changed.

  A main factor that causes the resistance value of the reference resistor Rst to fluctuate is that stress is generated in the semiconductor chip CP due to resin sealing in a resin-sealed semiconductor device in which the semiconductor chip CP is resin-sealed. . On the other hand, it has been confirmed by experimental data and the like that the capacitance value of the capacitor C1 hardly fluctuates due to the generation of this stress.

  In the first embodiment, the stress generated due to the resin-sealing of the semiconductor chip CP is detected, and the oscillation is performed by correcting the voltage Vo output from the voltage generator 12 according to the detected stress. Compensates for variations in frequency F. As a result, the oscillation frequency F of the oscillation unit 13 is stabilized. Similarly, for the circuits other than the oscillation circuit, the characteristic value is corrected in accordance with the stress generated in the semiconductor chip CP to compensate for the fluctuation of the characteristic value caused by the stress.

  Referring to FIG. 1 again, a stress sensor 10 is formed on the main surface of the semiconductor chip CP as a configuration for detecting the stress generated in the semiconductor chip CP. In a plurality of circuit regions including the oscillation circuit region OSC, the characteristic value of each circuit is corrected by receiving the detection value of the stress sensor 10.

Hereinafter, a specific configuration of the semiconductor device according to the first embodiment will be described.
(Overall configuration of semiconductor device)
First, the overall configuration of the semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment is a resin-encapsulated semiconductor device (semiconductor package) provided with a resin-encapsulated semiconductor chip CP (FIG. 1).

  FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 5 is a perspective view of the inside of the semiconductor device as viewed from the upper surface side of the semiconductor device according to the first embodiment.

  4 and 5, semiconductor device PKG according to the first embodiment includes a semiconductor chip CP, a die pad (chip mounting portion) DP that supports or mounts semiconductor chip CP, and a plurality of conductors. A lead LD, a plurality of leads LD, and a plurality of bonding wires BW that electrically connect the plurality of pad electrodes PD on the surface of the semiconductor chip CP, respectively, and a sealing resin portion MR that seals these together are provided. .

  The sealing resin portion MR is formed using a resin material such as a thermosetting resin material, for example. As an example, an epoxy resin containing a filler is used. Alternatively, a biphenyl thermosetting resin to which a phenolic curing agent, silicone rubber, filler, and the like are added may be used in order to reduce stress. The semiconductor chip CP, the lead LD, and the bonding wire BW are sealed by the sealing resin portion MR, and are electrically and mechanically protected. The sealing resin portion MR has a planar shape (outer shape) intersecting with its thickness, for example, a rectangular shape. The corners of the plane rectangle can be rounded.

  The semiconductor chip CP is manufactured by forming various semiconductor elements or semiconductor integrated circuits on the main surface of a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like and then separating the semiconductor substrate into each semiconductor chip by dicing or the like. It is.

  A plurality of pad electrodes PD are formed on one main surface of the semiconductor chip CP and on the main surface 1 on the side where the semiconductor elements are formed. Each pad electrode PD is electrically connected to a semiconductor element or a semiconductor integrated circuit formed inside or on the surface layer portion of the semiconductor chip CP. The plurality of pad electrodes PD are arranged along the periphery of the main surface 1 of the semiconductor chip CP. In the following description, in the semiconductor chip CP, the main surface 1 on the side where the semiconductor element is formed is referred to as a main surface 1, and the main surface 2 opposite to the main surface 1 is referred to as a back surface 2.

  The semiconductor chip CP is mounted on the upper surface of the die pad DP so that the main surface 1 faces upward. The back surface 2 of the semiconductor chip CP is bonded and fixed to the top surface of the die pad DP via an adhesive material 3. As the adhesive 3, a conductive or insulating adhesive can be used as necessary. Further, the semiconductor chip CP is sealed in the sealing resin portion MR and is not exposed from the sealing resin portion MR.

  The lead LD is made of a conductor and is typically made of a metal material such as copper or a copper alloy. Each lead LD includes an inner lead portion which is a portion located in the sealing resin portion MR of the lead LD and an outer lead portion which is a portion located outside the sealing resin portion MR of the lead LD. The outer lead portion protrudes outside the sealing resin portion MR from the side surface of the sealing resin portion MR. The plurality of leads LD are arranged around the semiconductor chip CP so that one end portion of the inner lead portion of each lead LD faces the semiconductor chip CP.

  Each pad electrode PD on the main surface 1 of the semiconductor chip CP is electrically connected to an inner lead portion of each lead LD via a bonding wire BW that is a conductive connecting member. The bonding wire BW is a conductive wire, and is preferably made of a fine metal wire such as a gold wire or a copper wire. The bonding wire BW is sealed in the resin sealing portion MR and is not exposed from the sealing resin portion MR.

  The outer lead portion of each lead LD is bent so that the lower surface near the end of the outer lead portion is positioned slightly below the lower surface of the sealing resin portion MR. The outer lead portion of the lead LD functions as an external connection terminal of the semiconductor chip CP.

  In this embodiment, the case where the semiconductor device PKG is a QFP (Quad Flat Package) type semiconductor device has been described. However, if the semiconductor device is a resin-encapsulated semiconductor device in which the semiconductor chip CP is resin-encapsulated, the semiconductor device The device PKG can be a semiconductor device of another form. As an example, the semiconductor device PKG may be in the form of a QFN (Quad Flat Non-leaded package), SOP (Small Outline Package), or DIP (Dual Inline Package) that is a semiconductor device manufactured using a lead frame. it can.

  Here, stress is generated in the semiconductor chip CP after the molding process of resin-sealing the semiconductor chip CP, the die pad PD, the plurality of leads LD, and the plurality of bonding wires BW. This is because the thermal expansion coefficient of the sealing resin portion MR is larger than the thermal expansion coefficient of the semiconductor substrate constituting the semiconductor chip CP. Specifically, in the molding process, the resin material is injected into the cavity of the mold for forming the sealing resin portion MR, and then the injected resin material is cured to form the sealing resin portion MR. The temperature at which the resin material is cured is as high as about 150 to 200 ° C., for example, and is cooled to room temperature after the resin material is cured. Since the shrinkage amount of the sealing resin portion MR at the time of cooling is larger than the shrinkage amount of the semiconductor chip CP, stress (particularly, compressive stress) as shown by an arrow in FIG. 5 is applied to the semiconductor chip CP. Become.

  When stress is applied to the semiconductor chip CP, the resistance value of the reference resistor Rst built in the semiconductor chip CP may vary due to the stress. This is because, as shown in FIG. 6, when the resistance wiring constituting the reference resistance Rst is deformed by stress, the resistance value fluctuates due to the deformation.

FIG. 6 is a diagram for explaining a change in the resistance value of the resistance wiring due to the stress.
FIG. 6 shows an outline of the resistance wiring constituting the reference resistance Rst. The dimension of the resistance wiring in the extending direction (wiring direction) is the wiring length L, the dimension perpendicular to the wiring direction is the wiring width W, the cross-sectional area perpendicular to the wiring direction is the conductor cross-sectional area A, and the resistance Let the resistivity of the wiring be the resistivity ρ, and let the resistance value of the resistive wiring be the resistance value R.

  The resistance change rate ΔR / R of the resistance wiring is approximated by the equation (5). That is, the resistance change rate ΔR / R of the resistance wiring due to stress is the change rate ΔL / L of the wiring length L due to stress, the change rate ΔA / A of the conductor cross-sectional area A due to stress, and the resistivity ρ due to stress. It is defined by the change rate Δρ / ρ.

  As can be seen from the above equation (5), the fluctuation of the resistance value of the wiring resistance is caused by the change of the wiring resistance shape (wiring length L and cross-sectional area A) due to the stress and the resistivity ρ of the wiring resistance. It is generated by doing. Note that the change in resistivity ρ due to stress is due to the piezoresistance effect. This piezoresistive effect is much greater when the wiring resistance is a semiconductor resistance formed of a silicon film than when the wiring resistance is a metal resistance formed of a metal film. Therefore, when the wiring resistance is a metal resistance, the variation in the resistance value of the wiring resistance mainly occurs due to a change in the shape of the wiring resistance. On the other hand, when the wiring resistance is a semiconductor resistance, the variation of the resistance value of the wiring resistance occurs mainly due to the change in the resistivity ρ.

  As described above, the variation amount of the resistance value of the wiring resistance due to the stress generated in the semiconductor chip CP varies depending on the structure of the wiring resistance. Further, the magnitude of the generated stress itself varies depending on the thermal expansion coefficient of the resin material constituting the sealing resin portion MR. Therefore, in the semiconductor device PKG, if the material of the sealing resin portion MR and the structure of the wiring resistance that constitutes the reference resistance Rst are changed, the amount of variation in the resistance value of the wiring resistance differs, so that the circuit formed in the semiconductor chip CP. The amount of fluctuation of the characteristic value will also change. Therefore, in order to enrich the variation of the semiconductor device PKG, it is necessary to grasp the variation amount of the characteristic value of the circuit due to the stress and appropriately compensate the variation amount for each semiconductor device PKG. This can be labor intensive and costly. Therefore, in order to realize a highly reliable semiconductor device at low cost, it is necessary to guarantee circuit characteristics that are not influenced by stress.

  Therefore, in the first embodiment, the stress sensor 10 is formed on the semiconductor chip CP, and the stress generated in the semiconductor chip CP is detected. Then, the characteristics of the circuit inside the semiconductor chip CP are corrected according to the detected stress. As a result, circuit characteristics independent of stress are realized.

(Configuration of stress sensor)
Next, a specific configuration of the stress sensor 10 mounted on the semiconductor device according to the first embodiment will be described.

  7 to 9 are circuit diagrams for explaining a configuration example of the stress sensor 10. Referring to FIGS. 7 to 9, the stress sensor 10 is a piezoresistive stress sensor, and is configured by combining two types of resistance elements R1 and R2 having different resistance fluctuation amounts with respect to the stress.

  In FIG. 7, the stress sensor 10 includes a resistance bridge circuit connected between the power supply voltage VDD and the ground voltage GND. This resistance bridge circuit is composed of two resistance elements R1 and R2, each including two resistance elements.

  Specifically, the resistance element R1 is a resistance element that is not easily affected by stress, and the resistance element R2 is a resistance element that is easily affected by stress. Therefore, the resistance element R1 has a smaller variation in resistance value with respect to the same stress than the resistance element R2.

  In the stress sensor 10, a potential difference Vo is generated between the two output terminals as the resistance value of each resistance element changes according to the stress. When the resistance value of the resistance element R1 is R1, and the resistance value of the resistance element R2 is R2, the potential difference Vo generated between the two output terminals is expressed by the following formula (6).

  The stress sensor 10 outputs a voltage signal Vo generated at the output terminal via an amplifier (not shown).

  In FIG. 8, the stress sensor 10 includes an inverting amplifier circuit including an operational amplifier 32 and resistance elements R1 and R2. The inverting amplifier circuit applies an input voltage Vref to the inverting input terminal (− terminal) via the resistor R1, and grounds the non-inverting input terminal (+ terminal). Then, negative feedback is applied from the output terminal to the inverting input terminal by the feedback resistor R2. The potential difference Vo generated at the output terminal is expressed by the following equation (7). The stress sensor 10 outputs a voltage signal Vo generated at the output terminal via an amplifier (not shown).

  In FIG. 9, the stress sensor 10 includes a differential amplifier 34 and resistance elements R1 and R2. A constant current Io is supplied to each of the resistance elements R1 and R2 from a constant current source (not shown). The differential amplifier 34 amplifies the voltage difference between the terminal voltage V1 (= Io × R1) of the resistor element R1 and the terminal voltage V2 (= Io × R2) of the resistor element R2 with a predetermined amplification factor A. The voltage signal Vo generated at the output terminal is expressed by the following equation (8).

  As described above, the stress sensor 10 is configured by combining two resistance elements R1 and R2 having different resistance value variations with respect to the same pressure. As a result, the stress sensor 10 outputs a voltage signal Vo proportional to the resistance value ratio (= R2 / R1) of the two resistance elements R1 and R2 or the difference between the resistance values (= R2−R1).

[Configuration of resistance element]
Hereinafter, a specific configuration of the resistance element applied to the stress sensor 10 will be described.

  In the first embodiment, the resistance elements R1 and R2 constituting the stress sensor 10 are formed by semiconductor resistance or metal resistance. Among these, the semiconductor resistance includes a diffusion resistance formed by introducing impurities into the semiconductor substrate and a polysilicon resistance formed by a polycrystalline silicon (polysilicon) film.

  FIG. 10 is a cross-sectional view of the diffusion resistance used for the resistance element of the stress sensor 10. FIG. 10 shows a cross-sectional view of a P-type diffusion resistance (P + diffusion resistance).

  Referring to FIG. 10, P-type diffusion region 104 is an N-side well (N-type semiconductor region) 102 formed over a predetermined depth from the main surface of semiconductor substrate 100 made of P-type single crystal silicon or the like. Further, for example, a P-type impurity such as In (indium) or B (boron) is ion-implanted. An insulating film 108 is deposited on the semiconductor substrate 100 so as to cover the P-type diffusion region 104, and the insulating film 108 is dry-etched to form a contact hole on the P-type diffusion region 104. The electrode 110 is formed by filling the contact hole with a conductor film. As a result, a P-type diffused resistor is formed.

  A resistance formation region, which is a region where a P-type diffusion resistor is formed, is defined by an element isolation region 106 formed on the main surface of the semiconductor substrate 100. The element isolation region 106 is formed by embedding an insulator made of silicon oxide or the like in the element isolation trench by, for example, STI (Shallow Trench Isolation) method.

  FIG. 11 is a diagram showing the relationship between the P-type impurity concentration and the piezoresistance coefficient in the P-type diffusion resistor. Referring to FIG. 11, the piezoresistance coefficient of the P-type diffused resistor changes according to the P-type impurity concentration. The piezoresistance coefficient decreases as the P-type impurity concentration increases. That is, in the P-type diffused resistor, the amount of fluctuation of the resistance value with respect to stress decreases as the P-type impurity concentration increases.

  Therefore, if two P-type diffused resistors having different P-type impurity concentrations are applied to the two resistance elements R1 and R2 of the stress sensor 10 shown in FIGS. The amount of fluctuation can be made different. Specifically, a P-type diffusion resistor having a higher P-type impurity concentration is used as the resistance element R1 that is not easily affected by stress. On the other hand, a P-type diffused resistor having a lower P-type impurity concentration is used as the resistive element R2 that is easily affected by stress.

  The same applies to the configuration using an N-type diffusion resistance (N + diffusion resistance) as the resistance element of the stress sensor 10. FIG. 12 is a cross-sectional view of an N-type diffusion resistor. Referring to FIG. 12, N-type diffusion region 112 is formed by ion-implanting N-type impurities such as P (phosphorus) As (arsenic) into the main surface of semiconductor substrate 100 made of P-type single crystal silicon or the like. Formed by. After the insulating film 108 is deposited so as to cover the N-type diffusion region 112, the insulating film 108 is dry-etched to form a contact hole above the N-type diffusion region 112. Then, the electrode 110 is formed by filling the contact hole with a conductor film. Thereby, an N-type diffused resistor is formed.

  FIG. 11 also shows the relationship between the N-type impurity concentration and the piezoresistance coefficient in the N-type diffused resistor. When the N-type diffusion resistance is used, the tendency of the resistance variation with respect to the stress of the P-type diffusion resistance is reversed. In the N-type diffused resistor as well, as the N-type impurity concentration increases, the piezoresistance coefficient decreases as the N-type impurity concentration increases, so that the amount of change in resistance value with respect to stress decreases. Therefore, an N-type diffused resistor having a higher N-type impurity concentration is used for the resistive element R1 of the stress sensor 10, while an N-type diffused resistor having a lower N-type impurity concentration is used for the resistive element R2. Note that the difference in impurity concentration between the resistance elements R1 and R2 can be realized, for example, by varying the amount of impurity ion implantation.

  FIG. 13 is a cross-sectional view of a polysilicon resistor used in the stress sensor 10. FIG. 13 shows a cross-sectional view of a P-type polysilicon resistor.

  Referring to FIG. 13, in the P-type polysilicon resistor, the polysilicon film 118 deposited on the element isolation region 116 formed on the main surface of the semiconductor substrate 100 is patterned using a photolithography method and a dry etching method. It is formed by doing.

  Sidewall spacers 120 are formed on the side walls of the polysilicon resistor. For example, the sidewall spacer 120 is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 100, and using the RIE (Reactive Ion Etching) method to deposit the silicon oxide film, the silicon nitride film, or the laminated film thereof. It can be formed by anisotropic etching, for example. After the formation of the sidewall spacer 120, a P-type impurity is ion-implanted into the polysilicon film 118. Then, an insulating film 108 is deposited on the semiconductor substrate 100 so as to cover the polysilicon film 118, and a contact hole is formed on the polysilicon film 118 by dry etching the insulating film 108. The electrode 110 is formed by filling the contact hole with a conductor film. As a result, a P-type polysilicon resistor is formed.

  Although not shown, the N-type polysilicon resistor can be formed by ion-implanting N-type impurities into the polysilicon film 118 of FIG.

  Also in the P-type polysilicon resistor and the N-type polysilicon resistor, the piezoresistance coefficient changes according to the concentration of the impurity implanted into the polysilicon film 118, similarly to the above-described diffused resistor. Specifically, like the relationship between the impurity concentration and the piezoresistance coefficient shown in FIG. 10, the piezoresistance coefficient decreases as the impurity concentration increases.

  Therefore, if two polysilicon resistors having different impurity concentrations are applied to the two resistance elements R1 and R2 of the stress sensor 10 shown in FIGS. 7 to 9, the amount of change in the resistance value with respect to the same stress. Can be different. As an example, a P-type polysilicon resistor having a higher P-type impurity concentration is used as the resistance element R1 that is not easily affected by stress. On the other hand, a P-type polysilicon resistor having a lower P-type impurity concentration is used as the resistance element R2 that is susceptible to stress. Alternatively, an N-type polysilicon resistor having a higher N-type impurity concentration is used as the resistance element R1 that is less susceptible to stress, while a lower N-type impurity concentration is used as the resistance element R2 that is more susceptible to stress. An N-type polysilicon resistor is used.

  Alternatively, instead of a configuration in which two semiconductor resistors having different impurity concentrations are applied to the two resistance elements R1, R2 of the stress sensor 10, a metal resistance and a semiconductor resistance may be applied. As described above, since the semiconductor resistance has a very large piezoresistance effect compared to the metal resistance, the amount of fluctuation of the resistance value with respect to the stress increases. Accordingly, a metal resistor can be used as the resistance element R1 that is less susceptible to stress, while a semiconductor resistance can be used as the element R2 that is susceptible to stress.

  Alternatively, in a semiconductor substrate (semiconductor wafer) made of single crystal silicon, two resistance elements R1 and R2 are formed on two different crystal axes by utilizing the fact that the piezoresistance coefficient varies depending on the crystal axes. It is also possible to configure using two diffused resistors.

  FIG. 14 is a diagram showing the crystal axis dependence of the piezoresistance coefficient in a P-type silicon substrate. Referring to FIG. 14, the <110> axis on the crystal plane orientation (100) plane of the P-type silicon substrate has a larger piezoresistance coefficient than the <100> axis. Therefore, it can be seen that the <110> axis is more susceptible to stress than the <100> axis.

  Therefore, as shown in FIG. 15, the resistance element R2 is formed on the <110> axis on the crystal plane orientation (100) plane, and the resistance element R1 is formed in the direction of 45 ° with respect to the <110> axis. .

  Such a dependency of the piezoresistance coefficient on the crystal axis is also observed in the N-type silicon substrate. Therefore, even in the N-type silicon substrate, the stress sensor 10 can be formed by forming the two resistance elements R1 and R2 on the two crystal axes having different piezoresistance coefficients.

  As described above, the magnitude of the piezoresistance coefficient of the semiconductor resistor varies depending on the impurity concentration and the direction of the crystal axis. Furthermore, the semiconductor resistance has a characteristic that when the conductivity type of the impurity is different, the direction of change of the resistance value with respect to the stress is reversed. FIG. 16 is a diagram for explaining a change in resistance value with respect to stress in a P-type polysilicon resistor and an N-type polysilicon resistor. In FIG. 16, the horizontal axis indicates the stress (compressive stress) generated in each polysilicon resistor, and the vertical axis indicates the variation rate of the resistance value in each polysilicon resistor. The variation rate of the resistance value is calculated by (R−Ro) / Ro using the resistance value R and the initial value Ro.

  Referring to FIG. 16, the rate of variation of the P-type polysilicon resistor increases in the negative direction as the stress in the compression direction increases. That is, the P-type polysilicon resistor has a negative stress dependency that the resistance value decreases as the stress increases.

  On the other hand, the variation rate of the N-type polysilicon resistor increases in the positive direction as the stress in the compression direction increases. In other words, the N-type polysilicon resistor has a positive stress dependency that the resistance value increases as the stress increases.

  As described above, the P-type polysilicon resistance and the N-type polysilicon resistance have opposite stress dependencies. Note that the same characteristics apply to the P-type diffusion resistance and the N-type diffusion resistance. Therefore, one of the resistance elements R1 and R2 of the stress sensor 10 is formed by P-type polysilicon resistance (or P-type diffusion resistance), and the other is formed by N-type polysilicon resistance (or N-type diffusion resistance). . Since the difference between the resistance values of these two resistance elements R1 and R2 increases as the stress increases, the stress sensor 10 with high detection accuracy can be realized.

  As shown in FIG. 11, both the P-type polysilicon resistance (or P-type diffusion resistance) and the N-type polysilicon resistance (or N-type diffusion resistance) have resistance values against stress as the impurity concentration decreases. The amount of fluctuation increases. Therefore, the detection accuracy can be further improved by lowering the impurity concentration of each of the P-type polysilicon resistor (or P-type diffused resistor) and the N-type polysilicon resistor (N-type diffused resistor).

(Correction of circuit characteristics in semiconductor chip)
Hereinafter, correction of circuit characteristics using the detected stress value by the stress sensor 10 will be described. In the first embodiment, as an example, as shown in FIG. 17, the characteristic values of the oscillation circuit (the high-speed oscillation circuit OSC1 and the low-speed oscillation circuit OSC2) and the temperature sensor THS are corrected by receiving the detection value of the stress sensor 10, respectively. Will be described.

  First, correction of the oscillation frequency of the high-speed oscillation circuit OSC1 and the low-speed oscillation circuit OSC2 will be described. FIG. 18 is a circuit diagram of the oscillation circuit. The oscillation circuit shown in FIG. 18 is obtained by further providing a correction unit 22 and an addition unit 24 in the oscillation circuit shown in FIG. That is, voltage-current converting unit 11, voltage generating unit 12, and oscillating unit 13 are the same as the configuration shown in FIG.

  The correction unit 22 corrects the voltage Vo input to the VCO 20 based on the detection value of the stress sensor 10. Specifically, the correction unit 22 acquires the relationship between the stress generated in the semiconductor chip CP and the fluctuation amount of the oscillation frequency F of the oscillation unit 13 in advance through experiments or the like, and stores the acquired relationship in a map format. When the detection value of the stress sensor 10 is received, the stored map is referred to and the fluctuation amount of the oscillation frequency F corresponding to the detection value is acquired. Then, a correction amount ΔVo of the input voltage Vo is calculated based on the acquired fluctuation amount.

  The adder 24 adds the correction amount ΔVo to the input voltage Vo and outputs the result to the VCO 20. The VCO 20 outputs an oscillation signal at a frequency F corresponding to the corrected input voltage Vo.

  FIG. 19 is a circuit diagram of the temperature sensor THS. Referring to FIG. 19, temperature sensor THS includes a temperature sensor element 40, an A / D converter 42, and a correction unit 44.

  The temperature sensor element 40 detects the temperature of the semiconductor chip CP and converts it into an electrical signal. The A / D converter 42 converts an electrical signal that is an analog signal generated by the temperature sensor element 40 into a digital signal.

  The correction unit 44 corrects the digital signal output from the A / D converter 42 based on the detection value of the stress sensor 10. Specifically, the correction unit 44 acquires in advance a relationship between the stress generated in the semiconductor chip CP and the amount of change in the output value of the temperature sensor THS through experiments or the like, and stores the acquired relationship in a map format. When the detection value of the stress sensor 10 is received, the stored map is referred to, and the fluctuation amount of the output value corresponding to the detection value is acquired. Then, the output value of the temperature sensor THS is corrected based on the acquired fluctuation amount.

  In this way, in the circuit mounted on the semiconductor chip CP, the characteristic value is corrected based on the detection value of the stress sensor 10. As a result, circuit characteristics independent of stress are realized.

(Example of stress sensor placement on a semiconductor chip)
Below, the example of arrangement | positioning of the stress sensor 10 in the semiconductor chip CP is demonstrated.

  FIG. 20 is a plan view (top view) of the semiconductor chip CP. FIG. 20 shows the main surface 1 side of the semiconductor chip CP. In addition, although illustration is abbreviate | omitted, several pad electrode PD (refer FIG. 1) is arrange | positioned along the four sides at the peripheral part of the main surface 1 of the semiconductor chip CP.

  The planar shape of the semiconductor chip CP is a square shape. In the semiconductor device PKG in which the semiconductor chip CP is sealed with resin, as described above, stress is generated in the semiconductor chip CP due to the resin sealing of the semiconductor chip CP. The stress sensor 10 formed in the semiconductor chip CP detects the stress generated in the semiconductor chip CP.

  FIG. 21 is a diagram showing the result of simulating the stress generated in the semiconductor chip CP. FIG. 21 shows the stress at a position along the solid line L1 in FIG. The horizontal axis in FIG. 21 corresponds to the distance from the center CT of the main surface 1 of the semiconductor chip CP at the position along the solid line L1, and the vertical axis in FIG. 21 represents the stress generated at the position along the solid line L1. Corresponding to The solid line L1 corresponds to a point connecting the center CT of the main surface 1 of the semiconductor chip CP and the center of the side S1. In FIG. 21, σx indicated by a square mark corresponds to a stress in a direction parallel to the side S1, and σy indicated by a diamond mark corresponds to a stress in a direction perpendicular to the side S1.

  Referring to FIG. 21, the stress at the position along solid line L1 in FIG. 20 is smaller in stress σy in the direction perpendicular to side S1 than in stress σx in the direction parallel to side S1. The stress generated in the semiconductor chip CP is a compressive stress (stress is a negative value). In this embodiment, “small stress” means “small absolute value of stress”. Yes.

  As can be seen from FIG. 21, the stress σy in the direction perpendicular to the side S1 decreases as the distance from the center CT of the main surface 1 of the semiconductor chip CP increases, and starts to increase as it approaches the position of the side S1. . On the other hand, the stress σx in the direction parallel to the side S1 hardly changes even when the distance from the center CT is increased, and starts to increase when approaching the position of the side S1. That is, the stress σy in the direction perpendicular to the side S1 has a larger amount of change depending on the distance from the center CT than the stress σx in the direction parallel to the side S1.

  The stress generated in the semiconductor chip CP in this way varies in magnitude depending on the distance from the center CT of the main surface 1 of the semiconductor chip CP. Therefore, depending on the relative positional relationship between the stress sensor 10 and the circuit, there is a possibility that a deviation occurs between the stress detected by the stress sensor 10 and the stress actually acting on the circuit. For example, when the stress sensor 10 is disposed at a position where the distance from the center CT is small and a circuit is disposed at a position where the distance from the center CT is large along the solid line L1 in FIG. The stress actually acting on the circuit is larger than that. As a result, there is a possibility that the correction of the characteristic value based on the detection value of the stress sensor 10 cannot be performed accurately.

  Therefore, in the first embodiment, the stress sensor 10 is arranged close to the circuit. Thereby, the deviation between the detection value of the stress sensor 10 and the stress acting on the circuit is reduced.

  FIG. 22 is a plan layout diagram showing an example of the arrangement of the stress sensor 10 and the circuit block. In FIG. 22, as an example, the arrangement of the stress sensor 10, the high-speed oscillation circuit OSC1, the low-speed oscillation circuit OSC2, the temperature sensor THS, and the logic circuit LOG will be described.

  Referring to FIG. 22, stress sensor 10 is arranged in a central region including center CT of the main surface of semiconductor chip CP. Then, the oscillation circuits OSC1, OSC2, the temperature sensor THS, and the logic circuit LOG are arranged so as to surround the stress sensor 10.

  As shown in FIG. 21, in the vicinity of the center CT of the main surface of the semiconductor chip CP, the amount of change in stress σx, σy due to the distance from the center CT is small. Therefore, by collecting and arranging the stress sensor 10 and circuits that are susceptible to the stress generated in the semiconductor chip CP in the region near the center CT, each circuit can be obtained using the detection value of one stress sensor 10. It is possible to compensate for fluctuations in the characteristic value.

  FIG. 23 is a plan layout view showing another example of the arrangement of the stress sensor 10 and the circuit block. In FIG. 23, the arrangement of the stress sensor 10 and the high-speed oscillation circuit OSC1 and the low-speed oscillation circuit OSC2 will be described.

  Referring to FIG. 23, stress sensor 10 is arranged in a central region including center CT of the main surface of semiconductor chip CP. On the other hand, the high-speed oscillation circuit OSC1 and the low-speed oscillation circuit OSC2 are arranged near the outer periphery of the main surface of the semiconductor chip CP, that is, in the end region.

  As shown in FIG. 23, when the oscillation circuits OSC1 and OSC2 cannot be disposed close to the stress sensor 10 due to the layout of the semiconductor chip CP, the reference resistor Rst included in each oscillation circuit is set to the semiconductor chip CP. It arrange | positions in the direction parallel to edge | side S1.

  As shown in FIG. 21, the stress σx in the direction parallel to the side S1 hardly changes with the distance from the center CT, while the stress σy in the direction perpendicular to the side S1 changes with the distance from the center CT. By disposing the reference resistor Rst in a direction parallel to the side S1, the resistance value of the reference resistor Rst mainly varies in response to the stress σx in the direction parallel to the side S1. Since the stress σx is almost the same as the stress detected by the stress sensor 10, the oscillation frequency F can be corrected based on the detected value of the stress sensor 10. Also in FIG. 23, similarly to FIG. 22, the variation in the characteristic value of each circuit can be compensated using the detection value of one stress sensor 10.

  FIG. 24 is a plan layout diagram showing another example of the arrangement of the stress sensor 10 and the circuit block. In FIG. 24, the arrangement of the stress sensor 10, the high-speed oscillation circuit OSC1, the low-speed oscillation circuit OSC2, and the temperature sensor THS will be described as an example.

  Referring to FIG. 24, each of oscillation circuits OSC1 and OSC2 and temperature sensor THS is arranged near the outer periphery of main surface 1 of semiconductor chip CP, that is, in an end region.

  When the stress sensor 10 cannot be arranged near the center CT of the main surface of the semiconductor chip CP due to the layout of the semiconductor chip CP, a stress sensor is built in for each circuit as shown in FIG.

  By incorporating the stress sensor 10A in the high-speed oscillation circuit OSC1, the stress sensor 10A can accurately detect the stress acting on the reference resistance Rst inside the high-speed oscillation circuit OSC1. Thereby, the oscillation frequency F of the high-speed oscillation circuit OSC1 can be corrected accurately based on the detection value of the stress sensor 10A. Similarly, the low-speed oscillation circuit OSC2 and the temperature sensor THS can correct the characteristic values accurately based on the detection values of the built-in stress sensors 10B and 10C.

  As described above, according to the semiconductor device according to the first embodiment, the stress generated in the semiconductor chip is detected by forming the stress sensor on the semiconductor chip, and the circuit built in the semiconductor chip is detected according to the detected stress. Correct the characteristics. Thereby, it is possible to guarantee the characteristics of the built-in circuit with high accuracy irrespective of the structure of the package for sealing the semiconductor chip.

[Embodiment 2]
In the semiconductor device according to the first embodiment described above, the relationship between the resistance values of the resistance elements R1 and R2 and the stress in the stress sensor 10 changes according to the temperature of the semiconductor chip CP. For this reason, the detection accuracy of the stress sensor 10 may be deteriorated due to the influence of temperature.

  In the second embodiment, the configuration of the stress sensor for making the detection value of the stress sensor independent of the temperature of the semiconductor chip CP will be described.

  FIG. 25 is a circuit diagram of the semiconductor chip CP constituting the semiconductor device according to the second embodiment.

  Referring to FIG. 25, the semiconductor chip CP according to the second embodiment is obtained by providing a stress sensor 10A instead of the stress sensor 10 in the semiconductor chip CP according to the first embodiment.

  The stress sensor 10A detects the stress generated in the semiconductor chip CP and outputs the detected value to each circuit built in the semiconductor chip CP. FIG. 25 illustrates a case where the characteristic values of the oscillation circuit (the high-speed oscillation circuit OSC1 and the low-speed oscillation circuit OSC2) and the temperature sensor THS are corrected by receiving the detection value of the stress sensor 10A.

  The temperature sensor THS corrects the output value based on the detection value of the stress sensor 10A using the configuration shown in FIG. The temperature sensor THS feeds back the corrected output value to the stress sensor 10A. The stress sensor 10A corrects the detected stress value based on the output value of the temperature sensor THS.

FIG. 26 is a circuit diagram for explaining a configuration example of the stress sensor 10A.
Referring to FIG. 26, stress sensor 10A according to the second embodiment is a piezoresistive type stress sensor similar to stress sensor 10 shown in FIG. The resistor elements R1 and R2 are combined.

  As shown in the first embodiment, the resistance elements R1 and R2 have two identical conductivity type semiconductor resistors (diffused resistors or polysilicon resistors) having different impurity concentrations, or the directions of crystal axes are mutually different. Two different diffusion resistors of the same conductivity type can be used.

  Alternatively, a metal resistor may be used for one of the resistance elements R1 and R2, and a semiconductor resistor may be used for the other. Alternatively, two semiconductor resistors having different conductivity types may be used for the resistance elements R1 and R2.

  When the resistance values of the resistance elements R1 and R2 change according to the stress, a potential difference Vo is generated between the output terminals of the stress sensor 10A. When the resistance value of the resistance element R1 is R1, and the resistance value of the resistance element R2 is R2, the potential difference Vo is expressed by the following equation (9).

  In the second embodiment, in a state where no stress is generated in the semiconductor chip CP, the difference between the resistance values of the two resistance elements R1 and R2 (= R2−R1) is zero regardless of the temperature of the semiconductor chip CP. Resistive elements R1 and R2 are formed so that Specifically, one of the resistance elements R1 and R2 is formed using two semiconductor resistors having different impurity concentrations. A configuration in which the resistance element R1 is formed using two semiconductor resistors Ra and Rb having different impurity concentrations will be described with reference to FIG.

  Referring to FIG. 27, resistance element R1 includes two semiconductor resistors Ra and Rb connected in series. With respect to the semiconductor resistance Ra, when the resistance value at a certain reference temperature To is Rao and the primary temperature coefficient is Ka, the temperature characteristic of the resistance value Ra at the temperature T can be approximated by the following equation (10).

However, ΔT = T−To.
Similarly, for the semiconductor resistor Rb, when the resistance value at the reference temperature To is Rbo and the primary temperature coefficient is Kb, the resistance value Rb at the temperature T can be approximated by the following equation (11).

  The resistance element R1 is formed by combining these two semiconductor resistors Ra and Rb at a ratio of α: β. Note that the ratio of α: β can be adjusted by the wiring length La and wiring width Wa of the semiconductor resistor Ra and the wiring length Lb and wiring width Wb of the semiconductor resistor Rb.

  The resistance value R1 at the temperature T of the resistance element R1 can be expressed as the following formula (12) by using the above formulas (10) and (11).

  On the other hand, regarding the semiconductor resistance Rc constituting the resistance element R2, the resistance value R2 at the temperature T can be approximated by the following equation (13), where Rco is the resistance value at the reference temperature To and Kc is the primary temperature coefficient.

  Here, as described above, in order to make the difference between the resistance values of the resistance elements R1 and R2 (= R2−R1) zero regardless of the temperature T in a state where no stress is generated in the semiconductor chip CP, The variables α and β may be determined so that R1 shown in the above equation (12) is equal to R2 shown in the above equation (13). The variables α and β can be calculated by solving the following equations (14) and (15).

  In this way, of the potential difference Vo shown in the above formula (9), the difference between the resistance values of the resistance elements R1 and R2 (= R2−R1) becomes zero regardless of the temperature of the semiconductor chip CP. Therefore, by correcting the magnitude of the power supply voltage VDD according to the output value of the temperature sensor THS so that the remaining VDD / (R1 + R2) is constant regardless of the temperature, the potential difference Vo is set to a value that does not depend on the temperature. can do.

(Modification of Embodiment 2)
When the resistance values of the resistance elements R1 and R2 are approximated considering the secondary temperature characteristics, each of the resistance elements R1 and R2 is formed using two semiconductor resistors having different impurity concentrations. Specifically, the resistor element R1 is formed by combining two semiconductor resistors Ra and Rb at a ratio of α: β, and the resistor element R2 is combined with two semiconductor resistors Rc and Rd at a ratio of 1: γ. Form.

  With respect to the semiconductor resistance Ra, when the resistance value at a certain reference temperature To is Rao, the primary temperature coefficient is Ka1, and the secondary temperature coefficient is Ka2, the temperature characteristic of the resistance value Ra at the temperature T is expressed by the following formula (16 ).

However, ΔT = T−To.
Similarly, for the semiconductor resistor Rb, when the resistance value at the reference temperature To is Rbo, the primary temperature coefficient is Kb1, and the secondary temperature coefficient is Kb2, the resistance value Rb at the temperature T is expressed by the following equation (17). Can be approximated by

  The resistance element R1 is formed by combining these two semiconductor resistors Ra and Rb at a ratio of α: β. The resistance value R1 at the temperature T of the resistance element R1 can be expressed as the following formula (18) by using the above formulas (16) and (17).

  Similarly, regarding the semiconductor resistance Rc, when the resistance value at the reference temperature To is Rco, the primary temperature coefficient is Kc1, and the secondary temperature coefficient is Kc2, the temperature characteristic of the resistance value Rc at the temperature T is expressed by the following equation. It can be approximated by (19).

However, ΔT = T−To.
Similarly, for the semiconductor resistor Rd, when the resistance value at the reference temperature To is Rdo, the primary temperature coefficient is Kd1, and the secondary temperature coefficient is Kd2, the resistance value Rb at the temperature T is expressed by the following equation (20). Can be approximated by

  The resistance element R2 is formed by combining these two semiconductor resistors Rc and Rd at a ratio of 1: γ. The resistance value R2 at the temperature T of the resistance element R2 can be expressed as the following formula (21) by using the above formulas (19) and (20).

  Here, as described above, in order to make the difference between the resistance values of the resistance elements R1 and R2 (= R2−R1) zero regardless of the temperature T in a state where no stress is generated in the semiconductor chip CP, The variables α, β, and γ may be determined so that R1 shown in the equation (18) is equal to R2 shown in the equation (21). The variables α, β, and γ can be calculated by solving the following equations (22), (23), and (24).

  In this way, of the potential difference Vo shown in the above formula (9), the difference between the resistance values of the resistance elements R1 and R2 (= R2−R1) becomes zero regardless of the temperature of the semiconductor chip CP. Therefore, by correcting the magnitude of the power supply voltage VDD according to the output value of the temperature sensor THS so that the remaining VDD / (R1 + R2) is constant regardless of the temperature, the potential difference Vo is set to a value that does not depend on the temperature. can do.

  Thus, according to the semiconductor device according to the second embodiment, it is possible to prevent the detection accuracy of the stress sensor formed on the semiconductor chip from being deteriorated due to the influence of temperature. This makes it possible to guarantee the characteristics of the circuit built in the semiconductor chip with higher accuracy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  DESCRIPTION OF SYMBOLS 1 Main surface, 2 Back surface, 3 Adhesive material, 10, 10A-10C Stress sensor, 11 Voltage current conversion part, 12 Voltage generation part, 13 Oscillation part, 20 VCO, 22,44 Correction part, 24 Addition part, 30 Control signal Generator, 40 Temperature sensor element, 42 A / D converter, 100 Semiconductor substrate, 102 N-side well, 104 P-type diffusion region, 106, 116 Element isolation region, 108 Insulating film, 110 electrode, 112 N-type diffusion region, 118 Polysilicon film, 120 sidewall spacer, CP semiconductor chip, OSC oscillation circuit area, RAM RAM area, LOG logic circuit area, FLA flash memory area, AD AD / DA area, IF I / F circuit area, PC power supply circuit area, PD pad electrode, PKG semiconductor device, MR sealing resin part, BW bonding Ear, DP die pad, LD lead, Rst reference resistor, THS temperature sensor.

Claims (12)

A plurality of circuits formed on the main surface of the semiconductor substrate;
A stress sensor that is formed on a main surface of the semiconductor substrate and detects stress acting on the plurality of circuits;
The stress sensor is
A first semiconductor resistor of a first conductivity type formed on a main surface of the semiconductor substrate and having a first impurity concentration;
A semiconductor device comprising: a second semiconductor resistor of the first conductivity type formed on a main surface of the semiconductor substrate and having a second impurity concentration lower than the first impurity concentration. The stress sensor is configured to output an electrical signal in accordance with a ratio or difference between the resistance values of the first and second resistance elements having different resistance values for the same stress.
The first semiconductor resistor constitutes the first resistance element,
The semiconductor device according to claim 1, wherein the second semiconductor resistor constitutes the second resistance element. The first semiconductor resistor is a diffusion resistor of the first conductivity type having the first impurity concentration;
The semiconductor device according to claim 2, wherein the second semiconductor resistor is a diffusion resistor of the first conductivity type having the second impurity concentration. The first semiconductor resistor is a polycrystalline silicon resistor of the first conductivity type having the first impurity concentration;
The semiconductor device according to claim 2, wherein the second semiconductor resistor is a polycrystalline silicon resistor of the first conductivity type having the second impurity concentration. The stress sensor is configured to output an electrical signal in accordance with a ratio or difference between the resistance values of the first and second resistance elements having different resistance values for the same stress.
The first resistance element is formed by combining the first semiconductor resistance and the second semiconductor resistance in a first ratio,
The first ratio is set such that resistance values of the first and second resistance elements when no stress is applied to the first and second resistance elements are equal regardless of temperature. The semiconductor device according to claim 1.   6. The semiconductor device according to claim 5, wherein the second resistance element is a second conductivity type semiconductor resistance. The second resistance element is formed by combining the second conductivity type third semiconductor resistor and the fourth semiconductor resistor having different impurity concentrations in a second ratio,
The first and second ratios are such that the resistance values of the first and second resistance elements when stress is not acting on the first and second resistance elements are equal regardless of temperature. The semiconductor device according to claim 6, wherein   The semiconductor device according to claim 5, wherein the second resistance element is a metal resistance. The first semiconductor resistor and the second semiconductor resistor are diffusion resistors formed in the first conductivity type impurity region on the main surface of the semiconductor substrate in the direction of the first crystal axis,
The semiconductor device according to claim 5, wherein the second resistance element is a diffused resistor formed in a direction of a second crystal axis in the impurity region of the first conductivity type on the main surface of the semiconductor substrate.   10. The semiconductor device according to claim 1, further comprising a correction unit configured to correct characteristic values of the plurality of circuits in accordance with a detection value of the stress sensor.   The semiconductor device according to claim 10, wherein each of the stress sensor and the plurality of circuits is disposed in proximity to a main surface of the semiconductor substrate. At least one of the plurality of circuits includes a third resistance element formed on the main surface of the semiconductor substrate,
The semiconductor device according to claim 11, wherein the third resistance element is arranged in a direction parallel to one chip side of the semiconductor device.

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