WO2021077355A1 - 阵列基板及其制造和控制方法、显示装置 - Google Patents

阵列基板及其制造和控制方法、显示装置 Download PDF

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Publication number
WO2021077355A1
WO2021077355A1 PCT/CN2019/113025 CN2019113025W WO2021077355A1 WO 2021077355 A1 WO2021077355 A1 WO 2021077355A1 CN 2019113025 W CN2019113025 W CN 2019113025W WO 2021077355 A1 WO2021077355 A1 WO 2021077355A1
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Prior art keywords
pixel
sub
light
array substrate
electrode
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PCT/CN2019/113025
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English (en)
French (fr)
Inventor
张超群
杨玉清
李锡平
官家建
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980002110.2A priority Critical patent/CN112997316A/zh
Priority to PCT/CN2019/113025 priority patent/WO2021077355A1/zh
Priority to US16/982,080 priority patent/US11568821B2/en
Publication of WO2021077355A1 publication Critical patent/WO2021077355A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing and control method thereof, and a display device.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing and control method thereof, and a display device.
  • the technical solutions are as follows:
  • an array substrate in one aspect, includes a base substrate, and a first sub-pixel, a second sub-pixel, and a dummy sub-pixel located in a display area of the base substrate.
  • the display area Having a notch, and in a target direction close to the notch along the center of the display area, the brightness attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel;
  • Each sub-pixel includes: a pixel circuit, a connection electrode, a light-emitting layer, and an electrode layer.
  • the light-emitting layer is electrically connected to the pixel circuit through the connection electrode, and the light-emitting layer is also electrically connected to the electrode layer.
  • the pixel circuit is used to drive the light-emitting layer to emit light through the connecting electrode, and the light-emitting layer in the dummy sub-pixel and the light-emitting layer in the first sub-pixel are used to emit light of the same color.
  • the connecting electrode of the dummy sub-pixel and the connecting electrode of the first sub-pixel are located in the same layer.
  • the area of the orthographic projection of the connecting electrode on the base substrate is less than or equal to the area of the orthographic projection of the light-emitting layer on the base substrate.
  • the ratio of the area of the orthographic projection of the connecting electrode on the base substrate to the area of the orthographic projection of the light-emitting layer on the base substrate is in the range of : 7% to 15%.
  • the array substrate further includes: auxiliary electrodes, and the auxiliary electrodes and the connecting electrodes in the dummy sub-pixels are sequentially arranged in a direction away from the base substrate;
  • the pixel circuit of the dummy sub-pixel, the auxiliary electrode, the connecting electrode of the dummy sub-pixel, and the light-emitting layer of the dummy sub-pixel are electrically connected in sequence.
  • the auxiliary electrode and the source and drain in the pixel circuit of the dummy sub-pixel are located in the same layer.
  • the array substrate further includes: a data line, a power signal line, a first shift register GOA unit, and a first shift register EOA unit;
  • the data line, the power signal line, the first GOA unit, and the first EOA unit are all electrically connected to the pixel circuit of the dummy sub-pixel;
  • the data line is used to provide a data signal to the pixel circuit of the virtual sub-pixel
  • the power signal line is used to provide a power signal to the pixel circuit of the virtual sub-pixel
  • the first GOA unit is used to provide
  • the pixel circuit of the dummy sub-pixel provides a gate driving signal
  • the first EOA unit is used to provide a light emission control signal to the pixel circuit of the dummy sub-pixel.
  • the array substrate further includes: a virtual GOA unit and a virtual EOA unit, and both the virtual GOA unit and the virtual EOA unit are electrically connected to the pixel circuit of the first sub-pixel. Pixels and the virtual sub-pixels are arranged in sequence along the target direction and are adjacent to each other;
  • the first EOA unit, the first GOA unit, and the first sub-pixel are arranged in sequence along the gate line scanning direction, and the virtual GOA unit and the first GOA unit are arranged in sequence along the target direction, The virtual EOA unit and the first EOA unit are arranged in sequence along the target direction;
  • the virtual EOA unit, the virtual GOA unit, and the first sub-pixel are sequentially arranged along the gate line scanning direction, and the virtual GOA unit and the first GOA unit are sequentially arranged along the direction opposite to the target direction.
  • the virtual EOA unit and the first EOA unit are arranged in sequence along a direction opposite to the target direction.
  • the array substrate further includes: at least one switch circuit corresponding to at least one signal line in the signal line set;
  • Each of the signal lines includes two conductive segments, and the two conductive segments are electrically connected by a switch circuit corresponding to the signal line.
  • the signal line set includes: the data line, the power signal line, and the A signal line electrically connected between the first GOA unit and the pixel circuit of the dummy sub-pixel, and a signal line electrically connected between the first EOA unit and the pixel circuit of the dummy sub-pixel;
  • the switch circuit is also electrically connected to the control signal terminal, and the switch circuit is used to control the on-off state of the two conductive sections electrically connected in response to the control signal provided by the control signal terminal.
  • the at least one switch circuit includes: a switch circuit corresponding to the data line, and a switch circuit corresponding to the power signal line.
  • the switch circuit includes: a transistor
  • the gate of the transistor is electrically connected to the control signal terminal, the first electrode of the transistor is electrically connected to a conductive section of a signal line, and the second electrode of the transistor is electrically connected to the other of the signal line. Segment electrical connection.
  • the array substrate further includes: a third sub-pixel located in the display area;
  • the colors of the light emitted by the first sub-pixel, the second sub-pixel, and the third sub-pixel are different, and in the gate line scanning direction, between the second sub-pixel and the third sub-pixel
  • Two sub-pixels for emitting light of a target color are arranged side by side, and the target color is the same as the color of the light emitted by the first sub-pixel.
  • the first sub-pixel is a green sub-pixel
  • the second sub-pixel is a red sub-pixel
  • the third sub-pixel is a blue sub-pixel.
  • a manufacturing method of an array substrate includes:
  • the pixel circuit structure includes: a pixel circuit of each sub-pixel, the driving electrode structure includes a connecting electrode of each sub-pixel, the light-emitting layer structure includes a light-emitting layer of each sub-pixel, and the electrode layer
  • the structure includes the electrode layer of each sub-pixel, and in each of the sub-pixels, the light-emitting layer is electrically connected to the pixel circuit through the connection electrode, and the light-emitting layer is also electrically connected to the electrode layer ,
  • the pixel circuit is used to drive the light-emitting layer to emit light through the connecting electrode;
  • the display area has a gap, and in a target direction near the gap along the center of the display area, the brightness attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel, and the virtual sub-pixel
  • the light-emitting layer of the pixel and the light-emitting layer of the first sub-pixel are used to emit light of the same color.
  • the array substrate further includes: auxiliary electrodes that are electrically connected to the connection electrodes of the dummy sub-pixels; and the pixel circuit structure, the driving electrode structure, the pixel circuit structure, the driving electrode structure, and the pixel circuit structure are sequentially formed in the display area of the base substrate.
  • Light-emitting layer structure and electrode layer structure including:
  • a gate pattern, an active layer pattern, and a source/drain pattern are formed on one side of the base substrate to obtain the pixel circuit structure, wherein the source/drain pattern includes the source/drain of each sub-pixel and The auxiliary electrode, the active layer pattern includes the active layer of each sub-pixel, and the gate pattern includes the gate of each sub-pixel;
  • the electrode layer structure is formed on the side of the light-emitting layer structure away from the base substrate.
  • a method for driving an array substrate for driving the array substrate as described in the above aspect, and the method includes:
  • a driving signal is provided to the pixel circuit of the dummy sub-pixel, and the pixel circuit of the dummy sub-pixel drives the light-emitting layer of the dummy sub-pixel to emit light through the connection electrode of the dummy sub-pixel in response to the driving signal.
  • the array substrate further includes: at least one switch circuit corresponding to at least one signal line in the signal line set, the switch circuit is also electrically connected to the control signal terminal;
  • the circuit provides driving signals, including:
  • control signal terminal Provides a control signal to the control signal terminal, and the switch circuit controls the conduction of the two conductive sections electrically connected thereto in response to the control signal;
  • the data signal is provided to the data line
  • the power signal is provided to the power signal line
  • the compensation signal is provided to the first GOA unit
  • the compensation signal is provided to the first EOA unit.
  • a control device for an array substrate is provided, the control device is electrically connected to a pixel circuit of a virtual sub-pixel, and the control device is used to execute the driving method of the array substrate as described in the above aspect.
  • a display device comprising: the array substrate according to the above-mentioned aspect, and the control device of the array substrate according to the above-mentioned aspect.
  • FIG. 1 is a schematic structural diagram of a special-shaped screen provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of a special-shaped screen recorded in related technologies
  • FIG. 3 is a schematic diagram of the substrate structure of a special-shaped screen recorded in the related art
  • FIG. 4 is a schematic diagram of a test result provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of another test result provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of another test result provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of yet another test result provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of still another test result provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of yet another test result provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • 15 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 16 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 17 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 18 is a flowchart of another method for manufacturing an array substrate provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of an array substrate formed with a pixel circuit structure provided by an embodiment of the present disclosure.
  • 20 is a schematic diagram of an array substrate formed with a driving electrode structure provided by an embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of an array substrate formed with a light-emitting layer structure provided by an embodiment of the present disclosure
  • 22 is a schematic diagram of an array substrate formed with an electrode layer structure provided by an embodiment of the present disclosure.
  • FIG. 23 is a flowchart of a driving method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 24 is a flowchart of another method for driving an array substrate provided by an embodiment of the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable.
  • the source electrode is referred to as the first electrode and the drain electrode is referred to as the second electrode, or the drain electrode is referred to as the first electrode and the source electrode is referred to as the second electrode.
  • the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistors used in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is high, and it is turned off when the gate is low.
  • multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential.
  • the first potential and the second potential only represent that the signal’s potential has two different state quantities, and does not represent the first potential in the full text.
  • the potential or the second potential has a specific value.
  • FIG. 1 is a schematic structural diagram of a special-shaped screen provided by an embodiment of the present disclosure.
  • a side of the display area A1 of the special-shaped screen has a gap K1
  • the display area A1 includes a plurality of effective sub-pixels
  • the display area A1 is close to the gap K1 side
  • the side away from the gap K1 is not
  • the display area includes a plurality of dummy pixels.
  • the effective sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels
  • the virtual sub-pixels may include red virtual sub-pixels, green virtual sub-pixels, and blue virtual sub-pixels.
  • the arrangement of the sub-pixels in each row can be an RGGB arrangement, that is, the sub-pixels in each row can be arranged in accordance with a red sub-pixel, two green sub-pixels and a blue sub-pixel arranged side by side. It should be noted that the provision of multiple virtual sub-pixels can protect the effective sub-pixels and ensure the uniformity of the sub-pixel arrangement.
  • the shapes of the green sub-pixels and the green virtual sub-pixels are both pentagons
  • the shapes of the blue sub-pixels and the blue virtual sub-pixels are both hexagons
  • the red sub-pixels and the red virtual sub-pixels are all oval.
  • the area of the orthographic projection of the two green sub-pixels arranged side by side on the base substrate, the area of the orthographic projection of the red sub-pixel on the base substrate, and the area of the orthographic projection of the blue sub-pixel on the base substrate are the same .
  • the orthographic projection area of the two green virtual sub-pixels arranged side by side on the base substrate, the orthographic projection area of the red virtual sub-pixel on the base substrate, and the orthographic projection of the blue virtual sub-pixel on the base substrate The area is the same.
  • each effective sub-pixel the pixel circuit and the light-emitting layer included in each effective sub-pixel are electrically connected, and each effective sub-pixel can be used for display.
  • Each virtual sub-pixel only includes a pixel circuit and a light-emitting layer, and the light-emitting layer is not electrically connected to the pixel circuit, that is, the virtual sub-pixels included in the related-art special-shaped screen display device are not used for display.
  • FIG. 3 uses adjacent effective green sub-pixels and virtual green sub-pixels as examples to introduce a special-shaped screen array substrate recorded in the related art. As shown in FIG.
  • the effective green sub-pixel P1 includes a light-emitting layer P11, a pixel circuit P12, and a connection electrode P13 electrically connecting the pixel circuit P12 and the light-emitting layer P11.
  • the dummy green sub-pixel P2 only includes: a light-emitting layer P21 and a pixel circuit P22, and the light-emitting layer P21 and the pixel circuit P22 are not electrically connected.
  • the array substrate further includes multiple insulating layers (not labeled in the figure).
  • the special-shaped screen may also include multiple effective shift register GOA units located on one side of the display area A1, multiple effective shift register EOA units, and more A dummy GOA unit and a plurality of dummy EOA units.
  • the effective GOA unit and the effective EOA may be electrically connected to the pixel circuit of the effective sub-pixel and used to provide driving signals to the pixel circuit.
  • the virtual GOA unit and the virtual EOA unit are not connected to any sub-pixels, that is, the virtual GOA unit and the virtual EOA unit are not used for driving and have no contribution to the display.
  • the brightness attenuation degree L_B of the sub-pixel is 25%. Comparing the brightness attenuation degrees of the three color sub-pixels, it can be determined that along the target direction X1, the brightness attenuation degree of the green sub-pixel is greater than the brightness attenuation degree of the blue sub-pixel and the red sub-pixel. Correspondingly, the display color on the side close to the gap K1 is unbalanced. For example, the test results: the color component Gx of the red sub-pixel on the side close to the gap K1 is 0.0018, and the color component Rx of the green sub-pixel is 0.0002, that is, the color component of the green sub-pixel The color component is smaller than the color component of the red sub-pixel.
  • FIGS. 4 to 9 are schematic diagrams of test results of performing a brightness test and a color test on the display screen shown in FIG. 2 provided by an embodiment of the present disclosure.
  • the color test uses the Commission Internationale de L'Eclairage (CIE) as the test standard.
  • CIE Commission Internationale de L'Eclairage
  • the abscissa X in Figures 4 to 9 refers to each sub-pixel point collected along the target direction X1
  • the ordinate Y of the test result shown in Figure 4 refers to the color component of the red sub-pixel in the X-axis direction of the CIE.
  • the ordinate Y of the test result shown in 5 refers to the color component of the green sub-pixel in the X-axis direction of the CIE
  • the ordinate Y of the test result shown in Figure 6 refers to the color component of the red sub-pixel in the Y-axis direction of the CIE.
  • the ordinate of the test result shown in 7 refers to the color component of the green sub-pixel in the Y-axis direction of the CIE.
  • the ordinate Y of the test result shown in Fig. 8 refers to the brightness value of the red sub-pixel.
  • the test result shown in Fig. 9 The ordinate Y refers to the brightness value of the green sub-pixel.
  • the embodiments of the present disclosure provide an array substrate, which can solve the problem of poor display effect of the related art special-shaped screen display device.
  • the non-virtual sub-pixels described in the following embodiments are all effective sub-pixels that can normally emit light
  • the non-virtual GOA units are all effective GOA units
  • the non-virtual EOA units are all effective EOA units
  • the pixels included in the array substrate The transistors in the circuit are all bottom gate structures.
  • the transistor of the pixel circuit may also have a top gate structure, which is not described in the embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate may include: a base substrate 00, and a first sub-pixel 10, a second sub-pixel 20, and a dummy sub-pixel 30 located in the display area A1 of the base substrate 00.
  • the display area A1 of the base substrate 00 has a gap K1, and in the target direction X1 near the gap K1 along the center of the display area A1, the brightness attenuation of the first sub-pixel 10 is greater than that of the second sub-pixel 20 The degree of brightness attenuation.
  • each sub-pixel may include a pixel circuit, a connecting electrode, a light-emitting layer, and an electrode layer.
  • its light-emitting layer can be electrically connected to its pixel circuit through its connecting electrode, and its light-emitting layer is also electrically connected to its electrode layer, and the pixel circuit can drive the light-emitting layer to emit light through the connecting electrode.
  • the light-emitting layer of the dummy sub-pixel 30 and the light-emitting layer of the first sub-pixel 10 can emit light of the same color. For example, assuming that the first sub-pixel 10 is a green sub-pixel, the light-emitting layer of the dummy sub-pixel 30 can emit green light.
  • the dummy sub-pixel 30 may include: a connecting electrode 301, a pixel circuit 302, a light-emitting layer 303, and an electrode layer 304.
  • the light-emitting layer 303 and the pixel circuit 302 can be electrically connected through the connecting electrode 301, and the light-emitting layer 303 is also electrically connected to the electrode layer 304.
  • the pixel circuit 302 can drive the light-emitting layer 303 to emit light through the connecting electrode 301.
  • the dummy sub-pixel 30 for emitting the same color as the light emitted by the first sub-pixel further includes a connecting electrode 301, and the connecting electrode 301
  • the pixel circuit 302 and the light-emitting layer 303 of the dummy sub-pixel 30 may be electrically connected.
  • the virtual sub-pixel 30 can be driven to emit light to compensate for the brightness attenuation of the first sub-pixel 10 with a greater degree of brightness attenuation, that is, the virtual sub-pixel 30 can be driven to emit light to reduce the effective sub-pixel (such as the first The difference in the brightness attenuation of the sub-pixel 10 and the second sub-pixel 20) indicates that the display device manufactured by the array substrate has a better display effect.
  • the display area A1 also includes a blue sub-pixel
  • the virtual sub-pixel 30 emits light, which can effectively reduce the difference in brightness attenuation of the three-color sub-pixels, and accordingly, it can effectively avoid the redness caused by the large brightness attenuation of the first sub-pixel.
  • the embodiments of the present disclosure provide an array substrate.
  • the array substrate includes a first sub-pixel, a second sub-pixel, and a dummy sub-pixel.
  • the brightness attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel, and the light-emitting layer of the dummy sub-pixel
  • the color of the emitted light is the same as the color of the light emitted by the first sub-pixel.
  • the dummy sub-pixel also includes a connection electrode electrically connecting its pixel circuit and the light-emitting layer, and the pixel circuit can drive the dummy sub-pixel to emit light through the connection electrode, the brightness of the first sub-pixel can be compensated by controlling the dummy sub-pixel to emit light. Attenuation, that is, the difference in brightness attenuation between the first sub-pixel and the second sub-pixel can be reduced by controlling the virtual sub-pixel to emit light, and the display device made of the array substrate has a better display effect.
  • the connecting electrode and the electrode layer may both be an anode or a cathode for driving the light-emitting layer to emit light, and the connecting electrode and the electrode layer may be different.
  • the connection electrode is used as the anode and the electrode layer is used as the cathode as an example for description.
  • FIG. 12 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • the connecting electrode 301 of the dummy sub-pixel 30 and the connecting electrode 101 of the first sub-pixel 10 may be located in the same layer.
  • the connecting electrode 301 and the connecting electrode 101 can be formed by one patterning process, and the connecting electrode 301 and the connecting electrode 101 can be the same type of electrode. That is, if the connecting electrode 101 is an anode, the connecting electrode 301 is an anode; if the connecting electrode 101 is a cathode, the connecting electrode 301 is a cathode. Avoid increasing the manufacturing cost and the complexity of the manufacturing process.
  • the light-emitting brightness of the light-emitting layer is proportional to the effective area of the connecting electrode, and the effective area refers to the orthographic projection of the connecting electrode on the base substrate and the light-emitting layer on the base substrate.
  • the overlap area of the orthographic projection That is, for each sub-pixel, the larger the effective area of the connecting electrode, the stronger the brightness of the light-emitting layer, and the smaller the effective area of the connecting electrode, the weaker the brightness of the light emitted.
  • the area of the orthographic projection of the connecting electrode 301 on the base substrate 00 may be less than or equal to the area of the orthographic projection of the light-emitting layer 303 on the base substrate 00.
  • the area of the orthographic projection of the connecting electrode 301 on the base substrate 00 is smaller than that of the light-emitting layer 303 on the base substrate 00. The projected area.
  • the first sub-pixel 10 can emit light by itself, correspondingly, it is only necessary to control the light-emitting brightness of the virtual sub-pixel 30 to compensate for the attenuation of the brightness of the first sub-pixel 10. Therefore, through the setting method of FIG. 12, it can be realized Under the premise of reliable compensation, manufacturing costs are reduced.
  • the brightness attenuation degree of the first sub-pixel 10 may be different, and accordingly, the brightness that needs to be compensated is different, and the brightness that the virtual sub-pixel 30 needs to emit is different.
  • the ratio of the area of the orthographic projection of the connecting electrode 301 on the base substrate 00 to the area of the orthographic projection of the light-emitting layer 303 of the dummy sub-pixel 30 on the base substrate 00 may satisfy a range of 7% to 15%. That is, when the area of the orthographic projection of the connecting electrode 301 on the base substrate 00 meets the ratio range, effective and reliable compensation for the brightness attenuation of the first sub-pixel 10 can be achieved.
  • the above is to control the light-emitting brightness of the light-emitting layer 303 of the virtual sub-pixel 30 by adjusting the effective area of the connection electrode 301 of the virtual sub-pixel 30.
  • the light-emitting brightness of each sub-pixel is also related to the voltage of the signal provided by its pixel circuit (such as the data signal Vdata), for the virtual sub-pixel 30, it is also possible to control the voltage of the signal provided by the pixel circuit 302 to achieve light-emitting. Flexible adjustment of the brightness of the light emitted by the layer 303.
  • the array substrate may further include: auxiliary electrodes 305.
  • the auxiliary electrode 305 and the connecting electrode 301 may be arranged in sequence along a direction away from the base substrate 00, and the pixel circuit 302, the auxiliary electrode 305, the connecting electrode 301 and the light-emitting layer 303 of the dummy sub-pixel 30 may be electrically connected in sequence.
  • the orthographic projection of the auxiliary electrode 305 on the base substrate 00 and the orthographic projection of the connection electrode 301 on the base substrate 00 may at least partially overlap.
  • FIG. 12 shows the orthographic projection of the auxiliary electrode 305 included in the array substrate on the base substrate 00, which completely covers the orthographic projection of the connection electrode 301 on the base substrate 00.
  • the auxiliary electrode 305 may also be located on the same layer as the source & drain (SD) in the pixel circuit 302 of the dummy sub-pixel 30.
  • the auxiliary electrode 305 and the source and drain SD of the pixel circuit 302 can be formed by one patterning process, so as to avoid increasing the manufacturing cost and the complexity of the manufacturing process.
  • the array substrate may further include: a buffer layer (buffer) B1, an active layer (poly ) L1 and the first gate insulating layer GI1, the gate G1 and the second gate insulating layer GI2, the planarization layer (PLN) N1 between the source and drain SD and the connection electrode 301, between the connection electrode 301 and the light-emitting layer 303 , And arranged in sequence along the Y1 direction, the pixel intermediate layer (PDL) D1 and the hole transport layer (HTL) H1, and the electron transport layer (ETL) E1 located between the light emitting layer 303 and the electrode layer 304.
  • buffer layer buffer layer
  • PLL pixel intermediate layer
  • HTL hole transport layer
  • ETL electron transport layer
  • FIG. 13 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure. 13 and 14 and the cross-sectional view of FIG. 12, it can be seen that the array substrate may also include: a data line V1 (connected to the data signal terminal Vdata), a power signal line V2 (connected to the power signal terminal VDD), and One GOA unit and the first EOA unit. Also, referring to FIGS. 13 and 14, the data line V1, the power signal line V2, the first GOA unit, and the first EOA unit may all be electrically connected to the pixel circuit 302 of the dummy sub-pixel 30.
  • the first GOA unit may be connected to the gate signal terminal GATE and the reset signal terminal RST of the pixel circuit 302, and the first EOA unit may be connected to the light emission control signal terminal EM of the pixel circuit 302.
  • the data line V1 can provide a data signal to the pixel circuit 302 of the virtual sub-pixel 30
  • the power signal line V2 can provide a power signal to the pixel circuit 302 of the virtual sub-pixel 30
  • the first GOA unit can provide the pixel circuit 302 of the virtual sub-pixel 30.
  • the first EOA unit can provide the light emission control signal EM to the pixel circuits 302 of the dummy sub-pixel 30.
  • the pixel circuit 302 can be driven by various signals to drive the light-emitting layer 303 of the dummy sub-pixel 30 to emit light.
  • each pixel circuit is also electrically connected to an initial power terminal Vinit, and the initial power terminal Vinit can provide an initial power signal to the pixel circuit electrically connected thereto.
  • the data line V1 and the power signal line V2 may both be located in the same layer as the source and drain SD.
  • the data line V1 and the power signal line V2 can be formed with the source and drain electrodes SD through a patterning process.
  • the array substrate may further include: a dummy GOA unit and a dummy EOA unit, and the dummy GOA unit and the dummy EOA unit may both be electrically connected to the pixel circuit 102 of the first sub-pixel 10.
  • the first sub-pixel 10 and The virtual sub-pixels 30 may be sequentially arranged and adjacent to each other along the target direction X1.
  • the first EOA unit, the first GOA unit, and the first sub-pixel 10 may be sequentially arranged along the gate line scanning direction S1, and the virtual GOA unit and the first GOA unit may be sequentially arranged along the target direction X1 , The virtual EOA unit and the first EOA unit may be arranged in sequence along the target direction X1.
  • the virtual EOA unit, the virtual GOA unit, and the first sub-pixel 10 may be sequentially arranged along the gate line scanning direction S1, and the virtual GOA unit and the first GOA unit may be sequentially arranged along the direction X2 opposite to the target direction X1 ,
  • the virtual EOA unit and the first EOA unit may be arranged in sequence along the direction X2 opposite to the target direction X1. It should be noted that both FIGS. 13 and 14 only show the pixel circuit 102 of the first sub-pixel 10 and the pixel circuit 302 of the dummy sub-pixel 30.
  • FIG. 15 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • the array substrate may further include: at least one switch circuit 40 corresponding to at least one signal line in the signal line set on a one-to-one basis.
  • Each of the at least one signal line may include two conductive segments, and the two conductive segments may be electrically connected through the switch circuit 40 corresponding to the signal line.
  • the set of signal lines may include: a data line V1, a power signal line V2, a signal line electrically connected between the first GOA unit and the pixel circuit 302 of the dummy sub-pixel 30, and a signal line between the first EOA unit and the dummy sub-pixel 30
  • the pixel circuit 302 is electrically connected to a signal line.
  • the switch circuit 40 may also be electrically connected to the control signal terminal Con1, and the switch circuit 40 may control the on-off state of the two conductive sections electrically connected in response to the control signal provided by the control signal terminal Con1.
  • the at least one switch circuit 40 may include: a switch circuit 40 corresponding to the data line V1 and a switch circuit 40 corresponding to the power signal line V2.
  • the switch circuit 40 corresponding to the data line V1 can control the two conductive segments of the data line V1 to conduct when the potential of the control signal provided by the control signal terminal Con1 is an effective potential.
  • the data line V1 can be connected to the pixel circuit 302. Input a data signal; and when the potential of the control signal is an invalid potential, the two conductive segments of the control data line V1 are disconnected.
  • the switch circuit 40 corresponding to the power signal line V2 can also control the two conductive sections of the power signal line V2 to conduct when the potential of the control signal provided by the control signal terminal Con1 is at an effective potential.
  • the power signal line V2 can A power signal is input to the pixel circuit 302; and when the potential of the control signal is an invalid potential, the two conductive sections of the control power signal line V2 are disconnected.
  • the switch circuit 40 By providing the switch circuit 40, flexible control of the pixel circuit 302 of the virtual sub-pixel 30 can be realized.
  • the signal provided by the first GOA unit to the pixel circuit 302 is a gate drive signal
  • the signal provided by the first EOA unit to the pixel circuit 302 is a light-emission control signal
  • the gate drive signal and the light-emission control signal are in a floating state Leakage is easy to occur under the situation, so by only setting the switch circuit corresponding to the data line V1 and the power signal line V2, the flexible control of the pixel circuit 302 can be realized to avoid the display effect caused by the leakage of the gate drive signal and the light-emitting control signal.
  • An abnormal phenomenon That is, on the premise of ensuring the controllability of the pixel circuit 302 of the virtual sub-pixel 30, the display effect is ensured.
  • the switch circuit 40 may include: a transistor T1.
  • the gate of the transistor T1 can be electrically connected to the control signal terminal Con1, the first electrode of the transistor T1 can be electrically connected to one conductive section of a signal line, and the second electrode of the transistor T1 can be electrically connected to another conductive section of the signal line. connection.
  • the gate of the transistor T1 corresponding to the data line V1 is electrically connected to the control signal terminal Con1
  • the first electrode is electrically connected to a conductive section of the data line V1
  • the second electrode is electrically connected to the data line V1.
  • the other conductive section is electrically connected.
  • the gate of the transistor T1 corresponding to the power signal line V2 is electrically connected to the control signal terminal Con1
  • the first electrode is electrically connected to a conductive section of the power signal line V2
  • the second electrode is electrically connected to the other conductive section of the power signal line V2 Electric connection.
  • FIG. 16 is a schematic structural diagram of still another array substrate provided by an embodiment of the present disclosure.
  • the array substrate may further include: a third sub-pixel 50 located in the display area A1.
  • the colors of the first sub-pixel 10, the second sub-pixel 20, and the third sub-pixel 50 may be different, and in the gate line scanning direction S1, the second sub-pixel 20 and the third sub-pixel 50 may be arranged side by side.
  • Two sub-pixels for emitting light of a target color are arranged, and the target color is the same as the color of the light emitted by the first sub-pixel.
  • two first sub-pixels may be arranged side by side between the second sub-pixel 20 and the third sub-pixel 50 10; Or, a first sub-pixel 10 and a dummy sub-pixel 30 may be arranged side by side between the second sub-pixel 20 and the third sub-pixel 50.
  • both the second sub-pixel 20 and the third sub-pixel 50 can achieve normal color ratio by sharing the two sub-pixels arranged in parallel therebetween. That is, normal display is realized by sharing sub-pixels.
  • the first sub-pixel 10 may be a green sub-pixel
  • the second sub-pixel 20 may be a red sub-pixel
  • the third sub-pixel 50 may be a blue sub-pixel.
  • the colors of the first sub-pixel 10, the second sub-pixel 20, and the third sub-pixel 50 are not limited to the description in the specification, that is, for other non-RGB arrangement display devices, they can also be implemented by the array substrate provided by the embodiment of the present disclosure. Effective compensation of brightness.
  • the structures (such as connecting electrodes, pixel circuits, and light-emitting layers) included in the above-mentioned sub-pixels all need to be made by a patterning process using a fine metal mask (FMM).
  • FMM fine metal mask
  • the electrical connection described in the embodiments of the present disclosure means that the two ends of the interconnection can transmit signals to each other, and the electrical connection may include a direct connection or an indirect connection.
  • an N-type transistor is used as the transistor, and the effective potential is a high potential, and the ineffective potential is a low potential as an example.
  • the transistor can also be a P-type transistor. When the transistor is a P-type transistor, the effective potential is a low potential and the ineffective potential is a high potential.
  • the embodiments of the present disclosure provide an array substrate.
  • the array substrate includes a first sub-pixel, a second sub-pixel, and a dummy sub-pixel.
  • the brightness attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel, and the light-emitting layer of the dummy sub-pixel
  • the color of the emitted light is the same as the color of the light emitted by the first sub-pixel.
  • the dummy sub-pixel also includes a connection electrode electrically connecting its pixel circuit and the light-emitting layer, and the pixel circuit can drive the dummy sub-pixel to emit light through the connection electrode, the brightness of the first sub-pixel can be compensated by controlling the dummy sub-pixel to emit light. Attenuation, that is, the difference in brightness attenuation between the first sub-pixel and the second sub-pixel can be reduced by controlling the virtual sub-pixel to emit light, and the display device made of the array substrate has a better display effect.
  • FIG. 17 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure, which is used to manufacture the array substrate shown in any one of FIGS. 10 to 16.
  • the manufacturing method may include:
  • Step 170 sequentially forming a pixel circuit structure, a driving electrode structure, a light-emitting layer structure, and an electrode layer structure in the display area of the base substrate to obtain a first sub-pixel, a second sub-pixel, and a dummy sub-pixel.
  • the pixel circuit structure may include: the pixel circuit of each sub-pixel; the driving electrode structure may include the connection electrode of each sub-pixel; the light-emitting layer structure may include the light-emitting layer of each sub-pixel; the electrode layer structure may include each sub-pixel The electrode layer of the pixel.
  • the light-emitting layer can be electrically connected to the pixel circuit through a connection electrode, the light-emitting layer can also be electrically connected to the electrode layer, and the pixel circuit can drive the light-emitting layer to emit light through the connection electrode.
  • the display area A1 may have a gap K1.
  • the brightness attenuation degree of the first sub-pixel 10 is greater than that of the second sub-pixel. 20
  • the light-emitting layer of the virtual sub-pixel and the light-emitting layer of the first sub-pixel are used to emit light of the same color.
  • the embodiments of the present disclosure provide a method for manufacturing an array substrate.
  • a virtual sub-pixel that includes the connecting electrode in the display area and emits the same color as the light emitted by the first sub-pixel with the greatest degree of brightness attenuation
  • the brightness attenuation of the first sub-pixel can be compensated by controlling the virtual sub-pixel to emit light, That is, the light emission of the virtual sub-pixel can be controlled to reduce the difference in brightness attenuation between the first sub-pixel and the second sub-pixel, and the display device corresponding to the array substrate manufactured by the array substrate manufacturing method has a better display effect.
  • the array substrate may further include an auxiliary electrode 305.
  • FIG. 18 is a flowchart of a method for sequentially forming a pixel circuit structure, a driving electrode structure, a light-emitting layer structure, and an electrode layer structure in a display area of a base substrate according to an embodiment of the present disclosure. As shown in Figure 18, the method may include:
  • Step 1701 forming a gate pattern, an active layer pattern, and a source/drain pattern on one side of a base substrate to obtain a pixel circuit structure.
  • the active layer pattern, the gate pattern, and the source and drain patterns may be sequentially formed in a direction away from the base substrate 00 through a patterning process, and the pixel circuit structure obtained by this method is a bottom gate structure.
  • an active layer pattern, a source/drain pattern, and a gate pattern are sequentially formed in a direction away from the base substrate 00, and the pixel circuit structure obtained by this method is a top gate structure.
  • the patterning process may include treatments such as glue coating, exposure, development, and etching.
  • the base substrate 00 formed with the pixel circuit structure may be as shown in FIG. 19.
  • the pixel circuit structure shown is a bottom gate structure, that is, the gate pattern M1 and the source/drain pattern M2 are arranged in sequence along a direction away from the base substrate 00.
  • the gate pattern M1 may include the gate G1 of each sub-pixel to be formed (such as the first sub-pixel 10, the second sub-pixel 20, and the dummy sub-pixel 30), and the source-drain pattern M2 may include each sub-pixel to be formed
  • the source and drain electrodes SD and the auxiliary electrode 305, the active layer pattern M3 may include the active layer L1 of each sub-pixel to be formed.
  • the source/drain pattern M2 may also include the data line V1, the power signal line V2, and the source/drain SD of the switch circuit 40 shown in any one of FIGS. 12 to 15 (not shown in the figure).
  • the gate pattern M1 may also include the gate of the switch circuit 40 shown in FIG. 10 (not shown in the figure).
  • FIG. 19 only shows the gate pattern, source/drain pattern, and active layer pattern corresponding to the first sub-pixel 10 and the dummy sub-pixel 30 to be formed.
  • Step 1702 forming a driving electrode structure on the side of the gate pattern, the active layer pattern, and the source/drain pattern away from the base substrate.
  • the patterning process can be continued to form the driving electrode structure on the side of the gate pattern, the active layer pattern, and the source/drain pattern away from the base substrate.
  • the base substrate 00 on which the driving electrode structure M4 is formed may be as shown in FIG. 20.
  • the driving electrode pattern M4 may include: a connection electrode of each sub-pixel to be formed.
  • FIG. 14 only shows the connection electrode 101 of the first sub-pixel 10 and the connection electrode 301 of the dummy sub-pixel 30 to be formed.
  • the formed driving electrode structure may be an anode or a cathode.
  • the exposure steps of the patterning process provided by the embodiments of the present disclosure are performed by using masks including hollow areas of different shapes and sizes. Since for the dummy sub-pixel 30, the area of the orthographic projection of the connecting electrode 301 formed on the base substrate 00 may be less than or equal to the area of the orthographic projection of the light-emitting layer 303 on the base substrate 00, therefore, the mask and the connecting electrode The area of the hollow area corresponding to 301 may be less than or equal to the area of the hollow area corresponding to the light-emitting layer 303.
  • Step 1703 forming a light-emitting layer structure on the side of the driving electrode structure away from the base substrate.
  • the patterning process can be continued to form the light-emitting layer structure M5 on the side of the driving electrode structure M4 away from the base substrate 00.
  • the base substrate 00 on which the light emitting layer structure M5 is formed may be as shown in FIG. 21.
  • the light-emitting layer pattern structure may include a light-emitting layer of each sub-pixel to be formed.
  • FIG. 21 only shows the light-emitting layer 103 of the first sub-pixel to be formed, and the light-emitting layer 303 of the dummy sub-pixel to be formed.
  • the pixel circuit 302 and the light-emitting layer 303 of the dummy sub-pixel may be electrically connected through the connecting electrode 301
  • the pixel circuit 102 and the light-emitting layer 103 of the first sub-pixel may be electrically connected through the connecting electrode 101 of the first sub-pixel .
  • the forming materials of the light-emitting layer patterns corresponding to the different sub-pixels may be different.
  • the material of the light-emitting layer structure M5 may be the light-emitting material forming the green sub-pixel.
  • Step 1704 forming an electrode layer structure on the side of the light emitting layer structure away from the base substrate.
  • the patterning process can be continued to form the electrode layer structure M6 on the side of the light emitting layer structure M5 away from the base substrate 00.
  • the base substrate 00 on which the electrode layer structure M6 is formed may be as shown in FIG. 22.
  • the electrode layer structure M6 may include: an electrode layer of each sub-pixel (FIG. 22 only shows the electrode layer 104 of the first sub-pixel and the electrode layer 304 of the dummy sub-pixel).
  • the formed electrode layer may be an anode or a cathode, and the electrode layer structure and the electrode corresponding to the driving electrode structure are different.
  • the method of forming sub-pixels further includes: forming the active layer L1 on one side of the base substrate 00 through a patterning process. Buffer layer B1; after the active layer L1 is formed, a first gate insulating layer GI1 is formed on the side of the active layer L1 away from the buffer layer B1; after the gate G1 is formed, the gate G1 is away from the first gate insulating layer GI1
  • the second gate insulating layer GI2 is formed on the side of the sd; after the source and drain SD is formed, a flat layer N1 is formed on the side of the source and drain SD away from the base substrate 00; after the driving electrode structure (including the connecting electrode) is formed, the flat layer N1 is formed on the side of the source and drain SD away from the base substrate 00; A pixel intermediate layer D1 is formed on the side of the driving electrode structure away from the flat layer N1; a hole transport layer H
  • first GOA unit, the first EOA unit, the virtual GOA unit and the virtual EOA unit can also be arranged at the edge position of the base substrate.
  • each GOA unit and each EOA unit are electrically connected to the pixel circuit of the sub-pixel to control the pixel circuit to drive the electrically connected sub-pixel to emit light.
  • the embodiments of the present disclosure provide a method for manufacturing an array substrate.
  • a virtual sub-pixel that includes the connecting electrode in the display area and emits the same color as the light emitted by the first sub-pixel with the greatest degree of brightness attenuation
  • the brightness attenuation of the first sub-pixel can be compensated by controlling the virtual sub-pixel to emit light, That is, the light emission of the virtual sub-pixel can be controlled to reduce the difference in brightness attenuation between the first sub-pixel and the second sub-pixel, and the display device corresponding to the array substrate manufactured by the array substrate manufacturing method has a better display effect.
  • FIG. 23 is a flowchart of a driving method of an array substrate provided by an embodiment of the present disclosure, which is used to drive the array substrate shown in any one of FIGS. 10 to 16. As shown in Figure 23, the method may include:
  • Step 230 Provide a driving signal to the pixel circuit of the dummy sub-pixel, and the pixel circuit of the dummy sub-pixel drives the light-emitting layer of the dummy sub-pixel to emit light through the connecting electrode of the dummy sub-pixel in response to the driving signal.
  • the array substrate may further include: at least one switch circuit 40 corresponding to at least one signal line in the signal line set, and the switch circuit 40 is also electrically connected to the control signal terminal Con1.
  • the foregoing step 230 may include:
  • Step 2301 Provide a control signal to the control signal terminal, and the switch circuit responds to the control signal to control the conduction of the two electrically connected conductive segments.
  • control device of the array substrate can first provide the control signal at the effective potential to the control signal terminal. Accordingly, the switch circuit can control the two electrically connected conductive sections under the control of the control signal. Conduction.
  • one switch circuit 40 can control the two conductive sections of the data line V1 electrically connected to conduct under the control of the control signal; the other switch circuit 40 can be controlled by the control signal.
  • the power signal line V2 which is electrically connected to it, is controlled to be turned on.
  • Step 2302 Provide a data signal to the data line, provide a power signal to the power signal line, provide a compensation signal to the first GOA unit, and provide a compensation signal to the first EOA unit.
  • the control device can control the circuit (such as the source driving circuit) connected to the data line V1 to provide the data signal to the data line V1.
  • the control device can control a circuit connected to the power signal line V2 to provide a power signal to the power signal line V2.
  • the control device can control a circuit connected to the first GOA unit to provide a compensation signal to the virtual GOA unit, and can control a circuit connected to the first EOA unit to provide a compensation signal to the virtual EOA unit.
  • the data line V1 can write the data signal to the pixel circuit
  • the power signal line V2 can write the power signal to the pixel circuit 302
  • the first GOA unit can output the gate drive signal and the reset signal to the pixel circuit 302
  • the first The EOA unit may output a light emission control signal to the pixel circuit 302.
  • the pixel circuit 302 can output a driving signal to the light-emitting layer 303 electrically connected to it under the control of the multiple signals to drive the light-emitting layer 303 electrically connected to it to emit light.
  • step 2301 and step 2302 can be performed simultaneously.
  • the embodiments of the present disclosure provide a method for controlling an array substrate.
  • the pixel circuit of the dummy sub-pixel can reliably drive the light-emitting layer of the dummy sub-pixel to emit light. Since the virtual sub-pixel can emit light of the same color as the light emitted by the first sub-pixel with the greatest degree of brightness attenuation, by controlling the virtual sub-pixel to emit light, the brightness attenuation of the first and second sub-pixels is effectively reduced. Depending on the degree of difference, the display effect of the display device corresponding to the array substrate made of the array substrate is better.
  • an embodiment of the present disclosure also provides a control device for an array substrate, the control device can be electrically connected to the pixel circuit of the virtual sub-pixel, and the control device can execute the array shown in any one of FIGS. 23 and 24.
  • the driving method of the substrate may be a processor.
  • an embodiment of the present disclosure further provides a display device, which may include: an array substrate as shown in any one of FIGS. 10 to 16 and a control device for the above-mentioned array substrate.
  • the display device can be: liquid crystal panel, electronic paper, organic light-emitting diode (OLED) panel, active-matrix organic light-emitting diode (AMOLED) panel, mobile phone, tablet computer , TVs, monitors, notebook computers, digital photo frames and other products or components with display functions.

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Abstract

本申请提供了一种阵列基板及其制造和控制方法、显示装置。该阵列基板包括：位于显示区域内的第一子像素、第二子像素和虚拟子像素，在沿目标方向上，第一子像素的衰减程度大于第二子像素的亮度衰减程度，且该虚拟子像素的发光层用于发出与第一子像素所发光颜色相同的光。由于该虚拟子像素还包括电连接像素电路和其发光层的连接电极，因此可以通过驱动该虚拟子像素发光，有效补偿第一子像素的亮度衰减，进而改善显示装置显示效果较差的问题，该阵列基板制成的显示装置的显示效果较好。

Description

阵列基板及其制造和控制方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制造和控制方法、显示装置。
背景技术
随着显示技术的发展，显示装置的显示屏不再满足于原有的全面屏设计，一系列具有缺口的异形(notch)屏应运而生。
发明内容
本公开实施例提供了一种阵列基板及其制造和控制方法、显示装置，所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板包括：衬底基板，以及位于所述衬底基板的显示区域内的第一子像素、第二子像素和虚拟子像素，所述显示区域具有缺口，在沿所述显示区域的中心靠近所述缺口的目标方向上，所述第一子像素的亮度衰减程度大于所述第二子像素的亮度衰减程度；
每个子像素均包括：像素电路、连接电极、发光层和电极层，所述发光层与所述像素电路通过所述连接电极电连接，所述发光层还与所述电极层电连接，所述像素电路用于通过所述连接电极驱动所述发光层发光，且所述虚拟子像素中的发光层与所述第一子像素中的发光层用于发出相同颜色的光。
可选的，所述虚拟子像素的连接电极与所述第一子像素的连接电极位于同层。
可选的，在所述虚拟子像素中，所述连接电极在所述衬底基板上的正投影的面积，小于或等于所述发光层在所述衬底基板上的正投影的面积。
可选的，在所述虚拟子像素中，所述连接电极在所述衬底基板上的正投影的面积，与所述发光层在所述衬底基板上的正投影的面积的比值范围为：7％至15％。
可选的，所述阵列基板还包括：辅助电极，且所述辅助电极与所述虚拟子 像素中的连接电极沿远离所述衬底基板的方向依次排布；
所述虚拟子像素的像素电路、所述辅助电极、所述虚拟子像素的连接电极和所述虚拟子像素的发光层依次电连接。
可选的，所述辅助电极与所述虚拟子像素的像素电路中的源漏极位于同层。
可选的，所述阵列基板还包括：数据线、电源信号线、第一移位寄存器GOA单元和第一移位寄存器EOA单元；
所述数据线、所述电源信号线、所述第一GOA单元和所述第一EOA单元均与所述虚拟子像素的像素电路电连接；
所述数据线用于向所述虚拟子像素的像素电路提供数据信号，所述电源信号线用于向所述虚拟子像素的像素电路提供电源信号，所述第一GOA单元用于向所述虚拟子像素的像素电路提供栅极驱动信号，所述第一EOA单元用于向所述虚拟子像素的像素电路提供发光控制信号。
可选的，所述阵列基板还包括：虚拟GOA单元和虚拟EOA单元，且所述虚拟GOA单元和所述虚拟EOA单元均与所述第一子像素的像素电路电连接，所述第一子像素和所述虚拟子像素沿所述目标方向依次排布且相邻；
所述第一EOA单元、所述第一GOA单元和所述第一子像素沿栅线扫描方向依次排布，所述虚拟GOA单元与所述第一GOA单元沿所述目标方向依次排布，所述虚拟EOA单元和所述第一EOA单元沿所述目标方向依次排布；
或者，所述虚拟EOA单元、所述虚拟GOA单元和所述第一子像素沿栅线扫描方向依次排布，所述虚拟GOA单元与所述第一GOA单元沿所述目标方向的反方向依次排布，所述虚拟EOA单元和所述第一EOA单元沿所述目标方向的反方向依次排布。
可选的，所述阵列基板还包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路；
每条所述信号线包括两个导电段，且所述两个导电段通过所述信号线对应的开关电路电连接，所述信号线集合包括：所述数据线，所述电源信号线，所述第一GOA单元与所述虚拟子像素的像素电路电连接的信号线，以及所述第一EOA单元与所述虚拟子像素的像素电路电连接的信号线；
所述开关电路还与控制信号端电连接，所述开关电路用于响应于所述控制信号端提供的控制信号，控制其电连接的两个导电段的通断状态。
可选的，所述至少一个开关电路包括：与所述数据线对应的开关电路，以 及与所述电源信号线对应的开关电路。
可选的，所述开关电路包括：晶体管；
所述晶体管的栅极与所述控制信号端电连接，所述晶体管的第一极与一条信号线的一个导电段电连接，所述晶体管的第二极与所述一条信号线的另一个导电段电连接。
可选的，所述阵列基板还包括：位于所述显示区域内的第三子像素；
所述第一子像素、所述第二子像素和所述第三子像素所发出光的颜色不同，且在栅线扫描方向上，所述第二子像素和所述第三子像素之间并列排布有两个用于发出目标颜色的光的子像素，所述目标颜色与所述第一子像素所发出光的颜色相同。
可选的，所述第一子像素为绿色子像素，所述第二子像素为红色子像素，所述第三子像素为蓝色子像素。
另一方面，提供了一种阵列基板的制造方法，所述方法包括：
在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构，以得到第一子像素、第二子像素和虚拟子像素；
其中，所述像素电路结构包括：每个子像素的像素电路，所述驱动电极结构包括所述每个子像素的连接电极，所述发光层结构包括所述每个子像素的发光层，所述电极层结构包括所述每个子像素的电极层，且在每个所述子像素中，所述发光层与所述像素电路通过所述连接电极电连接，所述发光层还与所述电极层电连接，所述像素电路用于通过所述连接电极驱动所述发光层发光；
所述显示区域具有缺口，在沿所述显示区域的中心靠近所述缺口的目标方向上，所述第一子像素的亮度衰减程度大于所述第二子像素的亮度衰减程度，所述虚拟子像素的发光层与所述第一子像素的发光层用于发出相同颜色的光。
可选的，所述阵列基板还包括：辅助电极，所述辅助电极与所述虚拟子像素的连接电极电连接；所述在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构，包括：
在所述衬底基板的一侧形成栅极图案、有源层图案和源漏极图案，得到所述像素电路结构，其中，所述源漏极图案包括所述每个子像素的源漏极以及所述辅助电极，所述有源层图案包括所述每个子像素的有源层，所述栅极图案包括所述每个子像素的栅极；
在所述栅极图案、所述有源层图案和所述源漏极图案远离所述衬底基板的 一侧形成所述驱动电极结构；
在所述驱动电极结构远离所述衬底基板的一侧形成所述发光层结构；
在所述发光层结构远离所述衬底基板的一侧形成所述电极层结构。
又一方面，提供了一种阵列基板的驱动方法，用于驱动如上述方面所述的阵列基板，所述方法包括：
向虚拟子像素的像素电路提供驱动信号，所述虚拟子像素的像素电路响应于所述驱动信号，通过所述虚拟子像素的连接电极驱动所述虚拟子像素的发光层发光。
可选的，所述阵列基板还包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路，所述开关电路还与控制信号端电连接；所述向虚拟子像素的像素电路提供驱动信号，包括：
向所述控制信号端提供控制信号，所述开关电路响应于所述控制信号，控制其电连接的两个导电段导通；
向数据线提供数据信号，向电源信号线提供电源信号，向第一GOA单元提供补偿信号，且向第一EOA单元提供补偿信号。
再一方面，提供了一种阵列基板的控制装置，所述控制装置与虚拟子像素的像素电路电连接，所述控制装置用于执行如上述方面所述的阵列基板的驱动方法。
再一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的阵列基板，以及如上述方面所述的阵列基板的控制装置。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种异形屏的结构示意图；
图2是相关技术记载的一种异形屏的结构示意图；
图3是相关技术记载的一种异形屏的基板结构示意图；
图4是本公开实施例提供的一种测试结果示意图；
图5是本公开实施例提供的另一种测试结果示意图；
图6是本公开实施例提供的又一种测试结果示意图；
图7是本公开实施例提供的再一种测试结果示意图；
图8是本公开实施例提供的再一种测试结果示意图；
图9是本公开实施例提供的再一种测试结果示意图；
图10是本公开实施例提供的一种阵列基板的结构示意图；
图11是本公开实施例提供的另一种阵列基板的结构示意图；
图12是本公开实施例提供的又一种阵列基板的结构示意图；
图13是本公开实施例提供的再一种阵列基板的结构示意图；
图14是本公开实施例提供的再一种阵列基板的结构示意图；
图15是本公开实施例提供的再一种阵列基板的结构示意图；
图16是本公开实施例提供的再一种阵列基板的结构示意图；
图17是本公开实施例提供的一种阵列基板的制造方法流程图；
图18是本公开实施例提供的另一种阵列基板的制造方法流程图；
图19是本公开实施例提供的一种形成有像素电路结构的阵列基板示意图；
图20是本公开实施例提供的一种形成有驱动电极结构的阵列基板示意图；
图21是本公开实施例提供的一种形成有发光层结构的阵列基板示意图；
图22是本公开实施例提供的一种形成有电极层结构的阵列基板示意图；
图23是本公开实施例提供的一种阵列基板的驱动方法流程图；
图24是本公开实施例提供的另一种阵列基板的驱动方法流程图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，或者，将其中漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止， N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位，第一电位和第二电位仅代表该信号的电位有2个不同的状态量，不代表全文中第一电位或第二电位具有特定的数值。
显示区域至少一侧具有缺口的异形屏目前已成显示技术领域的设计主流。示例的，图1是本公开实施例提供的一种异形屏的结构示意图。参考图1，该异形屏的显示区域A1的一侧具有缺口K1，该显示区域A1内包括多个有效子像素，该显示区域A1靠近缺口K1的一侧，以及远离该缺口K1一侧的非显示区域内包括多个虚拟子像素(dummy pixel)。
其中，参考图2，该有效子像素可以包括红色子像素、绿色子像素和蓝色子像素，该虚拟子像素可以包括红色虚拟子像素、绿色虚拟子像素和蓝色虚拟子像素。并且，各行子像素的排列方式均可以为RGGB排列，即各行子像素均可以按照红色(red)子像素、并列排布的两个绿色(green)子像素和蓝色(blue)子像素排列。需要说明的是，设置多个虚拟子像素，可以实现对有效子像素的保护，且可以保证子像素排布均一性。可选的，参考图2，绿色子像素和绿色虚拟子像素的形状均为五边形，蓝色子像素和蓝色虚拟子像素的形状均为六边形，红色子像素和红色虚拟子像素的形状均为椭圆形。且并列排布的两个绿色子像素在衬底基板上的正投影面积，红色子像素在衬底基板上的正投影的面积，以及蓝色子像素在衬底基板上的正投影的面积相同。并列排布的两个绿色虚拟子像素在衬底基板上的正投影面积，红色虚拟子像素在衬底基板上的正投影的面积，以及蓝色虚拟子像素在衬底基板上的正投影的面积相同。
相关技术中，每个有效子像素包括的像素电路和发光层电连接，每个有效子像素均能够做显示使用。每个虚拟子像素仅包括像素电路和发光层，且该发光层并未与像素电路电连接，即相关技术的异形屏显示装置包括的虚拟子像素均不做显示使用。示例的，图3以相邻的有效绿色子像素和虚拟绿色子像素为例，介绍相关技术记载的一种异形屏阵列基板。如图3所示，该有效绿色子像素P1包括：发光层P11，像素电路P12，以及电连接该像素电路P12和发光层P11的连接电极P13。该虚拟绿色子像素P2仅包括：发光层P21和像素电路P22，且该发光层P21和像素电路P22未电连接。另外，参考图3，该阵列基板还包括多层绝缘层(图中未进行标号)。
并且，为了驱动各行子像素正常发光，以及为了保证排布均一性，该异形屏还可以包括位于显示区域A1一侧的多个有效移位寄存器GOA单元，多个有效移位寄存器EOA单元，多个虚拟(dummy)GOA单元和多个虚拟EOA单元。其中，有效GOA单元和有效EOA可以与有效子像素的像素电路电连接，并用于向像素电路提供驱动信号。虚拟GOA单元和虚拟EOA单元不与任何子像素连接，即虚拟GOA单元和虚拟EOA单元不做驱动使用，对显示无贡献。
在本公开实施例中，经过长程均一性(long range uniformity，LRU)测试，即经亮度均一性测试得出以下结论：结合图1和图2，在沿显示区域A1的中心靠近缺口K1的目标方向X1上，各个子像素的亮度均发生不同程度的衰减，相应的，靠近缺口K1一侧的显示色彩出现异常。例如，对于图2所示的RGGB排列的显示屏，在沿目标方向X1上，绿色子像素的衰减程度L_G为31％(百分之)，红色子像素的衰减程度L_R为27％，蓝色子像素的亮度衰减程度L_B为25％。对比该三种颜色子像素的亮度衰减程度可以确定：在沿目标方向X1上，绿色子像素的亮度衰减程度大于蓝色子像素和红色子像素的亮度衰减程度。相应的，靠近缺口K1一侧的显示色彩失衡，例如，测试得出：靠近缺口K1一侧的红色子像素的色彩分量Gx为0.0018，绿色子像素的色彩分量Rx为0.0002，即绿色子像素的色彩分量小于红色子像素的色彩分量。
示例的，图4至图9是本公开实施例提供的一种对图2所示的显示屏进行亮度测试和色彩测试的测试结果示意图。且色彩测试均以国际照明委员会(Commission Internationale de L'Eclairage，CIE)作为测试标准。图4至图9的横坐标X均是指沿目标方向X1采集到的各个子像素点，图4所示的测试结果纵坐标Y是指红色子像素在CIE的X轴方向的色彩分量，图5所示的测试结果纵坐标Y是指绿色子像素在CIE的X轴方向的色彩分量，图6所示的测试结果纵坐标Y是指红色子像素在CIE的Y轴方向的色彩分量，图7所示的测试结果纵坐标是指绿色子像素在CIE的Y轴方向的色彩分量，图8所示的测试结果的纵坐标Y是指红色子像素的亮度值，图9所示的测试结果的纵坐标Y是指绿色子像素的亮度值。参考图4至图9可以看出：在沿目标方向X1上，红色子像素在CIE坐标系统的X轴方向和Y轴方向上，色彩分量均逐渐升高，但变化情况较为平缓。绿色子像素在CIE坐标系统的X轴方向上，色彩分量逐渐下降，在色彩坐标系统的Y轴方向上，色彩分量逐渐升高，且变换情况较为突出，红色子像素的亮度衰减程度明显小于绿色子像素的亮度衰减程度。由于在绿色子像 素的亮度衰减程度较大时，显示效果整体会偏红，因此相关技术提供的异形屏显示装置，其靠近缺口K1的一侧易出现发红现象。
本公开实施例提供了一种阵列基板，其可以解决相关技术的异形屏显示装置显示效果较差的问题。需要说明的是，下述实施例介绍的非虚拟子像素均为能够正常发光的有效子像素，非虚拟GOA单元均为有效GOA单元，非虚拟EOA单元均为有效EOA单元，阵列基板包括的像素电路中的晶体管均为底栅结构。当然，像素电路的晶体管也可以为顶栅结构，在本公开实施例不做介绍。
图10是本公开实施例提供的一种阵列基板的结构示意图。如图10所示，该阵列基板可以包括：衬底基板00，以及位于衬底基板00的显示区域A1内的第一子像素10、第二子像素20和虚拟子像素30。参考图10，该衬底基板00的显示区域A1具有缺口K1，且在沿显示区域A1的中心靠近缺口K1的目标方向X1上，第一子像素10的亮度衰减程度大于第二子像素20的亮度衰减程度。
其中，每个子像素均可以包括像素电路、连接电极、发光层和电极层。对于每个子像素，其发光层可以与其像素电路通过其连接电极电连接，其发光层还与其电极层电连接，像素电路可以通过连接电极驱动发光层发光。且虚拟子像素30的发光层与第一子像素10的发光层可以发出相同颜色的光。例如，假设第一子像素10为绿色子像素，则虚拟子像素30的发光层即可发出绿色的光。
可选的，参考图11，其以虚拟子像素30为例，示出了本公开实施例提供的另一种阵列基板的结构示意图。如图11所示，该虚拟子像素30可以包括：连接电极301、像素电路302、发光层303和电极层304。其中，该发光层303与像素电路302可以通过连接电极301电连接，且该发光层303还与电极层304电连接。该像素电路302可以通过该连接电极301驱动发光层303发光。
对比图3和图11，由于本公开实施例提供的阵列基板的显示区域A1内，用于发出与第一子像素所发光颜色相同的虚拟子像素30还包括连接电极301，且该连接电极301可以电连接该虚拟子像素30的像素电路302和发光层303。因此本公开实施例可以通过驱动该虚拟子像素30发光来补偿亮度衰减程度较大的第一子像素10的亮度衰减，即通过驱动该虚拟子像素30发光来减小有效子像素(如第一子像素10和第二子像素20)的亮度衰减差异程度，该阵列基板制造的显示装置的显示效果较好。
例如，假设第一子像素10为绿色子像素，第二子像素20为红色子像素， 虚拟子像素30为绿色虚拟子像素，且该显示区域A1内还包括蓝色子像素，则通过驱动该虚拟子像素30发光，可以有效减小该三种颜色子像素的亮度衰减差异程度，相应的，即可有效避免因第一子像素亮度衰减较大而造成的发红现象。
综上所述，本公开实施例提供了一种阵列基板。该阵列基板包括第一子像素、第二子像素和虚拟子像素，在目标方向上，该第一子像素的亮度衰减程度大于第二子像素的亮度衰减程度，且该虚拟子像素的发光层发出的光的颜色与该第一子像素发出的光的颜色相同。由于该虚拟子像素还包括电连接其像素电路和发光层的连接电极，且该像素电路可以通过连接电极驱动虚拟子像素发光，因此可以通过控制该虚拟子像素发光来补偿第一子像素的亮度衰减，即可以通过控制该虚拟子像素发光来减小第一子像素和第二子像素的亮度衰减差异程度，该阵列基板制成的显示装置的显示效果较好。
可选的，在本公开实施例中，该连接电极和该电极层可以均为用于驱动发光层发光的阳极(anode)或阴极(cathode)，且该连接电极和该电极层可以不同。本公开下述实施例中以该连接电极为阳极，电极层为阴极为例进行说明。
图12是本公开实施例提供的又一种阵列基板的结构示意图。如图12所示，该虚拟子像素30的连接电极301与第一子像素10的连接电极101可以位于同层。相应的，该连接电极301即可以与连接电极101通过一次构图工艺形成，且该连接电极301可以与连接电极101为同一类型的电极。即若连接电极101为阳极，则该连接电极301即为阳极；若连接电极101为阴极，则该连接电极301即为阴极。避免了增加制造成本和制造工艺的复杂度。
可选的，由于对于各个子像素而言，发光层的发光亮度和连接电极的有效面积成正比，该有效面积是指连接电极在衬底基板上的正投影与发光层在衬底基板上的正投影的重叠面积。即对于每个子像素，连接电极的有效面积越大，其发光层所发光的亮度越强，连接电极的有效面积越小，其所发光的亮度越弱。
因此，在虚拟子像素30中，其连接电极301在衬底基板00上的正投影的面积，可以小于或等于其发光层303在衬底基板00上的正投影的面积。例如，参考图12，本公开实施例提供的阵列基板中的虚拟子像素30，其连接电极301在衬底基板00上的正投影的面积，小于其发光层303在衬底基板00上的正投影的面积。并且，由于第一子像素10自身可以发光，相应的，仅需控制虚拟子像素30的发光亮度可以弥补第一子像素10的亮度衰减即可，因此，通过图12 的设置方式，可以在实现可靠补偿的前提下，减少制造成本。
需要说明的是，对于不同尺寸和不同发光材料，第一子像素10的亮度衰减程度可能不同，相应的，需要补偿的亮度大小即不同，虚拟子像素30所需发光的亮度即不同。例如，经过算法测试，在第一子像素10为绿色子像素，虚拟子像素30为绿色虚拟子像素时，结合绿色子像素的发光材料、膜层特性以及亮度衰减程度得出：虚拟子像素的连接电极301在衬底基板00上的正投影的面积，与虚拟子像素30的发光层303在衬底基板00上的正投影的面积的比值范围可以满足：7％至15％。也即是，在连接电极301在衬底基板00上的正投影的面积满足该比值范围时，即可以实现对第一子像素10亮度衰减的有效可靠补偿。
还需要说明的是，上述是通过调整虚拟子像素30的连接电极301的有效面积来实现对虚拟子像素30的发光层303发光亮度的控制。另外，由于每个子像素的发光亮度还与其像素电路提供的信号的电压有关(如数据信号Vdata)，因此对于虚拟子像素30，还可以通过控制其像素电路302提供的信号的电压，来实现发光层303所发光亮度的灵活调节。
可选的，结合图12，由于虚拟子像素30的像素电路302与发光层303之间可能存在一定间距，因此为了实现像素电路302和发光层303的可靠电连接。参考图12，该阵列基板还可以包括：辅助电极305。该辅助电极305与该连接电极301可以沿远离衬底基板00的方向依次排布，且该虚拟子像素30的像素电路302、辅助电极305、连接电极301和发光层303可以依次电连接。
并且，为了进一步实现像素电路302和发光层303的可靠电连接，该辅助电极305在衬底基板00上的正投影，与连接电极301在衬底基板00上的正投影可以至少部分重叠。例如，图12示出的阵列基板包括的辅助电极305在衬底基板00上的正投影，完全覆盖连接电极301在衬底基板00上的正投影。通过完全覆盖，保证了辅助电极305和连接电极301的可靠电连接，进而保证了像素电路302与发光层303的可靠电连接。
可选的，参考图12，在本公开实施例中，辅助电极305还可以与虚拟子像素30的像素电路302中的源漏极(source & drain，SD)位于同层。相应的，辅助电极305可以与像素电路302的源漏极SD即可以通过一次构图工艺形成，避免增加制造成本和制造工艺的复杂度。
可选的，参考图12，该阵列基板还可以包括：位于衬底基板00和源漏极SD之间且沿远离衬底基板的方向依次层叠的缓冲层(buffer)B1、有源层(poly) L1和第一栅绝缘层GI1、栅极G1和第二栅绝缘层GI2，位于源漏极SD与连接电极301之间的平坦层(PLN)N1，位于连接电极301和发光层303之间，且沿Y1方向依次排布的像素介定层(PDL)D1和空穴传输层(HTL)H1，以及位于发光层303和电极层304之间的电子传输层(ETL)E1。
图13是本公开实施例提供的再一种阵列基板的结构示意图。图14是本公开实施例提供的再一种阵列基板的结构示意图。结合图13和图14，以及图12的截面图可以看出，该阵列基板还可以包括：数据线V1(与数据信号端Vdata连接)、电源信号线V2(与电源信号端VDD连接)、第一GOA单元和第一EOA单元。并且，参考图13和图14，数据线V1、电源信号线V2、第一GOA单元和第一EOA单元可以均与虚拟子像素30的像素电路302电连接。
例如，参考图13和图14，该第一GOA单元可以与像素电路302的栅极信号端GATE和复位信号端RST连接，该第一EOA单元可以与像素电路302的发光控制信号端EM连接。该数据线V1可以向虚拟子像素30的像素电路302提供数据信号，电源信号线V2可以向虚拟子像素30的像素电路302提供电源信号，第一GOA单元可以向虚拟子像素30的像素电路302提供栅极驱动信号GATE和复位信号RST，第一EOA单元可以向虚拟子像素30的像素电302路提供发光控制信号EM。该像素电路302可以在各信号的驱动下工作，以驱动虚拟子像素30的发光层303发光。可选的，参考图13和图14，各个像素电路还与初始电源端Vinit电连接，该初始电源端Vinit可以向其电连接的像素电路提供初始电源信号。
需要说明的是，结合图12可以看出，该数据线V1和电源信号线V2可以均与源漏极SD位于同层。相应的，该数据线V1和电源信号线V2可以与源漏极SD通过一次构图工艺形成。
参考图13和图14，阵列基板还可以包括：虚拟GOA单元和虚拟EOA单元，且虚拟GOA单元和虚拟EOA单元可以均与第一子像素10的像素电路102电连接，第一子像素10和虚拟子像素30可以沿目标方向X1依次排布且相邻。
可选的，参考图13，第一EOA单元、第一GOA单元和第一子像素10可以沿栅线扫描方向S1依次排布，虚拟GOA单元与第一GOA单元可以沿目标方向X1依次排布，虚拟EOA单元和第一EOA单元可以沿目标方向X1依次排布。
或者，参考图14，虚拟EOA单元、虚拟GOA单元和第一子像素10可以沿栅线扫描方向S1依次排布，虚拟GOA单元与第一GOA单元可以沿目标方向 X1的反方向X2依次排布，虚拟EOA单元和第一EOA单元可以沿目标方向X1的反方向X2依次排布。需要说明的是，图13和图14均仅示出第一子像素10的像素电路102，以及虚拟子像素30的像素电路302。
对比图13和图14的排布方式和连接方式可以看出，采用图13所示的排布方式和连接方式，可以减少布线长度，便于第一GOA单元和第一EOA单元与虚拟子像素30的像素电路302连接，节省制造成本，有利于窄边框的实现。
可选的，图15是本公开实施例提供的再一种阵列基板的结构示意图。如图15所示，该阵列基板还可以包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路40。该至少一条信号线中的每条信号线可以包括两个导电段，且该两个导电段可以通过该条信号线对应的开关电路40电连接。
可选的，该信号线集合可以包括：数据线V1，电源信号线V2，第一GOA单元与虚拟子像素30的像素电路302电连接的信号线，以及第一EOA单元与虚拟子像素30的像素电路302电连接的信号线。该开关电路40还可以与控制信号端Con1电连接，该开关电路40可以响应于控制信号端Con1提供的控制信号，控制其电连接的两个导电段的通断状态。
示例的，参考图15，该至少一个开关电路40可以包括：与数据线V1对应的开关电路40，以及与电源信号线V2对应的开关电路40。与数据线V1对应的开关电路40可以在控制信号端Con1提供的控制信号的电位为有效电位时，控制数据线V1的两个导电段导通，此时，数据线V1即可以向像素电路302输入数据信号；并在控制信号的电位为无效电位时，控制数据线V1的两个导电段断开连接。与电源信号线V2对应的开关电路40也可以在控制信号端Con1提供的控制信号的电位为有效电位时，控制电源信号线V2的两个导电段导通，此时，电源信号线V2即可以向像素电路302输入电源信号；并在控制信号的电位为无效电位时，控制电源信号线V2的两个导电段断开连接。
通过设置开关电路40，可以实现对虚拟子像素30的像素电路302的灵活控制。另外，由于第一GOA单元向像素电路302提供的信号为栅极驱动信号，以及第一EOA单元向像素电路302提供的信号为发光控制信号，且该栅极驱动信号和发光控制信号在悬空状态下易出现漏电现象，因此通过仅设置数据线V1和电源信号线V2对应的开关电路，可以在实现对像素电路302的灵活控制下，避免因栅极驱动信号和发光控制信号漏电而导致显示效果异常的现象。即在保证对虚拟子像素30的像素电路302的可控性的前提下，确保了显示效果。
可选的，参考图15，该开关电路40可以包括：晶体管T1。晶体管T1的栅极可以与控制信号端Con1电连接，晶体管T1的第一极可以与一条信号线的一个导电段电连接，晶体管T1的第二极可以与该条信号线的另一个导电段电连接。
示例的，参考图15，该数据线V1对应的晶体管T1的栅极与控制信号端Con1电连接，第一极与该数据线V1的一个导电段电连接，第二极与该数据线V1的另一个导电段电连接。该电源信号线V2对应的晶体管T1的栅极与控制信号端Con1电连接，第一极与该电源信号线V2的一个导电段电连接，第二极与该电源信号线V2的另一个导电段电连接。
可选的，图16是本公开实施例提供的再一种阵列基板的结构示意图。如图16所示，该阵列基板还可以包括：位于显示区域A1内的第三子像素50。该第一子像素10、第二子像素20和第三子像素50的颜色可以不同，且在栅线扫描方向S1上，该第二子像素20和该第三子像素50之间可以并列排布有两个用于发出目标颜色的光的子像素，该目标颜色与第一子像素所发出光的颜色相同。
由于虚拟子像素30与第一子像素10所发出的光的颜色相同，因此参考图16，该第二子像素20和该第三子像素50之间可以并列排布有两个第一子像素10；或者，该第二子像素20和第三子像素50之间可以并列排布有一个第一子像素10和一个虚拟子像素30。
采用图16所示的排布方式，可以使得第二子像素20和第三子像素50均可以通过共用其之间并列排布的两个子像素实现正常色彩配比。即通过共用子像素实现正常显示。可选的，该第一子像素10可以为绿色子像素，第二子像素20可以为红色子像素，第三子像素50可以为蓝色子像素。
当然，第一子像素10、第二子像素20和第三子像素50的颜色不限于说明书的记载，即对于其他非RGB排列的显示装置，还可以通过本公开实施例提供的阵列基板，实现亮度的有效补偿。
需要说明的是，上述各个子像素包括的结构(如连接电极、像素电路和发光层)均需要通过构图工艺，采用精细金属掩模版(fine metal mask，FMM)制成。而由于本公开实施例未对有效子像素的结构进行调整，因此本公开实施例无需对FMM对应有效子像素部分的镂空区域进行改动。
还需要说明的是，本公开实施例记载的电连接是指互相连接的两端可以相互传输信号，且电连接可以包括直接连接或者间接连接。且在上述各实施例中，是以晶体管采用N型晶体管，且有效电位为高电位，无效电位为低电位为例进 行的说明。当然，晶体管还可以采用P型晶体管，当该晶体管采用P型晶体管时，该有效电位为低电位，该无效电位为高电位。
综上所述，本公开实施例提供了一种阵列基板。该阵列基板包括第一子像素、第二子像素和虚拟子像素，在目标方向上，该第一子像素的亮度衰减程度大于第二子像素的亮度衰减程度，且该虚拟子像素的发光层发出的光的颜色与该第一子像素发出的光的颜色相同。由于该虚拟子像素还包括电连接其像素电路和发光层的连接电极，且该像素电路可以通过连接电极驱动虚拟子像素发光，因此可以通过控制该虚拟子像素发光来补偿第一子像素的亮度衰减，即可以通过控制该虚拟子像素发光来减小第一子像素和第二子像素的亮度衰减差异程度，该阵列基板制成的显示装置的显示效果较好。
图17是本公开实施例提供的一种阵列基板的制造方法流程图，用于制造如图10至图16任一所示的阵列基板，参考图17，该制造方法可以包括：
步骤170、在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构，以得到第一子像素、第二子像素和虚拟子像素。
其中，该像素电路结构可以包括：每个子像素的像素电路；该驱动电极结构可以包括每个子像素的连接电极；该发光层结构可以包括每个子像素的发光层；该电极层结构可以包括每个子像素的电极层。并且，在每个子像素中，发光层可以与像素电路通过连接电极电连接，发光层还可以与电极层电连接，像素电路可以通过连接电极驱动发光层发光。
在本公开实施例中，参考图10，该显示区域A1可以具有缺口K1，在沿显示区域A1的中心靠近缺口K1的目标方向X1上，第一子像素10的亮度衰减程度大于第二子像素20的亮度衰减程度，且虚拟子像素的发光层与第一子像素的发光层用于发出相同颜色的光。
综上所述，本公开实施例提供了一种阵列基板的制造方法。通过在显示区域内形成包括连接电极，且发出与亮度衰减程度最大的第一子像素所发光的颜色相同的虚拟子像素，可以通过控制该虚拟子像素发光来补偿第一子像素的亮度衰减，即可以通过控制该虚拟子像素发光来减小第一子像素和第二子像素的亮度衰减差异程度，该阵列基板制造方法制成的阵列基板对应的显示装置的显示效果较好。
可选的，参考图12，该阵列基板还可以包括：辅助电极305。相应的，图 18是本公开实施例提供的一种在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构的方法流程图。如图18所示，该方法可以包括：
步骤1701、在衬底基板的一侧形成栅极图案、有源层图案和源漏极图案，得到像素电路结构。
在本公开实施例中，可以通过构图工艺，在远离衬底基板00的方向依次形成有源层图案、栅极图案和源漏极图案，该方法得到的像素电路结构为底栅结构。或者，通过构图工艺，在远离衬底基板00的方向依次形成有源层图案、源漏极图案和栅极图案，该方法得到的像素电路结构为顶栅结构。可选的，该构图工艺可以包括：涂胶、曝光、显影和刻蚀等处理。
示例的，形成有像素电路结构的衬底基板00可以如图19所示。参考图19，其示出的像素电路结构为底栅结构，即栅极图案M1和源漏极图案M2沿远离衬底基板00的方向依次排布。该栅极图案M1可以包括待形成的每个子像素(如第一子像素10、第二子像素20和虚拟子像素30)的栅极G1，源漏极图案M2可以包括待形成的每个子像素的源漏极SD以及该辅助电极305，有源层图案M3可以包括待形成的每个子像素的有源层L1。
可选的，参考图19，该源漏极图案M2还可以包括图12至图15任一所示的数据线V1、电源信号线V2以及开关电路40的源漏极SD(图中未示出)。该栅极图案M1还可以包括图10所示的开关电路40的栅极(图中未示出)。
需要说明的是，图19仅示出了待形成的第一子像素10和虚拟子像素30对应的栅极图案、源漏极图案和有源层图案。
步骤1702、在栅极图案、有源层图案和源漏极图案远离衬底基板的一侧形成驱动电极结构。
在本公开实施例中，在形成像素电路后，可以继续采用构图工艺，在栅极图案、有源层图案和源漏极图案远离衬底基板的一侧形成驱动电极结构。
示例的，形成有驱动电极结构M4的衬底基板00可以如图20所示。参考图20，该驱动电极图案M4可以包括：待形成的每个子像素的连接电极。图14仅示出了待形成的第一子像素10的连接电极101和虚拟子像素30的连接电极301。可选的，形成的驱动电极结构可以为阳极或者阴极。
需要说明的是，本公开实施例提供的构图工艺的曝光步骤，是采用包括不同形状和大小镂空区域的掩膜版执行的。由于对于虚拟子像素30，形成的连接 电极301在衬底基板00上的正投影的面积可以小于或等于发光层303在衬底基板00上的正投影的面积，因此，掩膜版与连接电极301对应的镂空区域的面积，可以小于或等于与发光层303对应的镂空区域的面积。
步骤1703、在驱动电极结构远离衬底基板的一侧形成发光层结构。
同理，可以继续采用构图工艺，在驱动电极结构M4远离衬底基板00的一侧形成发光层结构M5。
示例的，形成有发光层结构M5的衬底基板00可以如图21所示。参考图21，该发光层图案结构可以包括待形成的每个子像素的发光层。例如，图21仅示出了待形成的第一子像素的发光层103，以及待形成的虚拟子像素的发光层303。并且，参考图21，该虚拟子像素的像素电路302与发光层303可以通过连接电极301电连接，第一子像素的像素电路102与发光层103可以通过第一子像素的连接电极101电连接。
可选的，该不同子像素对应的发光层图案的形成材料可以不同。例如，在第一子像素10为绿色子像素，虚拟子像素30为绿色虚拟子像素时，该发光层结构M5的材料即可以为形成该绿色子像素的发光材料。
步骤1704、在发光层结构远离衬底基板的一侧形成电极层结构。
同理，可以继续采用构图工艺，在发光层结构M5远离衬底基板00的一侧形成电极层结构M6。
示例的，形成有电极层结构M6的衬底基板00可以如图22所示。参考图22，该电极层结构M6可以包括：每个子像素的电极层(图22仅示出了第一子像素的电极层104和虚拟子像素的电极层304)。可选的，形成的电极层可以为阳极或阴极，且该电极层结构和驱动电极结构对应的电极不同。
需要说明的是，结合图19至图22，对于底栅结构的阵列基板，形成子像素的方法还包括：通过构图工艺，在形成有源层L1之前，在衬底基板00的一侧先形成缓冲层B1；在形成有源层L1之后，在有源层L1远离缓冲层B1的一侧形成第一栅绝缘层GI1；在形成栅极G1之后，在栅极G1远离第一栅绝缘层GI1的一侧形成第二栅绝缘层GI2；在形成源漏极SD之后，在源漏极SD远离衬底基板00的一侧形成平坦层N1；在形成驱动电极结构(包括连接电极)之后，在驱动电极结构远离平坦层N1的一侧形成像素介定层D1；在像素介定层D1远离驱动电极结构的一侧形成空穴传输层H1；以及在形成发光层结构(包括发光层)之后，在发光层结构远离空穴传输层H1的一侧形成电子传输层E1。
还需要说明的是，还可以在衬底基板的边缘位置设置第一GOA单元、第一EOA单元、虚拟GOA单元和虚拟EOA单元。且各GOA单元和各EOA单元均与子像素的像素电路电连接，以控制像素电路驱动其电连接的子像素发光。
综上所述，本公开实施例提供了一种阵列基板的制造方法。通过在显示区域内形成包括连接电极，且发出与亮度衰减程度最大的第一子像素所发光的颜色相同的虚拟子像素，可以通过控制该虚拟子像素发光来补偿第一子像素的亮度衰减，即可以通过控制该虚拟子像素发光来减小第一子像素和第二子像素的亮度衰减差异程度，该阵列基板制造方法制成的阵列基板对应的显示装置的显示效果较好。
图23是本公开实施例提供的一种阵列基板的驱动方法流程图，用于驱动如图10至图16任一所示的阵列基板。如图23所示，该方法可以包括：
步骤230、向虚拟子像素的像素电路提供驱动信号，虚拟子像素的像素电路响应于驱动信号，通过虚拟子像素的连接电极驱动虚拟子像素的发光层发光。
可选的，参考图15，该阵列基板还可以包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路40，开关电路40还与控制信号端Con1电连接。相应的，参考图24，上述步骤230可以包括：
步骤2301、向控制信号端提供控制信号，开关电路响应于控制信号，控制其电连接的两个导电段导通。
在本公开实施例中，阵列基板的控制装置可以先向控制信号端提供处于有效电位的控制信号，相应的，开关电路即可以在该控制信号的控制下，控制其电连接的两个导电段导通。
例如，对于图15所示的阵列基板，一个开关电路40可以在控制信号的控制下，控制其电连接的数据线V1的两个导电段导通；另一个开关电路40可以在控制信号的控制下，控制其电连接的电源信号线V2导通。
步骤2302、向数据线提供数据信号，向电源信号线提供电源信号，向第一GOA单元提供补偿信号，且向第一EOA单元提供补偿信号。
在本公开实施例中，在向控制信号端Con1提供处于有效电位的控制信号后，控制装置可以控制与数据线V1连接的电路(如源极驱动电路)向数据线V1提供数据信号。该控制装置可以控制与电源信号线V2连接的电路向电源信号线V2提供电源信号。该控制装置可以控制与第一GOA单元连接的电路向虚拟 GOA单元提供补偿信号，以及可以控制与第一EOA单元连接的电路向虚拟EOA单元提供补偿信号。
然后，数据线V1可以将数据信号写入至像素电路，电源信号线V2可以将电源信号写入至像素电路302，第一GOA单元可以向像素电路302输出栅极驱动信号和复位信号，第一EOA单元可以向像素电路302输出发光控制信号。相应的，像素电路302可以在该多个信号的控制下，向其所电连接的发光层303输出驱动信号，以驱动其所电连接的发光层303发光。
需要说明的是，本公开实施例对上述步骤2301和步骤2302的先后顺序不做限定。例如，步骤2301和步骤2302可以同步执行。
综上所述，本公开实施例提供了一种阵列基板的控制方法。通过向各信号线、第一GOA单元和第一EOA单元提供信号，使得虚拟子像素的像素电路可以可靠驱动虚拟子像素的发光层发光。由于该虚拟子像素可以发出与亮度衰减程度最大的第一子像素所发光的颜色相同的光，因此通过控制该虚拟子像素发光，有效减小了第一子像素和第二子像素的亮度衰减差异程度，该阵列基板制成的阵列基板对应的显示装置的显示效果较好。
可选的，本公开实施例还提供了一种阵列基板的控制装置，该控制装置可以与虚拟子像素的像素电路电连接，该控制装置可以执行如图23和图24任一所示的阵列基板的驱动方法。例如，该控制装置可以为处理器。
可选的，本公开实施例还提供了一种显示装置，该显示装置可以包括：如图10至图16任一所示的阵列基板，以及上述阵列基板的控制装置。该显示装置可以为：液晶面板、电子纸、有机发光二极管(Organic Light-Emitting Diode，OLED)面板、有源矩阵有机发光二极管(Active-matrix organic light-emitting diode，AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的阵列基板、各电路以及阵列基板的控制装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (19)

  1. 一种阵列基板，其特征在于，所述阵列基板包括：衬底基板，以及位于所述衬底基板的显示区域内的第一子像素、第二子像素和虚拟子像素，所述显示区域具有缺口，在沿所述显示区域的中心靠近所述缺口的目标方向上，所述第一子像素的亮度衰减程度大于所述第二子像素的亮度衰减程度；
    每个子像素均包括：像素电路、连接电极、发光层和电极层，所述发光层与所述像素电路通过所述连接电极电连接，所述发光层还与所述电极层电连接，所述像素电路用于通过所述连接电极驱动所述发光层发光，且所述虚拟子像素中的发光层与所述第一子像素中的发光层用于发出相同颜色的光。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述虚拟子像素的连接电极与所述第一子像素的连接电极位于同层。
  3. 根据权利要求1所述的阵列基板，其特征在于，在所述虚拟子像素中，所述连接电极在所述衬底基板上的正投影的面积，小于或等于所述发光层在所述衬底基板上的正投影的面积。
  4. 根据权利要求3所述的阵列基板，其特征在于，在所述虚拟子像素中，所述连接电极在所述衬底基板上的正投影的面积，与所述发光层在所述衬底基板上的正投影的面积的比值范围为：7％至15％。
  5. 根据权利要求1至4任一所述的阵列基板，其特征在于，所述阵列基板还包括：辅助电极，且所述辅助电极与所述虚拟子像素中的连接电极沿远离所述衬底基板的方向依次排布；
    所述虚拟子像素的像素电路、所述辅助电极、所述虚拟子像素的连接电极和所述虚拟子像素的发光层依次电连接。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述辅助电极与所述虚拟子像素的像素电路中的源漏极位于同层。
  7. 根据权利要求1至6任一所述的阵列基板，其特征在于，所述阵列基板还包括：数据线、电源信号线、第一移位寄存器GOA单元和第一移位寄存器EOA单元；
    所述数据线、所述电源信号线、所述第一GOA单元和所述第一EOA单元均与所述虚拟子像素的像素电路电连接；
    所述数据线用于向所述虚拟子像素的像素电路提供数据信号，所述电源信号线用于向所述虚拟子像素的像素电路提供电源信号，所述第一GOA单元用于向所述虚拟子像素的像素电路提供栅极驱动信号，所述第一EOA单元用于向所述虚拟子像素的像素电路提供发光控制信号。
  8. 根据权利要求7所述的阵列基板，其特征在于，所述阵列基板还包括：虚拟GOA单元和虚拟EOA单元，且所述虚拟GOA单元和所述虚拟EOA单元均与所述第一子像素的像素电路电连接，所述第一子像素和所述虚拟子像素沿所述目标方向依次排布且相邻；
    所述第一EOA单元、所述第一GOA单元和所述第一子像素沿栅线扫描方向依次排布，所述虚拟GOA单元与所述第一GOA单元沿所述目标方向依次排布，所述虚拟EOA单元和所述第一EOA单元沿所述目标方向依次排布；
    或者，所述虚拟EOA单元、所述虚拟GOA单元和所述第一子像素沿栅线扫描方向依次排布，所述虚拟GOA单元与所述第一GOA单元沿所述目标方向的反方向依次排布，所述虚拟EOA单元和所述第一EOA单元沿所述目标方向的反方向依次排布。
  9. 根据权利要求7所述的阵列基板，其特征在于，所述阵列基板还包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路；
    每条所述信号线包括两个导电段，且所述两个导电段通过所述信号线对应的开关电路电连接，所述信号线集合包括：所述数据线，所述电源信号线，所述第一GOA单元与所述虚拟子像素的像素电路电连接的信号线，以及所述第一EOA单元与所述虚拟子像素的像素电路电连接的信号线；
    所述开关电路还与控制信号端电连接，所述开关电路用于响应于所述控制信号端提供的控制信号，控制其电连接的两个导电段的通断状态。
  10. 根据权利要求9所述的阵列基板，其特征在于，所述至少一个开关电路包括：与所述数据线对应的开关电路，以及与所述电源信号线对应的开关电路。
  11. 根据权利要求9所述的阵列基板，其特征在于，所述开关电路包括：晶体管；
    所述晶体管的栅极与所述控制信号端电连接，所述晶体管的第一极与一条信号线的一个导电段电连接，所述晶体管的第二极与所述一条信号线的另一个导电段电连接。
  12. 根据权利要求1至11任一所述的阵列基板，其特征在于，所述阵列基板还包括：位于所述显示区域内的第三子像素；
    所述第一子像素、所述第二子像素和所述第三子像素所发出光的颜色不同，且在栅线扫描方向上，所述第二子像素和所述第三子像素之间并列排布有两个用于发出目标颜色的光的子像素，所述目标颜色与所述第一子像素所发出光的颜色相同。
  13. 根据权利要求12所述的阵列基板，其特征在于，所述第一子像素为绿色子像素，所述第二子像素为红色子像素，所述第三子像素为蓝色子像素。
  14. 一种阵列基板的制造方法，其特征在于，所述方法包括：
    在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构，以得到第一子像素、第二子像素和虚拟子像素；
    其中，所述像素电路结构包括：每个子像素的像素电路，所述驱动电极结构包括所述每个子像素的连接电极，所述发光层结构包括所述每个子像素的发光层，所述电极层结构包括所述每个子像素的电极层，且在每个所述子像素中，所述发光层与所述像素电路通过所述连接电极电连接，所述发光层还与所述电极层电连接，所述像素电路用于通过所述连接电极驱动所述发光层发光；
    所述显示区域具有缺口，在沿所述显示区域的中心靠近所述缺口的目标方向上，所述第一子像素的亮度衰减程度大于所述第二子像素的亮度衰减程度，所述虚拟子像素的发光层与所述第一子像素的发光层用于发出相同颜色的光。
  15. 根据权利要求14所述的方法，其特征在于，所述阵列基板还包括：辅助电极，所述辅助电极与所述虚拟子像素的连接电极电连接；所述在衬底基板的显示区域内依次形成像素电路结构、驱动电极结构、发光层结构和电极层结构，包括：
    在所述衬底基板的一侧形成栅极图案、有源层图案和源漏极图案，得到所述像素电路结构，其中，所述源漏极图案包括所述每个子像素的源漏极以及所述辅助电极，所述有源层图案包括所述每个子像素的有源层，所述栅极图案包括所述每个子像素的栅极；
    在所述栅极图案、所述有源层图案和所述源漏极图案远离所述衬底基板的一侧形成所述驱动电极结构；
    在所述驱动电极结构远离所述衬底基板的一侧形成所述发光层结构；
    在所述发光层结构远离所述衬底基板的一侧形成所述电极层结构。
  16. 一种阵列基板的驱动方法，其特征在于，用于驱动如权利要求1至13任一所述的阵列基板，所述方法包括：
    向虚拟子像素的像素电路提供驱动信号，所述虚拟子像素的像素电路响应于所述驱动信号，通过所述虚拟子像素的连接电极驱动所述虚拟子像素的发光层发光。
  17. 根据权利要求16所述的方法，其特征在于，所述阵列基板还包括：与信号线集合中的至少一条信号线一一对应的至少一个开关电路，所述开关电路还与控制信号端电连接；所述向虚拟子像素的像素电路提供驱动信号，包括：
    向所述控制信号端提供控制信号，所述开关电路响应于所述控制信号，控制其电连接的两个导电段导通；
    向数据线提供数据信号，向电源信号线提供电源信号，向第一GOA单元提供补偿信号，且向第一EOA单元提供补偿信号。
  18. 一种阵列基板的控制装置，其特征在于，所述控制装置与虚拟子像素的像素电路电连接，所述控制装置用于执行如权利要求16或17所述的阵列基板的驱动方法。
  19. 一种显示装置，其特征在于，所述显示装置包括：如权利要求1至13任一所述的阵列基板，以及如权利要求18所述的阵列基板的控制装置。
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