WO2024041311A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024041311A1
WO2024041311A1 PCT/CN2023/110033 CN2023110033W WO2024041311A1 WO 2024041311 A1 WO2024041311 A1 WO 2024041311A1 CN 2023110033 W CN2023110033 W CN 2023110033W WO 2024041311 A1 WO2024041311 A1 WO 2024041311A1
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WO
WIPO (PCT)
Prior art keywords
node
pixel
coupled
capacitor
transistor
Prior art date
Application number
PCT/CN2023/110033
Other languages
English (en)
French (fr)
Inventor
李宗祥
刘耀
姚丽清
吕耀朝
陈曦
张千
朱敬光
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024041311A1 publication Critical patent/WO2024041311A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the special-shaped display panel refers to a display panel with a special-shaped display area.
  • the special-shaped display area is generally in a non-rectangular shape such as a circle or a fan shape. That is, the edges of the special-shaped display area are generally curved (eg, rounded corners).
  • the pixels located at the edge of the special-shaped display panel have poor uniformity. Furthermore, the special-shaped display panel is prone to rainbow patterns during display, and the display effect is poor.
  • a display panel and display device are provided, and the technical solution is as follows:
  • a display panel is provided, and the display panel includes:
  • the base substrate has a special-shaped display area, the special-shaped display area is divided into a special-shaped edge area and a main display area, and the special-shaped edge area is close to the special-shaped edge of the special-shaped display area relative to the main display area;
  • a plurality of first pixels are located on one side of the base substrate and in the main display area;
  • a plurality of second pixels are located on one side of the base substrate and in the special-shaped edge area;
  • the number of the plurality of second pixels is less than the number of the plurality of first pixels
  • both the first pixels and the second pixels include: a pixel circuit and a light-emitting element, and the pixel circuit and the The light-emitting element is coupled and used to transmit a driving signal to the light-emitting element to drive the light-emitting element to emit light;
  • each second pixel includes a pixel circuit that transmits the driving signal to the light-emitting element
  • the potential of the signal is smaller than the potential of the driving signal transmitted to the light-emitting element by the pixel circuit included in any first pixel.
  • the plurality of second pixels include: multiple pixel groups, the multiple pixel groups are arranged sequentially along the direction from the main display area to the special-shaped edge, and each pixel group is at a distance from the special-shaped edge. The distances vary;
  • Each second pixel in each pixel group is arranged in a step-like manner in an extending direction parallel to the irregularly shaped edge, and each second pixel in each pixel group is equidistant from the irregularly shaped edge;
  • the potentials of the driving signals transmitted from the pixel circuits included in each second pixel to the light-emitting elements are equal, and along the main display area to the In the direction of the irregular edge, in each pixel group, the potential of the driving signal transmitted by the pixel circuit included in the second pixel to the light-emitting element gradually decreases, so that the display gray level of the second pixel gradually decreases.
  • the potential of the driving signal transmitted from the pixel circuit of the second pixel to the light-emitting element decreases according to the target decrement value, so that the voltage along the main display area to the edge of the special-shaped direction, in every two adjacent pixel groups, the ratio of the display gray level of the second pixel included in one pixel group to the display gray level of the second pixel included in the other pixel group is the target ratio.
  • the target ratio is 1/2.
  • the pixel circuit includes: a data writing circuit, a lighting control circuit, a potential adjustment circuit and a driving circuit;
  • the data writing circuit is coupled to the data signal terminal, the first scanning terminal and the first node respectively, and is used to control the data signal terminal and the first scanning terminal in response to the first scanning signal provided by the first scanning terminal. On/off of a node;
  • the light emitting control circuit is respectively coupled to the second scanning end, the light emitting control end, the first power end, the second power end, the first node, the second node and the third node, and is used to respond to the second
  • the second scan signal provided by the scan terminal controls the on-off of the second power terminal and the first node, controls the on-off of the second node and the third node, and responds to the lighting control
  • the light-emitting control signal provided by the terminal controls the connection between the first power terminal and the third node;
  • the potential adjustment circuit is coupled to the first node, the second node and the fourth node respectively, and is used to adjust the potential of the first node, the second node and the fourth node;
  • the driving circuit is coupled to the second node, the third node and the fourth node respectively, and is used to drive the voltage to the fourth node based on the potential of the second node and the potential of the third node.
  • the node transmits the driving signal
  • the light-emitting element is coupled to the fourth node and the second power terminal respectively, and is configured to emit light based on the potential of the fourth node and the second power signal provided by the second power terminal.
  • the potential adjustment circuit includes: a first capacitor and a second capacitor;
  • One end of the first capacitor is coupled to the first node, and the other end of the first capacitor is coupled to the second node;
  • One end of the second capacitor is coupled to the second node, and the other end of the second capacitor is coupled to the fourth node.
  • the capacitance values of the second capacitors included in the pixel circuit are equal, the capacitance value of the first capacitor is a target multiple of the capacitance value of the second capacitor, and the target multiple is less than or equal to 1;
  • the target multiple is related to the distance between the second pixel and the abnormal-shaped edge, so that among the plurality of second pixels, the distance between the second pixel and the abnormal-shaped edge is Different second pixels include pixel circuits that transmit different potentials of driving signals to the light-emitting elements.
  • both the first capacitor and the second capacitor include: a first electrode plate, an insulating layer and a second electrode plate sequentially stacked in a direction away from the base substrate, and the first electrode plate
  • the orthographic projection on the base substrate overlaps with the orthographic projection of the second electrode layer on the base substrate;
  • the dielectric constant of the insulating layer in the first capacitor and the second capacitor is the same, and in the first capacitor and the second capacitor, the first electrode plate and the The spacing between the second electrode plates is equal, and the overlapping area of the first electrode plate and the second electrode plate in the first capacitor is the overlapping area of the first electrode plate and the second electrode plate in the second capacitor. multiple of the target.
  • the area of the first electrode plate in the first capacitor is the target multiple of the area of the first electrode plate in the second capacitor
  • the area of the second electrode plate in the first capacitor is the The target multiple of the area of the second electrode plate in the second capacitor.
  • the area of one electrode plate among the first electrode plate and the second electrode plate included in the first capacitor is equal to the area of one electrode plate among the first electrode plate and the second electrode plate included in the second capacitor.
  • the area of the other electrode plate is the target multiple of the area of the other electrode plate among the first electrode plate and the second electrode plate included in the second capacitor.
  • the one electrode plate is the first electrode plate
  • the other electrode plate is the second electrode plate
  • the lighting control circuit is further coupled to the third scanning terminal and the fourth node, and is configured to control the second power terminal and the third scanning signal in response to the third scanning signal provided by the third scanning terminal. Describe the fourth Node on and off; the lighting control circuit includes: a first reset sub-circuit, a second reset sub-circuit, a compensation sub-circuit and a lighting control sub-circuit;
  • the first reset subcircuit is coupled to the second scan terminal, the second power terminal and the first node respectively, and is used to control the second power terminal and the first node in response to the second scan signal. On/off of the first node;
  • the second reset subcircuit is coupled to the third scan terminal, the second power terminal and the fourth node respectively, and is used to control the second power terminal and the fourth node in response to the third scan signal. On/off of the fourth node;
  • the compensation subcircuit is coupled to the second scan terminal, the second node and the third node respectively, and is used to control the second node and the third node in response to the second scan signal. Node connection and disconnection;
  • the lighting control sub-circuit is coupled to the lighting control terminal, the first power terminal and the third node respectively, and is used to control the first power terminal and the third node in response to the lighting control signal. Three-node switching.
  • the data writing circuit includes: a first transistor; the first reset sub-circuit includes: a second transistor; the second reset sub-circuit includes: a third transistor; and the compensation sub-circuit includes: a third transistor.
  • the lighting control sub-circuit includes: a fifth transistor; the driving circuit includes: a sixth transistor;
  • the gate electrode of the first transistor is coupled to the first scan terminal, the first electrode of the first transistor is coupled to the data signal terminal, and the second electrode of the first transistor is coupled to the first scan terminal. node coupling;
  • the gate of the second transistor is coupled to the second scan terminal, the first pole of the second transistor is coupled to the second power terminal, and the second pole of the second transistor is coupled to the second power terminal.
  • a node is coupled;
  • the gate of the third transistor is coupled to the third scan terminal, the first pole of the third transistor is coupled to the second power terminal, and the second pole of the third transistor is coupled to the third scan terminal.
  • the gate electrode of the fourth transistor is coupled to the second scan terminal, the first electrode of the fourth transistor is coupled to the third node, and the second electrode of the fourth transistor is coupled to the second scan terminal. node coupling;
  • the gate of the fifth transistor is coupled to the light-emitting control terminal, the first pole of the fifth transistor is coupled to the first power terminal, and the second pole of the fifth transistor is coupled to the third node coupling;
  • the gate electrode of the sixth transistor is coupled to the second node, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the fourth node. coupling.
  • the base substrate also has a non-display area adjacent to the special-shaped display area; the display panel further includes:
  • a black matrix layer is located on the side of the plurality of first pixels and the second pixels away from the base substrate, and is located in the special-shaped display area and the non-display area.
  • a display device which includes: a power supply component, and the display panel as described in the above aspect;
  • the power supply component is coupled to the display panel and used to power the display panel.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of yet another display panel provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a timing diagram of a signal terminal coupled to a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of yet another display panel provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic cross-sectional view of a capacitor provided by an embodiment of the present disclosure.
  • Figure 11 is an overlapping top view of an upper plate and a lower plate in a capacitor provided by an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of a capacitor design provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram of another capacitor design provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of a capacitor design provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an implementation of the present disclosure. As shown in FIG. 1 , the display panel includes: a base substrate 01 , a plurality of first pixels 02 and a plurality of second pixels 03 .
  • the base substrate 01 has a special-shaped display area A1.
  • the special-shaped display area A1 can be divided into a special-shaped edge area A11 and a main display area A12, and the special-shaped edge area A11 is closer to the special-shaped edge of the special-shaped display area A1 relative to the main display area A12. That is, referring to FIG. 1 , the special-shaped edge area A11 and the main display area A12 may be arranged sequentially in a direction away from the special-shaped edge.
  • the special-shaped display area A1 is generally in a non-rectangular shape such as a fan shape, an arc shape, a circle, a cylinder, or a polygon.
  • shaped edges are generally curved.
  • the special-shaped display area A1 of the substrate 01 shown in FIG. 1 is arc-shaped, and the special-shaped edge is arc-shaped.
  • the plurality of first pixels 02 are located on one side of the base substrate 01 and in the main display area A12.
  • the plurality of second pixels 03 are located on one side of the base substrate 01 and in the special-shaped edge area A11.
  • the area of the special-shaped edge area A11 may be smaller than the area of the main display area A12.
  • the number of the plurality of second pixels 03 may be smaller than the number of the plurality of first pixels 02 .
  • the first pixel 02 and the second pixel 03 in the embodiment of the present disclosure each include: a pixel circuit P1 and a light-emitting element L1.
  • the pixel circuit P1 is coupled to the light-emitting element L1 and is used to transmit a driving signal to the light-emitting element L1 to drive the light-emitting element L1 to emit light. Therefore, the luminance of the light-emitting element L1 can be controlled by the potential of the drive signal, and is positively correlated with the potential of the drive signal. That is, the greater the potential of the driving signal, the brighter the luminous brightness of the light-emitting element L1 can be; conversely, the smaller the potential of the driving signal, the darker the luminous brightness of the light-emitting element L1 can be.
  • the light-emitting element L1 can be a current-driven organic light-emitting diode (OLED).
  • the driving signal transmitted from the pixel circuit P1 to the light-emitting element L1 can be a driving current, and the potential of the driving signal is is the size of the driving current.
  • the luminance of the light-emitting element L1 can be controlled by the magnitude of the driving current, and is positively related to the magnitude of the driving current.
  • the display panel may be an OLED display panel. OLED display panels have many advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, and flexible display capabilities.
  • the light emitting element L1 is not limited to OLED.
  • the light-emitting element L1 may be a micro Micro LED or a mini mini LED.
  • each of the plurality of first pixels 02 and the plurality of second pixels 03 may include a plurality of different colors. pixels.
  • it generally includes multiple red (red, R) pixels, multiple green (green, G) pixels and multiple blue (blue, B) pixels. Since the second pixels 03 are located in the special-shaped edge area A11, affected by the special-shaped edge, the arrangement of the plurality of second pixels 03 has poor uniformity and is arranged in a non-periodic manner, and the proportions of the three RGB colors are unequal.
  • the display panel displays a target grayscale (eg, L255) picture
  • the potential of the driving signal transmitted by the pixel circuit P1 to the light-emitting element L1 in each pixel of the same color including the first pixel 02 and the second pixel 03
  • Equal that is, the luminous brightness of each pixel in the same color is the same.
  • the proportions of RGB three colors in the special-shaped edge area A11 are unequal, it is easy to cause color shift, which in turn causes rainbow patterns on the display panel and poor display effect.
  • the pixel circuit P1 included in each second pixel 03 with a different distance from the edge of the irregular shape can be transmitted to
  • the potential of the driving signal of the light-emitting element L1 is different, and the potential of the driving signal transmitted by the pixel circuit P1 included in each second pixel 03 to the light-emitting element L1 is smaller than the driving signal transmitted by the pixel circuit P1 included in any first pixel 02 to the light-emitting element L1 signal potential.
  • the pixel circuit P1 included in each second pixel 03 is set to transmit the driving signal to the light-emitting element L1
  • the potential is related to the distance from the edge of the special shape, and is smaller than the potential of the driving signal transmitted to the light-emitting element L1 by the pixel circuit P1 included in any first pixel 02 .
  • the potential of the drive signal may be the magnitude of the drive current. In this way, the luminous brightness of each second pixel 03 at different distances from the edge of the special-shaped shape can be made different.
  • the luminous brightness of each second pixel 03 gradually changes, and the plurality of second pixels 03
  • the maximum luminous brightness is smaller than the luminous brightness of the first pixel 02, which can reliably improve the rainbow pattern problem caused by uneven pixel arrangement and ensure a better display effect.
  • the pixel circuit P1 included in each second pixel 03 is set to transmit the drive to the light-emitting element L1
  • the potential of the signal is positively related to the distance from the edge of the profile. That is, among the plurality of second pixels 03, it is possible to set the second pixels 03 that are closer to the edge of the special shape (that is, the farther from the main display area A12), the higher the potential of the driving signal transmitted by the pixel circuit P1 to the light-emitting element L1.
  • the distance The luminous brightness of each second pixel 03 at different distances from the edge of the special shape gradually decreases.
  • each second pixel 03 described in the embodiment of the present disclosure is used to indicate that the luminous brightness of each second pixel 03 in the same color is the same.
  • the potential of the driving signal is designed based on distance, it is also for the same
  • the second pixel 03 of a color is illustrated.
  • the brightness proportions of the second pixels 03 of different colors in the target grayscale image can be different.
  • the potential designs of the driving signals for the second pixels 03 of different colors can be different, but the design principles are all: second pixel 03
  • the potential of the driving signal transmitted by the included pixel circuit P1 to the light-emitting element L1 is positively correlated with the distance from the edge of the profile.
  • inventions of the present disclosure provide a display panel.
  • the display panel includes a base substrate, a plurality of first pixels and a plurality of second pixels.
  • the base substrate has a special-shaped display area, and the special-shaped display area is divided into a special-shaped edge area and a main display area arranged sequentially in a direction away from the special-shaped edge.
  • the first pixel is located in the main display area.
  • the second pixel is located in the edge area of the special shape.
  • the potentials of the pixel circuits of the second pixels with different distances from the edges of the special-shaped shapes are transmitted to the light-emitting element driving signals, and are smaller than the potentials of the pixel circuits of the first pixels that are transmitted to the light-emitting elements.
  • the potential of the driving signal of the element can cause the luminous brightness of each second pixel at different distances from the edge of the special shape to gradually change, and the maximum luminous brightness of the second pixel is smaller than the luminous brightness of the first pixel.
  • the rainbow pattern problem caused by uneven pixel arrangement can be improved to ensure a better display effect.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure.
  • the base substrate 01 may also have a non-display area B1 adjacent to the special-shaped display area A1.
  • the display panel may also include: a black matrix (BM) layer 04, also known as the BM layer.
  • BM black matrix
  • the black matrix layer 04 may be located on a side of the plurality of first pixels 02 and the plurality of second pixels 03 away from the base substrate 01 , and may be located in the special-shaped display area A1 and the non-display area B1.
  • the orthographic projection of the black matrix layer 04 on the base substrate 01 and the orthographic projections of the plurality of first pixels 02 and the plurality of second pixels 03 on the base substrate 01 may not overlap. That is, the black matrix layer 04 may have openings that expose the first pixels 02 and the second pixels 03 so that the luminous lines emitted by the plurality of first pixels 02 and the plurality of second pixels 03 can be reliably emitted.
  • FIG. 2 schematically shows only a portion of the black matrix layer 04 located in the non-display area B1.
  • the boundary of this part of the black matrix layer 04 close to the special-shaped display area A1 may coincide with the special-shaped edge of the special-shaped display area A1.
  • the aperture ratio of the black matrix layer 04 can also be changed to solve the rainbow pattern problem caused by uneven pixel arrangement.
  • the aperture ratio is not changed, and the aperture ratio is only transferred to the pixel circuit P1 to emit light. Designing the potential of element L1 can not only solve the rainbow pattern, but also reliably avoid the problem of peripheral BM sawtooth problems caused by changes in the aperture ratio, thereby ensuring that the display effect of the display panel can be better.
  • the plurality of second pixels 03 may include: multiple pixel groups Z1. A total of four pixel groups are shown in FIG. 2, respectively identified as Z1-1, Z1-. 2. Z1-3 and Z1-4.
  • the plurality of pixel groups Z1 may be arranged sequentially along the direction from the main display area A12 to the edge of the special shape, and the distance between each pixel group Z1 and the edge of the special shape may be different.
  • the second pixels 03 in each pixel group Z1 may be arranged in a staircase shape in an extending direction parallel to the edge of the special shape, and the distances between the second pixels 03 in each pixel group Z1 and the edge of the special shape may be equal.
  • each second pixel 03 in each pixel group Z1 can be arranged in a staircase shape.
  • Figure 2 also schematically shows three color pixels of R, G and B. The same fill pattern represents the same color, and different fill patterns represent different colors.
  • each pixel group Z1 when the display panel displays a target grayscale picture, in each pixel group Z1, the potential of the driving signal transmitted to the light-emitting element L1 by the pixel circuit P1 included in each second pixel 03 can be equal, so that In each pixel group Z1, the luminous brightness of each second pixel 03 may be the same.
  • Luminous brightness can be characterized by display gray scale.
  • the display gray level of the second pixel 03 in each pixel group Z1 can be made the same, and the display gray level of the second pixel 03 in each pixel group Z1 gradually decreases along the direction from the main display area A12 to the edge of the special shape. .
  • the potential of the driving signal transmitted by the pixel circuit P1 included in the second pixel 03 to the light-emitting element L1 can be reduced according to the target decrement value, so that Along the direction from the main display area A12 to the edge of the special shape, in every two adjacent pixel groups Z1, the display gray level of the second pixel 03 included in one pixel group Z1 is the same as the display gray level of the second pixel 03 included in the other pixel group Z1.
  • the ratios of the steps can all be the target ratios.
  • the potential of the driving signal transmitted from the pixel circuit P1 included in the second pixel 03 in each two adjacent pixel groups Z1 to the light-emitting element L1 decreases according to the same target decrease value.
  • the display gray scale of the second pixel 03 in each two adjacent pixel groups Z1 also decreases according to the same gray scale value, that is, the decrease amplitude is the same. In this way, it is possible to ensure better display uniformity of the display panel and further improve the display effect.
  • the target ratio can be 1/2. That is, along the direction from the main display area A12 to the edge of the special shape, the display gray scale (which can also be considered as the luminous brightness) of the second pixel 03 in each pixel group Z1 is gradually reduced by half. In this way, the rainbow pattern can be better improved and ensure a better display effect.
  • the display gray level of each second pixel 03 can be 127.
  • Figure 3 respectively identifies the display gray levels of a red R pixel, a green G pixel and a blue B pixel in the first pixel group Z1-1 : R127, G127 and B127.
  • the display gray level of each second pixel 03 can be reduced to 64, which is the second pixel in the first pixel group Z1-1.
  • 03 displays 1/2 of the gray scale.
  • Figure 3 respectively identifies the display gray scales of a red R pixel, a green G pixel and a blue B pixel in the second pixel group Z1-2: R64, G64 and B64.
  • the display gray level of each second pixel 03 can be reduced to 32, which is the second pixel in the second pixel group Z1-2.
  • 03 displays 1/2 of the gray scale.
  • Figure 3 respectively identifies the display gray scale of a blue B pixel in the third pixel group Z1-3: B32.
  • the display gray level of each second pixel 03 can be reduced to 16, which is the second pixel in the third pixel group Z1-3.
  • 03's display grayscale is 1/2.
  • Figure 3 respectively identifies the display grayscales of a red R pixel, a green G pixel and a blue B pixel in the fourth pixel group Z1-4: R16, G16 and B16.
  • the decreasing amplitude may also be different. That is, taking three adjacent pixel groups Z1 as an example, the decreasing amplitude of the middle pixel group Z1 is different from that of the adjacent one pixel group Z1 and from the decreasing amplitude of another adjacent pixel group Z1. And, when the decreasing amplitude is the same, the target ratio can also be other values, such as 1/3.
  • FIG. 4 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit P1 may include: a data writing circuit P11 , a light emission control circuit P12 , a potential adjustment circuit P13 and a driving circuit P14 .
  • the data writing circuit P11 can be coupled to the data signal terminal Data, the first scanning terminal Scan1 and the first node N1 respectively, and can be used to control the data signal in response to the first scanning signal provided by the first scanning terminal Scan1
  • the terminal Data is connected to the first node N1.
  • the data writing circuit P11 may provide the first scanning signal at the first scanning terminal Scan1 When the potential of is the first potential, the data signal terminal Data is controlled to be connected to the first node N1. At this time, the data signal provided by the data signal terminal Data can be transmitted to the first node N1 to charge the first node N1. Moreover, the data writing circuit P11 can control the data signal terminal Data to disconnect from the first node N1 when the potential of the first scan signal provided by the first scan terminal Scan1 is the second potential.
  • the first potential may be an effective potential
  • the second potential may be an ineffective potential
  • the first potential may be a higher potential than the second potential
  • the lighting control circuit P12 can be coupled to the second scanning terminal Scan2, the lighting control terminal EM, the first power terminal VDD, the second power terminal VSS, the first node N1, the second node N2 and the third node N3 respectively, and can for controlling the on-off of the second power terminal VSS and the first node N1, and controlling the on-off of the second node N2 and the third node N3 in response to the second scan signal provided by the second scan terminal Scan2, and can respond to
  • the light-emitting control signal provided by the light-emitting control terminal EM controls the connection between the first power terminal VDD and the third node N3.
  • the light-emitting control circuit P12 can control the second power terminal VSS to conduct with the first node N1 when the potential of the second scan signal provided by the second scan terminal Scan2 is the first potential, and control the second node N2 to conduct with the first node N1.
  • Three nodes N3 are turned on.
  • the second power signal provided by the second power terminal VSS can be transmitted to the first node N1 to reset the first node N1, and the potential of the second node N2 and the potential of the third node N3 can influence each other.
  • the light-emitting control circuit P12 can control the second power terminal VSS to disconnect from the first node N1 when the potential of the second scan signal provided by the second scan terminal Scan2 is the second potential, and control the second node N2 It is disconnected from the third node N3.
  • the lighting control circuit P12 can control the first power supply terminal VDD to conduct with the third node N3 when the potential of the lighting control signal provided by the lighting control terminal EM is the first potential. At this time, the first power signal provided by the first power terminal VDD can be transmitted to the third node N3 to charge the third node N3. Furthermore, the light emission control circuit P12 can control the first power supply terminal VDD to disconnect from the third node N3 when the potential of the light emission control signal provided by the light emission control terminal EM is the second potential.
  • the first power signal may be at a high potential relative to the second power signal.
  • the second power supply terminal VSS can be the ground terminal.
  • the potential adjustment circuit P13 may be coupled to the first node N1, the second node N2, and the fourth node N4 respectively, and may be used to adjust the potentials of the first node N1, the second node N2, and the fourth node N4.
  • the driving circuit P14 can be coupled to the second node N2, the third node N3 and the fourth node N4 respectively, and can be used to drive the fourth node N4 to the fourth node N4 based on the potential of the second node N2 and the potential of the third node N3. Transmitting a driving signal (such as the driving current described in the above embodiment).
  • the light-emitting element L1 may be coupled to the fourth node N4 and the second power terminal VSS respectively, and may be used to emit light based on the potential of the fourth node N4 and the second power signal provided by the second power terminal VSS.
  • the light-emitting element L1 can emit light under the action of a voltage difference between the potential of the fourth node N4 and the second power signal.
  • the anode of the light-emitting element L1 may be coupled to the fourth node N4, and the cathode of the light-emitting element L1 may be coupled to the second power terminal VSS.
  • the anode and cathode of the light-emitting element L1 can also be interchanged.
  • Figure 5 shows a schematic structural diagram of another pixel circuit.
  • the light emitting control circuit P12 can also be coupled to the third scanning terminal Scan3 and the fourth node N4, and can be used to control the second power terminal in response to the third scanning signal provided by the third scanning terminal Scan3.
  • the light-emitting control circuit P12 can also control the second power terminal VSS to conduct with the fourth node N4 when the potential of the third scan signal provided by the third scan terminal Scan3 is the first potential.
  • the second power signal provided by the second power terminal VSS can be transmitted to the fourth node N4 to reset the fourth node N4. Since the fourth node N4 is coupled to the anode of the light-emitting element L1, it can also be considered as resetting the anode of the light-emitting element L1.
  • the light emission control circuit P12 can also control the second power supply terminal VSS to disconnect from the fourth node N4 when the potential of the third scanning signal provided by the third scanning terminal Scan3 is the second potential. That is, the light emission control circuit P12 may reset the anode of the light emitting element L1 in addition to resetting the first node N1 as shown in FIG. 4 .
  • FIG. 6 shows a schematic structural diagram of yet another pixel circuit.
  • the lighting control circuit P12 may include: a first reset sub-circuit P121 , a second reset sub-circuit P122 , a compensation sub-circuit P123 and a lighting control sub-circuit P124 .
  • the first reset sub-circuit P121 can be coupled to the second scan terminal Scan2, the second power terminal VSS and the first node N1 respectively, and can be used to control the second power terminal VSS and the first node N1 in response to the second scan signal.
  • One node N1 is switched on and off.
  • the first reset sub-circuit P121 can control the second power terminal VSS to conduct with the first node N1 when the potential of the second scan signal is the first potential. , causing the second power terminal VSS to be disconnected from the first node N1.
  • the second reset sub-circuit P122 can be connected to the third scanning terminal Scan3, the second power terminal VSS and The fourth node N4 is coupled and can be used to control the connection between the second power terminal VSS and the fourth node N4 in response to the third scan signal.
  • the second reset sub-circuit P122 can control the second power terminal VSS to conduct with the fourth node N4 when the potential of the third scan signal is the first potential, or can control the second power terminal VSS to conduct with the fourth node N4 when the potential of the third scan signal is the second potential. , controlling the second power terminal VSS to be disconnected from the fourth node N4.
  • the compensation sub-circuit P123 can be coupled to the second scan terminal Scan2, the second node N2 and the third node N3 respectively, and can be used to control the on-off of the second node N2 and the third node N3 in response to the second scan signal. .
  • the compensation subcircuit P123 can control the second node N2 and the third node N3 to be conductive when the potential of the second scan signal is the first potential, and can control the third node N3 to be conductive when the potential of the second scan signal is the second potential.
  • the second node N2 and the third node N3 are disconnected.
  • the lighting control sub-circuit P124 can be coupled to the lighting control terminal EM, the first power terminal VDD and the third node N3 respectively, and can be used to control the communication between the first power terminal VDD and the third node N3 in response to the lighting control signal. break.
  • the light-emitting control sub-circuit P124 can control the first power terminal VDD to conduct with the third node N3 when the potential of the light-emitting control signal is the first potential, and can control the third node N3 when the potential of the light-emitting control signal is the second potential.
  • a power terminal VDD is disconnected from the third node N3.
  • FIG. 7 shows a schematic structural diagram of yet another pixel circuit.
  • the data writing circuit P11 may include a first transistor T1.
  • the first reset sub-circuit P121 may include: a second transistor T2.
  • the second reset sub-circuit P122 may include: a third transistor T3.
  • the compensation sub-circuit P123 may include: a fourth transistor T4.
  • the light emission control sub-circuit P124 may include: a fifth transistor T5.
  • the driving circuit P14 may include a sixth transistor T6.
  • the potential adjustment circuit P13 may include: a first capacitor C1 and a second capacitor C2.
  • the gate of the first transistor T1 can be coupled with the first scanning terminal Scan1
  • the first pole of the first transistor T1 can be coupled with the data signal terminal Data
  • the second pole of the first transistor T1 can be coupled with the first node N1 coupling.
  • the gate of the second transistor T2 may be coupled to the second scan terminal Scan2, the first pole of the second transistor T2 may be coupled to the second power terminal VSS, and the second pole of the second transistor T2 may be coupled to the first node N1. catch.
  • the gate of the third transistor T3 may be coupled to the third scan terminal Scan3, and the gate of the third transistor T3 One pole may be coupled to the second power terminal VSS, and the second pole of the third transistor T3 may be coupled to the fourth node N4.
  • the gate electrode of the fourth transistor T4 may be coupled to the second scan terminal Scan2, the first electrode of the fourth transistor T4 may be coupled to the third node N3, and the second electrode of the fourth transistor T4 may be coupled to the second node N2. .
  • the gate of the fifth transistor T5 may be coupled to the light emitting control terminal EM, the first electrode of the fifth transistor T5 may be coupled to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 may be coupled to the third node N3 .
  • the gate electrode of the sixth transistor T6 may be coupled to the second node N2, the first electrode of the sixth transistor T6 may be coupled to the third node N3, and the second electrode of the sixth transistor T6 may be coupled to the fourth node N4.
  • One end of the first capacitor C1 may be coupled to the first node N1, and the other end of the first capacitor C1 may be coupled to the second node N2.
  • One end of the second capacitor C2 may be coupled to the second node N2, and the other end of the second capacitor C2 may be coupled to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure can all be field effect transistors or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their role in the circuit.
  • the first and second electrodes of the transistor one may be called the source and the other may be called the drain.
  • the middle terminal of the transistor is the gate
  • the signal input terminal is the first pole
  • the signal output terminal is the second pole.
  • the transistors used in the embodiments of the present disclosure may include any of P-type transistors and N-type transistors.
  • the first potential ie, effective potential
  • the second potential ie, ineffective potential
  • the P-type transistor is turned on when the potential of the gate is low, and when the gate is at a low potential, the P-type transistor is turned on. It is cut off when the potential of the pole is high.
  • the first potential ie, effective potential
  • the second potential ie, ineffective potential
  • the N-type transistor is turned on when the potential of the gate is high. It is cut off when the potential of the pole is low.
  • multiple signals in various embodiments of the present disclosure correspond to effective potentials and ineffective potentials. The effective potentials and ineffective potentials only represent that the potential of the signal has two state quantities, and do not represent specific values. The embodiments of the present disclosure are described assuming that each transistor is an N-type transistor.
  • the pixel circuit recorded in the embodiment of the present disclosure can also have other structures, as long as the above figure is included.
  • the two capacitors shown in 7 are enough.
  • it can also be a 5T2C structure.
  • each transistor in the pixel circuit is an N-type transistor, that is, the first potential is a high potential, and the second potential is a low potential
  • the working principle of the pixel circuit recorded in the embodiment of the present disclosure is introduced as follows. :
  • FIG. 8 shows a signal timing diagram of each signal terminal coupled to a pixel circuit.
  • the entire process of driving the light-emitting element by the pixel circuit may include four stages executed in sequence: t1 to t4.
  • the potential of the first power signal provided by the first power terminal VDD remains at the first potential, that is, the high potential.
  • the potential of the second power signal provided by the second power terminal VSS remains at the second potential, that is, the low potential.
  • the data signal terminal Data continuously provides a data signal of a certain potential.
  • the potential of the lighting control signal provided by the lighting control terminal EM, the potential of the second scanning signal provided by the second scanning terminal Scan2, and the potential of the third scanning signal provided by the third scanning terminal Scan3 are all the first potential.
  • the potential of the first scanning signal provided by the first scanning terminal Scan1 is the second potential.
  • the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are all turned on, and the first transistor T1 is turned off.
  • the second power signal provided by the second power terminal VSS can be transmitted to the first node N1 through the turned-on second transistor T2, and can be transmitted to the fourth node N4 through the turned-on third transistor T3, so as to respectively respond to the first node N1.
  • the node N1 and the fourth node N4 are reset.
  • the first power signal provided by the first power terminal VDD may be transmitted to the third node N3 through the turned-on fifth transistor T5 to precharge the third node N3.
  • the potential transmitted to the third node N3 can be transmitted to the second node N2 through the turned-on fourth transistor T4 to precharge the second node N2, so that the sixth transistor T6 is pre-turned on.
  • phase t1 can also be called the inversion & precharge phase.
  • the potential of the second scanning signal provided by the second scanning terminal Scan2 and the potential of the third scanning signal provided by the third scanning terminal Scan3 are both the first potential, and the potential of the lighting control signal provided by the lighting control terminal EM is equal to the potential of the third scanning signal provided by the third scanning terminal Scan3.
  • the potentials of the first scanning signals provided by a scanning terminal Scan1 are all the second potentials.
  • the second transistor T2 and the third transistor T3 are both turned on, the first transistor T1 and the fifth transistor T5 are both turned off, and the sixth transistor T6 remains turned on.
  • the second power signal provided by the second power terminal VSS can continue to be transmitted to the first node N1 through the turned-on second transistor T2, and can continue to be transmitted to the fourth node N4 through the turned-on third transistor T3. And, because the fifth transistor T5 is turned off and the fourth transistor T4 continues to remain on, the potential transmitted to the second node N2 in the stage t1 will now pass through the sixth The transistor T6 is released until the potential of the second node N2 is equal to the threshold voltage Vth of the sixth transistor T6, thereby achieving locking of the threshold voltage Vth of the sixth transistor T6.
  • phase t2 can also be called the Vth locking phase.
  • the potential of the first scanning signal provided by the first scanning terminal Scan1 and the potential of the third scanning signal provided by the third scanning terminal Scan3 are both the first potential, and the potential of the lighting control signal provided by the lighting control terminal EM is the same as the potential of the third scanning signal provided by the third scanning terminal Scan3.
  • the potentials of the second scanning signals provided by the two scanning terminals Scan2 are all the second potential.
  • the first transistor T1 and the third transistor T3 are both turned on, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are all turned off.
  • the data signal provided by the data signal terminal Data can be transmitted to the first node N1 through the turned-on first transistor T1 to charge the first node N1.
  • the second power signal provided by the second power terminal VSS may continue to be transmitted to the fourth node N4 through the turned-on third transistor T3.
  • phase t3 can also be called the data writing phase.
  • the potential of the second power signal is 0, the potential of the data signal is Vdata, the capacitance of the first capacitor C1 is c1, and the capacitance of the second capacitor C2 is c2.
  • the potential of the lighting control signal provided by the lighting control terminal EM is the first potential
  • the potential of the first scanning signal provided by the first scanning terminal Scan1 the potential of the second scanning signal provided by the second scanning terminal Scan2 and the third potential.
  • the potentials of the third scanning signals provided by the scanning terminal Scan3 are all the second potential.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off, and only the fifth transistor T5 and the sixth transistor T6 remain on.
  • a series path is formed between the first power supply terminal VDD, the fifth transistor T5, the sixth transistor T6, the light-emitting element L1 and the second power supply terminal VSS.
  • the first power signal provided by the first power terminal VDD is transmitted to the third node N3 through the turned-on fifth transistor T5.
  • the sixth transistor T6 can transmit the signal to the fourth node N4 based on the potential of the second node N2 and the potential of the third node N3.
  • a driving signal i.e., driving current
  • the signal emits light due to the voltage difference between the potential of the signal and the potential of the second power signal provided by the second power terminal VSS.
  • the driving current I DS finally transmitted from the pixel circuit P1 to the light-emitting element L1 can be expressed as:
  • ⁇ refers to the carrier mobility of the sixth transistor T6
  • COX is the capacitance of the gate insulating layer of the sixth transistor T6
  • W/L is the width-to-length ratio of the sixth transistor T6. They all belong to the same category as the sixth transistor T6. process design related constants. It can be seen that when the light-emitting element L1 is operating normally, the size of the driving current used to drive the light-emitting element L1 has nothing to do with the threshold voltage Vth of the driving transistor T0, but is related to the capacitance c1 of the first capacitor C1 and the capacitance of the second capacitor C2. The value c2 is related to the potential Vdata of the data signal.
  • the potential Vdata of the data signal is generally fixed and cannot be set regionally, and the capacitance c2 of the second capacitor C2 is generally fixed to reliably maintain the potential of the second node N2 and the fourth node The potential of N4. That is, in each second pixel 03, the capacitance c2 of the second capacitor C2 included in the pixel circuit P1 may be equal.
  • the capacitance c1 of the first capacitor C1 can be adjusted so that each pixel circuit P1 can still output driving currents I DS of different sizes under the same potential Vdata of the data signal, thereby achieving adjustment.
  • the second pixel 03 is for brightness purposes.
  • the capacitance c1 of the first capacitor C1 may be a target multiple of c2 of the capacitance of the second capacitor C2, and the target multiple may be greater than 0 and less than or equal to 1. And, for each second pixel 03, the target multiple may be related to the distance between the second pixel 03 and the edge of the abnormal shape.
  • the capacitance value of the first capacitor C1 can be smaller than the capacitance value of the second capacitor C2, and the distance between the capacitance value of the first capacitor C1 and the second pixel 03 from the edge of the abnormal shape satisfies a certain
  • the relationship is such that among the plurality of second pixels 03 , the potential of the driving signal transmitted to the light-emitting element L1 by the pixel circuit P1 of each second pixel 03 having a different distance from the edge of the irregular shape can be different.
  • the target multiple can be positively related to the distance between the second pixel 03 and the edge of the profile, so that the pixel circuit P1 included in the second pixel 03 transmits the driving signal to the light-emitting element L1
  • the potential is positively related to the distance from the edge of the profile.
  • the target multiple can be smaller, and the capacitance value of the first capacitor C1 can be smaller; for the second pixel 03 that is farther from the edge of the abnormal shape, The target multiple can be larger, and the capacitance value of the first capacitor C1 can be larger.
  • the capacitance value of the first capacitor C1 The larger the value, the greater the potential of the driving signal transmitted by the pixel circuit P1 to the light-emitting element L1, and the brighter the light-emitting brightness of the light-emitting element L1 can be.
  • the plurality of second pixels 03 are divided into a plurality of pixel groups Z1, and the luminous brightness of the second pixels 03 gradually decreases along the direction from the main display area A12 to the edge of the special shape, It can be set that along the direction from the main display area A12 to the edge of the special shape, the capacitance value of the first capacitor C1 of the pixel circuit P1 included in the second pixel 03 in each pixel group Z1 gradually decreases, and the second pixel 03 in each pixel group Z1 includes The capacitance values of the first capacitor C1 of the pixel circuit P1 are equal to achieve the purpose of gradually decreasing the brightness.
  • the decreasing amplitude of the capacitance value of the first capacitor C1 of the pixel circuit P1 included in the second pixel 03 in each pixel group Z1 may be the same.
  • A is a constant.
  • the driving current I DS needs to be reduced to 0.063A accordingly.
  • the driving current I DS needs to be reduced to 0.0313A accordingly.
  • the driving current I DS needs to be reduced to 0.0156A accordingly.
  • the capacitance c1 should be reduced to 0.143 times the capacitance c2 of the second capacitor C2, that is, the target multiple is 0.143.
  • both the first capacitor C1 and the second capacitor C2 may include: a first electrode plate C01 (ie, a lower electrode plate) sequentially stacked in a direction away from the base substrate 01 , an insulating layer J1 and the second electrode plate C02 (ie, the upper electrode plate), and the orthographic projection of the first electrode plate C01 on the base substrate 01 overlaps with the orthographic projection of the second electrode layer on the base substrate 01 .
  • Figure 11 shows a top view of the overlap, with the overlap area S identified.
  • ⁇ refers to the dielectric constant of the insulating layer J1
  • S refers to the overlapping area of the first electrode plate C01 and the second electrode plate C02
  • d refers to the distance between the first electrode plate C01 and the second electrode plate C02. , that is, the thickness of the insulating layer J1.
  • the capacitance c1 of the first capacitor C1 can be set by improving the overlapping area S between the upper plate and the lower plate. That is, the capacitance c1 of the first capacitor C1 is the same as the overlapping area S between the upper plate and the lower plate.
  • the dielectric constant ⁇ of the insulating layer J1 in the first capacitor C1 and the second capacitor C2 can be the same, and the dielectric constant ⁇ of the first capacitor C1 and the second capacitor C2 can be the same.
  • the distance d between one electrode plate C01 and the second electrode plate C02 may be equal, and the overlapping area S of the first electrode plate C01 and the second electrode plate C02 in the first capacitor C1 may be the first electrode in the second capacitor C2
  • the overlapping area S of the first electrode plate C01 and the second electrode plate C02 in the first capacitor C1 included in the second pixel 03 can be positively correlated with the distance from the edge of the special shape,
  • the overlapping area S between the upper plate and the lower plate of the first capacitor C1 can gradually decrease, and be consistent with the upper plate of the second capacitor C2.
  • the overlapping area S between the plate and the lower plate is in a multiple relationship.
  • the overlapping area S between the upper plate and the lower plate of the first capacitor C1 may be the same.
  • the second pixel 03 when the capacitance c2 of the second capacitor C2 is fixed, in each pixel group Z1 arranged sequentially in the direction from the main display area A12 to the edge of the special shape, the second pixel 03 includes
  • the overlapping area S between the upper plate and the lower plate of the first capacitor C1 can be respectively: 0.547 times and 0.333 times the overlapping area S between the upper plate and the lower plate of the second capacitor C2, 0.215 times and 0.143 times.
  • the overlapping area S between the upper plate and the lower plate of the first capacitor C1 included in the first pixel 02 may be the overlap between the upper plate and the lower plate of the second capacitor C2. 1 times the area S.
  • the embodiment of the present disclosure provides the following design methods:
  • the area of the first electrode plate C01 in the first capacitor C1 is a target multiple of the area of the first electrode plate C01 in the second capacitor C2, and the second electrode in the first capacitor C1
  • the area of plate C02 is a target multiple of the area of second electrode plate C02 in second capacitor C2. That is, according to the distance between the second pixel 03 and the edge of the special shape, the area of the first electrode plate C01 and the area of the second electrode plate C02 can be set to a target multiple of the area of the corresponding electrode plate in the second capacitor C2 to design the first capacitor.
  • the capacitance value of C1 is c1.
  • this implementation can be considered as: both the area of the first electrode plate C01 and the area of the second electrode plate C02 are gradually reduced.
  • the area of one electrode plate may be the same as the area of the first electrode plate included in the second capacitor C2.
  • the area of one of the first electrode plate C01 and the second electrode plate C02 is the same, and the area of the other electrode plate can be the area of the other of the first electrode plate C01 and the second electrode plate C02 included in the second capacitor C2 target multiple.
  • the area of the first electrode plate C01 or the area of the second electrode plate C02 can be set to a target multiple of the corresponding electrode plate area in the second capacitor C2 to design the first capacitor C1 The capacity value c1.
  • this implementation can be considered as: the area of the first electrode plate C01 or the area of the second electrode plate C02 is gradually reduced.
  • the implementation shown in FIG. 13 is: along the direction from the main display area A12 to the edge of the special shape, the area of the first electrode plate C01 is fixed, and the area of the second electrode plate C02 gradually decreases. That is, among the first capacitor C1 and the second capacitor C2, one electrode plate is the first electrode plate C01, and the other electrode plate is the second electrode plate C02. Since the first electrode plate C01 is located on the side closest to the base substrate 01, it is generally also used for light shielding. In this way, by setting the first electrode plate C01 to be fixed, that is, not decreasing, it is possible to achieve a better light shielding effect on the basis of setting the capacitance according to the distance.
  • the implementation shown in Figure 14 is: along the direction from the main display area A12 to the edge of the special shape, the area of the first electrode plate C01 gradually decreases, And the area of the second electrode plate C02 is fixed. That is, among the above-mentioned first capacitor C1 and second capacitor C2, one electrode plate is the second electrode plate C02, and the other electrode plate is the first electrode plate C01.
  • Figures 12 to 14 are all based on the method shown in Figure 9 as an example. From left to right, the overlapping areas S of the first electrode plate C01 and the second electrode plate C02 in the first capacitor C1 are shown as follows: : C2, 0.547C2, 0.333C2, 0.215C2 and 0.143C2, where C2 is used to indicate the overlapping area of the first electrode plate C01 and the second electrode plate C02 in the second capacitor C2.
  • the first pixel 02 and the second pixel 03 may generally include: a gate metal layer (gate, G) and a source-drain metal layer (G) sequentially stacked in a direction away from the base substrate 01 source, SD).
  • gate gate
  • G source-drain metal layer
  • the first electrode plate C01 may be located on the same layer as the gate metal layer G
  • the second electrode plate C02 may be located on the same layer as the source-drain metal layer SD.
  • a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located on "the same layer" are made of the same material and formed through the same patterning process. In this way, the manufacturing process and manufacturing costs can be saved, and the manufacturing efficiency can be accelerated. That is, in the embodiment of the present disclosure, the first electrode plate C01 and the gate metal layer G can be formed of the same material through one patterning process. Furthermore, the second electrode plate C02 and the source-drain metal layer SD can be formed using the same material through a patterning process.
  • the material of the first electrode plate C01 and the material of the second electrode plate C02 include: copper (Cu) or aluminum (Al).
  • the material of the insulating layer J1 may include silicon nitride (SiNx) and/or silicon oxide (SiOx).
  • the capacitance c2 of the second capacitor C2 is fixed, and the capacitance c1 of the first capacitor C1 is adjusted to achieve the purpose of adjusting the driving current.
  • the capacitance c1 of the first capacitor C1 can also be fixed and the capacitance c2 of the second capacitor C2 can be adjusted to achieve the purpose of adjusting the driving current.
  • the capacitance c1 of the first capacitor C1 and the capacitance c2 of the second capacitor C2 are changed simultaneously to achieve the purpose of adjusting the driving current. No matter which method is used, it can be set by combining the adjustment principles of Figures 3 and 9 so that the adjusted second pixel 03 faces the direction close to the edge of the special shape and the brightness gradually decreases.
  • the embodiment of the present disclosure adjusts the driving current transmitted from the pixel circuit P1 to the light-emitting element L1 by designing the capacitance value of the first capacitor C1 in the pixel circuit P1, so that the second pixel O3 in the special-shaped edge area A11 emits light.
  • the brightness gradually decreases toward the edge of the special shape, and the edge is modeled.
  • Pasty display treatment to reduce the risk of rainbow streaks on the edges.
  • inventions of the present disclosure provide a display panel.
  • the display panel includes a base substrate, a plurality of first pixels and a plurality of second pixels.
  • the base substrate has a special-shaped display area, and the special-shaped display area is divided into a special-shaped edge area and a main display area arranged sequentially in a direction away from the special-shaped edge.
  • the first pixel is located in the main display area.
  • the second pixel is located in the edge area of the special shape.
  • the potentials of the pixel circuits of the second pixels with different distances from the edges of the special-shaped shapes are transmitted to the light-emitting element driving signals, and are smaller than the potentials of the pixel circuits of the first pixels that are transmitted to the light-emitting elements.
  • the potential of the driving signal of the element can cause the luminous brightness of each second pixel at different distances from the edge of the special shape to gradually change, and the maximum luminous brightness of the second pixel is smaller than the luminous brightness of the first pixel.
  • the rainbow pattern problem caused by uneven pixel arrangement can be improved to ensure a better display effect.
  • FIG. 15 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 15 , the display device includes: a power supply component J1 and a display panel 00 as shown in the above figures.
  • the power supply component J1 can be coupled to the display panel 00 and used to power the display panel 00 .
  • the display device recorded in the embodiments of the present disclosure can be: OLED display device, Micro-LED display device, mini LED display device, dashboard in the car, smart watch, wearable component, mobile phone, tablet computer, flexible display Any product or component with a display function such as a device or television.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
  • plurality means two or more, unless otherwise Clear limits.

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Abstract

提供了一种显示面板及显示装置，属于显示技术领域。该显示面板包括衬底基板，多个第一像素和多个第二像素。衬底基板具有异形显示区，且该异形显示区又被划分为沿远离异形边缘的方向依次排布的异形边缘区和主显示区。第一像素位于主显示区。第二像素位于异形边缘区。因在显示面板显示目标灰阶的画面时，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件驱动信号的电位不同，且小于第一像素中像素电路传输至发光元件的驱动信号的电位，故可以使得距异形边缘不同距离位置处各个第二像素的发光亮度发生渐变，且第二像素的最大发光亮度小于第一像素的发光亮度。进而，可以改善像素排布不均带来的彩虹纹问题，确保显示效果较好。

Description

显示面板及显示装置
本公开要求于2022年8月24日提交的申请号为202211021460.3、发明名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
随着显示技术的不断发展，各类异形显示面板被广泛应用于显示装置中。
其中，异形显示面板是指具有异形显示区的显示面板，异形显示区一般呈圆形或扇形等非矩形状，即，异形显示区的边缘一般呈曲线(如，圆角)。
但是，受边缘呈曲线的影响，导致异形显示面板中位于边缘的像素排布均一性较差。进而，导致异形显示面板在显示时易出现彩虹纹，显示效果较差。
发明内容
提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，具有异形显示区，所述异形显示区被划分为异形边缘区和主显示区，且所述异形边缘区相对于所述主显示区靠近所述异形显示区的异形边缘；
多个第一像素，位于所述衬底基板的一侧，且位于所述主显示区；
多个第二像素，位于所述衬底基板的一侧，且位于所述异形边缘区；
其中，所述多个第二像素的数量小于所述多个第一像素的数量，且所述第一像素和所述第二像素均包括：像素电路和发光元件，所述像素电路与所述发光元件耦接，并用于向所述发光元件传输驱动信号，以驱动所述发光元件发光；
并且，在所述显示面板显示目标灰阶的画面时，所述多个第二像素中，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件的驱动信号的电位不同，且每个第二像素包括的像素电路传输至发光元件的驱动信 号的电位小于任一第一像素包括的像素电路传输至发光元件的驱动信号的电位。
可选的，所述多个第二像素包括：多个像素组，所述多个像素组沿所述主显示区至所述异形边缘的方向依次排布，且各个像素组距所述异形边缘的距离不等；
每个像素组中的各个第二像素在平行于所述异形边缘的延伸方向上呈阶梯状排布，且每个像素组中的各个第二像素距所述异形边缘的距离相等；
其中，在所述显示面板显示目标灰阶的画面时，每个像素组中，各个第二像素包括的像素电路传输至发光元件的驱动信号的电位相等，且沿所述主显示区至所述异形边缘的方向，各个像素组中，第二像素包括的像素电路传输至发光元件的驱动信号的电位逐渐递减，以使第二像素的显示灰阶逐渐递减。
可选的，任意相邻两个像素组中，第二像素包括的像素电路传输至发光元件的驱动信号的电位均按照目标递减值递减，以使沿所述主显示区至所述异形边缘的方向，每相邻两个像素组中，一个像素组包括的第二像素的显示灰阶与另一个像素组包括的第二像素的显示灰阶的比值均为目标比值。
可选的，所述目标比值为1/2。
可选的，所述像素电路包括：数据写入电路、发光控制电路、电位调节电路和驱动电路；
所述数据写入电路分别与数据信号端、第一扫描端和第一节点耦接，并用于响应于所述第一扫描端提供的第一扫描信号，控制所述数据信号端与所述第一节点的通断；
所述发光控制电路分别与第二扫描端、发光控制端、第一电源端、第二电源端、所述第一节点、第二节点和第三节点耦接，并用于响应于所述第二扫描端提供的第二扫描信号，控制所述第二电源端与所述第一节点的通断，且控制所述第二节点与所述第三节点的通断，以及响应于所述发光控制端提供的发光控制信号，控制所述第一电源端与所述第三节点的通断；
所述电位调节电路分别与所述第一节点、所述第二节点和第四节点耦接，并用于调节所述第一节点、所述第二节点和所述第四节点的电位；
所述驱动电路分别与所述第二节点、所述第三节点和所述第四节点耦接，并用于基于所述第二节点的电位和所述第三节点的电位，向所述第四节点传输驱动信号；
所述发光元件分别与所述第四节点和所述第二电源端耦接，并用于基于所述第四节点的电位和所述第二电源端提供的第二电源信号发光。
可选的，所述电位调节电路包括：第一电容和第二电容；
所述第一电容的一端与所述第一节点耦接，所述第一电容的另一端与所述第二节点耦接；
所述第二电容的一端与所述第二节点耦接，所述第二电容的另一端与所述第四节点耦接。
可选的，各个第二像素中，像素电路包括的第二电容的容值相等，第一电容的容值为第二电容的容值的目标倍数，且所述目标倍数小于等于1；
以及，对于每个第二像素而言，所述目标倍数与所述第二像素距所述异形边缘之间的距离相关，以使所述多个第二像素中，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件的驱动信号的电位不同。
可选的，所述第一电容和所述第二电容均包括：沿远离所述衬底基板的方向依次层叠的第一电极板、绝缘层和第二电极板，且所述第一电极板在所述衬底基板上的正投影与所述第二电极层在所述衬底基板上的正投影交叠；
其中，每个第二像素中，所述第一电容和所述第二电容中，绝缘层的介电常数相同，所述第一电容和所述第二电容中，第一电极板与所述第二电极板之间的间距相等，且所述第一电容中第一电极板与第二电极板的交叠面积为所述第二电容中第一电极板与第二电极板的交叠面积的所述目标倍数。
可选的，所述第一电容中第一电极板的面积为所述第二电容中第一电极板的面积的所述目标倍数，且所述第一电容中第二电极板的面积为所述第二电容中第二电极板的面积的所述目标倍数。
可选的，所述第一电容包括的第一电极板和第二电极板中，一个电极板的面积与所述第二电容包括的第一电极板和第二电极板中一个电极板的面积相同，另一个电极板的面积为所述第二电容包括的第一电极板和第二电极板中另一个电极板的面积的所述目标倍数。
可选的，所述第一电容和所述第二电容中，所述一个电极板为所述第一电极板，所述另一个电极板为所述第二电极板。
可选的，所述发光控制电路还与第三扫描端和所述第四节点耦接，并用于响应于所述第三扫描端提供的第三扫描信号，控制所述第二电源端与所述第四 节点的通断；所述发光控制电路包括：第一复位子电路、第二复位子电路、补偿子电路和发光控制子电路；
所述第一复位子电路分别与所述第二扫描端、所述第二电源端和所述第一节点耦接，并用于响应于所述第二扫描信号，控制所述第二电源端与所述第一节点的通断；
所述第二复位子电路分别与所述第三扫描端、所述第二电源端和所述第四节点耦接，并用于响应于所述第三扫描信号，控制所述第二电源端与所述第四节点的通断；
所述补偿子电路分别与所述第二扫描端、所述第二节点和所述第三节点耦接，并用于响应于所述第二扫描信号，控制所述第二节点与所述第三节点的通断；
所述发光控制子电路分别与所述发光控制端、所述第一电源端和所述第三节点耦接，并用于响应于所述发光控制信号，控制所述第一电源端与所述第三节点的通断。
可选的，所述数据写入电路包括：第一晶体管；所述第一复位子电路包括：第二晶体管；所述第二复位子电路包括：第三晶体管；所述补偿子电路包括：第四晶体管；所述发光控制子电路包括：第五晶体管；所述驱动电路包括：第六晶体管；
所述第一晶体管的栅极与所述第一扫描端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与所述第一节点耦接；
所述第二晶体管的栅极与所述第二扫描端耦接，所述第二晶体管的第一极与所述第二电源端耦接，所述第二晶体管的第二极与所述第一节点耦接；
所述第三晶体管的栅极与所述第三扫描端耦接，所述第三晶体管的第一极与所述第二电源端耦接，所述第三晶体管的第二极与所述第四节点耦接；
所述第四晶体管的栅极与所述第二扫描端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第二节点耦接；
所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述第一电源端耦接，所述第五晶体管的第二极与所述第三节点耦接；
所述第六晶体管的栅极与所述第二节点耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述第四节点耦接。
可选的，所述衬底基板还具有与所述异形显示区相邻的非显示区；所述显示面板还包括：
黑矩阵层，所述黑矩阵层位于所述多个第一像素和所述第二像素远离所述衬底基板的一侧，且位于所述异形显示区和所述非显示区。
另一方面，提供了一种显示装置，所述显示装置包括：供电组件，以及如上述方面所述的显示面板；
其中，所述供电组件与所述显示面板耦接，并用于为所述显示面板供电。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示面板的结构示意图；
图2是本公开实施例提供的另一种显示面板的结构示意图；
图3是本公开实施例提供的又一种显示面板的结构示意图；
图4是本公开实施例提供的一种像素电路的结构示意图；
图5是本公开实施例提供的另一种像素电路的结构示意图；
图6是本公开实施例提供的又一种像素电路的结构示意图；
图7是本公开实施例提供的再一种像素电路的结构示意图；
图8是本公开实施例提供的一种像素电路所耦接的信号端的时序图；
图9是本公开实施例提供的再一种显示面板的结构示意图；
图10是本公开实施例提供的一种电容的截面示意图；
图11是本公开实施例提供的一种电容中上极板和下极板的交叠俯视图；
图12是本公开实施例提供的一种电容设计示意图；
图13是本公开实施例提供的另一种电容设计示意图；
图14是本公开实施例提供的一种电容设计示意图；
图15是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开实施提供的一种显示面板的结构示意图。如图1所示，该显示面板包括：衬底基板01，多个第一像素02和多个第二像素03。
其中，该衬底基板01具有异形显示区A1。该异形显示区A1能够被划分为异形边缘区A11和主显示区A12，且异形边缘区A11相对于主显示区A12靠近异形显示区A1的异形边缘。即，参考图1，异形边缘区A11和主显示区A12可以沿远离异形边缘的方向依次排布。
可选的，异形显示区A1一般呈扇形、弧形、圆形、圆柱形或多边形等非矩形状。相应的，异形边缘一般呈曲线。如，图1示出的衬底基板01的异形显示区A1呈圆弧形，异形边缘呈弧线。
该多个第一像素02，位于衬底基板01的一侧且位于主显示区A12。该多个第二像素03，位于衬底基板01的一侧且位于异形边缘区A11。
可选的，在本公开实施例中，异形边缘区A11的面积可以小于主显示区A12的面积。相应的，多个第二像素03的数量可以小于多个第一像素02的数量。
继续参考图1中第一像素02和第二像素03的放大示意图可知，本公开实施例中的第一像素02和第二像素03均包括：像素电路P1和发光元件L1。
其中，像素电路P1与发光元件L1耦接，并用于向发光元件L1传输驱动信号，以驱动发光元件L1发光。由此，发光元件L1的发光亮度可以由驱动信号的电位所控制，与驱动信号的电位正相关。即，驱动信号的电位越大，发光元件L1的发光亮度可以越亮；反之，驱动信号的电位越小，发光元件L1的发光亮度可以越暗。如，发光元件L1可以为电流驱动发亮的有机发光二极管(organic light-emitting diode，OLED)，相应的，像素电路P1传输至发光元件L1的驱动信号可以为驱动电流，驱动信号的电位大小即为驱动电流的大小。发光元件L1的发光亮度可以由该驱动电流大小所控制，与驱动电流的大小正相关。显示面板可以为OLED显示面板。OLED显示面板具有自发光、驱动电压低、发光效率高、响应时间短和可实现柔性显示等诸多优点。
当然，发光元件L1也不限于OLED。如，在一些其他实施例中，发光元件L1可以为微型Micro LED，或者迷你mini LED。
可选的，多个第一像素02和多个第二像素03均可以包括多种不同颜色的 像素。如，一般可以包括多个红色(red，R)像素、多个绿色(green，G)像素和多个蓝色(blue，B)像素。因第二像素03位于异形边缘区A11，故受异形边缘影响，多个第二像素03的排布均一性较差，呈非周期性排列，进而RGB三色占比不等。目前，在显示面板显示目标灰阶(如，L255)的画面时，同一种颜色的各个像素(包括第一像素02和第二像素03)中像素电路P1传输至发光元件L1的驱动信号的电位相等，即同一种颜色中各个像素的发光亮度相同。如此，在异形边缘区A11中RGB三色占比不等基础上，极易造成色偏现象，进而造成显示面板出现彩虹纹，显示效果较差。
而在本公开实施例中，可以在显示面板显示目标灰阶的画面时，设置多个第二像素03中，与异形边缘之间的距离不同的各个第二像素03包括的像素电路P1传输至发光元件L1驱动信号的电位不同，且每个第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位小于任一第一像素02包括的像素电路P1传输至发光元件L1的驱动信号的电位。即，在显示面板中，所有第一像素02和所有第二像素03均用于显示相同的灰阶画面时，设置每个第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位与距异形边缘之间的距离相关，且小于任一第一像素02包括的像素电路P1传输至发光元件L1的驱动信号的电位。并且，驱动信号的电位可以为驱动电流的大小。如此，可以使得距异形边缘不同距离位置处各个第二像素03的发光亮度不同，沿主显示区A12至异形边缘的方向，各个第二像素03的发光亮度发生渐变，且多个第二像素03的最大发光亮度小于第一像素02的发光亮度，从而可以可靠改善像素排布不均带来的彩虹纹问题，确保显示效果可以较好。
示例的，可以在显示面板中，所有第一像素02和所有第二像素03均用于显示相同的灰阶画面时，设置每个第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位与距异形边缘之间的距离正相关。即，可以设置多个第二像素03中，与异形边缘距离越近(即，距主显示区A12越远)的第二像素03中，像素电路P1传输至发光元件L1的驱动信号的电位越小，使得与异形边缘距离越近的第二像素03中发光元件L1的发光亮度越暗，以及与异形边缘距离越远(即，距主显示区A12越近)的第二像素03中，像素电路P1传输至发光元件L1的驱动信号的电位越大，使得与异形边缘距离越远的第二像素03中发光元件L1的发光亮度越亮。最终使得沿主显示区A12至异形边缘的方向，距 异形边缘不同距离位置处各个第二像素03的发光亮度逐渐递减。
需要说明的是，本公开实施例记载的各个第二像素03的发光亮度相同用于指示同一种颜色中各个第二像素03的发光亮度相同，在基于距离设计驱动信号的电位时，也是针对同一种颜色的第二像素03进行说明。不同颜色的第二像素03在目标灰阶画面中的亮度占比可以不同，相应的，针对不同颜色的第二像素03，驱动信号的电位设计可以不同，但设计原理均为：第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位与距异形边缘之间的距离正相关。
综上所述，本公开实施例提供了一种显示面板。该显示面板包括衬底基板，多个第一像素和多个第二像素。衬底基板具有异形显示区，且该异形显示区又被划分为沿远离异形边缘的方向依次排布的异形边缘区和主显示区。第一像素位于主显示区。第二像素位于异形边缘区。因在显示面板显示目标灰阶的画面时，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件驱动信号的电位不同，且小于第一像素中像素电路传输至发光元件的驱动信号的电位，故可以使得距异形边缘不同距离位置处各个第二像素的发光亮度发生渐变，且第二像素的最大发光亮度小于第一像素的发光亮度。进而，可以改善像素排布不均带来的彩虹纹问题，确保显示效果较好。
可选的，图2是本公开实施例提供的另一种显示面板的结构示意图。如图2所示，该衬底基板01还可以具有与异形显示区A1相邻的非显示区B1。该显示面板还可以包括：黑矩阵(black matrix，BM)层04，又称BM层。
其中，该黑矩阵层04可以位于多个第一像素02和多个第二像素03远离衬底基板01的一侧，且可以位于异形显示区A1和非显示区B1。该黑矩阵层04在衬底基板01上的正投影与多个第一像素02和多个第二像素03在衬底基板01上的正投影可以不重叠。即该黑矩阵层04可以具有暴露第一像素02和第二像素03的开口，以使多个第一像素02和多个第二像素03所发光线可靠射出。
示例的，图2仅示意性示出位于非显示区B1的部分黑矩阵层04。该部分黑矩阵层04靠近异形显示区A1的边界可以与异形显示区A1的异形边缘重合。
目前，在一些实施例中，还可以通过改变黑矩阵层04的开口率，以解决像素排布不均带来的彩虹纹问题，但是在改变开口率的同时，会造成周边BM锯齿不良问题。而本公开实施例不改变开口率，仅通过对像素电路P1传输至发光 元件L1的电位进行设计，可以在解决彩虹纹的同时，还可靠避免开口率变化引起的周边BM锯齿不良问题，从而确保显示面板的显示效果可以较好。
可选的，继续参考图2，在本公开实施例中，多个第二像素03可以包括：多个像素组Z1，图2中共示出四个像素组，分别标识为Z1-1、Z1-2、Z1-3和Z1-4。其中，该多个像素组Z1可以沿主显示区A12至异形边缘的方向依次排布，各个像素组Z1距异形边缘的距离可以不等。每个像素组Z1中的各个第二像素03可以在平行于异形边缘的延伸方向上呈阶梯状排布，且每个像素组Z1中的各个第二像素03距异形边缘的距离可以相等。
即，可以在异形边缘区A11内，沿异形边缘指向主显示区A12的方向(即，图2中箭头所指方向)，按照与异形边缘之间的距离，将多个第二像素03划分为多个像素组Z1。且，受呈弧形的异形边缘影响，每个像素组Z1中各个第二像素03可以均呈阶梯状排布。图2中还示意性示出R、G和B三个颜色像素，同一种填充图案代表同一种颜色，不同的填充图案代表不同的颜色。
在以上实施例划分基础上，当显示面板显示目标灰阶的画面时，每个像素组Z1中，各个第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位可以相等，使得每个像素组Z1中，各个第二像素03的发光亮度可以相同。并且，沿主显示区A12至异形边缘的方向，各个像素组Z1中，第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位可以逐渐递减，使得沿主显示区A12至异形边缘的方向，各个像素组Z1中第二像素03的发光亮度逐渐递减，即亮度渐变。发光亮度可以用显示灰阶表征。故，也即是可以使得每个像素组Z1中第二像素03的显示灰阶相同，且沿主显示区A12至异形边缘的方向，各个像素组Z1中第二像素03的显示灰阶逐渐递减。
可选的，在本公开实施例中，任意相邻两个像素组Z1中，第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位均可以按照目标递减值递减，以使沿主显示区A12至异形边缘的方向，每相邻两个像素组Z1中，一个像素组Z1包括的第二像素03的显示灰阶与另一个像素组Z1包括的第二像素03的显示灰阶的比值可以均为目标比值。即，沿主显示区A12至异形边缘的方向，每相邻两个像素组Z1中第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位均按照相同的目标递减值递减。相应的，每相邻两个像素组Z1中第二像素03的显示灰阶也均按照相同的灰阶值递减，即递减幅度相同。 如此，可以确保显示面板的显示均一性较好，进一步改善显示效果。
可选的，该目标比值可以为1/2。即，沿主显示区A12至异形边缘的方向，各个像素组Z1中，第二像素03的显示灰阶(也可以认为是发光亮度)逐渐减半。如此，可以更好的改善彩虹纹，确保显示效果较好。
例如，以目标灰阶为L255，目标比值为1/2为例，结合图2和图3，异形边缘区A11中，沿主显示区A12至异形边缘的方向，第一个像素组Z1-1中，各个第二像素03的显示灰阶可以为127，图3中分别标识了第一个像素组Z1-1中，一个红色R像素、一个绿色G像素和一个蓝色B像素的显示灰阶：R127、G127和B127。与第一个像素组Z1-1相邻的第二个像素组Z1-2中，各个第二像素03的显示灰阶可以减小为64，为第一个像素组Z1-1中第二像素03的显示灰阶的1/2，图3中分别标识了第二个像素组Z1-2中，一个红色R像素、一个绿色G像素和一个蓝色B像素的显示灰阶：R64、G64和B64。与第二个像素组Z1-2相邻的第三个像素组Z1-3中，各个第二像素03的显示灰阶可以减小为32，为第二个像素组Z1-2中第二像素03的显示灰阶的1/2，图3中分别标识了第三个像素组Z1-3中，一个蓝色B像素的显示灰阶：B32。与第三个像素组Z1-3相邻的第四个像素组Z1-4中，各个第二像素03的显示灰阶可以减小为16，为第三个像素组Z1-3中第二像素03的显示灰阶的1/2，图3中分别标识了第四个像素组Z1-4中，一个红色R像素、一个绿色G像素和一个蓝色B像素的显示灰阶：R16、G16和B16。
当然，在一些其他实施例中，递减幅度也可以不同。即，以相邻的三个像素组Z1为例，中间的像素组Z1与相邻的一个像素组Z1的递减幅度，以及与相邻的另一个像素组Z1的递减幅度不同。以及，在递减幅度相同时，目标比值也可以为其他数值，如1/3。
图4是本公开实施例提供的一种像素电路的结构示意图。如图4所示，该像素电路P1可以包括：数据写入电路P11、发光控制电路P12、电位调节电路P13和驱动电路P14。
其中，该数据写入电路P11可以分别与数据信号端Data、第一扫描端Scan1和第一节点N1耦接，并可以用于响应于第一扫描端Scan1提供的第一扫描信号，控制数据信号端Data与第一节点N1的通断。
例如，该数据写入电路P11可以在第一扫描端Scan1提供的第一扫描信号 的电位为第一电位时，控制数据信号端Data与第一节点N1导通。此时，数据信号端Data提供的数据信号可以传输至第一节点N1，以对第一节点N1充电。以及，该数据写入电路P11可以在第一扫描端Scan1提供的第一扫描信号的电位为第二电位时，控制数据信号端Data与第一节点N1断开耦接。
可选的，第一电位可以为有效电位，第二电位可以为无效电位。且，在本公开实施例中，第一电位相对于第二电位可以为高电位。
该发光控制电路P12可以分别与第二扫描端Scan2、发光控制端EM、第一电源端VDD、第二电源端VSS、第一节点N1、第二节点N2和第三节点N3耦接，并可以用于响应于第二扫描端Scan2提供的第二扫描信号，控制第二电源端VSS与第一节点N1的通断，且控制第二节点N2与第三节点N3的通断，以及可以响应于发光控制端EM提供的发光控制信号，控制第一电源端VDD与第三节点N3的通断。
例如，该发光控制电路P12可以在第二扫描端Scan2提供的第二扫描信号的电位为第一电位时，控制第二电源端VSS与第一节点N1导通，且控制第二节点N2与第三节点N3导通。此时，第二电源端VSS提供的第二电源信号可以传输至第一节点N1，以对第一节点N1复位，第二节点N2的电位与第三节点N3的电位可以相互影响。以及，该发光控制电路P12可以在第二扫描端Scan2提供的第二扫描信号的电位为第二电位时，控制第二电源端VSS与第一节点N1断开耦接，且控制第二节点N2与第三节点N3断开耦接。
同理，该发光控制电路P12可以在发光控制端EM提供的发光控制信号的电位为第一电位时，控制第一电源端VDD与第三节点N3导通。此时，第一电源端VDD提供的第一电源信号可以传输至第三节点N3，以对第三节点N3充电。以及，该发光控制电路P12可以在发光控制端EM提供的发光控制信号的电位为第二电位时，控制第一电源端VDD与第三节点N3断开耦接。
可选的，在本公开实施例中，第一电源信号相对于第二电源信号可以为高电位。第二电源端VSS可以为地端。
该电位调节电路P13可以分别与第一节点N1、第二节点N2和第四节点N4耦接，并可以用于调节第一节点N1、第二节点N2和第四节点N4的电位。
该驱动电路P14可以分别与第二节点N2、第三节点N3和第四节点N4耦接，并可以用于基于第二节点N2的电位和第三节点N3的电位，向第四节点N4 传输驱动信号(如，上述实施例记载的驱动电流)。
该发光元件L1可以分别与第四节点N4和第二电源端VSS耦接，并可以用于基于第四节点N4的电位和第二电源端VSS提供的第二电源信号发光。
例如，该发光元件L1可以在第四节点N4的电位与第二电源信号的电位压差作用下发光。
可选的，参考图4，在发光元件L1为OLED时，可以是发光元件L1的阳极与第四节点N4耦接，发光元件L1的阴极与第二电源端VSS耦接。当然，在一些其他实施例中，发光元件L1的阳极和阴极也可以互换。
在图4基础上，图5示出了另一种像素电路的结构示意图。如图5所示，该发光控制电路P12还可以与第三扫描端Scan3和第四节点N4耦接，并可以用于响应于第三扫描端Scan3提供的第三扫描信号，控制第二电源端VSS与第四节点N4的通断。
例如，该发光控制电路P12还可以在第三扫描端Scan3提供的第三扫描信号的电位为第一电位时，控制第二电源端VSS与第四节点N4导通。此时，第二电源端VSS提供的第二电源信号可以传输至第四节点N4，以对第四节点N4复位。因第四节点N4是与发光元件L1的阳极耦接，故也可以认为是对发光元件L1的阳极进行复位。以及，该发光控制电路P12还可以在第三扫描端Scan3提供的第三扫描信号的电位为第二电位时，控制第二电源端VSS与第四节点N4断开耦接。即，发光控制电路P12除了可以如图4所示对第一节点N1复位，也可以对发光元件L1的阳极复位。
在图5基础上，图6示出了再一种像素电路的结构示意图。如图6所示，该发光控制电路P12可以包括：第一复位子电路P121、第二复位子电路P122、补偿子电路P123和发光控制子电路P124。
其中，该第一复位子电路P121可以分别与第二扫描端Scan2、第二电源端VSS和第一节点N1耦接，并可以用于响应于第二扫描信号，控制第二电源端VSS与第一节点N1的通断。
例如，该第一复位子电路P121可以在第二扫描信号的电位为第一电位时，制第二电源端VSS与第一节点N1导通，可以在第二扫描信号的电位为第二电位时，制第二电源端VSS与第一节点N1断开耦接。
该第二复位子电路P122可以分别与第三扫描端Scan3、第二电源端VSS和 第四节点N4耦接，并可以用于响应于第三扫描信号，控制第二电源端VSS与第四节点N4的通断。
例如，该第二复位子电路P122可以在第三扫描信号的电位为第一电位时，控制第二电源端VSS与第四节点N4导通，可以在第三扫描信号的电位为第二电位时，控制第二电源端VSS与第四节点N4断开耦接。
该补偿子电路P123可以分别与第二扫描端Scan2、第二节点N2和第三节点N3耦接，并可以用于响应于第二扫描信号，控制第二节点N2与第三节点N3的通断。
例如，该补偿子电路P123可以在第二扫描信号的电位为第一电位时，控制第二节点N2与第三节点N3导通，可以在第二扫描信号的电位为第二电位时，控制第二节点N2与第三节点N3断开耦接。
该发光控制子电路P124可以分别与发光控制端EM、第一电源端VDD和第三节点N3耦接，并可以用于响应于发光控制信号，控制第一电源端VDD与第三节点N3的通断。
例如，该发光控制子电路P124可以在发光控制信号的电位为第一电位时，控制第一电源端VDD与第三节点N3导通，可以在发光控制信号的电位为第二电位时，控制第一电源端VDD与第三节点N3断开耦接。
在图6基础上，图7示出了再一种像素电路的结构示意图。如图7所示，数据写入电路P11可以包括：第一晶体管T1。第一复位子电路P121可以包括：第二晶体管T2。第二复位子电路P122可以包括：第三晶体管T3。补偿子电路P123可以包括：第四晶体管T4。发光控制子电路P124可以包括：第五晶体管T5。驱动电路P14可以包括：第六晶体管T6。电位调节电路P13可以包括：第一电容C1和第二电容C2。
其中，第一晶体管T1的栅极可以与第一扫描端Scan1耦接，第一晶体管T1的第一极可以与数据信号端Data耦接，第一晶体管T1的第二极可以与第一节点N1耦接。
第二晶体管T2的栅极可以与第二扫描端Scan2耦接，第二晶体管T2的第一极可以与第二电源端VSS耦接，第二晶体管T2的第二极可以与第一节点N1耦接。
第三晶体管T3的栅极可以与第三扫描端Scan3耦接，第三晶体管T3的第 一极可以与第二电源端VSS耦接，第三晶体管T3的第二极可以与第四节点N4耦接。
第四晶体管T4的栅极可以与第二扫描端Scan2耦接，第四晶体管T4的第一极可以与第三节点N3耦接，第四晶体管T4的第二极可以与第二节点N2耦接。
第五晶体管T5的栅极可以与发光控制端EM耦接，第五晶体管T5的第一极可以与第一电源端VDD耦接，第五晶体管T5的第二极可以与第三节点N3耦接。
第六晶体管T6的栅极可以与第二节点N2耦接，第六晶体管T6的第一极可以与第三节点N3耦接，第六晶体管T6的第二极可以与第四节点N4耦接。
第一电容C1的一端可以与第一节点N1耦接，第一电容C1的另一端可以与第二节点N2耦接。
第二电容C2的一端可以与第二节点N2耦接，第二电容C2的另一端可以与第四节点N4耦接。
需要说明的是，本公开实施例所采用的晶体管均可以为场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。晶体管的第一极和第二极中，一极可以称为源极，另一极可以称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为第一极、信号输出端为第二极。此外，本公开实施例所采用的晶体管可以包括P型晶体管和N型晶体管中的任一种。对于P型晶体管而言，第一电位(即，有效电位)相对于第二电位(即，无效电位)可以为低电位，即P型晶体管在栅极的电位为低电位时导通，在栅极的电位为高电位时截止。对于N型晶体管而言，第一电位(即，有效电位)相对于第二电位(即，无效电位)可以为高电位，即N型晶体管在栅极的电位为高电位时导通，在栅极的电位为低电位时截止。此外，本公开各个实施例中的多个信号都对应有有效电位和无效电位，有效电位和无效电位仅代表该信号的电位有2个状态量，不代表具有特定的数值。本公开实施例以各个晶体管均为N型晶体管说明。
还需要说明的是，本公开实施例记载的像素电路除了可以为图7所示的6T2C(即，包括6个晶体管和2个电容)结构外，还可以为其他结构，前提是只要包括上述图7所示的2个电容即可。如还可以为5T2C结构。
以图7所示像素电路，且像素电路中各个晶体管均为N型晶体管，即第一电位为高电位，第二电位为低电位为例，对本公开实施例记载的像素电路的工作原理介绍如下：
示例的，图8示出了一种像素电路所耦接的各个信号端的信号时序图。如图8所示，像素电路驱动发光元件的整个过程可以包括依次执行的四个阶段：t1至t4。在阶段t1至t4中，第一电源端VDD提供的第一电源信号的电位保持为第一电位，即高电位。第二电源端VSS提供的第二电源信号的电位保持为第二电位，即低电位。数据信号端Data持续提供一定电位的数据信号。
其中，在阶段t1，发光控制端EM提供的发光控制信号的电位、第二扫描端Scan2提供的第二扫描信号的电位和第三扫描端Scan3提供的第三扫描信号的电位均为第一电位。第一扫描端Scan1提供的第一扫描信号的电位为第二电位。在此基础上，第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5均开启，第一晶体管T1关断。相应的，第二电源端VSS提供的第二电源信号可以经开启的第二晶体管T2传输至第一节点N1，且可以经开启的第三晶体管T3传输至第四节点N4，以分别对第一节点N1和第四节点N4复位。第一电源端VDD提供的第一电源信号可以经开启的第五晶体管T5传输至第三节点N3，以对第三节点N3预充电。且，传输至该第三节点N3的电位可以经开启的第四晶体管T4传输至第二节点N2，以对第二节点N2预充电，使得第六晶体管T6预开启。相应的，阶段t1也可以称为反置&预充电阶段。
例如，假设第一电源信号的电位为Vdd，第二电源信号的电位为0，则在阶段t1后，第一节点N1的电位VN1和第四节点N4的电位VN4均为0，即VN1＝VN4＝0，第二节点N2的电位VN2与第三节点N3的电位VN3均为Vdd，即VN2＝VN3＝Vdd。
在阶段t2，第二扫描端Scan2提供的第二扫描信号的电位和第三扫描端Scan3提供的第三扫描信号的电位均为第一电位，发光控制端EM提供的发光控制信号的电位和第一扫描端Scan1提供的第一扫描信号的电位均为第二电位。在此基础上，第二晶体管T2和第三晶体管T3均开启，第一晶体管T1和第五晶体管T5均关断，第六晶体管T6依然保持开启。第二电源端VSS提供的第二电源信号可以继续经开启的第二晶体管T2传输至第一节点N1，且可以继续经开启的第三晶体管T3传输至第四节点N4。以及，因第五晶体管T5关断，而第四晶体管T4继续保持开启，故在阶段t1传输至第二节点N2的电位此时会经第六 晶体管T6释放，直至第二节点N2的电位等于第六晶体管T6的阈值电压Vth为止，从而实现对第六晶体管T6的阈值电压Vth的锁定。相应的，阶段t2也可以称为Vth锁定阶段。
例如，假设第二电源信号的电位为0，则在阶段t2后，第一节点N1的电位VN1和第四节点N4的电位VN4依然均为0，即VN1＝VN4＝0，第二节点N2的电位VN2等于Vth，即VN2＝Vth。
在阶段t3，第一扫描端Scan1提供的第一扫描信号的电位和第三扫描端Scan3提供的第三扫描信号的电位均为第一电位，发光控制端EM提供的发光控制信号的电位和第二扫描端Scan2提供的第二扫描信号的电位均为第二电位。在此基础上，第一晶体管T1和第三晶体管T3均开启，第二晶体管T2、第四晶体管T4和第五晶体管T5均关断。相应的，数据信号端Data提供的数据信号可以经开启的第一晶体管T1传输至第一节点N1，以对第一节点N1充电。第二电源端VSS提供的第二电源信号可以继续经开启的第三晶体管T3传输至第四节点N4。相应的，阶段t3也可以称为数据写入阶段。
例如，假设第二电源信号的电位为0，数据信号的电位为Vdata，第一电容C1的容值为c1，第二电容C2的容值为c2。则在阶段t3后，第一节点N1的电位VN1为Vdata，即VN1＝Vdata。第四节点N4的电位VN4依然为0，即VN4＝0。因第二节点N2在第一电容C1与第二电容C2之间浮接，故在电容耦合效应下，第二节点N2的电位VN2可以满足：VN2＝Vth+c1/(c1+c2)*Vdata，第六晶体管T6依然保持开启。同时因第四节点N4的电位VN4为0，故第二电容C2的一端与另一端之间的压差即为：Vth+c1/(c1+c2)*Vdata，持续保持到下一帧。
在阶段t4，发光控制端EM提供的发光控制信号的电位为第一电位，第一扫描端Scan1提供的第一扫描信号的电位、第二扫描端Scan2提供的第二扫描信号的电位和第三扫描端Scan3提供的第三扫描信号的电位均为第二电位。在此基础上，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均关断，仅第五晶体管T5和第六晶体管T6保持开启。相应的，第一电源端VDD、第五晶体管T5、第六晶体管T6、发光元件L1和第二电源端VSS之间即形成串联通路。第一电源端VDD提供的第一电源信号经开启的第五晶体管T5传输至第三节点N3，第六晶体管T6可以基于第二节点N2的电位和第三节点N3的电位，向第四节点N4传输驱动信号(即，驱动电流)，发光元件L1在该驱动信 号的电位与第二电源端VSS提供的第二电源信号的电位压差作用下发光。
例如，假设第二电源信号的电位为0，数据信号的电位为Vdata，第一电容C1的容值为c1，第二电容C2的容值为c2。则像素电路P1最终传输至发光元件L1的驱动电流IDS可以表示为：
其中，μ是指第六晶体管T6的载流子迁移率，COX为第六晶体管T6的栅极绝缘层的电容，W/L为第六晶体管T6的宽长比，均属于与第六晶体管T6的工艺设计相关常数。如此可知确定，在发光元件L1正常工作时，用于驱动发光元件L1的驱动电流的大小与驱动晶体管T0的阈值电压Vth无关，而与第一电容C1的容值c1、第二电容C2的容值c2和数据信号的电位Vdata有关。
在显示面板显示目标灰阶的画面时，数据信号的电位Vdata一般固定，无法实现区域性设置，且第二电容C2的容值c2一般固定，以可靠维持第二节点N2的电位和第四节点N4的电位。即，各个第二像素03中，像素电路P1包括的第二电容C2的容值c2可以相等。为此，在本公开实施例中，可以通过调整第一电容C1的容值c1使各个像素电路P1在相同的数据信号的电位Vdata下，依然能够输出不同大小的驱动电流IDS，从而达到调整第二像素03亮度的目的。
可选的，在本公开实施例中，第一电容C1的容值c1可以为第二电容C2的容值的c2目标倍数，且目标倍数可以大于0且小于等于1。以及，对于每个第二像素03而言，目标倍数可以与第二像素03距异形边缘之间的距离相关。即，每个第二像素03中，第一电容C1的容值均可以小于第二电容C2的容值，且第一电容C1的容值与第二像素03距异形边缘之间的距离满足一定关系，以使多个第二像素03中，与异形边缘之间的距离不同的各个第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位可以不同。
如，对于每个第二像素03而言，目标倍数可以与第二像素03距异形边缘之间的距离正相关，以使第二像素03包括的像素电路P1传输至发光元件L1的驱动信号的电位与距异形边缘之间的距离正相关。换言之，多个第二像素03中，对于距异形边缘越近的第二像素03，目标倍数可以越小，第一电容C1的容值可以越小；距异形边缘越远的第二像素03，目标倍数可以越大，第一电容C1的容值可以越大。第一电容C1的容值越小，像素电路P1传输至发光元件L1的驱动信号的电位可以越小，发光元件L1的发光亮度可以越暗，第一电容C1的容值 越大，像素电路P1传输至发光元件L1的驱动信号的电位可以越大，发光元件L1的发光亮度可以越亮。
例如，对于图2和图3中，将多个第二像素03划分为多个像素组Z1，且沿主显示区A12至异形边缘的方向，第二像素03的发光亮度逐渐递减的实施例，可以设置沿主显示区A12至异形边缘的方向，各个像素组Z1中第二像素03包括的像素电路P1的第一电容C1的容值逐渐递减，且每个像素组Z1中第二像素03包括的像素电路P1的第一电容C1的容值相等，以达到亮度逐渐递减的目的。
并且，对于递减幅度相同的实施例而言，各个像素组Z1中第二像素03包括的像素电路P1的第一电容C1的容值递减幅度可以相同。
示例的，可以将上述公式(1)简化为下述公式(2)：
其中，A为常量。
在上述公式2基础上，假设第二电容C2的容值c2为1皮法(pF)，则当目标灰阶为L255，驱动电流IDS为0.25安培(A)时，代入上述公式(2)可知，第一电容C1的容值c1应该等于c2，即c1＝c2＝1pF。主显示区A12中，各个第一像素02中第一电容C1的容值c1和第二电容C2的容值c2可以满足该设计。
结合图3和图9，沿主显示区A12至异形边缘的方向，若第一个像素组Z1中各个第二像素03的显示灰阶需要减小至L127，则驱动电流IDS相应的需要减小至0.125A，代入上述公式(2)可知，第一电容C1的容值c1此时应该减小为第二电容C2的容值c2的0.547倍，即目标倍数为0.547，c1＝0.547c2＝0.547pF。
若第二个像素组Z1中各个第二像素03的显示灰阶需要减小至L64，则驱动电流IDS相应的需要减小至0.063A，代入上述公式(2)可知，第一电容C1的容值c1此时应该减小为第二电容C2的容值c2的0.333倍，即目标倍数为0.333，c1＝0.333c2＝0.333pF。
若第三个像素组Z1中各个第二像素03的显示灰阶需要减小至L32，则驱动电流IDS相应的需要减小至0.0313A，代入上述公式(2)可知，第一电容C1的容值c1此时应该减小为第二电容C2的容值c2的0.215倍，即目标倍数为0.215，c1＝0.215c2＝0.215pF。
若第四个像素组Z1中各个第二像素03的显示灰阶需要减小至L16，则驱动电流IDS相应的需要减小至0.0156A，代入上述公式(2)可知，第一电容C1的容值c1此时应该减小为第二电容C2的容值c2的0.143倍，即目标倍数为0.143， c1＝0.143c2＝0.143pF。
参考图10，在本公开实施例中，第一电容C1和第二电容C2均可以包括：沿远离衬底基板01的方向依次层叠的第一电极板C01(即，下极板)、绝缘层J1和第二电极板C02(即，上极板)，且第一电极板C01在衬底基板01上的正投影与第二电极层在衬底基板01上的正投影交叠。图11示出交叠俯视图，并标识出交叠面积S。
电容的容值c计算公式满足：其中，ε是指绝缘层J1的介电常数，S是指第一电极板C01和第二电极板C02的交叠面积，d是指第一电极板C01与第二电极板C02之间的间距，即绝缘层J1的厚度。
在显示面板的制造过程中，因设计限制，一般绝缘层J1的厚度和材料是固定的，相应的可知，ε和d即是固定的。基于此，在本公开实施例中，可以通过改善上极板与下极板之间的交叠面积S，来设置第一电容C1的容值c1。即，第一电容C1的容值c1与上极板与下极板之间的交叠面积S相同。
即，本公开实施例记载的每个第二像素03中，第一电容C1和第二电容C2中，绝缘层J1的介电常数ε可以相同，第一电容C1和第二电容C2中，第一电极板C01与第二电极板C02之间的间距d可以相等，且第一电容C1中第一电极板C01与第二电极板C02的交叠面积S可以为第二电容C2中第一电极板C01与第二电极板C02的交叠面积S的目标倍数。即，沿主显示区A12至异形边缘的方向，第二像素03包括的第一电容C1中第一电极板C01与第二电极板C02的交叠面积S与距异形边缘的间距可以正相关，间距越小，交叠面积可以越小；反之，间距越大，交叠面积可以越大。
如，在将多个第二像素03划分为多个像素组Z1，且沿主显示区A12至异形边缘的方向，第二像素03的发光亮度逐渐递减的实施例基础上，沿主显示区A12至异形边缘的方向，各个像素组Z1包括的第二像素03中，第一电容C1的上极板与下极板之间的交叠面积S可以逐渐递减，且与第二电容C2的上极板与下极板之间的交叠面积S呈倍数关系。每个像素组Z1包括的各个第二像素03中，第一电容C1的上极板与下极板之间的交叠面积S可以相同。
示例的，以上述图9实施例为例，当第二电容C2的容值c2固定时，沿主显示区A12至异形边缘的方向，依次排布的各个像素组Z1中，第二像素03包括的第一电容C1的上极板与下极板之间的交叠面积S可以分别为：第二电容C2的上极板与下极板之间的交叠面积S的0.547倍，0.333倍，0.215倍和0.143 倍。主显示区A12中，第一像素02包括的第一电容C1的上极板与下极板之间的交叠面积S可以为第二电容C2的上极板与下极板之间的交叠面积S的1倍。
因第一电极板C01与第二电极板C02的交叠面积S与第一电极板C01的面积和第二电极板C02的面积相关，本公开实施例给出以下几种设计方式：
一种可选的实现方式：参考图12，第一电容C1中第一电极板C01的面积为第二电容C2中第一电极板C01的面积的目标倍数，且第一电容C1中第二电极板C02的面积为第二电容C2中第二电极板C02的面积的目标倍数。即，可以根据第二像素03与异形边缘的距离，设置第一电极板C01的面积和第二电极板C02的面积均为第二电容C2中对应电极板面积的目标倍数，来设计第一电容C1的容值c1。在沿主显示区A12至异形边缘的方向，各个像素组Z1包括的第二像素03中，第一电容C1的上极板与下极板之间的交叠面积S逐渐递减的实施例基础上，该实现方式可以认为是：设置第一电极板C01的面积和第二电极板C02的面积均逐渐递减。
作为另一种可选的实现方式：参考图13和图14，第一电容C1包括的第一电极板C01和第二电极板C02中，一个电极板的面积可以与第二电容C2包括的第一电极板C01和第二电极板C02中一个电极板的面积相同，另一个电极板的面积可以为第二电容C2包括的第一电极板C01和第二电极板C02中另一个电极板的面积的目标倍数。即，可以根据第二像素03与异形边缘的距离，设置第一电极板C01的面积或第二电极板C02的面积为第二电容C2中对应电极板面积的目标倍数，来设计第一电容C1的容值c1。在沿主显示区A12至异形边缘的方向，各个像素组Z1包括的第二像素03中，第一电容C1的上极板与下极板之间的交叠面积S逐渐递减的实施例基础上，该实现方式可以认为是：设置第一电极板C01的面积或第二电极板C02的面积逐渐递减。
例如，图13中示出的实现方式为：沿主显示区A12至异形边缘的方向，第一电极板C01的面积固定不变，且第二电极板C02的面积逐渐递减。即，上述第一电容C1和第二电容C2中，一个电极板为第一电极板C01，另一个电极板为第二电极板C02。因第一电极板C01位于最靠近衬底基板01的一侧，故一般还用于进行遮光。如此，通过设置第一电极板C01固定不变，即不递减，可以在实现根据距离设置容值的基础上，还确保遮光效果较好。图14中示出的实现方式为：沿主显示区A12至异形边缘的方向，第一电极板C01的面积逐渐递减， 且第二电极板C02的面积固定不变。即，上述第一电容C1和第二电容C2中，一个电极板为第二电极板C02，另一个电极板为第一电极板C01。
可选的，图12至图14均是以图9所示方式为例，从左至右依次示出第一电容C1中第一电极板C01与第二电极板C02的交叠面积S分别为：C2、0.547C2、0.333C2，0.215C2和0.143C2，此处C2用于指示第二电容C2中第一电极板C01与第二电极板C02的交叠面积。
可选的，在本公开实施例中，第一像素02和第二像素03一般均可以包括：沿远离衬底基板01的方向依次层叠的栅金属层(gate，G)和源漏金属层(source，SD)。上述第一电容C1和第二电容C2中，第一电极板C01可以与栅金属层G位于同层，第二电极板C02可以与源漏金属层SD位于同层。
位于同层可以是指采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同层”的多个元件、部件、结构和/或部分由相同的材料构成，并通过同一次构图工艺形成。如此，可以节省制造工艺和制造成本，并且可以加快制造效率。即本公开实施例中，第一电极板C01与栅金属层G可以采用相同材料，通过一次构图工艺形成。以及，第二电极板C02与源漏金属层SD可以采用相同材料，通过一次构图工艺形成。
可选的，第一电极板C01的材料和第二电极板C02的材料均包括：铜(Cu)或铝(Al)。绝缘层J1的材料可以包括：氮化硅(SiNx)和/或氧化硅(SiOx)。
需要说明的是，上述实施例均是以第二电容C2的容值c2固定，调节第一电容C1的容值c1来达到调节驱动电流目的。在一些实施例中，也可以以第一电容C1的容值c1固定，调节第二电容C2的容值c2来达到调节驱动电流目的。或者，同时改变第一电容C1的容值c1和第二电容C2的容值c2来达到调节驱动电流目的。无论是采用何种方式，均可以结合图3和图9的调节原理进行设置，使得调节后的第二像素03朝靠近异形边缘的方向，亮度逐渐递减即可。
结合上述实施例可知，本公开实施例通过设计像素电路P1中第一电容C1的容值，来调节像素电路P1传输至发光元件L1的驱动电流，使得异形边缘区A11内第二像素03的发光亮度朝靠近异形边缘的方向逐步降低，对边缘进行模 糊状的显示处理，从而达到降低边缘出现彩虹纹的风险。
综上所述，本公开实施例提供了一种显示面板。该显示面板包括衬底基板，多个第一像素和多个第二像素。衬底基板具有异形显示区，且该异形显示区又被划分为沿远离异形边缘的方向依次排布的异形边缘区和主显示区。第一像素位于主显示区。第二像素位于异形边缘区。因在显示面板显示目标灰阶的画面时，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件驱动信号的电位不同，且小于第一像素中像素电路传输至发光元件的驱动信号的电位，故可以使得距异形边缘不同距离位置处各个第二像素的发光亮度发生渐变，且第二像素的最大发光亮度小于第一像素的发光亮度。进而，可以改善像素排布不均带来的彩虹纹问题，确保显示效果较好。
图15是本公开实施例提供的一种显示装置的结构示意图。如图15所示，该显示装置包括：供电组件J1，以及如上述附图所示的显示面板00。
其中，供电组件J1可以与显示面板00耦接，并用于为显示面板00供电。
可选的，本公开实施例记载的显示装置可以为：OLED显示装置、Micro-LED显示装置、mini LED显示装置、汽车内的仪表板、智慧手表、穿戴式元件、手机、平板电脑、柔性显示装置或电视机等任何具有显示功能的产品或部件。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
以及，本公开实施方式部分使用的术语仅用于对本公开的实施例进行解释，而非旨在限定本公开。除非另作定义，本公开的实施方式使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
如，在本公开实施例中，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有 明确的限定。
同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。
“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。
“上”、“下”、“左”或者“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种显示面板，所述显示面板包括：
    衬底基板，具有异形显示区，所述异形显示区被划分为异形边缘区和主显示区，且所述异形边缘区相对于所述主显示区靠近所述异形显示区的异形边缘；
    多个第一像素，位于所述衬底基板的一侧，且位于所述主显示区；
    多个第二像素，位于所述衬底基板的一侧，且位于所述异形边缘区；
    其中，所述多个第二像素的数量小于所述多个第一像素的数量，且所述第一像素和所述第二像素均包括：像素电路和发光元件，所述像素电路与所述发光元件耦接，并用于向所述发光元件传输驱动信号，以驱动所述发光元件发光；
    并且，在所述显示面板显示目标灰阶的画面时，所述多个第二像素中，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件的驱动信号的电位不同，且每个第二像素包括的像素电路传输至发光元件的驱动信号的电位小于任一第一像素包括的像素电路传输至发光元件的驱动信号的电位。
  2. 根据权利要求1所述的显示面板，其中，所述多个第二像素包括：多个像素组，所述多个像素组沿所述主显示区至所述异形边缘的方向依次排布，且各个像素组距所述异形边缘的距离不等；
    每个像素组中的各个第二像素在平行于所述异形边缘的延伸方向上呈阶梯状排布，且每个像素组中的各个第二像素距所述异形边缘的距离相等；
    其中，在所述显示面板显示目标灰阶的画面时，每个像素组中，各个第二像素包括的像素电路传输至发光元件的驱动信号的电位相等，且沿所述主显示区至所述异形边缘的方向，各个像素组中，第二像素包括的像素电路传输至发光元件的驱动信号的电位逐渐递减，以使第二像素的显示灰阶逐渐递减。
  3. 根据权利要求2所述的显示面板，其中，任意相邻两个像素组中，第二像素包括的像素电路传输至发光元件的驱动信号的电位均按照目标递减值递减，以使沿所述主显示区至所述异形边缘的方向，每相邻两个像素组中，一个像素组包括的第二像素的显示灰阶与另一个像素组包括的第二像素的显示灰阶的比值均为目标比值。
  4. 根据权利要求3所述的显示面板，其中，所述目标比值为1/2。
  5. 根据权利要求1至4任一所述的显示面板，其中，所述像素电路包括：数据写入电路、发光控制电路、电位调节电路和驱动电路；
    所述数据写入电路分别与数据信号端、第一扫描端和第一节点耦接，并用于响应于所述第一扫描端提供的第一扫描信号，控制所述数据信号端与所述第一节点的通断；
    所述发光控制电路分别与第二扫描端、发光控制端、第一电源端、第二电源端、所述第一节点、第二节点和第三节点耦接，并用于响应于所述第二扫描端提供的第二扫描信号，控制所述第二电源端与所述第一节点的通断，且控制所述第二节点与所述第三节点的通断，以及响应于所述发光控制端提供的发光控制信号，控制所述第一电源端与所述第三节点的通断；
    所述电位调节电路分别与所述第一节点、所述第二节点和第四节点耦接，并用于调节所述第一节点、所述第二节点和所述第四节点的电位；
    所述驱动电路分别与所述第二节点、所述第三节点和所述第四节点耦接，并用于基于所述第二节点的电位和所述第三节点的电位，向所述第四节点传输驱动信号；
    所述发光元件分别与所述第四节点和所述第二电源端耦接，并用于基于所述第四节点的电位和所述第二电源端提供的第二电源信号发光。
  6. 根据权利要求5所述的显示面板，其中，所述电位调节电路包括：第一电容和第二电容；
    所述第一电容的一端与所述第一节点耦接，所述第一电容的另一端与所述第二节点耦接；
    所述第二电容的一端与所述第二节点耦接，所述第二电容的另一端与所述第四节点耦接。
  7. 根据权利要求6所述的显示面板，其中，各个第二像素中，像素电路包括的第二电容的容值相等，第一电容的容值为第二电容的容值的目标倍数，且所 述目标倍数小于等于1；
    以及，对于每个第二像素而言，所述目标倍数与所述第二像素距所述异形边缘之间的距离相关，以使所述多个第二像素中，与异形边缘之间的距离不同的各个第二像素包括的像素电路传输至发光元件的驱动信号的电位不同。
  8. 根据权利要求7所述的显示面板，其中，所述第一电容和所述第二电容均包括：沿远离所述衬底基板的方向依次层叠的第一电极板、绝缘层和第二电极板，且所述第一电极板在所述衬底基板上的正投影与所述第二电极层在所述衬底基板上的正投影交叠；
    其中，每个第二像素中，所述第一电容和所述第二电容中，绝缘层的介电常数相同，所述第一电容和所述第二电容中，第一电极板与所述第二电极板之间的间距相等，且所述第一电容中第一电极板与第二电极板的交叠面积为所述第二电容中第一电极板与第二电极板的交叠面积的所述目标倍数。
  9. 根据权利要求8所述的显示面板，其中，所述第一电容中第一电极板的面积为所述第二电容中第一电极板的面积的所述目标倍数，且所述第一电容中第二电极板的面积为所述第二电容中第二电极板的面积的所述目标倍数。
  10. 根据权利要求8所述的显示面板，其中，所述第一电容包括的第一电极板和第二电极板中，一个电极板的面积与所述第二电容包括的第一电极板和第二电极板中一个电极板的面积相同，另一个电极板的面积为所述第二电容包括的第一电极板和第二电极板中另一个电极板的面积的所述目标倍数。
  11. 根据权利要求10所述的显示面板，其中，所述第一电容和所述第二电容中，所述一个电极板为所述第一电极板，所述另一个电极板为所述第二电极板。
  12. 根据权利要求6至11任一所述的显示面板，其中，所述发光控制电路还与第三扫描端和所述第四节点耦接，并用于响应于所述第三扫描端提供的第三扫描信号，控制所述第二电源端与所述第四节点的通断；所述发光控制电路包括：第一复位子电路、第二复位子电路、补偿子电路和发光控制子电路；
    所述第一复位子电路分别与所述第二扫描端、所述第二电源端和所述第一节点耦接，并用于响应于所述第二扫描信号，控制所述第二电源端与所述第一节点的通断；
    所述第二复位子电路分别与所述第三扫描端、所述第二电源端和所述第四节点耦接，并用于响应于所述第三扫描信号，控制所述第二电源端与所述第四节点的通断；
    所述补偿子电路分别与所述第二扫描端、所述第二节点和所述第三节点耦接，并用于响应于所述第二扫描信号，控制所述第二节点与所述第三节点的通断；
    所述发光控制子电路分别与所述发光控制端、所述第一电源端和所述第三节点耦接，并用于响应于所述发光控制信号，控制所述第一电源端与所述第三节点的通断。
  13. 根据权利要求12所述的显示面板，其中，所述数据写入电路包括：第一晶体管；所述第一复位子电路包括：第二晶体管；所述第二复位子电路包括：第三晶体管；所述补偿子电路包括：第四晶体管；所述发光控制子电路包括：第五晶体管；所述驱动电路包括：第六晶体管；
    所述第一晶体管的栅极与所述第一扫描端耦接，所述第一晶体管的第一极与所述数据信号端耦接，所述第一晶体管的第二极与所述第一节点耦接；
    所述第二晶体管的栅极与所述第二扫描端耦接，所述第二晶体管的第一极与所述第二电源端耦接，所述第二晶体管的第二极与所述第一节点耦接；
    所述第三晶体管的栅极与所述第三扫描端耦接，所述第三晶体管的第一极与所述第二电源端耦接，所述第三晶体管的第二极与所述第四节点耦接；
    所述第四晶体管的栅极与所述第二扫描端耦接，所述第四晶体管的第一极与所述第三节点耦接，所述第四晶体管的第二极与所述第二节点耦接；
    所述第五晶体管的栅极与所述发光控制端耦接，所述第五晶体管的第一极与所述第一电源端耦接，所述第五晶体管的第二极与所述第三节点耦接；
    所述第六晶体管的栅极与所述第二节点耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述第四节点耦接。
  14. 根据权利要求1至13任一所述的显示面板，其中，所述衬底基板还具有与所述异形显示区相邻的非显示区；所述显示面板还包括：
    黑矩阵层，所述黑矩阵层位于所述多个第一像素和所述第二像素远离所述衬底基板的一侧，且位于所述异形显示区和所述非显示区。
  15. 一种显示装置，所述显示装置包括：供电组件，以及如权利要求1至14任一所述的显示面板；
    其中，所述供电组件与所述显示面板耦接，并用于为所述显示面板供电。
PCT/CN2023/110033 2022-08-24 2023-07-28 显示面板及显示装置 WO2024041311A1 (zh)

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