WO2021073445A1

WO2021073445A1 - Display backplane and manufacturing method therefor, display panel, and display device

Info

Publication number: WO2021073445A1
Application number: PCT/CN2020/119969
Authority: WO
Inventors: 冯雪欢; 李永谦
Original assignee: 京东方科技集团股份有限公司; 合肥京东方卓印科技有限公司
Priority date: 2019-10-15
Filing date: 2020-10-09
Publication date: 2021-04-22
Also published as: CN110690231A

Abstract

A display backplane (10) and a manufacturing method therefor, a display panel, and a display device. The display backplane (10) comprises: a substrate (100); a patterned metal layer (200) arranged on part of a first surface (110) of the substrate (100), and comprising a light shielding layer (210) and a sub-metal layer (220) which are spaced apart; a buffer layer (300) arranged on the first surface (110) and covering the patterned metal layer (200); and a patterned semiconductor layer (400) arranged on part of the surface of the buffer layer (300) distant from the patterned metal layer (200), and comprising an active layer (410) and a sub-semiconductor layer (420) which are spaced part, wherein the patterned metal layer (200) and the patterned semiconductor layer (400) are the same in shape.

Description

Display backplane and manufacturing method thereof, display panel and display device

Technical field

This application relates to the field of display technology, in particular, to a display backplane and a manufacturing method thereof, a display panel, and a display device.

Background technique

At present, the manufacturing process of the display backplane is relatively complicated.

Therefore, the related technology of the existing display backplane still needs to be improved.

Summary of the invention

This application aims to solve one of the technical problems in the related technology at least to a certain extent. To this end, one purpose of the present application is to propose a display background that can use the same mask when forming a patterned metal layer and a patterned semiconductor layer, can significantly reduce production costs, or is suitable for large-scale industrialization. board.

In one aspect of the present application, the present application provides a display backplane. According to an embodiment of the present application, the display backplane includes: a substrate; a patterned metal layer disposed on a part of the first surface of the substrate, and the patterned metal layer includes a spaced-apart The light-shielding layer and the sub-metal layer; a buffer layer, the buffer layer is provided on the first surface, and covers the patterned metal layer; a patterned semiconductor layer, the patterned semiconductor layer is provided on the The buffer layer is on a part of the surface away from the patterned metal layer, and the patterned semiconductor layer includes an active layer and a sub-semiconductor layer arranged at intervals, wherein the patterned metal layer and the patterned semiconductor layer The shape is the same. Since the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used when forming the patterned metal layer and the patterned semiconductor layer of the display backplane, compared with related technologies The manufacturing process of the display backplane in China reduces a mask, which can significantly reduce the production cost and is suitable for large-scale industrialization.

According to an embodiment of the present application, the orthographic projection of the patterned metal layer on the substrate overlaps the orthographic projection of the patterned semiconductor layer on the substrate.

According to the embodiment of the present application, the orthographic projections of the active layer and the light shielding layer on the substrate overlap, and the orthographic projections of the sub-semiconductor layer and the sub-metal layer overlap on the substrate.

According to an embodiment of the present application, the buffer layer includes a first via hole and a second via hole, the light shielding layer and the active layer are connected through the first via hole, and the sub-metal layer and the The sub-semiconductor layers are connected through the second via hole.

According to the embodiment of the present application, it further includes a gate insulating layer and a gate, the gate insulating layer is disposed on a part of the surface of the active layer away from the substrate, and the gate is disposed on the gate insulating layer away from the substrate. On the surface of the active layer, orthographic projections of the gate insulating layer and the gate on the substrate overlap.

According to an embodiment of the present application, the display backplane further includes an interlayer insulating layer disposed on the buffer layer, the patterned semiconductor layer and the surface of the gate away from the substrate, so The interlayer insulating layer has a third via, the orthographic projection of the third via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap, and the sub-semiconductor layer and The source electrode or the drain electrode is connected through the third via hole.

According to an embodiment of the present application, the display backplane includes: the substrate; the patterned metal layer, the patterned metal layer is disposed on a part of the first surface of the substrate, and the patterned metal The layer includes a light-shielding layer and a sub-metal layer arranged at intervals; the buffer layer, the buffer layer is arranged on the first surface, and covers the patterned metal layer; the patterned semiconductor layer, the pattern A semiconductor layer is provided on a part of the surface of the buffer layer away from the patterned metal layer, and the patterned semiconductor layer includes an active layer and a sub-semiconductor layer arranged at intervals; the gate insulating layer and the gate The gate insulating layer is arranged on a part of the surface of the active layer away from the substrate, the gate electrode is arranged on the surface of the gate insulating layer away from the active layer, the gate insulating layer and The orthographic projection of the gate electrode on the substrate overlaps; the interlayer insulating layer, the interlayer insulating layer is disposed on the buffer layer, the patterned semiconductor layer, and the gate electrode away from the substrate On the surface, the interlayer insulating layer has a third via, and the orthographic projection of the third via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap, so The sub-semiconductor layer and the source electrode or the drain electrode are connected through the third via hole, wherein the buffer layer includes a first via hole and a second via hole, and the light shielding layer and the active layer pass through the The first via is connected, the sub-metal layer and the sub-semiconductor layer are connected through the second via, the orthographic projection of the patterned metal layer on the substrate and the patterned semiconductor The orthographic projections of the layers on the substrate overlap.

In another aspect of the present application, the present application provides a method for manufacturing the aforementioned display backplane. According to an embodiment of the present application, the method includes: forming a patterned metal layer on a part of the first surface of the substrate; forming a buffer layer covering the patterned metal layer on the first surface; A patterned semiconductor layer is formed on a part of the surface of the layer away from the patterned metal layer, wherein the patterned metal layer and the patterned semiconductor layer are formed by the same mask. The method is simple, convenient, and easy to implement, and when forming the patterned metal layer and the patterned semiconductor layer of the display backplane, the same mask can be used, which is compared with that of the display backplane in the related art. The production process reduces a mask, which can significantly reduce production costs, and is suitable for large-scale industrialization.

According to an embodiment of the present application, before forming the patterned semiconductor layer, the method further includes: forming a first via hole and a second via hole in the buffer layer.

According to an embodiment of the present application, the method further includes: forming a prefabricated gate insulating layer on the surface of the active layer away from the substrate; and forming a prefabricated gate on the surface of the prefabricated gate insulating layer away from the active layer An electrode layer; the prefabricated gate insulating layer and the prefabricated gate layer are etched through a patterning process to form the gate insulating layer and the gate of the display backplane.

According to an embodiment of the present application, after forming the gate insulating layer and the gate, the method further includes: applying the buffer layer, the patterned semiconductor layer, and the surface of the gate away from the substrate An insulating layer is formed on the insulating layer; a third via is formed in the insulating layer to form an interlayer insulating layer; and a source electrode is formed on a part of the surface of the interlayer insulating layer and the patterned semiconductor layer away from the substrate And a drain; forming a planarization layer on the surface of the source, the drain, and the interlayer insulating layer away from the substrate; forming a resin layer on the surface of the planarization layer away from the substrate; A fourth via is formed in the planarization layer and the resin layer; an electrode layer is formed on the surface of the resin layer away from the substrate.

In another aspect of the present application, the present application provides a display panel. According to an embodiment of the present application, the display panel includes the aforementioned display backplane. The display panel has a low production cost, is suitable for large-scale industrialization, and has all the features and advantages of the display backplane described above, and will not be repeated here.

In another aspect of the present application, the present application provides a display device. According to an embodiment of the present application, the display device includes the aforementioned display panel. The display device has a low production cost, is suitable for large-scale industrialization, and has all the features and advantages of the aforementioned display panel, which will not be repeated here.

Description of the drawings

FIG. 1 shows a schematic diagram of a cross-sectional structure of a display backplane according to an embodiment of the present application.

FIG. 2 shows a schematic cross-sectional structure diagram of a display backplane according to another embodiment of the present application.

FIG. 3 shows a schematic cross-sectional structure diagram of a display backplane according to another embodiment of the present application.

FIG. 4 shows a schematic cross-sectional structure diagram of a display backplane according to another embodiment of the present application.

Fig. 5 shows a process flow diagram of a method for manufacturing a display backplane according to an embodiment of the present application.

6a, 6b, and 6c show a process flow diagram of a method for manufacturing a display backplane according to another embodiment of the present application.

Fig. 7 shows a process flow diagram of a method for manufacturing a display backplane according to another embodiment of the present application.

Fig. 8a, Fig. 8b, Fig. 8c, and Fig. 8d show a process flow diagram of a method for manufacturing a display backplane according to another embodiment of the present application.

Fig. 9a, Fig. 9b, Fig. 9c, Fig. 9d, Fig. 9e, Fig. 9f, Fig. 9g, Fig. 9h show a process flow diagram of a method for manufacturing a display backplane according to still another embodiment of the present application.

Reference signs:

10: Display backplane 100: Substrate 110: First surface 200: Patterned metal layer 210: Light-shielding layer 220: Sub-metal layer 300: Buffer layer 400: Patterned semiconductor layer 410: Active layer 420: Sub-semiconductor layer 510: Gate insulating layer 520: Gate 600: Interlayer insulating layer 700: Source 800: Drain 810: Planarization layer 820: Resin layer 900: Electrode layer H ₁ : First via H ₂ : Second via H ₃ : The third via H ₄ : The fourth via

Detailed ways

The embodiments of the present application are described in detail below. The embodiments described below are exemplary, and are only used to explain the present application, and cannot be understood as a limitation to the present application. Where specific techniques or conditions are not indicated in the examples, it shall be carried out in accordance with the techniques or conditions described in the literature in the field or in accordance with the product specification.

In the related art, the manufacturing process of the display backplane usually requires eight photolithography steps. Correspondingly, eight masks are also required, namely: the light-shielding layer, the active layer, the gate, and the buffer in the display backplane are formed. For the via holes in the layer, the interlayer insulating layer, the source and drain electrodes, the via holes in the resin layer, and the electrode layer, each requires a mask for photolithography processing, but the mask is expensive As a result, the manufacturing process cost of the display backplane is relatively high, and it is difficult for large-scale industrialization.

Based on the above research, in one aspect of the present application, the present application provides a display backplane. According to an embodiment of the present application, referring to FIG. 1, the display backplane 10 includes: a substrate 100; a patterned metal layer disposed on a part of the first surface 110 of the substrate 100; The patterned metal layer includes a light-shielding layer 210 and a sub-metal layer 220 arranged at intervals; a buffer layer 300, which is arranged on the first surface 110 and covers the patterned metal layer; and a patterned semiconductor The patterned semiconductor layer is disposed on a part of the surface of the buffer layer 300 away from the patterned metal layer, and the patterned semiconductor layer includes an active layer 410 and a sub-semiconductor layer 420 that are arranged at intervals, wherein The shape of the patterned metal layer and the patterned semiconductor layer are the same (for a schematic plan view of the patterned metal layer 200 and the patterned semiconductor layer 400, refer to FIGS. 9a and 9c). Since the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10, compared to the related The manufacturing process of the display backplane in the technology reduces a mask, which can significantly reduce the production cost and is suitable for large-scale industrialization.

According to an embodiment of the present application, referring to FIG. 1, further, the orthographic projection of the patterned metal layer on the substrate 100 and the orthographic projection of the patterned semiconductor layer on the substrate 100 overlap. Therefore, when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10, the same mask can be used. Compared with the manufacturing process of the display backplane in the related art, one mask is reduced. The film version further significantly reduces the production cost and is suitable for large-scale industrialization.

According to an embodiment of the present application, referring to FIG. 1, furthermore, the orthographic projections of the active layer 410 and the light shielding layer 210 on the substrate 100 overlap, and the sub-semiconductor layer 420 and the sub-metal layer The orthographic projections of 220 on the substrate 100 overlap. Therefore, when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10, the same mask can be used. Compared with the manufacturing process of the display backplane in the related art, one mask is reduced. The film version further significantly reduces the production cost and is suitable for large-scale industrialization.

According to the embodiment of the present application, as long as the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used for formation, thereby significantly reducing production costs and being suitable for large-scale industrialization. That is to say, in other embodiments of the present application, those skilled in the art can understand that the orthographic projection of the patterned metal layer on the substrate 100 and the patterned semiconductor layer on the substrate 100 The above orthographic projection can also be non-overlapping (not shown in the figure), which can also achieve the technical effect of significantly reducing production costs and being suitable for large-scale industrialization, which will not be repeated here.

According to an embodiment of the present disclosure, in addition to the previously described structure, with reference to FIG. 2, the buffer layer 300 may further include a first through hole and the second through hole H ₁ H _2, the light shielding layer 210 and the a first active layer 410 through the via hole H ₁ is connected to the sub-metal layer 220 and the second sub semiconductor layer 420 through the hole H ₂ is connected through. Thereby, since the sub-metal layer 220 of the semiconductor layer ₂ and the sub 420 via a second via hole H, 220 may be connected such that the source or drain of the thin film transistor in the display sub-backplane metal layer, so that it will not Floating (floating) metal state is formed, which in turn makes the state of the thin film transistor in the display backplane more stable.

According to an embodiment of the present application, referring to FIG. 3, the display backplane 10 further includes a gate insulating layer 510 and a gate 520, the gate insulating layer 510 is disposed on a part of the surface of the active layer 410 away from the substrate 100 Above, the gate 520 is disposed on the surface of the gate insulating layer 510 away from the active layer 410, and the orthographic projections of the gate insulating layer 510 and the gate 520 on the substrate 100 overlap.

According to an embodiment of the present application, referring to FIG. 3, the display backplane 10 further includes an interlayer insulating layer 600 disposed on the buffer layer 300, the semiconductor layer 410, and the gate 520 away from all the layers. said upper surface of the substrate 100, the interlayer insulating layer 600 having a third through hole H _3, a third via hole H to the orthogonal projection ₃ on the substrate 100 through a second hole H ₂ in the said orthogonal projection on the substrate 100 at least partially overlap, the semiconductor sub-layer 420 and the source 700 or the drain electrode 800 through the third via hole H ₃ is connected (Incidentally, in the case shown in FIG. The sub-semiconductor layer 420 is connected to the drain 800. Those skilled in the art can understand that in other embodiments of the present application, the sub-semiconductor layer 420 is connected to the source 700, which will not be repeated here). Thereby, since the sub 420 and the drain semiconductor layer 800 through the third via hole H ₃ is connected to further sub-metal layer 220 is not formed of metal Floating state (floating), and further such that the thin-film transistor display backplane The state is more stable; in addition, since the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10 Compared with the manufacturing process of the display backplane in the related technology, the mask plate is reduced by one mask, which can further significantly reduce the production cost and is suitable for large-scale industrialization.

In a specific embodiment of the present application, referring to FIG. 4, the display backplane 10 includes: a substrate 100; a patterned metal layer disposed on a part of the first surface of the substrate 100, The patterned metal layer includes a light shielding layer 210 and a sub-metal layer 220 arranged at intervals; a buffer layer 300, which is arranged on the first surface 110 and covers the patterned metal layer, the buffer layer 300 comprises a first via hole and the second through hole H ₁ H _2, the light shielding layer 210 and the active layer 410 through the first through hole H ₁ is connected to the metal layer 220 and the sub- said sub 420 through the second semiconductor layer connected to the via hole H _2; patterned semiconductor layer, the patterned semiconductor layer disposed on a surface of the buffer layer 300 remote from the metal layer, the patterned portion, The patterned semiconductor layer includes an active layer 410 and a sub-semiconductor layer 420 arranged at intervals; a gate insulating layer 510, which is arranged on a surface of the active layer 410 away from the substrate 100; and a gate electrode 520, the gate 520 is disposed on the surface of the gate insulating layer 510 away from the substrate 100; an interlayer insulating layer 600, the interlayer insulating layer 600 is disposed on the buffer layer 300, and the patterned The semiconductor layer and the gate 520 are far away from the surface of the substrate 100. The interlayer insulating layer 600 has a third via hole H ₃ and a source 700 and a drain 800. The third via H _{3 is} located on the surface of the substrate 100. The orthographic projection on the substrate 100 and the orthographic projection of the second via H ₂ on the substrate 100 at least partially overlap, and the sub-semiconductor layer 420 and the drain 800 are connected through the third via H ₃ , Wherein the patterned metal layer and the patterned semiconductor layer have the same shape. Therefore, the manufacturing cost of the display backplane is low, and it is suitable for large-scale industrialization.

According to the embodiments of the present application, those skilled in the art can understand that, in addition to the aforementioned structure, the display backplane 10 also includes a planarization layer 810, a resin layer 820, and an electrode layer 900. The specific positions of the planarization layer, the resin layer, and the electrode layer in the backplane are the same, and will not be repeated here.

In another aspect of the present application, the present application provides a method for manufacturing the aforementioned display backplane. According to the embodiment of the present application, referring to FIG. 5 and FIG. 6a, FIG. 6b, and FIG. 6c, the method includes the following steps:

S100: A patterned metal layer is formed on a part of the first surface 110 of the substrate 100. The patterned metal layer includes a light-shielding layer 210 and a sub-metal layer 220 (refer to FIG. 6a for the structural schematic diagram).

According to an embodiment of the present application, the patterned metal layer may be specifically formed by a patterning process, and the patterning process may include forming a pre-patterned metal layer on a part of the first surface 110 of the substrate 100, and applying light. After the resist is covered with a mask on the surface of the pre-patterned metal layer, the steps of exposure, development, etching, and photoresist stripping are performed to form a patterned metal layer. The specific process parameters of each step in the patterning process are all process parameters of the conventional patterning process, and will not be repeated here. Therefore, the manufacturing process is simple, convenient, easy to realize, and easy to industrialized production.

S200: forming a buffer layer 300 covering the patterned metal layer on the first surface 110 (refer to FIG. 6b for the structural schematic diagram).

According to an embodiment of the present application, the process of forming the buffer layer 300 covering the patterned metal layer on the first surface 110 may include vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, and the like. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, and inkjet printing are all process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, and inkjet printing, which are not too many here. Go into details. Therefore, the manufacturing process is simple, convenient, easy to realize, and easy to industrialized production.

S300: forming a patterned semiconductor layer on a part of the surface of the buffer layer 300 away from the patterned metal layer. The patterned semiconductor layer includes an active layer 410 and a sub-semiconductor layer 420, wherein the patterned semiconductor layer The metal layer and the patterned semiconductor layer are formed through the same mask (see FIG. 6c for the structure diagram).

According to the embodiment of the present application, the patterned semiconductor layer may be specifically formed by a patterning process, and the patterning process may include forming a pre-patterned pattern on a part of the surface of the buffer layer 300 away from the patterned metal layer After forming the semiconductor layer, coating photoresist, and covering the mask on the surface of the pre-patterned semiconductor layer, exposure, development, etching, photoresist stripping and other steps are performed to form a patterned semiconductor layer. The specific process parameters of each step in the patterning process are all process parameters of the conventional patterning process, and will not be repeated here. Therefore, the manufacturing process is simple, convenient, easy to realize, and easy to industrialized production.

According to the embodiment of the present application, as described above, since the patterned metal layer and the patterned semiconductor layer have the same shape, when the patterned metal layer and the patterned semiconductor layer described above are formed, it is possible to Using the same mask for exposure, compared with the manufacturing process of the display backplane in the related technology, one less mask is used, which can significantly reduce the production cost and is suitable for large-scale industrialization.

In some other embodiments of the present application, referring to FIGS. 7 and 8a, 8b, 8c, and 8d, before forming the patterned semiconductor layer, the method further includes the following steps:

S400: forming a first via hole H ₁ and a second via hole H ₂ in the buffer layer 300 (refer to FIG. 8c for the structural schematic diagram).

According to an embodiment of the present disclosure, the first via and the second H step ₁ H ₂ via the through hole ₂ forming a first via hole H ₁ and H in the second buffer layer 300 may be formed through a conventional The steps of the hole will not be repeated here.

According to an embodiment of the present application, referring to FIGS. 8a, 8b, and 8d, _{the steps before and after forming the first via H 1} and the second via H ₂ in the buffer layer 300 are the same as those described above. , I won’t repeat them here.

According to an embodiment of the present application, in the display backplane described in the present application, the gate and the gate insulating layer in the display backplane may be formed by a single patterning process. Specifically, a prefabricated insulating layer may be formed on the surface of the patterned semiconductor layer away from the substrate; then a prefabricated gate layer may be formed on the surface of the prefabricated insulating layer away from the substrate; finally, a patterning The process performs etching treatment on the prefabricated insulating layer and the prefabricated gate layer, the prefabricated insulating layer after the etching treatment constitutes the gate insulating layer 510 in the display backplane, and all the prefabricated insulating layers after the etching treatment The prefabricated gate layer constitutes the gate 520 in the display backplane (refer to FIG. 3 and FIG. 4 for the structure diagram). Therefore, compared with the manufacturing method in the related art, one patterning process is reduced, so the operation is simple, convenient, easy to realize, and easy to industrialized production.

According to the embodiment of the present application, after the gate insulating layer 510 and the gate 520 are formed, the method may further include: separating the buffer layer 300, the patterned semiconductor layer, and the gate 510 away from each other. An insulating layer is formed on the surface of the substrate 100; a third via hole H ₃ is formed in the insulating layer to form an interlayer insulating layer 600; the interlayer insulating layer 600 and the patterned semiconductor layer are far away A source 700 and a drain 800 are formed on part of the surface of the substrate 100; a planarization layer 810 is formed on the surface of the source 700, the drain 800, and the interlayer insulating layer 600 away from the substrate 100 A resin layer 820 is formed on the surface of the planarization layer 810 away from the substrate 100; a fourth via H ₄ is formed in the planarization layer 810 and the resin layer 820; the resin layer 820 is away An electrode layer 900 is formed on the surface of the substrate 100 (refer to FIG. 4 for a structural diagram). The specific methods, process conditions and parameters of the above steps are the specific methods, process conditions and parameters of the steps in the conventional display backplane forming method. , I won’t repeat them here.

In a specific embodiment of the present application, referring to Figure 9a, Figure 9b, Figure 9c, Figure 9d, Figure 9e, Figure 9f, Figure 9g and Figure 9h, the method may specifically include: forming on part of the first surface of the substrate Patterned metal layer 200 (refer to FIG. 9a for a schematic diagram of the planar structure, but it should be noted that in FIG. 9a and subsequent drawings, the substrate is not shown); The buffer layer of the metal layer 200 (for the convenience of showing the covered structure, the buffer layer is not shown in the figure); the first via hole H ₁ and the second via hole are formed in the buffer layer (refer to the schematic diagram of the planar structure) FIG. 9b, and it should be noted that, in FIG. 9b, only the first via hole H ₁ is shown, and the second via hole is not shown); a patterned semiconductor layer 400 is formed, and the patterned semiconductor layer 400 and The shape of the patterned metal layer described above is the same (refer to FIG. 9c for a schematic diagram of the plan structure). Therefore, since the shape of the patterned metal layer and the patterned semiconductor layer are the same, the patterning of the display backplane is formed When the metal layer and the patterned semiconductor layer, the same mask can be used. Compared with the manufacturing process of the display backplane in the related art, one mask is reduced, which can significantly reduce the production cost and is suitable for large-scale production. Large-scale industrialization; forming a gate insulating layer (not shown in the figure); forming a gate 520 (refer to FIG. 9d for a schematic diagram of the planar structure); in the buffer layer, the patterned semiconductor layer and the gate 520 away from all An insulating layer is formed on the surface of the substrate (for convenience to show the covered structure, the insulating layer is not shown in the figure); a third via H ₃ is formed in the insulating layer to form an interlayer insulating layer (Refer to FIG. 9e for the schematic diagram of the planar structure. It should be noted that the connection between the sub-semiconductor layer and the source or drain through the third via is not shown in the schematic diagram of the planar structure, and the structure can be seen in FIG. 4); A source 700 and a drain 800 are formed on the surface of the interlayer insulating layer and the patterned semiconductor layer away from the substrate (refer to FIG. 9f for a schematic plan view); on the source 700, the drain A planarization layer is formed on the surface of the electrode 800 and the interlayer insulating layer away from the substrate; a resin layer is formed on the surface of the planarization layer away from the substrate; in the planarization layer and the resin layer A fourth via hole H _{4 is} formed (refer to FIG. 9g for a schematic plan view of the structure. It should be noted that the connection between the sub-semiconductor layer and the source or drain through the fourth via hole is not shown in the schematic plan view. The structure can be seen in FIG. 4); an electrode layer 900 is formed on the surface of the resin layer away from the substrate (see FIG. 9h for a schematic diagram of the planar structure).

According to the embodiments of the present application, the display panel includes other necessary structures and components in addition to the display backplane described above, for example, a color filter substrate and a housing, etc., and those skilled in the art can refer to the specific display panel. Types and usage requirements are supplemented and designed, so I won’t repeat them here.

According to the embodiment of the present application, the display device includes other necessary structures and components in addition to the aforementioned display panel. Those skilled in the art can supplement and design according to the specific types and use requirements of the display device. To repeat it too much.

According to the embodiment of the present application, the specific type of the display device is not particularly limited, and includes, but is not limited to, mobile phones, tablet computers, wearable devices, game consoles, etc., for example.

In the description of this application, it should be understood that the terms “first” and “second” are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present application, "a plurality of" means two or more than two, unless otherwise specifically defined.

In this application, unless expressly stipulated and limited otherwise, the terms "connected", "connected" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or a whole; it can be a mechanical The connection may also be an electrical connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be a connection between two elements or an interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above-mentioned terms in this application can be understood according to specific circumstances.

In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean specific features described in conjunction with the embodiment or example , The structure, materials, or characteristics are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples and the features of the different embodiments or examples described in this specification without contradicting each other.

Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present application. A person of ordinary skill in the art can comment on the foregoing within the scope of the present application. The embodiment undergoes changes, modifications, substitutions, and modifications.

Claims

A display backplane is characterized in that it comprises:

Substrate

A patterned metal layer, the patterned metal layer is arranged on a part of the first surface of the substrate, and the patterned metal layer includes a light shielding layer and a sub-metal layer that are arranged at intervals;

A buffer layer, the buffer layer is disposed on the first surface and covers the patterned metal layer;

A patterned semiconductor layer, the patterned semiconductor layer is arranged on a part of the surface of the buffer layer away from the patterned metal layer, the patterned semiconductor layer includes an active layer and a sub-semiconductor layer arranged at intervals,

Wherein, the patterned metal layer and the patterned semiconductor layer have the same shape.
The display backplane of claim 1, wherein the orthographic projection of the patterned metal layer on the substrate overlaps the orthographic projection of the patterned semiconductor layer on the substrate.
The display backplane according to claim 1 or 2, wherein the orthographic projections of the active layer and the light-shielding layer on the substrate overlap, and the sub-semiconductor layer and the sub-metal layer are on the substrate. The orthographic projections on the substrate overlap.
The display backplane according to any one of claims 1 to 3, wherein the buffer layer comprises a first via hole and a second via hole,

The light shielding layer and the active layer are connected through the first via hole, and the sub-metal layer and the sub-semiconductor layer are connected through the second via hole.
The display backplane according to any one of claims 1 to 4, further comprising a gate insulating layer and a gate, the gate insulating layer is disposed on a part of the surface of the active layer away from the substrate The gate is arranged on a surface of the gate insulating layer away from the active layer, and the orthographic projections of the gate insulating layer and the gate on the substrate overlap.
The display backplane according to any one of claims 1 to 5, further comprising an interlayer insulating layer, the interlayer insulating layer is disposed on the buffer layer, the patterned semiconductor layer and the On the surface of the gate far away from the substrate, the interlayer insulating layer has a third via, and the orthographic projection of the third via on the substrate is similar to that of the second via on the substrate. The orthographic projections overlap at least partially, and the sub-semiconductor layer and the source electrode or the drain electrode are connected through the third via hole.
The display backplane according to claim 6, characterized in that it comprises:

The substrate;

The patterned metal layer, the patterned metal layer is arranged on a part of the first surface of the substrate, and the patterned metal layer includes a light shielding layer and a sub-metal layer that are arranged at intervals;

The buffer layer, the buffer layer is disposed on the first surface and covers the patterned metal layer;

The patterned semiconductor layer, the patterned semiconductor layer is arranged on a part of the surface of the buffer layer away from the patterned metal layer, and the patterned semiconductor layer includes an active layer and sub-semiconductors arranged at intervals Floor;

The gate insulating layer and the gate, the gate insulating layer is arranged on a part of the surface of the active layer away from the substrate, and the gate is arranged on the gate insulating layer away from the active layer On the surface, the orthographic projection of the gate insulating layer and the gate on the substrate overlap;

The interlayer insulating layer, the interlayer insulating layer is disposed on the buffer layer, the patterned semiconductor layer, and the surface of the gate away from the substrate, and the interlayer insulating layer has a third pass Hole, the orthographic projection of the third via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap, the sub-semiconductor layer and the source or drain pass through the first Three vias are connected,

Wherein, the buffer layer includes a first via hole and a second via hole, the light shielding layer and the active layer are connected through the first via hole, and the sub-metal layer and the sub-semiconductor layer pass through the The second via is connected, and the orthographic projection of the patterned metal layer on the substrate overlaps the orthographic projection of the patterned semiconductor layer on the substrate.
A method for manufacturing a display backplane, which is characterized in that it comprises:

Forming a patterned metal layer on a part of the first surface of the substrate, the patterned metal layer including a light-shielding layer and a sub-metal layer;

Forming a buffer layer covering the patterned metal layer on the first surface;

Forming a patterned semiconductor layer on a part of the surface of the buffer layer away from the patterned metal layer, and the patterned semiconductor layer includes an active layer and a sub-semiconductor layer,

Wherein, the patterned metal layer and the patterned semiconductor layer are formed by the same mask.
8. The method according to claim 8, characterized in that, before forming the patterned semiconductor layer, further comprising:

A first via hole and a second via hole are formed in the buffer layer.
The method according to claim 8 or 9, characterized in that it comprises:

Forming a prefabricated gate insulating layer on the surface of the active layer away from the substrate;

Forming a prefabricated gate layer on the surface of the prefabricated gate insulating layer away from the active layer;

The prefabricated gate insulating layer and the prefabricated gate layer are etched through one patterning process to form the gate insulating layer and the gate of the display backplane.
11. The method of claim 10, further comprising: after forming the gate insulating layer and the gate electrode:

Forming an insulating layer on the buffer layer, the patterned semiconductor layer and the surface of the gate away from the substrate;

Forming a third via hole in the insulating layer to form an interlayer insulating layer;

Forming a source electrode and a drain electrode on a part of the surface of the interlayer insulating layer and the patterned semiconductor layer away from the substrate;

Forming a planarization layer on the surface of the source electrode, the drain electrode, and the interlayer insulating layer away from the substrate;

Forming a resin layer on the surface of the planarization layer away from the substrate;

Forming a fourth via hole in the planarization layer and the resin layer;

An electrode layer is formed on the surface of the resin layer away from the substrate.
A display panel, characterized by comprising the display backplane according to any one of claims 1-7.
A display device, characterized by comprising the display panel described in claim 12.