CN110690231A - Display back plate and manufacturing method thereof, display panel and display device - Google Patents
Display back plate and manufacturing method thereof, display panel and display device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 239000010410 layer Substances 0.000 claims description 408
- 238000000034 method Methods 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 16
- 229920005989 resin Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 6
- 238000009776 industrial production Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007641 inkjet printing Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
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- 239000010409 thin film Substances 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The invention provides a display back plate, a manufacturing method thereof, a display panel and a display device. The display backplane includes: a substrate; the patterned metal layer is arranged on part of the first surface of the substrate and comprises a light shielding layer and a sub-metal layer which are arranged at intervals; the buffer layer is arranged on the first surface and covers the patterned metal layer; the patterned semiconductor layer is arranged on a part of the surface of the buffer layer far away from the patterned metal layer and comprises an active layer and a sub-semiconductor layer which are arranged at intervals, wherein the patterned metal layer and the patterned semiconductor layer are the same in shape. In the display back plate, the patterned metal layer and the patterned semiconductor layer are in the same shape, so that the same mask can be used when the patterned metal layer and the patterned semiconductor layer of the display back plate are formed, and compared with the manufacturing process of the display back plate in the related art, one mask is reduced, so that the production cost can be obviously reduced, and the display back plate is suitable for large-scale industrialization.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display back plate, a manufacturing method of the display back plate, a display panel and a display device.
Background
At present, the manufacturing process of the display back plate is relatively complex.
Thus, the related art of the existing display backplane still needs to be improved.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a display backplane that can use the same mask when forming a patterned metal layer and a patterned semiconductor layer, can significantly reduce production costs, or is suitable for mass industrialization.
In one aspect of the invention, a display backplane is provided. According to an embodiment of the present invention, the display backplane comprises: a substrate; the patterned metal layer is arranged on part of the first surface of the substrate and comprises a light shielding layer and a sub-metal layer which are arranged at intervals; a buffer layer disposed on the first surface and covering the patterned metal layer; the patterned semiconductor layer is arranged on a part of the surface of the buffer layer far away from the patterned metal layer and comprises an active layer and a sub-semiconductor layer which are arranged at intervals, wherein the patterned metal layer and the patterned semiconductor layer are the same in shape. Because the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used when the patterned metal layer and the patterned semiconductor layer of the display back plate are formed, and compared with the manufacturing process of the display back plate in the related art, one mask is reduced, so that the production cost can be obviously reduced, and the display back plate is suitable for large-scale industrialization.
According to an embodiment of the invention, an orthographic projection of the patterned metal layer on the substrate and an orthographic projection of the patterned semiconductor layer on the substrate overlap.
According to an embodiment of the present invention, orthographic projections of the active layer and the light shielding layer on the substrate overlap, and orthographic projections of the sub-semiconductor layer and the sub-metal layer on the substrate overlap.
According to the embodiment of the invention, the buffer layer comprises a first via hole and a second via hole, the light shielding layer and the active layer are connected through the first via hole, and the sub-metal layer and the sub-semiconductor layer are connected through the second via hole.
According to the embodiment of the invention, the liquid crystal display device further comprises a gate insulating layer and a gate electrode, wherein the gate insulating layer is arranged on the part of the surface of the active layer far away from the substrate, the gate electrode is arranged on the surface of the gate insulating layer far away from the active layer, and orthographic projections of the gate insulating layer and the gate electrode on the substrate are overlapped.
According to an embodiment of the present invention, the display backplane further includes an interlayer insulating layer disposed on the buffer layer, the patterned semiconductor layer, and the gate electrode on a surface away from the substrate, the interlayer insulating layer having a third via, an orthographic projection of the third via on the substrate at least partially overlapping an orthographic projection of the second via on the substrate, the sub-semiconductor layer and the source or drain electrode being connected through the third via.
According to an embodiment of the present invention, the display backplane comprises: the substrate; the patterned metal layer is arranged on part of the first surface of the substrate and comprises a light shielding layer and a sub-metal layer which are arranged at intervals; the buffer layer is arranged on the first surface and covers the patterned metal layer; the patterned semiconductor layer is arranged on a part of the surface of the buffer layer far away from the patterned metal layer and comprises an active layer and a sub-semiconductor layer which are arranged at intervals; the gate insulating layer is arranged on a part of the surface of the active layer far away from the substrate, the gate electrode is arranged on the surface of the gate insulating layer far away from the active layer, and orthographic projections of the gate insulating layer and the gate electrode on the substrate are overlapped; the interlayer insulating layer is arranged on the surface, far away from the substrate, of the buffer layer, the patterned semiconductor layer and the grid electrode, and provided with a third through hole, the orthographic projection of the third through hole on the substrate is at least partially overlapped with the orthographic projection of the second through hole on the substrate, the sub-semiconductor layer is connected with the source electrode or the drain electrode through the third through hole, the buffer layer comprises a first through hole and a second through hole, the shading layer is connected with the active layer through the first through hole, the sub-metal layer is connected with the sub-semiconductor layer through the second through hole, and the orthographic projection of the patterned metal layer on the substrate is overlapped with the orthographic projection of the patterned semiconductor layer on the substrate.
In another aspect of the invention, a method of making the display backplane described above is provided. According to an embodiment of the invention, the method comprises: forming a patterned metal layer on a portion of the first surface of the substrate; forming a buffer layer on the first surface covering the patterned metal layer; and forming a patterned semiconductor layer on the partial surface of the buffer layer far away from the patterned metal layer, wherein the patterned metal layer and the patterned semiconductor layer are formed through the same mask. The method is simple and convenient to operate and easy to realize, the same mask can be used when the patterned metal layer and the patterned semiconductor layer of the display back plate are formed, and compared with the manufacturing process of the display back plate in the related technology, one mask is reduced, so that the production cost can be obviously reduced, and the method is suitable for large-scale industrialization.
According to an embodiment of the invention, before forming the patterned semiconductor layer, the method further comprises: forming a first via and a second via in the buffer layer.
According to an embodiment of the invention, the method further comprises: forming a prefabricated gate insulating layer on the surface of the active layer far away from the substrate; forming a prefabricated gate electrode layer on the surface of the prefabricated gate insulating layer far away from the active layer; and etching the prefabricated gate insulating layer and the prefabricated gate layer by a one-step composition process to form the gate insulating layer and the gate of the display back plate.
According to an embodiment of the present invention, after forming the gate insulating layer and the gate electrode, the method further includes: forming an insulating layer on the buffer layer, the patterned semiconductor layer and the surface of the grid electrode far away from the substrate; forming a third via hole in the insulating layer so as to form an interlayer insulating layer; forming a source electrode and a drain electrode on the interlayer insulating layer and a part of the surface of the patterned semiconductor layer away from the substrate; forming a planarization layer on surfaces of the source electrode, the drain electrode, and the interlayer insulating layer away from the substrate; forming a resin layer on a surface of the planarization layer away from the substrate; forming a fourth via hole in the planarization layer and the resin layer; and forming an electrode layer on the surface of the resin layer far away from the substrate.
In yet another aspect of the present invention, a display panel is provided. According to an embodiment of the present invention, the display panel includes the display backplane described above. The display panel has low production cost, is suitable for large-scale industrialization, has all the characteristics and advantages of the display back panel, and is not described in detail herein.
In yet another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the display panel described above. The display device has low production cost, is suitable for large-scale industrialization, has all the characteristics and advantages of the display panel, and is not described in detail herein.
Drawings
Fig. 1 is a schematic cross-sectional view of a display backplane according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a display back plate according to another embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a display back plate according to another embodiment of the invention.
FIG. 4 is a schematic cross-sectional view of a display backplane according to yet another embodiment of the present invention.
FIG. 5 shows a process flow diagram of a method of fabricating a display backplane according to one embodiment of the present invention.
Fig. 6a, 6b and 6c are process flow diagrams of a method for fabricating a display backplate according to another embodiment of the present invention.
FIG. 7 is a process flow diagram of a method of fabricating a display backplane according to yet another embodiment of the present invention.
Fig. 8a, 8b, 8c, and 8d are process flow diagrams illustrating a method of fabricating a display backplane according to yet another embodiment of the present invention.
Fig. 9a, 9b, 9c, 9d, 9e, 9f, 9g, and 9h illustrate a process flow diagram of a method of fabricating a display backplane according to yet another embodiment of the present invention.
Reference numerals:
10: display backplane 100: substrate 110: first surface 200: patterned metal layer 210: light-shielding layer 220: sub-metal layer 300: buffer layer 400: patterned semiconductor layer 410: active layer 420: the sub-semiconductor layer 510: gate insulating layer 520: a grid electrode 600: interlayer insulating layer 700: source 800: drain electrode 810: planarization layer 820: resin layer 900: electrode layer H1: first via hole H2: second via H3: third via H4: a fourth via hole
Detailed Description
The following describes embodiments of the present invention in detail. The following examples are illustrative only and are not to be construed as limiting the invention. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications.
In the related art, the manufacturing process of the display backplane usually requires eight photolithography steps, and accordingly, eight masks are required, that is: when a light shielding layer, an active layer, a gate electrode, a via hole in a buffer layer, an interlayer insulating layer, a source electrode, a drain electrode, a via hole in a resin layer and an electrode layer in a display back plate are formed, a mask is required to be used for photoetching respectively, but the mask is expensive, so that the manufacturing process cost of the display back plate is high, and large-scale industrialization is difficult.
Based on the above research, in one aspect of the present invention, the present invention provides a display backplane. According to an embodiment of the present invention, referring to fig. 1, the display backplane 10 includes: a substrate 100; a patterned metal layer disposed on a portion of the first surface 110 of the substrate 100, the patterned metal layer including a light-shielding layer 210 and a sub-metal layer 220 disposed at intervals; a buffer layer 300, the buffer layer 300 being disposed on the first surface 110 and covering the patterned metal layer; a patterned semiconductor layer disposed on a portion of the surface of the buffer layer 300 away from the patterned metal layer, the patterned semiconductor layer including an active layer 410 and a sub-semiconductor layer 420 disposed at an interval, wherein the patterned metal layer and the patterned semiconductor layer have the same shape (the schematic plan structure of the patterned metal layer 200 and the patterned semiconductor layer 400 refers to fig. 9a and 9 c). Since the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask may be used when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10, and compared with the manufacturing process of the display backplane in the related art, one mask is reduced, so that the production cost may be significantly reduced, and the method is suitable for large-scale industrialization.
According to an embodiment of the present invention, referring to fig. 1, further, an orthographic projection of the patterned metal layer on the substrate 100 and an orthographic projection of the patterned semiconductor layer on the substrate 100 overlap. Therefore, when the patterned metal layer and the patterned semiconductor layer of the display backplane 10 are formed, the same mask can be used, and compared with the manufacturing process of the display backplane in the related art, one mask is reduced, so that the production cost is further remarkably reduced, and the method is suitable for large-scale industrialization.
According to an embodiment of the present invention, referring to fig. 1, further, orthographic projections of the active layer 410 and the light shielding layer 210 on the substrate 100 overlap, and orthographic projections of the sub-semiconductor layer 420 and the sub-metal layer 220 on the substrate 100 overlap. Therefore, when the patterned metal layer and the patterned semiconductor layer of the display backplane 10 are formed, the same mask can be used, and compared with the manufacturing process of the display backplane in the related art, one mask is reduced, so that the production cost is further remarkably reduced, and the method is suitable for large-scale industrialization.
According to the embodiment of the invention, as long as the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask can be used in the forming process, so that the production cost is obviously reduced, and the method is suitable for large-scale industrialization. That is, in other embodiments of the present invention, it can be understood by those skilled in the art that the orthographic projection of the patterned metal layer on the substrate 100 and the orthographic projection of the patterned semiconductor layer on the substrate 100 may not overlap (not shown in the figure), which can also achieve the technical effect of significantly reducing the production cost and being suitable for large-scale industrialization, and redundant description is not repeated herein.
According to an embodiment of the present invention, in addition to the foregoing structure, referring to fig. 2, the buffer layer 300 may further include a first via H therein1And a second via H2The light-shielding layer 210 and the active layer 410 pass through the first via hole H1The sub-metal layer 220 and the sub-semiconductor layer 420 are connected through the second via hole H2Are connected. Thus, since the sub-metal layer 220 passes through the second via hole H2The sub-metal layer 220 is connected to the sub-semiconductor layer 420, so that it is not in a Floating metal state in the display backplane, and the state of the thin film transistor in the display backplane is more stable.
According to an embodiment of the present invention, referring to fig. 3, the display backplane 10 further includes a gate insulating layer 510 and a gate electrode 520, the gate insulating layer 510 is disposed on a portion of the surface of the active layer 410 away from the substrate 100, the gate electrode 520 is disposed on a surface of the gate insulating layer 510 away from the active layer 410, and orthographic projections of the gate insulating layer 510 and the gate electrode 520 on the substrate 100 overlap.
According to an embodiment of the present invention, referring to fig. 3, the display backplane 10 further includes an interlayer insulating layer 600, the interlayer insulating layer 600 is disposed on the surface of the buffer layer 300, the semiconductor layer 410 and the gate electrode 520 far away from the substrate 100, the interlayer insulating layer 600 has a third via H3The third via hole H3The orthographic projection on the substrate 100 and the second via hole H2The orthographic projections on the substrate 100 are at least partially overlapped, and the sub-semiconductor layer 420 and the source electrode 700 or the drain electrode 800 pass through the third via hole H3Connected (it should be noted that the sub-semiconductor layer 420 is connected to the drain 800 in the illustrated case, and those skilled in the art can understand that in other embodiments of the present invention, the sub-semiconductor layer 420 is connected to the source 700, which is not described herein in detail too). Thereby, since the sub-semiconductor layer 420 and the drain electrode 800 pass through the third via hole H3The sub-metal layer 220 is connected, so that a Floating metal state is not formed, and the state of the thin film transistor in the display backplane is more stable; in addition, since the patterned metal layer and the patterned semiconductor layer have the same shape, the same mask may be used when forming the patterned metal layer and the patterned semiconductor layer of the display backplane 10, and compared with the manufacturing process of the display backplane in the related art, one mask is reduced, so that the production cost may be further significantly reduced, and the method is suitable for large-scale industrialization.
In one specific embodiment of the present invention, referring to fig. 4, the display backplane 10 comprises: a substrate 100; a patterned metal layer disposed on a portion of the first surface of the substrate 100, the patterned metal layer including a light-shielding layer 210 and a sub-metal layer 220 disposed at intervals; a buffer layer 300, the buffer layer 300 being disposed on the first surface 110 and covering the patterned metal layer, the buffer layer 300 including a first via H1And a second via H2The light-shielding layer 210 and the active layer 410 pass through the first via hole H1The sub-metal layer 220 and the sub-semiconductor layer 420 are connected through the second via hole H2Connecting; patternedA semiconductor layer disposed on a portion of the surface of the buffer layer 300 away from the patterned metal layer, the patterned semiconductor layer including an active layer 410 and a sub-semiconductor layer 420 disposed at an interval; a gate insulating layer 510, wherein the gate insulating layer 510 is arranged on the surface of the active layer 410 far away from the substrate 100; a gate electrode 520, wherein the gate electrode 520 is arranged on the surface of the gate insulating layer 510 far away from the substrate 100; an interlayer insulating layer 600, the interlayer insulating layer 600 being disposed on the buffer layer 300, the patterned semiconductor layer and the gate electrode 520 on a surface thereof away from the substrate 100, the interlayer insulating layer 600 having a third via hole H3And a source 700 and a drain 800, wherein the third via hole H3The orthographic projection on the substrate 100 and the second via hole H2The orthographic projections on the substrate 100 are at least partially overlapped, and the sub-semiconductor layer 420 and the drain electrode 800 pass through the third via hole H3And connecting, wherein the patterned metal layer and the patterned semiconductor layer have the same shape. Therefore, the display back plate is low in manufacturing cost and suitable for large-scale industrialization.
According to the embodiment of the present invention, it can be understood by those skilled in the art that, in addition to the foregoing structure, the display backplane 10 further includes the planarization layer 810, the resin layer 820 and the electrode layer 900, and the specific arrangement positions thereof are the same as those of the planarization layer, the resin layer and the electrode layer in the conventional display backplane, and therefore, redundant description thereof is omitted.
In another aspect of the invention, a method of making the display backplane described above is provided. According to an embodiment of the invention, referring to fig. 5 and 6a, 6b, 6c, the method comprises the steps of:
s100: a patterned metal layer is formed on a portion of the first surface 110 of the substrate 100, and the patterned metal layer includes a light-shielding layer 210 and a sub-metal layer 220 (refer to fig. 6a for a schematic structural diagram).
According to an embodiment of the present invention, the patterned metal layer may be formed by a patterning process, and the patterning process may include forming a pre-patterned metal layer on a portion of the first surface 110 of the substrate 100, coating a photoresist, and exposing, developing, etching, and stripping the photoresist after covering a mask on the surface of the pre-patterned metal layer, so as to form the patterned metal layer. The specific process parameters and the like of each step in the composition process are process parameters of a conventional composition process, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S200: a buffer layer 300 is formed on the first surface 110 to cover the patterned metal layer (fig. 6 b).
According to an embodiment of the present invention, the process of forming the buffer layer 300 on the first surface 110 to cover the patterned metal layer may include vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing, and the like. The process parameters of vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like are the process parameters of conventional vacuum evaporation, chemical vapor deposition, spin coating, inkjet printing and the like, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
S300: a patterned semiconductor layer is formed on a portion of the surface of the buffer layer 300 away from the patterned metal layer, where the patterned semiconductor layer includes an active layer 410 and a sub-semiconductor layer 420, and the patterned metal layer and the patterned semiconductor layer are formed by using the same mask (refer to fig. 6c for a schematic structural diagram).
According to an embodiment of the present invention, the patterned semiconductor layer may be formed by a patterning process, and the patterning process may include forming a pre-patterned semiconductor layer on a portion of the surface of the buffer layer 300 away from the patterned metal layer, coating a photoresist, and performing exposure, development, etching, and photoresist stripping after covering a mask on the surface of the pre-patterned semiconductor layer, so as to form the patterned semiconductor layer. The specific process parameters and the like of each step in the composition process are process parameters of a conventional composition process, and are not described in detail herein. Therefore, the preparation process is simple and convenient, is easy to realize and is easy for industrial production.
According to the embodiments of the present invention, as described above, since the patterned metal layer and the patterned semiconductor layer have the same shape, when the patterned metal layer and the patterned semiconductor layer are formed, the same mask may be used for exposure, and compared with the manufacturing process of the display backplane in the related art, one mask is reduced, so that the manufacturing cost may be significantly reduced, and the method is suitable for large-scale industrialization.
In further embodiments of the present invention, before forming the patterned semiconductor layer with reference to fig. 7 and 8a, 8b, 8c, 8d, the method further comprises the steps of:
s400: forming a first via hole H in the buffer layer 3001And a second via H2(the schematic structure is shown in FIG. 8 c).
According to an embodiment of the present invention, a first via hole H is formed in the buffer layer 3001And a second via H2In which a first via hole H is formed1And a second via H2The step (2) can be a step of conventionally forming a via hole, and is not described in detail herein.
According to an embodiment of the present invention, referring to fig. 8a, 8b and 8d, a first via hole H is formed in the buffer layer 3001And a second via H2The previous and subsequent steps are the same as those described above, and will not be described in detail.
According to an embodiment of the present invention, in the display backplane of the present invention, the gate electrode and the gate insulating layer in the display backplane may be formed by a single patterning process. Specifically, a prefabricated insulating layer may be formed on a surface of the patterned semiconductor layer away from the substrate; then forming a prefabricated gate layer on the surface of the prefabricated insulating layer far away from the substrate; finally, the prefabricated insulating layer and the prefabricated gate layer are etched through a one-step patterning process, the prefabricated insulating layer after the etching process forms a gate insulating layer 510 in the display backplane, and the prefabricated gate layer after the etching process forms a gate 520 in the display backplane (the structural schematic diagram refers to fig. 3 and 4). Therefore, compared with the manufacturing method in the related technology, the method reduces one-time composition process, so the operation is simple, convenient and easy to realize, and the industrial production is easy to realize.
According to an embodiment of the present invention, after forming the gate insulating layer 510 and the gate electrode 520, the method may further include: forming an insulating layer on surfaces of the buffer layer 300, the patterned semiconductor layer, and the gate electrode 510 away from the substrate 100; forming a third via H in the insulating layer3So as to form an interlayer insulating layer 600; forming a source electrode 700 and a drain electrode 800 on the interlayer insulating layer 600 and a portion of the surface of the patterned semiconductor layer away from the substrate 100; forming a planarization layer 810 on surfaces of the source electrode 700, the drain electrode 800, and the interlayer insulating layer 600 away from the substrate 100; forming a resin layer 820 on a surface of the planarization layer 810 away from the substrate 100; forming fourth via holes H in the planarization layer 810 and the resin layer 8204(ii) a The electrode layer 900 is formed on the surface of the resin layer 820 far from the substrate 100 (the structure schematic diagram refers to fig. 4), and the specific manner, the process conditions and the parameters of the above steps are those of the steps in the conventional method for forming the display backplane, and are not described in detail herein.
In a specific embodiment of the present invention, referring to fig. 9a, 9b, 9c, 9d, 9e, 9f, 9g, and 9h, the method may specifically include: forming a patterned metal layer 200 on a portion of the first surface of the substrate (the schematic plan view of the structure is shown in fig. 9a, and it should be noted that, in fig. 9a and the following drawings, the substrate is not shown); forming a buffer layer on the first surface covering the patterned metal layer 200 (for convenience of illustrating the covered structure, the buffer layer is not shown in the figure); forming a first via H in the buffer layer1And a second via (the schematic plan view is shown in fig. 9b, and it should be noted that fig. 9b only shows the first via H1Second vias not shown); forming a patterned semiconductor layer 400, the patterned semiconductor layer 400 and the previously describedThe patterned metal layer has the same shape (the schematic plan structure diagram refers to fig. 9c), so that the same mask can be used when the patterned metal layer and the patterned semiconductor layer of the display backplane are formed, compared with the manufacturing process of the display backplane in the related art, one mask is reduced, the production cost can be remarkably reduced, and the display backplane is suitable for large-scale industrialization; forming a gate insulating layer (not shown); forming a gate 520 (refer to fig. 9d for a schematic plane structure); forming an insulating layer (not shown for convenience of illustration, so the insulating layer is not shown) on surfaces of the buffer layer, the patterned semiconductor layer and the gate electrode 520 remote from the substrate; forming a third via H in the insulating layer3So as to form an interlayer insulating layer (a schematic plan view is shown in fig. 9e, it should be noted that the neutron semiconductor layer and the source or drain are not shown in the schematic plan view through the third via, and the structure thereof can be seen in fig. 4); forming a source electrode 700 and a drain electrode 800 on the interlayer insulating layer and a part of the surface of the patterned semiconductor layer away from the substrate (refer to fig. 9f for a schematic plan structure); forming a planarization layer on the source electrode 700, the drain electrode 800 and the surface of the interlayer insulating layer away from the substrate; forming a resin layer on a surface of the planarization layer away from the substrate; forming a fourth via hole H in the planarization layer and the resin layer4(the schematic plan view is shown in fig. 9g, it should be noted that the neutron semiconductor layer and the source or drain are not shown in the schematic plan view through the fourth via, and the structure thereof can be seen in fig. 4); an electrode layer 900 is formed on a surface of the resin layer away from the substrate (see fig. 9h for a schematic plan view).
In yet another aspect of the present invention, a display panel is provided. According to an embodiment of the present invention, the display panel includes the display backplane described above. The display panel has low production cost, is suitable for large-scale industrialization, has all the characteristics and advantages of the display back panel, and is not described in detail herein.
According to the embodiment of the present invention, the display panel further includes other necessary structures and components besides the display backplane described above, specifically, for example, a color film substrate, a housing, and the like, and those skilled in the art can supplement and design the display panel according to the specific type and the use requirement of the display panel, and therefore, redundant description is not repeated herein.
In yet another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the display panel described above. The display device has low production cost, is suitable for large-scale industrialization, has all the characteristics and advantages of the display panel, and is not described in detail herein.
According to the embodiment of the present invention, the display device includes other necessary structures and components besides the display panel described above, and those skilled in the art can supplement and design the display device according to the specific kind and use requirements of the display device, and therefore, redundant description is not repeated herein.
According to an embodiment of the present invention, the specific kind of the display device is not particularly limited, for example, including but not limited to a mobile phone, a tablet computer, a wearable device, a game machine, and the like.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected" and "connected" are to be construed broadly, e.g., as meaning either a fixed connection or a removable connection, or an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (13)
1. A display backplane, comprising:
a substrate;
the patterned metal layer is arranged on part of the first surface of the substrate and comprises a light shielding layer and a sub-metal layer which are arranged at intervals;
a buffer layer disposed on the first surface and covering the patterned metal layer;
a patterned semiconductor layer disposed on a portion of a surface of the buffer layer away from the patterned metal layer, the patterned semiconductor layer including an active layer and a sub-semiconductor layer disposed at intervals,
wherein the patterned metal layer and the patterned semiconductor layer have the same shape.
2. The display backplane of claim 1, wherein an orthographic projection of the patterned metal layer on the substrate and an orthographic projection of the patterned semiconductor layer on the substrate overlap.
3. The display backplane of claim 2, wherein orthographic projections of the active layer and the light-shielding layer on the substrate overlap, and orthographic projections of the sub-semiconductor layer and the sub-metal layer on the substrate overlap.
4. The display backplane of claim 1, wherein the buffer layer comprises a first via and a second via,
the light shielding layer is connected with the active layer through the first through hole, and the sub-metal layer is connected with the sub-semiconductor layer through the second through hole.
5. The display backplane of claim 4, further comprising a gate insulating layer disposed on a portion of a surface of the active layer remote from the substrate, and a gate electrode disposed on a surface of the gate insulating layer remote from the active layer, wherein orthographic projections of the gate insulating layer and the gate electrode on the substrate overlap.
6. The display backplane according to claim 5, further comprising an interlayer insulating layer disposed on surfaces of the buffer layer, the patterned semiconductor layer, and the gate electrode away from the substrate, the interlayer insulating layer having a third via, an orthographic projection of the third via on the substrate at least partially overlapping an orthographic projection of the second via on the substrate, the sub-semiconductor layer and the source or drain electrode being connected by the third via.
7. A display backplane according to claim 6, comprising:
the substrate;
the patterned metal layer is arranged on part of the first surface of the substrate and comprises a light shielding layer and a sub-metal layer which are arranged at intervals;
the buffer layer is arranged on the first surface and covers the patterned metal layer;
the patterned semiconductor layer is arranged on a part of the surface of the buffer layer far away from the patterned metal layer and comprises an active layer and a sub-semiconductor layer which are arranged at intervals;
the gate insulating layer is arranged on a part of the surface of the active layer far away from the substrate, the gate electrode is arranged on the surface of the gate insulating layer far away from the active layer, and orthographic projections of the gate insulating layer and the gate electrode on the substrate are overlapped;
the interlayer insulating layer is arranged on the surface, far away from the substrate, of the buffer layer, the patterned semiconductor layer and the grid electrode, and is provided with a third through hole, the orthographic projection of the third through hole on the substrate is at least partially overlapped with the orthographic projection of the second through hole on the substrate, and the sub-semiconductor layer and the source electrode or the drain electrode are connected through the third through hole,
the buffer layer comprises a first through hole and a second through hole, the light shielding layer is connected with the active layer through the first through hole, the sub-metal layer is connected with the sub-semiconductor layer through the second through hole, and the orthographic projection of the patterned metal layer on the substrate is overlapped with the orthographic projection of the patterned semiconductor layer on the substrate.
8. A method of making a display backplane, comprising:
forming a patterned metal layer on a portion of the first surface of the substrate, the patterned metal layer including a light-shielding layer and a sub-metal layer;
forming a buffer layer on the first surface covering the patterned metal layer;
forming a patterned semiconductor layer on a portion of a surface of the buffer layer remote from the patterned metal layer, the patterned semiconductor layer including an active layer and a sub-semiconductor layer,
wherein the patterned metal layer and the patterned semiconductor layer are formed through the same mask.
9. The method of claim 8, further comprising, prior to forming the patterned semiconductor layer:
forming a first via and a second via in the buffer layer.
10. The method of claim 8, comprising:
forming a prefabricated gate insulating layer on the surface of the active layer far away from the substrate;
forming a prefabricated gate electrode layer on the surface of the prefabricated gate insulating layer far away from the active layer;
and etching the prefabricated gate insulating layer and the prefabricated gate layer by a one-step composition process to form the gate insulating layer and the gate of the display back plate.
11. The method of claim 10, further comprising, after forming the gate insulating layer and the gate electrode:
forming an insulating layer on the buffer layer, the patterned semiconductor layer and the surface of the grid electrode far away from the substrate;
forming a third via hole in the insulating layer so as to form an interlayer insulating layer;
forming a source electrode and a drain electrode on the interlayer insulating layer and a part of the surface of the patterned semiconductor layer away from the substrate;
forming a planarization layer on surfaces of the source electrode, the drain electrode, and the interlayer insulating layer away from the substrate;
forming a resin layer on a surface of the planarization layer away from the substrate;
forming a fourth via hole in the planarization layer and the resin layer;
and forming an electrode layer on the surface of the resin layer far away from the substrate.
12. A display panel comprising the display backplane according to any one of claims 1 to 7.
13. A display device characterized by comprising the display panel described in claim 12.
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| CN201910978142.8A CN110690231A (en) | 2019-10-15 | 2019-10-15 | Display back plate and manufacturing method thereof, display panel and display device |
| PCT/CN2020/119969 WO2021073445A1 (en) | 2019-10-15 | 2020-10-09 | Display backplane and manufacturing method therefor, display panel, and display device |
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| CN201910978142.8A CN110690231A (en) | 2019-10-15 | 2019-10-15 | Display back plate and manufacturing method thereof, display panel and display device |
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