WO2021068397A1

WO2021068397A1 - Cmos structure, image sensor, and handheld apparatus

Info

Publication number: WO2021068397A1
Application number: PCT/CN2019/123732
Authority: WO
Inventors: 林奇青; 杨富强; 杨孟达
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2019-10-10
Filing date: 2019-12-06
Publication date: 2021-04-15
Also published as: CN111052730A; CN111052730B; WO2021068157A1

Abstract

Disclosed in the present application are a CMOS structure (103_1), an image sensor, and a handheld apparatus. The CMOS structure is coupled to a thin film semiconductor structure, the thin film semiconductor structure comprises at least one pixel, and the pixel is used for generating a reset signal in a reset stage and outputting same to the CMOS structure and for generating a sensing signal in a sensing stage and only outputting the sensing signal to the CMOS structure in a readout stage. The CMOS structure comprises: an operational amplifier (206), a positive terminal (+) selectively receiving the reset signal from the thin film semiconductor structure, and a negative terminal (-) selectively receiving the sensing signal from the thin film semiconductor structure; a first feedback circuit (201), which is coupled between the negative terminal of the operational amplifier and an output terminal and which is used to be configured as a unity gain buffer together with the operational amplifier during the reset stage; and a second feedback circuit (203), which is used to be configured as a charge amplifier together with the first feedback circuit and the operational amplifier during the readout stage.

Description

CMOS structure, image sensor and handheld device

Technical field

This application relates to semiconductor structures, and more particularly to a complementary metal oxide semiconductor (CMOS) structure and related image sensors and handheld devices.

Background technique

With the popularization of fingerprint recognition functions on handheld devices, the requirements for the area on the screen that can perform fingerprint recognition are getting higher and higher. The cost of image sensors implemented using CMOS structures is much higher than that of images using thin-film semiconductor structures. Sensors, but image sensors implemented using thin-film semiconductor structures have many shortcomings that need to be overcome, such as slow signal speed and small sensing signals. Therefore, it is necessary to further improve related circuits to overcome the above-mentioned problems.

Summary of the invention

One of the objectives of the present application is to disclose a CMOS structure and related image sensors and handheld devices to solve the above-mentioned problems.

An embodiment of the present application discloses a CMOS structure coupled to a thin film semiconductor structure, the thin film semiconductor structure includes at least one pixel, and the pixel is used to generate a reset signal during a reset stage and output to the CMOS structure , And generate a sensing signal in the sensing stage, and output the sensing signal to the CMOS structure in the read-out stage. The CMOS structure includes an operational amplifier with a positive terminal, a negative terminal and an output terminal, so The positive terminal selectively receives the reset signal from the thin film semiconductor structure, the negative terminal selectively receives the sensing signal from the thin film semiconductor structure; a first feedback circuit is coupled to the operation Between the negative terminal and the output terminal of the amplifier, it is configured to be a unity gain buffer together with the operational amplifier during the reset phase; and a second feedback circuit is used for reading When exiting the stage, it is configured as a charge amplifier together with the first feedback circuit and the operational amplifier.

An embodiment of the present application discloses an image sensor including the CMOS structure and the thin film semiconductor structure.

An embodiment of the present application discloses a handheld device for sensing a fingerprint of a specific object. The handheld device includes a display panel; and the image sensor. The thin film semiconductor structure is disposed on the display panel. Next, it is used to sense the fingerprint of the specific object.

An embodiment of the present application discloses a handheld device for sensing the fingerprint of a specific object, the handheld device comprising: the image sensor for sensing the fingerprint of the specific object; and a display panel, and The thin film semiconductor structures of the image sensor are integrated together.

The CMOS structure, related image sensor and handheld device disclosed in the present application can reduce cost without affecting performance. Specifically, the CMOS structure, related image sensor and handheld device disclosed in the present application can solve the problem of sensing signal reading when a thin film semiconductor structure is used to implement a pixel structure.

Description of the drawings

FIG. 1 is a schematic diagram of an embodiment of the image sensor of the application.

FIG. 2 is a schematic diagram of an embodiment of the thin film semiconductor structure of the application.

FIG. 3 is a schematic diagram of the first embodiment of the CMOS structure of this application.

FIG. 4 is an operation timing diagram of the CMOS structure of FIG. 3.

FIG. 5 is a configuration diagram of the CMOS structure of FIG. 3 operating in the reset phase.

FIG. 6 is a configuration diagram of the CMOS structure of FIG. 3 operating in the sensing phase.

FIG. 7 is a configuration diagram of the CMOS structure of FIG. 3 operating in the read phase.

FIG. 8 is a schematic diagram of a second embodiment of the CMOS structure of this application.

FIG. 9 is an operation timing diagram of the CMOS structure of FIG. 8.

FIG. 10 is a schematic diagram of an embodiment of a handheld device of this application.

Detailed ways

The source follower transistor in the pixel array implemented by the traditional CMOS structure needs to quickly read out the sensing result after the sensing phase, and the length of time is about microseconds. Compared with the CMOS structure, the mobility of the thin film transistor (TFT) under the thin film semiconductor structure is poor, so the speed of the TFT is much slower than the transistor speed under the CMOS structure. If the above-mentioned traditional pixel array is directly replaced with a thin film semiconductor structure without changing the circuit and operation mode, the problem of insufficient speed of the source follower thin film transistor will be encountered.

The thin film semiconductor structure disclosed in the present application uses TFT technology to realize the pixel array. The difference from the traditional pixel array is that the pixel array of the present application uses a source follower thin film transistor to read out the sensing result in real time during the sensing phase. It is temporarily stored in the capacitor, and the charge in the capacitor is read out after the sensing phase ends and the readout phase is entered. Since the time of the sensing phase is long enough, on the order of milliseconds, the source follower thin film transistor has enough time to read out the sensing result and temporarily store it in the capacitor, which solves the above-mentioned problem. In addition, this application also proposes a corresponding CMOS structure for the above-mentioned pixel array realized by the TFT process, which is used to read the sensing result of the pixel. The following is a detailed description of the thin film of this application in conjunction with a number of embodiments and drawings. The technical content of semiconductor structure, CMOS structure and related image sensors and handheld devices.

FIG. 1 is a schematic diagram of an embodiment of an image sensor 100 of this application. The image sensor 100 includes a thin film semiconductor structure 101 and a CMOS structure 103. The thin film semiconductor structure 101 includes a pixel array composed of at least one pixel. In FIG. 1, only pixels P11, P21, P12, and P22 are shown. In fact, the pixel array may include, for example, a pixel array of n rows*m columns, where n and m are integers greater than zero. The CMOS structure 103 includes a plurality of reading circuits, such as reading circuits 103_1, 103_22, etc., which are respectively coupled to multiple columns of pixels in the pixel array of the thin film semiconductor structure 101.

The image sensor 100 has a reset phase, a sensing phase, and a readout phase. Each pixel in the thin-film semiconductor structure 101 generates a reset signal during the reset stage and outputs it to the corresponding reading circuit in the CMOS structure 103, and generates a sensing signal during the sensing stage, and in the read The sensing signal is output to the corresponding read circuit in the CMOS structure 103 at the output stage. Please note that in this application, the type of the reset signal is a voltage signal, and the type of the sensing signal is a charge. signal. In this embodiment, the pixel array in the thin film semiconductor structure 101 can output multiple reset signals or sensing signals corresponding to the entire row of pixels to the corresponding reading circuit in the CMOS structure 103 line by line. For example, the charges of the pixel P11 and the pixel P12 are output to the reading circuits 103_1 and 103_2 in the CMOS structure 103 through the bit line BL1 and the bit line BL2, respectively, and then the charges of the pixel P21 and the pixel P22 are passed through the bit line BL1 and the bit line respectively. BL2 is output to the reading circuits 103_1 and 103_2 in the CMOS structure 103. The reading circuits 103_1 and 103_2 will correspondingly output the reading results S1 and S2.

FIG. 2 is a schematic diagram of an embodiment of the thin film semiconductor structure 101 of this application. For brevity, FIG. 2 only shows the pixel P11 in the thin film semiconductor structure 101. The pixel P11 in FIG. 2 includes a photodiode 102, a reset thin film transistor 104, a source follower thin film transistor 106, a current source 108, a switch 114, and a capacitor 110. And row selection thin film transistor 112. The photodiode 102 is used to convert light into electric charges, for example, the light reflected from a fingerprint and entering the photodiode 102 is converted into electric charges. One end (cathode) of the photodiode 102 is coupled to the gate of the source follower thin film transistor 106, and the other end (anode) of the photodiode 102 is coupled to the first voltage V _1. In this embodiment, the first voltage V ₁ is Ground voltage, but this application is not limited to this. The drain of the reset thin film transistor 104 is coupled to the gate of the source follower thin film transistor 106 and the one end (cathode) of the photodiode 102, and the source of the reset thin film transistor 104 is coupled to the second voltage V ₂ , and according to The control signal R for resetting the gate of the thin film transistor 104 is selectively turned on. In this embodiment, the second voltage V _{2 is} greater than the first voltage V ₁ .

The gate of the source follower thin film transistor 106 is coupled to the one end (cathode) of the photodiode 102 and the drain of the reset thin film transistor 104, the drain of the source follower thin film transistor 106 is coupled to the first voltage V ₁ , and the source follower The source of the thin film transistor 106 is coupled to the current source 108. In this embodiment, the current source 108 is implemented by a current source thin film transistor 108, the drain of the current source thin film transistor 108 is coupled to the source of the source follower thin film transistor 106, and the source of the current source thin film transistor 108 is coupled to the second The voltage V ₂ is selectively turned on according to the bias voltage B of the gate of the current source thin film transistor 108. The switch 114 is selectively turned on according to the gate control signal S2, the drain of the switch 114 is coupled to the source of the source follower thin film transistor 106 and the drain of the current source thin film transistor 108, and the source of the switch 114 is coupled The drain of the thin film transistor 112 and one end of the capacitor 110 are selected for the row. The other end of the capacitor 110 is coupled to the first voltage V ₁ . The source of the row selection thin film transistor 112 is coupled to the bit line BL1, and is selectively turned on according to the control signal S of the gate of the row selection thin film transistor 112.

FIG. 3 is a schematic diagram of the first embodiment of the CMOS structure 103 of this application. For brevity, FIG. 3 only shows the reading circuit 103_1 in the CMOS structure 103. The reading circuit 103_1 in FIG. 3 includes an operational amplifier 206, a first feedback circuit 201, a second feedback circuit 203, and an analog-to-digital converter 212. The operational amplifier 206 has a positive terminal (+), a negative terminal (-), and an output terminal. The positive terminal of the operational amplifier 206 is selectively coupled to the bit line BL1 through the switch 204; the negative terminal of the operational amplifier 206 is selectively coupled through the switch 202 Coupled to the bit line BL1. The analog-to-digital converter 212 is coupled to the output terminal of the operational amplifier 206 and outputs the read result S1. The first feedback circuit 201 is coupled between the negative terminal and the output terminal of the operational amplifier 206; the second feedback circuit 203 is coupled between the positive terminal and the output terminal of the operational amplifier 206, specifically In other words, the second feedback circuit 203 is coupled between the positive terminal of the operational amplifier 206 and the analog-to-digital converter 212. The first feedback circuit 201 includes a capacitor 208 and a switch 210, which are arranged in parallel with each other. The second feedback circuit 203 includes a digital-to-analog converter 214 and a switch 216, and the switch 216 is coupled between the digital-to-analog converter 214 and the positive terminal of the operational amplifier 206.

In this embodiment, the

switches

202, 204, 210, and 216 are P-type CMOS transistors, and the control signals H, HREFB, RST, and HREF are used to control whether they are turned on or not, but the realization of the

switches

202, 204, 210, and 216 The method is not limited to this. In addition, the digital-to-analog converter 214 is controlled by the control signal EN. When EN is at the first potential (high potential in this embodiment), the digital-to-analog converter 214 is in the conversion mode, and the output from the analog-to-digital converter 212 can be The read result S1 is converted from a digital signal type to an analog signal type; when EN is at the second potential (low potential in this embodiment), the digital-to-analog converter 214 is in the hold mode, and the continuous output EN is changed from the first The output when the electric potential is changed to the second electric potential.

FIG. 4 is an operation timing diagram of the CMOS structure of FIG. 3. 5 to 7 are configuration diagrams of the CMOS structure operation of FIG. 3 in the reset phase, the sensing phase, and the readout phase, respectively. In Figures 5-7, the circuits that are turned on will be represented in darker colors; otherwise, the circuits that are turned off will be represented in lighter colors.

Please refer to FIGS. 4 and 5 at the same time. In the reset phase, the switch 204 is turned on, so that the positive terminal of the operational amplifier 206 receives the reset signal from the thin film semiconductor structure 101 through the bit line BL1. The switch 202 is not turned on, and the switch 210 is turned on, so that the negative terminal of the operational amplifier 206 is not coupled to the bit line BL1, but is directly coupled to the output terminal of the operational amplifier 206 through the switch 210. The switch 216 is not turned on, so that the second feedback circuit 203 is disconnected from the positive terminal of the operational amplifier 206. In this way, the first feedback circuit 201 and the operational amplifier 206 are jointly configured as a unity gain buffer. As mentioned above, the type of the reset signal is a voltage signal. Therefore, the unity gain buffer configured by the first feedback circuit 201 and the operational amplifier 206 will output the reset signal, and the reset signal will be converted through the analog-to-digital converter 212. The reset signal is converted from an analog signal type to a digital signal type.

Please refer to FIGS. 4 and 6 at the same time. In the sensing phase, the

switches

202 and 204 are not turned on, so that the positive and negative terminals of the operational amplifier 206 are not coupled to the bit line BL1, the switch 210 is not turned on, and the switch 216 Is turned on. At this stage, the analog-to-digital converter 212 has completed the conversion of the reset signal from the analog signal type to the digital signal type, and outputs the read result S1, and the digital-to-analog converter 214 will be controlled as the In the conversion mode, the reset signal of the digital signal type is converted back to the analog signal type, that is, the reset signal after two conversions.

Please refer to FIGS. 4 and 7 at the same time. In the read phase, the switch 202 is turned on, so that the negative terminal of the operational amplifier 206 receives the sensing signal from the thin film semiconductor structure 101 via the bit line BL1. The switch 204 is not turned on, and the switch 216 is turned on, so that the positive terminal of the operational amplifier 206 is not coupled to the bit line BL1, but is coupled to the output terminal of the digital-to-analog converter 214 through the switch 216. The switch 210 is not turned on, so that the first feedback circuit 201 is a capacitor 208 coupled to the negative terminal and the output terminal of the operational amplifier 206. In this way, the first feedback circuit 201, the second feedback circuit 203 and the operational amplifier 206 are jointly configured as a charge amplifier. As mentioned above, the type of the sensing signal is a charge signal. Therefore, the charge amplifier configured with the first feedback circuit 201, the second feedback circuit 203 and the operational amplifier 206 will determine the difference between the positive terminal and the negative terminal of the operational amplifier 206. Converted to a voltage-type output sensing signal, the analog-to-digital converter 212 converts the output sensing signal from an analog signal type to a digital signal type and outputs the read result S1. Since the digital-to-analog converter 214 is controlled in the holding mode during the readout phase, the output when the sensing phase is switched to the readout phase is maintained, that is, the reset signal is output after the analog mode. The signal obtained after the digital converter 212 and the digital-to-analog converter 214. Therefore, the charge amplifier configured with the first feedback circuit 201, the second feedback circuit 203 and the operational amplifier 206 will convert the sensing signal and the two conversions. The difference of the subsequent reset signal is converted into the output sensing signal of voltage type.

Through the above three stages, the purpose of using the reset signal to correct the sensing signal is achieved. In other words, the reading circuit 103_1 of the CMOS structure 103 with the thin film semiconductor structure 101 has correlated double sampling (CDS ) Function.

FIG. 8 is a schematic diagram of a second embodiment of the CMOS structure 103 of this application. For brevity, FIG. 8 only shows the reading circuit 103_1 in the CMOS structure 103. The difference from the reading circuit 103_1 in FIG. 3 is that the reading circuit 103_1 in FIG. 8 replaces the digital-to-analog converter 214 with a sample-and-hold circuit 314 And the sample-and-hold circuit 314 is coupled to the output terminal of the operational amplifier 206 instead of the output terminal of the analog-to-digital converter 212. In other words, the sample-and-hold circuit 314 receives an analog signal, and the digital-to-analog converter 214 receives Digital signal. The sample-and-hold circuit 314 is controlled by the control signal MEM. When MEM is at the second potential (low potential in this embodiment), the sample-and-hold circuit 314 is in the sampling mode and can sample the output of the operational amplifier 206. ; When MEM is the first potential (high potential in this embodiment), the sample-and-hold circuit 314 is in the hold mode, which can hold and continuously output the MEM when the second potential is changed to the first potential Sampling results. The rest of FIG. 8 is roughly the same as that of FIG. 3.

FIG. 9 is an operation timing diagram of the CMOS structure of FIG. 8. The difference between FIG. 9 and FIG. 4 is only the control of the sample and hold circuit 314. Since the sample-and-hold circuit 314 samples the output of the output terminal of the operational amplifier 206, the waiting time for the conversion of the analog-to-digital converter 212 is reduced, so the reset signal can be sampled during the reset stage, unlike FIG. 4 The digital-to-analog converter 214 may need to wait until the sensing phase to output the reset signal after the two conversions, so the sample-and-hold circuit 314 only needs to be controlled in the sampling mode during the reset phase, It is sufficient that both the sensing and reading phases after the reset phase are controlled in the holding mode. The rest of the operation in FIG. 9 is roughly the same as that in FIG. 4.

In some embodiments, the image sensor 100 may further include a microlens array (not shown in the figure) disposed on the pixel array of the thin film semiconductor structure 101, and the microlenses in the microlens array may be combined with the thin film semiconductor structure. The pixels in the pixel array of 101 have a one-to-one correspondence, or one microlens in the microlens array may correspond to multiple pixels in the pixel array of the thin film semiconductor structure 101. Optionally, the one microlens may correspond to four pixels. Pixels. In some embodiments, the image sensor 100 may further include a filter (not shown in the figure) disposed between the pixel array of the thin film semiconductor structure 101 and the microlens or on the microlens, Used to pass specific light waves with specific wavelengths.

FIG. 10 is a schematic diagram of an embodiment of a handheld device of this application. The handheld device 600 can be used to sense the fingerprint of a specific object. The handheld device 600 includes a display panel 602 and an image sensor 100. In some embodiments, the thin-film semiconductor structure 101 is disposed under the display panel 602 to sense all the fingerprints. Describe the fingerprint of a specific object. In some embodiments, the thin film semiconductor structure 101 and the display panel 602 can be integrated together. For example, the display panel 602 is a thin film semiconductor display panel, including a display area and a fingerprint sensing area. The fingerprint sensing area is The area where the thin film semiconductor structure 101 is located. The handheld device 600 can be used to perform optical under-screen/in-screen fingerprint sensing to sense the fingerprint of a specific object. Among them, the handheld device 600 may be any handheld electronic device such as a smart phone, a personal digital assistant, a handheld computer system, or a tablet computer. And because the cost of the thin film semiconductor structure 101 is lower than that of the conventional pixel sensing element using CMOS structure, the thin film semiconductor structure 101 of the handheld device 600 can have a larger area, which is convenient for users to perform fingerprint sensing. The area of the semiconductor structure 101 can reach 1/4 to 1/2 of the display panel 602, or even larger.

Claims

A CMOS structure is coupled to a thin film semiconductor structure. The thin film semiconductor structure includes at least one pixel. The pixel is used to generate a reset signal during the reset phase and output to the CMOS structure, and to generate a sense during the sensing phase. And output the sensing signal to the CMOS structure in the readout stage, and the CMOS structure includes:

The operational amplifier has a positive terminal, a negative terminal and an output terminal, the positive terminal selectively receives the reset signal from the thin film semiconductor structure, and the negative terminal selectively receives the sense signal from the thin film semiconductor structure. Test signal

A first feedback circuit, coupled between the negative terminal and the output terminal of the operational amplifier, is configured to be a unity gain buffer together with the operational amplifier during the reset phase; and

The second feedback circuit is used for configuring as a charge amplifier together with the first feedback circuit and the operational amplifier during the readout stage.
The CMOS structure of claim 1, wherein in the reset phase, the positive terminal receives the reset signal from the thin film semiconductor structure, and the negative terminal does not receive the reset signal from the thin film semiconductor structure. Reset signal.
The CMOS structure of claim 1, wherein in the sensing phase, the positive terminal does not receive the sensing signal from the thin film semiconductor structure, and the negative terminal does not receive the sensing signal from the thin film semiconductor structure. The sensing signal.
The CMOS structure of claim 1, wherein in the readout phase, the positive terminal does not receive the sensing signal from the thin film semiconductor structure, and the negative terminal receives the sensing signal from the thin film semiconductor structure. Sensing signal.
3. The CMOS structure of claim 1, wherein the type of the reset signal is a voltage signal, and during the reset phase, the unity gain buffer outputs the reset signal.
The CMOS structure of claim 1, wherein the type of the sensing signal is a charge signal, and during the readout phase, the charge amplifier converts the sensing signal into a voltage-type output sensing signal .
5. The CMOS structure of claim 1, further comprising an analog-to-digital converter coupled to the output terminal of the operational amplifier.
8. The CMOS structure of claim 7, wherein the second feedback circuit is coupled between the positive terminal of the operational amplifier and the output terminal of the analog-to-digital converter.
The CMOS structure of claim 8, wherein the analog-to-digital converter is used to convert the reset signal from an analog signal type to a digital signal type before the readout stage, and the second feedback circuit includes A digital-to-analog converter for converting the reset signal of the digital signal type to the analog signal type before the readout stage.
9. The CMOS structure of claim 9, wherein the digital-to-analog converter continuously outputs the reset signal of the analog signal type to the positive terminal of the operational amplifier during the readout phase.
7. The CMOS structure of claim 7, wherein the second feedback circuit is coupled between the positive terminal of the operational amplifier and the output terminal of the operational amplifier.
11. The CMOS structure of claim 11, wherein the second feedback circuit includes a sample-and-hold circuit for sampling the reset signal during the sensing phase.
11. The CMOS structure of claim 12, wherein the sample-and-hold circuit holds and outputs the reset signal to the positive terminal of the operational amplifier during the readout phase.
5. The CMOS structure of claim 1, wherein the first feedback circuit further comprises a capacitor.
The CMOS structure according to claim 14, wherein the first feedback circuit further comprises a first switch, which is arranged in parallel with the capacitor, the first switch is turned on during the reset phase, and when the sensing Neither the phase nor the read phase conducts.
The CMOS structure of claim 1, wherein the second feedback circuit further comprises a second switch for selectively determining whether the second feedback circuit and the positive terminal of the operational amplifier are conductive , The second switch is not turned on during the reset phase, and is turned on during both the sensing phase and the readout phase.
An image sensor, including:

The CMOS structure according to any one of claims 1-16; and

The thin film semiconductor structure.
The image sensor according to claim 17, further comprising a micro lens array, comprising a plurality of micro lenses arranged on the thin film semiconductor structure, the thin film semiconductor structure comprising a pixel array composed of a plurality of pixels, and the micro lens The plurality of microlenses in the array may correspond to the plurality of pixels in the pixel array in a one-to-one or one-to-many manner.
The image sensor according to claim 18, further comprising a filter, the filter being arranged between the thin film semiconductor structure and the microlens or on the microlens.
A handheld device for sensing a fingerprint of a specific object, the handheld device comprising:

Display panel; and

19. The image sensor according to any one of claims 17-19, wherein the thin film semiconductor structure is disposed under the display panel for sensing the fingerprint of the specific object.
A handheld device for sensing a fingerprint of a specific object, the handheld device comprising:

The image sensor according to any one of claims 17-19, for sensing the fingerprint of the specific object; and

The display panel is integrated with the thin film semiconductor structure of the image sensor.