WO2021068335A1 - 一种数据处理方法、装置及存储介质 - Google Patents

一种数据处理方法、装置及存储介质 Download PDF

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Publication number
WO2021068335A1
WO2021068335A1 PCT/CN2019/117692 CN2019117692W WO2021068335A1 WO 2021068335 A1 WO2021068335 A1 WO 2021068335A1 CN 2019117692 W CN2019117692 W CN 2019117692W WO 2021068335 A1 WO2021068335 A1 WO 2021068335A1
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Prior art keywords
data
link
channel
data transmission
identifier
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PCT/CN2019/117692
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English (en)
French (fr)
Inventor
王东
贺伟
朱彬
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盛科网络（苏州）有限公司
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Priority to US17/767,935 priority Critical patent/US20240104042A1/en
Publication of WO2021068335A1 publication Critical patent/WO2021068335A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Definitions

  • the present invention relates to the field of electronic technology, in particular to a data processing method, device and storage medium.
  • the physical link has a link crossing condition on the printed circuit board (Printed Circuit Board , PCB) of the chip. Therefore. How to realize the anti-crossing between each physical link port and the data transmission link inside the switching chip and ensure that there is a one-to-one correspondence between the physical link port and the data transmission link is a technical problem that needs to be solved.
  • PCB printed Circuit Board
  • the embodiments of the present application provide a data processing method, device, and storage medium, so that when there is a link cross on the printed circuit board of the chip, it is ensured that the physical link port and the data transmission link of the chip are still one-to-one. corresponding.
  • an embodiment of the present application provides a data processing method, and the method includes:
  • the data of the at least one first data transmission channel is sent to the corresponding data transmission link.
  • the link cross information of the printed circuit board includes:
  • the method further includes:
  • the channel identifier of the at least one first data transmission channel is configured according to the link cross information of the printed circuit board.
  • the transmitting the at least one second data to the at least one first data transmission channel includes:
  • the second data is transmitted to the first data transmission channel matching the channel identifier of the second data.
  • the method further includes:
  • the link identifier of the at least one data transmission link is configured according to the link cross information of the printed circuit board.
  • the configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes:
  • the link cross information of the printed circuit board is that the m-th data transmission link corresponds to the n-th physical link port
  • the port identifiers of the link ports match, so that the data of the m-th data transmission link can be transmitted to the n-th physical link port;
  • the sending the data of the at least one first data transmission channel to the corresponding data transmission link includes:
  • an embodiment of the present application provides a data processing method, and the method includes:
  • the at least one piece of third data is sent to the corresponding data reassembly link.
  • the method further includes:
  • a channel identifier of at least one second data transmission channel that receives the at least one third data is configured.
  • the sending the at least one piece of third data to the corresponding data reassembly link according to the channel identifier and the link identifier of the third data includes:
  • data of at least one second data transmission channel that matches the channel identifier of the request information is sent to the data reorganization link that sends the request information.
  • an embodiment of the present application provides a data processing device, and the device includes:
  • the first receiving unit is configured to receive first data including at least one second data
  • a data gating unit configured to transmit the at least one second data to at least one first data transmission channel
  • the data distribution unit is configured to send the data of the at least one first data transmission channel to the corresponding data transmission link according to the link cross information of the printed circuit board.
  • the device further includes:
  • the configuration unit is configured to configure the channel identifier of the at least one first data transmission channel according to the link cross information of the printed circuit board.
  • the data gating unit is further configured to:
  • the second data is transmitted to the first data transmission channel matching the channel identifier of the second data.
  • the configuration unit is further configured to:
  • the link identifier of the at least one data transmission link is configured according to the link cross information of the printed circuit board.
  • the configuration unit is configured to configure the m-th data transmission when the link cross information of the printed circuit board is that the m-th data transmission link corresponds to the n-th physical link port
  • the link identifier of the link matches the port identifier of the nth physical link port, so that the data of the mth data transmission link can be transmitted to the nth link port;
  • the data distribution unit is configured to send the second data to a data transmission link matching the link identifier of the second data.
  • an embodiment of the present application provides a data processing method, and the device includes:
  • the second receiving unit is configured to respectively receive at least one piece of third data based on at least one port;
  • the data buffer unit is configured to send the at least one third data to the corresponding data reassembly link according to the channel identifier and the link identifier of the third data.
  • the device further includes: a configuration unit configured to configure a channel identifier of at least one second data transmission channel that receives the at least one third data according to the channel identifier of the third data;
  • the data buffer unit is further configured to transmit the third data to a second data transmission channel matching the channel identifier of the third data.
  • the data buffer unit is further configured to send data of at least one second data transmission channel matching the channel identifier of the request information to the channel identifier carried in the request information sent by the data reorganization link The data reassembly link that sent the request information;
  • the device further includes: a data reorganization unit configured to send the request information to the data caching unit; and configured to reorganize the at least one third data according to the link identifier of the at least one third data.
  • An embodiment of the present application also provides a data processing device, including a memory, a processor, and an executable program stored on the memory and capable of being run by the processor.
  • the processor implements the The steps of the data processing method.
  • the embodiments of the present application provide a data processing method, device, and storage medium, by receiving first data including at least one second data; transmitting the at least one second data to at least one first data transmission channel;
  • the link cross information of the circuit board sends the data of the at least one first data transmission channel to the corresponding data transmission link. So that when the physical link of the chip has a link cross on the printed circuit board of the chip, when the chip transmits data to the physical link ports of other modules on the printed circuit board, it can still ensure that the data transmission link inside the chip is The physical link ports of other modules on the printed circuit board have a one-to-one correspondence.
  • the data processing method provided by the embodiment of the application has high scalability and is also applicable to chips with multiple data transmission channels and multiple data transmission links; and, the data processing method provided by the embodiment of the application does not introduce data logic
  • the link will not increase the burden of the chip data selection module, nor will it increase the complexity of the real-time clock tree analysis on the back-end of the chip due to the clock of the data logic link.
  • Figure 1 is a schematic diagram of the link connection between the Ethernet switch chip and the QSFP optical module on the PCB;
  • Figure 2 is the second schematic diagram of the link connection between the Ethernet switch chip and the QSFP optical module on the PCB;
  • Figure 3 is a schematic diagram of the link connection between the Ethernet switch chip and the Ethernet interface chip on the backplane;
  • FIG. 4 is a schematic diagram of the chip connection structure for realizing PCB link anti-crossing in the prior art
  • FIG. 5 is a schematic diagram of an optional process of sending data by a chip of a data processing method provided by an embodiment of the application;
  • FIG. 6 is a schematic diagram of an optional process for transmitting at least one second data to at least one first data transmission channel by a chip provided in an embodiment of the application;
  • FIG. 7 is a schematic diagram of an optional process for a chip in an embodiment of the application to send data of at least one first data transmission channel to a corresponding data transmission link;
  • FIG. 8 is a schematic diagram of an optional process of receiving data by a chip of a data processing method provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of an optional process for transmitting at least one third data to at least one second data transmission channel by a chip provided in an embodiment of the application;
  • FIG. 10 is a schematic diagram of an optional process of a data processing method provided by an embodiment of this application.
  • FIG. 11 is a schematic diagram 1 of an optional structure of a chip sending device of a data processing device according to an embodiment of the application;
  • FIG. 12 is a schematic diagram 1 of an optional structure of a chip receiving device of a data processing device according to an embodiment of the application;
  • FIG. 13 is a second schematic diagram of an optional structure of the chip sending device of the data processing device according to an embodiment of the application;
  • FIG. 14 is a second schematic diagram of an optional structure of the chip receiving device of the data processing device according to an embodiment of the application.
  • the current switching chip can provide 12.8 terabyte (Terabyte, T) input/output (In/Out, IO) switching bandwidth.
  • the switching chip that can provide 12.8T bandwidth includes 256 physical links that support 56 Gigabyte (G) switching bandwidth, and can support a maximum of 128 physical link ports of 100G switching bandwidth.
  • Figure 1 shows the schematic diagram 1 of the link connection of the Ethernet switch chip and the Quad Small Form-factor Pluggable (QSFP) optical module on the PCB.
  • QSFP Quad Small Form-factor Pluggable
  • the model of the QSFP is QSFP28, which includes 4 physical links supporting 25G switching bandwidth.
  • the QSFP28 optical module includes four physical medium dependent lanes (PMDL), which are PMDL0_TX to PMDL3_TX.
  • PMDL physical medium dependent lanes
  • the channel in the Ethernet switching chip is a channel (Port) supporting 100G switching bandwidth
  • the channel includes 4 links, which is equal to the number of channels of QSFP28.
  • the physical coding sublayer (PCS) of the channel that supports 100G bandwidth inside the switching chip supports link reorganization after link cross, and there will be no mismatch between the physical link and the physical link port ; That is, in the case that there is only one channel in the Ethernet switching chip, and the number of links contained in the channel is the same as the number of physical link ports of the device panel port, there will be no link crossover that causes the physical link and the physical link A situation where the link ports cannot correspond one-to-one.
  • Figure 2 shows the second schematic diagram of the link connection between the Ethernet switch chip and the QSFP optical module on the PCB.
  • the model of the QSFP is QSFP28, which includes 4 physical links supporting 25G switching bandwidth.
  • both Port0 and Port1 include two links.
  • the two links of Port0 are connected to the PMDL0_TX physical link port and PMDL1_TX physical link port on the device panel port; the two links of Port1 are connected to the PMDL2_TX physical link port on the device panel port And PMDL3_TX physical link port. If the PCB links are crossed, you need to ensure that the two links of Port0 are still connected to the PMDL0_TX physical link port and PMDL1_TX physical link port of the device panel port, and the two links of Port1 are still connected to the PMDL2_TX physical link of the device panel port Road port and PMDL3_TX physical link port.
  • Figure 3 shows a schematic diagram of the link connection between the Ethernet switch chip and the Ethernet interface chip on the backplane.
  • the channels in the Ethernet switching chip are two channels Port0 and Port1 that support 100G switching bandwidth, and each channel contains 4 links. If the 8 links of the Ethernet switch chip and the 8 links of the Ethernet interface chip are not connected in a one-to-one correspondence, but there are cross-connections, in order to avoid cross-connections, it is necessary to add an additional counter to the Ethernet switch chip. Cross logic.
  • Fig. 4 shows a schematic diagram of the chip connection structure for realizing PCB link anti-crossing in the prior art.
  • the channels in the Ethernet switching chip are two channels Port0 and Port1 that support 50G switching bandwidth, and each channel contains two links.
  • the link cross information on the PCB is: Physical Medium Attachment Lane (PMAL) of the Ethernet switch chip 0 connects to the PMDL2_TX physical link port of the QSFP28 optical module, PMAL1_TX connects to the PMDL0_TX physical link port of the QSFP28 optical module, PMAL2_TX Connect the PMDL1_TX physical link port of the QSFP28 optical module, and PMAL3_TX connect the PMDL3_TX physical link port of the QSFP28 optical module.
  • PMAL Physical Medium Attachment Lane
  • each 50G bandwidth inside the Ethernet switch chip is connected to the PMDL0_TX physical link port, PMDL1_TX physical link port, PMDL2_TX.
  • the physical link port and the PMDL3_TX physical link port need to be connected inside the Ethernet switch chip, between the gearbox (Gearbox) and the PMAL.
  • the PMAL clock domain in the sending direction adds data Choose logic.
  • the data selection logic not only selects the data, but also selects the clock of the PMAL link connected to the clock used by each Gearbox, thereby realizing an anti-crossing process.
  • the data selection logic is also more complicated; consequently, the data selection logic needs to make more data selections, and the cost is greatly increased; at the same time, , The data selection logic will also introduce more clocks, increasing the complexity of real-time clock tree analysis on the back-end of the Ethernet switching chip.
  • this application proposes a data processing method that can solve the technical problems and shortcomings that cannot be solved in the existing technical solutions.
  • FIG. 5 shows a schematic diagram of an optional process flow at the sending end of a data processing method provided by the present application, which will be described according to each step.
  • Step S101 receiving first data including at least one second data.
  • the chip receives first data including at least one second data.
  • the second data is data sent by a link included in the internal channel of the chip, and the first data is a set of all second data.
  • each first data transmission channel of the chip receives first data including at least one second data
  • the first data transmission channel is a channel for transmitting data in the chip.
  • the first data transmission channel corresponds to at least one data transmission link, and the number of the data transmission link is the total number of links included in all the internal channels of the chips that transmit the first data.
  • the numbers of data transmission links corresponding to the first data transmission channels included in the chip are all equal.
  • the first first data transmission channel corresponds to two data transmission links
  • the second first data transmission channel also corresponds to two data transmission links.
  • the first data is total data sent by all channels of the chip.
  • the first data is sent to all the first data transmission channels of the chip by broadcasting.
  • the first data further includes: channel information corresponding to a channel through which each data in the first data is sent; the channel information may be a channel identifier.
  • the second data carries the channel identifier of the channel through which the second data is sent.
  • the first data further includes: link information corresponding to a link that sends each data in the first data; the link information may be a link identifier.
  • the second data carries the link identifier of the link through which the second data is sent.
  • each 50G PCS channel sends M/2 data.
  • the first data is the total M data sent by the 2 50G PCS channels, and the sending station
  • the number of first data transmission channels of the chip is 4, and each first data transmission channel receives M pieces of data, and each of the M pieces of data corresponds to the identification of the channel for sending the data and/or Link ID.
  • the first data may also be data sent by all channels on the system side, and time division multiplexing (TDM) coded total data.
  • TDM time division multiplexing
  • the chip contains two 50G PCS channels, each 50G PCS channel sends M/2 data, and the two links corresponding to each 50G PCS channel send M/4 data.
  • the M/4 data sent by each link is TDM encoded to form the first data.
  • the second data refers to M/4 data sent by each link.
  • Step S102 Transmit the at least one second data to at least one first data transmission channel.
  • the chip transmitting the at least one second data to the at least one first data transmission channel includes step S201 to step S202.
  • FIG. 6 shows a schematic diagram of an optional process for the chip to transmit the at least one second data to the at least one first data transmission channel in an embodiment of the present application, which will be described according to each step.
  • Step S201 Configure the channel identifier of the at least one first data transmission channel according to the link cross information of the printed link board.
  • the link cross information of the printed circuit board includes: a correspondence between a data transmission link and a physical link port.
  • the link cross information of the printed circuit board is: PMAL0_TX of the Ethernet switch chip is connected to the PMDL2_TX physical link port of the QSFP28 optical module, PMAL1_TX is connected to the PMDL0_TX physical link port of the QSFP28 optical module, and PMAL2_TX is connected to QSFP28 The PMDL1_TX physical link port of the optical module, and PMAL3_TX connects to the PMDL3_TX physical link port of the QSFP28 optical module.
  • the chip configuring the channel identifier of the at least one first data transmission channel according to the link cross information of the printed link board includes: the chip configures the channel identifier of the at least one first data transmission channel according to the link cross information.
  • the first data transmission channel is configured with a corresponding channel identifier.
  • the first data transmission channel corresponds to at least one data transmission link, and the numbers of data transmission links corresponding to the first data transmission channel included in the chip are all equal.
  • the chip includes two first data transmission channels, the first data transmission channel corresponds to two data transmission links, and the second data transmission channel also corresponds to two data transmission links.
  • the channel identifiers of the first first data transmission channel to the fourth first data transmission channel in the configuration chip are 1, 0, 0, and 1 in order.
  • the chip configuring the channel identifier of the at least one first data transmission channel according to the link cross information of the printed circuit board includes: the link cross information on the printed circuit board is the mth In the case where two data transmission channels correspond to the n-th physical link port, the channel identifier of the m-th data transmission channel is configured to match the port identifier of the n-th physical link port, so that the m-th data transmission The data of the channel can be transmitted to the nth physical link port; wherein, the m and n are both positive integers.
  • the chip's internal channel 50G_0 PCS TX sends data to Gearbox0 TX and Gearbox1 TX through the PCSL0 link and PCSL1 link respectively;
  • channel 50G_1 PCS TX sends data to Gearbox2 TX and Gearbox3 TX through the PCSL0 link and PCSL1 link respectively
  • the channel ID of the channel 50G_0 PCS TX is 0, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the channel 50G_0 PCS TX is sent by the PCSL0 link.
  • the channel ID carried is 0 and the link ID is 0; the second data sent by the PCSL1 link of channel 50G_0 PCS TX, the channel ID carried is 0, and the link ID is 1.
  • the channel ID of the channel 50G_1 PCS TX is 1, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the second data sent by the PCSL0 link of the channel 50G_1 PCS TX ,
  • the carried channel ID is 1, and the link ID is 0; the second data sent by the PCSL1 link of channel 50G_1 PCS TX, the carried channel ID is 1, and the link ID is 1.
  • the second data sent by the PCSL0 link of the channel 50G_0 PCS TX carries the channel ID 0, the link ID 0, and is sent to the Gearbox 0 TX inside the chip, and then It is sent to PMAL0 TX via Gearbox0 TX, and then sent to the first physical link port PMDL0 TX of QSFP28 via PMAL0 TX.
  • the PMAL0 data will be sent to the third physical link port of the QSFP28 through the printed circuit board, that is, PMDL2 TX.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: in the case that there is no link cross on the printed circuit board of the chip, the third part of the QSFP28 Two physical link ports PMDL2 TX receive the data of PMAL2, that is, the data with the channel ID of 1 and the link ID of 0. In order to realize the anti-crossing of the link, set the channel ID 1 and link ID 0 for the physical link corresponding to the PMAL0. , To ensure that the third physical link port PMDL2 TX of the QSFP28 receives data with a channel ID of 1 and a link ID of 0.
  • Step S202 Transmit the second data to the first data transmission channel matching the channel identifier of the second data.
  • the chip transmitting the second data to the first data transmission channel matching the channel identifier of the second data includes: transmitting the channel identifier corresponding to the second data to the first data transmission channel. When the channel identifiers of the channels match, the chip transmits the second data to the first data transmission channel.
  • the channel identifier corresponding to the second data matches the channel identifier of the first data transmission channel, which means that the channel identifier corresponding to the second data is equal to the channel identifier of the first data transmission channel.
  • the channel ID corresponding to the second data is 1, and the channel ID of the first data transmission channel is also 1. It is considered that the channel ID corresponding to the second data matches the channel ID of the first data transmission channel, and the chip identifies the channel as The second data of 1 is transmitted to the first data transmission channel with the channel ID of 1; if the channel ID corresponding to the second data is 1, and the channel ID of the first data transmission channel is 0, the channel ID corresponding to the second data is considered to be the same as that of the first data transmission channel. If the channel identifier of the first data transmission channel does not match, the chip will not transmit the second data with the channel identifier 1 to the first data transmission channel with the channel identifier 0.
  • the chip transmits the second data to the first data transmission channel matching the channel identifier of the second data according to the channel identifier corresponding to the second data.
  • the channel identifiers of the first first data transmission channel to the fourth first data transmission channel in the configuration chip are 1, 0, 0, 1 in order.
  • the chip transmits the second data whose channel ID is 0 to the second first data transmission channel and the third first data transmission channel; the chip will receive the first data, the channel ID The second data that is 1 is transmitted to the first first data transmission channel and the fourth first data transmission channel.
  • the sending end of the switching chip has only one first data transmission channel, and the chip transmits all the first data to the first data transmission channel.
  • Step S103 Send the data of the at least one first data transmission channel to the corresponding data transmission link according to the link cross information of the printed circuit board.
  • the chip sending the data of the at least one first data transmission channel to the corresponding data transmission link according to the link cross information of the printed circuit board includes step S301 to step S302.
  • FIG. 7 shows a schematic diagram of an optional process for the chip in an embodiment of the present application to send data of the at least one first data transmission channel to a corresponding data transmission link, which will be described according to each step.
  • Step S301 Configure the link identifier of the at least one data transmission link according to the link cross information of the printed link board.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed link board includes: the chip configures the link identifier for each data transmission link according to the link cross information The link identifier corresponding to the transmission link configuration.
  • the link cross information of the printed circuit board includes: the corresponding relationship between the data transmission link and the physical link port.
  • the link cross information of the printed circuit board is: PMAL0_TX of the Ethernet switch chip is connected to the PMDL2_TX physical link port of the QSFP28 optical module, PMAL1_TX is connected to the PMDL0_TX physical link port of the QSFP28 optical module, and PMAL2_TX is connected to QSFP28 The PMDL1_TX physical link port of the optical module, and PMAL3_TX connects to the PMDL3_TX physical link port of the QSFP28 optical module.
  • PMAL0_TX receives the data sent by the data transmission link with the channel ID of 1 and the link ID of 0;
  • PMAL1_TX receives the data sent by the data transmission link with the channel ID of 0 and the link ID of 0;
  • PMAL2_TX receives the channel ID 0, the data sent by the data transmission link with the link ID of 1;
  • PMAL0_TX receives the data sent by the data transmission link with the channel ID of 1, and the link ID of 1; according to the link cross information of the printed circuit board,
  • the link identifiers of the first data transmission link to the fourth data transmission link in the configuration chip are 0, 0, 1, 1 in order.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: the link cross information on the printed circuit board is the mth data When the transmission link corresponds to the n-th physical link port, the link identifier of the m-th data transmission link is configured to match the port identifier of the n-th physical link port, so that the m-th data The data of the transmission link can be transmitted to the nth link port; wherein, the m and n are both positive integers.
  • the chip's internal channel 50G_0 PCS TX sends data to Gearbox0 TX and Gearbox1 TX through the PCSL0 link and PCSL1 link respectively;
  • channel 50G_1 PCS TX sends data to Gearbox2 TX and Gearbox3 TX through the PCSL0 link and PCSL1 link respectively
  • the channel ID of the channel 50G_0 PCS TX is 0, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the channel 50G_0 PCS TX is sent by the PCSL0 link.
  • Second data the channel ID carried is 0, and the link ID is 0; the second data sent by the PCSL1 link of the channel 50G_0 PCS TX, the channel ID carried is 0, and the link ID is 1.
  • the channel ID of the channel 50G_1 PCS TX is 1, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the second data sent by the PCSL0 link of the channel 50G_1 PCS TX ,
  • the carried channel ID is 1, and the link ID is 0; the second data sent by the PCSL1 link of channel 50G_1 PCS TX, the carried channel ID is 1, and the link ID is 1.
  • the second data sent by the PCSL0 link of the channel 50G_0 PCS TX carries the channel ID 0, the link ID 0, and is sent to the Gearbox 0 TX inside the chip, and then It is sent to PMAL0 TX via Gearbox0 TX, and then sent to the first physical link port PMDL0 TX of QSFP28 via PMAL0 TX.
  • the PMAL0 data will be sent to the third physical link port of the QSFP28 through the printed circuit board, that is, PMDL2 TX.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: in the case that there is no link cross on the printed circuit board of the chip, the third part of the QSFP28 Two physical link ports PMDL2 TX receive the data of PMAL2, that is, the data with the channel ID of 1 and the link ID of 0. In order to realize the anti-crossing of the link, set the channel ID 1 and link ID 0 for the physical link corresponding to the PMAL0. , To ensure that the third physical link port PMDL2 TX of the QSFP28 receives data with a channel ID of 1 and a link ID of 0.
  • Step S302 Send the data of the at least one first data transmission channel to the corresponding data transmission link.
  • the chip sending the data of the at least one first data transmission channel to the corresponding data transmission link includes: the chip sending the data of the first data transmission channel to the link with the data Identifies the same data transmission link.
  • the chip sends the second data to the first data transmission channel matching the link identifier of the second data according to the link identifier corresponding to the second data.
  • the second data includes at least one piece of fourth data, and the channel identifiers of the fourth data are the same, but the link identifiers are different.
  • the chip sends the fourth data to the data transmission link matching the link identifier of the fourth data according to the link identifier of the fourth data.
  • the first data transmission channel corresponds to two data transmission links.
  • the first to N/2th data are data with a link identifier of 0; /2+1 to Nth data are data with a link ID of 1.
  • the chip sends the 1st to N/2th data to the link ID according to the link ID of the N data.
  • the data transmission link of 0 sends the N/2+1 to the Nth data to the data transmission link with the link identifier 1.
  • the first data transmission channel corresponds to two data transmission links, and among the N data received by the first data transmission channel, data with an odd number is data with a link identifier of 0; data with an even number is a link According to the link ID of the N data, the chip sends the data with the odd number to the data transmission link with the link ID of 0, and sends the data with the even number to the link.
  • the chip can configure the channel identifier of the first data transmission channel according to the link cross information of the printed circuit board, and/or the chip can configure the channel identifier of the first data transmission channel according to the link cross information of the printed circuit board.
  • the chip sends data according to the channel identification and link identification, so that reverse printing is realized when sending data The effect of circuit board link crossover.
  • the embodiment of the present application does not use a logical link, and thus does not introduce redundant clocks, and further does not increase the burden of selecting the clock tree at the back end of the chip.
  • the embodiment of the present application can configure the channel identification of the first data transmission channel in the chip and/or the link identification of the data transmission link in the chip according to the actual situation to realize multiple channels and Anti-printed circuit board link crossover in multiple link scenarios, with strong scalability.
  • FIG. 8 shows a schematic diagram of an optional process at the sending end of a data processing method provided by the present application, which will be described according to each step.
  • Step S401 receiving at least one third data based on at least one port.
  • the chip is based on at least one port of at least one third data; further, each data transmission channel of the chip receives one third data.
  • the third data carries the channel identifier of the channel through which the third data is sent, and/or the third data carries the link identifier of the link through which the sending end sends the third data.
  • the third data is data sent by the data transmission link of the chip.
  • Step S402 Send the at least one piece of third data to the corresponding data reassembly link according to the channel identifier and link identifier of the third data.
  • the chip sending the at least one third data to the corresponding data reassembly link according to the channel identifier and the link identifier of the third data includes step S501 to step S502.
  • FIG. 9 shows a schematic diagram of an optional process for the chip in an embodiment of the present application to send the at least one third data to the corresponding data reassembly link according to the channel identifier and the link identifier of the third data, including step S501 To step S502, description will be made according to each step.
  • Step S501 Configure a channel identifier of at least one second data transmission channel that receives the at least one third data according to the channel identifier of the third data.
  • the third data carries a channel identifier and a link identifier for transmitting the third data.
  • the configuring the channel identifier of the at least one second data transmission channel for receiving the at least one third data according to the channel identifier of the third data includes: configuring the channel identifier of the second data transmission channel as the second The channel identifier of the third data received by the data transmission channel.
  • PMAL1_RX and PMAL2_RX receive data with channel identification 0;
  • PMAL0_RX and PMAL3_RX receive data with channel identification 1.
  • the channel identifiers of the first second data transmission channel to the fourth second data transmission channel in the configuration chip are 1, 0, 0, and 1 in order.
  • Step S502 According to the channel identifier carried in the request information sent by the data reorganization link, the data of at least one second data transmission channel that matches the channel identifier of the request information is sent to the data reorganization link that sent the request information .
  • the request information is sent by a data reassembly link and used to request third data that matches the channel identifier of the request information.
  • the chip receives the request information, and according to the channel identifier of the request information, sends the data of at least one second data transmission channel that matches the channel identifier of the request information to the data sending the request information Reorganize the link.
  • the channel identification matching means that the channel identification of the requested information is equal to the channel identification of the second data transmission channel.
  • the channel ID of the request information received by the chip is 0, and the channel IDs of the first to fourth second data transmission channels included in the chip are 1, 0, 0, 1 in order; according to the channel of the request information
  • the chip sends the data of the second transmission channel with the channel ID of 0 to the data reorganization link that sends the request information; for the data of the second transmission channel with the channel ID of 1, the chip does not do any processing for the time being.
  • the chip sends the data of the second transmission channel with the channel identifier 1 to the data reassembly link that sent the request information according to the channel identifier of the request information.
  • the data reorganization link is used to reorganize the third data with the same channel identifier.
  • the data reassembly link sends request information to the chip, and the channel ID of the request information is 0, and the chip sends the received data with the channel ID 0 to the chip.
  • Data reassembly link that is, the chip sends the data in the second second data transmission channel and the third second data transmission channel to the data reassembly link.
  • the third data is M/4 data
  • the data reorganization link receives M/2 data with a channel identifier of 0, and reorganizes the data with the M/2 channel identifier as 0 .
  • the data reassembly link reorganizes the third data according to the link identification of the data.
  • the data reorganization link receives M/2 data with a channel identifier of 0, it sorts the M/2 data in the order of the link, and reorganizes the M/2 data.
  • the data reassembly link receives M/2 data with a channel identifier of 0, and the M/2 data includes M/4 data with a link identifier of 0 and M/4 data with a link identifier of 1. Data, sort the M/2 data according to the link identifier, and recombine the M/2 data.
  • the method further includes: performing TDM decoding on the data reorganized by the data reorganization link according to the channel identifier.
  • the method further includes: when the number of second data transmission channels corresponding to the same channel identifier of the chip is greater than the maximum value of the link identifier carried in the third data currently received, the chip According to the channel identification of the requested information, all data matching the channel identification in the third data are sent to the data reassembly link. In the case that the chip receives the request information of the channel identification again, the chip matches all the channel identification data in the third data, and the link number is greater than the maximum value of the link identification carried in the third data last time The data is sent to the data reassembly link.
  • the number of second data transmission channels whose channel identifier is 0 is Y, and among the data whose channel identifier is 0 carried in the third data currently received by the chip, the maximum value of the link identifier is X, and the Y>X.
  • the data reassembly link sends request information to the chip, requesting data with a channel identifier of 0, and the chip sends the X pieces of data to the data reassembly link.
  • the chip sends the data with a link ID greater than X to the data reorganization link; until the data reorganization link receives a link ID of Y data.
  • the chip can still send all the data of the corresponding channel identifier to the data reassembly link according to the multiple request information, so that the data reassembly link can The data is reorganized.
  • the chip can configure the channel identifier of the second data transmission channel according to the link cross information of the printed circuit board.
  • the chip realizes the effect of anti-printed circuit board link crossing by receiving data according to the channel identifier.
  • the embodiment of the present application does not use a logical link, and thus does not introduce redundant clocks, and further does not increase the burden of selecting the clock tree at the back end of the chip.
  • the embodiment of the present application can configure the channel identification of the second data transmission channel inside the chip according to the actual situation, so as to realize the anti-printed circuit board link crossover of multiple channels and multiple links. , Strong scalability.
  • FIG. 10 shows an optional flowchart of a data processing method provided by the present application, which will be described according to each step.
  • Step S601 Receive first data including at least one second data.
  • the chip receives first data including at least one second data.
  • the second data is data sent by a link included in the internal channel of the chip, and the first data is a set of all second data.
  • each first data transmission channel of the chip receives first data including at least one second data
  • the first data transmission channel is a channel for transmitting data in the chip.
  • the first data transmission channel corresponds to at least one data transmission link, and the number of the data transmission link is the total number of links included in all the internal channels of the chips that transmit the first data.
  • the numbers of data transmission links corresponding to the first data transmission channels included in the chip are all equal.
  • the first first data transmission channel corresponds to two data transmission links
  • the second first data transmission channel also corresponds to two data transmission links.
  • the first data is total data sent by all channels of the chip.
  • the first data is sent to all the first data transmission channels of the chip by broadcasting.
  • the first data further includes: channel information corresponding to a channel through which each data in the first data is sent; the channel information may be a channel identifier.
  • the second data carries the channel identifier of the channel through which the second data is sent.
  • the first data further includes: link information corresponding to a link that sends each data in the first data; the link information may be a link identifier.
  • the second data carries the link identifier of the link through which the second data is sent.
  • Step S602 Configure the channel identifier of the at least one first data transmission channel according to the link cross information of the printed link board.
  • the link cross information of the printed circuit board includes: a correspondence between a data transmission link and a physical link port.
  • the chip configuring the channel identifier of the at least one first data transmission channel according to the link cross information of the printed link board includes: the chip configures the channel identifier of the at least one first data transmission channel according to the link cross information.
  • the first data transmission channel is configured with a corresponding channel identifier.
  • the first data transmission channel corresponds to at least one data transmission link, and in the chip, the data transmission links corresponding to each first data transmission channel are equal.
  • configuring the channel identifier of the at least one first data transmission channel by the chip according to the link cross information of the printed circuit board includes: corresponding to the nth physical link on the mth data transmission link In the case of a port, the link identifier of the m-th data transmission link is configured as the link identifier of the n-th data transmission link; wherein, both m and n are positive integers.
  • the PCB link crossover includes: the data transmission link of the chip does not correspond to the physical link ports of other modules than the chip one-to-one.
  • the PMAL0_TX of the Ethernet switch chip is connected to the PMDL2_TX physical link port of the QSFP28 optical module
  • PMAL1_TX is connected to the PMDL0_TX physical link port of the QSFP28 optical module
  • PMAL2_TX is connected to the PMDL1_TX physical link port of the QSFP28 optical module
  • PMAL3_TX is connected to the QSFP28
  • the PMDL3_TX physical link port of the optical module, the data transmission link of the Ethernet switching chip and the furnace link port of the QSFP optical module do not correspond one-to-one, and it is considered that there is a PCB link cross.
  • Step S603 Transmit the second data to the first data transmission channel matching the channel identifier of the second data.
  • the chip transmitting the second data to the first data transmission channel matching the channel identifier of the second data includes: transmitting the channel identifier corresponding to the second data to the first data transmission channel. When the channel identifiers of the channels match, the chip transmits the second data to the first data transmission channel.
  • the chip transmits the second data to the first data transmission channel matching the channel identifier of the second data according to the channel identifier corresponding to the second data.
  • the channel identifiers of the first data transmission channel to the fourth data transmission channel in the chip are 1, 0, 0, 1 in order.
  • the chip transmits the second data whose channel ID is 0 to the second first data transmission channel and the third first data transmission channel; the chip will receive the first data, the channel ID The second data that is 1 is transmitted to the first first data transmission channel and the fourth first data transmission channel.
  • the sending end of the switching chip has only one first data transmission channel, and the chip transmits all the first data to the first data transmission channel.
  • Step S604 Configure the link identifier of the at least one data transmission link according to the link cross information of the printed link board.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed link board includes: the chip configures the link identifier for each data transmission link according to the link cross information The link identifier corresponding to the transmission link configuration.
  • the link cross information of the printed circuit board includes: a correspondence between a data transmission link and a physical link port.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: the link cross information on the printed circuit board is the mth data When the transmission link corresponds to the n-th physical link port, the link identifier of the m-th data transmission link is configured to match the port identifier of the n-th physical link port, so that the m-th data The data of the transmission link can be transmitted to the nth link port; wherein, the m and n are both positive integers.
  • the chip's internal channel 50G_0 PCS TX sends data to Gearbox0 TX and Gearbox1 TX through the PCSL0 link and PCSL1 link respectively;
  • channel 50G_1 PCS TX sends data to Gearbox2 TX and Gearbox3 TX through the PCSL0 link and PCSL1 link respectively
  • the channel ID of the channel 50G_0 PCS TX is 0, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the channel 50G_0 PCS TX is sent by the PCSL0 link.
  • the channel ID carried is 0 and the link ID is 0; the second data sent by the PCSL1 link of channel 50G_0 PCS TX, the channel ID carried is 0, and the link ID is 1.
  • the channel ID of the channel 50G_1 PCS TX is 1, the link ID of the corresponding PCSL0 link is 0, and the link ID of the corresponding PCSL1 link is 1; that is, the second data sent by the PCSL0 link of the channel 50G_1 PCS TX ,
  • the carried channel ID is 1, and the link ID is 0; the second data sent by the PCSL1 link of channel 50G_1 PCS TX, the carried channel ID is 1, and the link ID is 1.
  • the second data sent by the PCSL0 link of the channel 50G_0 PCS TX carries the channel ID 0, the link ID 0, and is sent to the Gearbox 0 TX inside the chip, and then It is sent to PMAL0 TX via Gearbox0 TX, and then sent to the first physical link port PMDL0 TX of QSFP28 via PMAL0 TX.
  • the PMAL0 data will be sent to the third physical link port of the QSFP28 through the printed circuit board, that is, PMDL2 TX.
  • the chip configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: in the case that there is no link cross on the printed circuit board of the chip, the third part of the QSFP28 Two physical link ports PMDL2 TX receive the data of PMAL2, that is, the data with the channel ID of 1 and the link ID of 0. In order to realize the anti-crossing of the link, set the channel ID 1 and link ID 0 for the physical link corresponding to the PMAL0. , To ensure that the third physical link port PMDL2 TX of the QSFP28 receives data with a channel ID of 1 and a link ID of 0.
  • Step S605 Transmit the at least one second data to at least one first data transmission channel.
  • the chip transmitting the second data to the first data transmission channel matching the channel identifier of the second data includes: transmitting the channel identifier corresponding to the second data to the first data transmission channel. When the channel identifiers of the channels match, the chip transmits the second data to the first data transmission channel.
  • the chip transmits the second data to the first data transmission channel matching the channel identifier of the second data according to the channel identifier corresponding to the second data.
  • the switching chip transmits all the first data to the first data transmission channel.
  • Step S606 Send the data of the at least one first data transmission channel to the corresponding data transmission link.
  • the chip sending the data of the at least one first data transmission channel to the corresponding data transmission link includes: the chip sending the data of the first data transmission channel to the link with the data Identifies the same data transmission link.
  • the chip sends the second data to the first data transmission channel matching the link identifier of the second data according to the link identifier corresponding to the second data.
  • the second data includes at least one piece of fourth data, and the channel identifiers of the fourth data are the same, but the link identifiers are different.
  • the chip sends the fourth data to the data transmission link matching the link identifier of the fourth data according to the link identifier of the fourth data.
  • Step S607 Receive at least one third data based on at least one port.
  • the chip receives at least one third data based on at least one port; further, each data transmission channel of the chip receives one third data.
  • the third data carries the channel identifier of the channel through which the third data is sent, and/or the third data carries the link identifier of the link through which the sending end sends the third data.
  • the third data is data sent by the data transmission link of the chip.
  • Step S608 according to the channel identifier of the third data, configure the channel identifier of the at least one second data transmission channel that receives the at least one third data.
  • the third data carries a channel identifier and a link identifier for transmitting the third data.
  • the configuring the channel identifier of the at least one second data transmission channel for receiving the at least one third data according to the channel identifier of the third data includes: configuring the channel identifier of the second data transmission channel as the second The channel identifier of the third data received by the data transmission channel.
  • PMAL1_RX and PMAL2_RX receive data with channel identification 0;
  • PMAL0_RX and PMAL3_RX receive data with channel identification 1.
  • the channel identifiers of the first second data transmission channel to the fourth second data transmission channel in the configuration chip are 1, 0, 0, and 1 in order.
  • Step S609 According to the channel identifier carried in the request information sent by the data reorganization link, the data of at least one second data transmission channel that matches the channel identifier of the request information is sent to the data reorganization link that sent the request information .
  • the request information is sent by a data reassembly link and used to request third data that matches the channel identifier of the request information.
  • the chip receives the request information, and according to the channel identifier of the request information, sends the data of at least one second data transmission channel that matches the channel identifier of the request information to the data sending the request information Reorganize the link.
  • the channel identification matching means that the channel identification of the requested information is equal to the channel identification of the second data transmission channel.
  • the channel ID of the request information received by the chip is 0, and the channel IDs of the first to fourth second data transmission channels included in the chip are 1, 0, 0, 1 in order; according to the channel of the request information
  • the chip sends the data of the second transmission channel with the channel ID of 0 to the data reorganization link that sends the request information; for the data of the second transmission channel with the channel ID of 1, the chip does not do any processing for the time being.
  • the chip sends the data of the second transmission channel with the channel identifier 1 to the data reassembly link that sent the request information according to the channel identifier of the request information.
  • the data reorganization link is used to reorganize the third data with the same channel identifier.
  • the data reassembly link sends request information to the chip, and the channel ID of the request information is 0, and the chip sends the received data with the channel ID 0 to the chip.
  • Data reassembly link that is, the chip sends the data in the second second data transmission channel and the third second data transmission channel to the data reassembly link.
  • the third data is M/4 data
  • the data reorganization link receives M/2 data with a channel identifier of 0, and reorganizes the data with the M/2 channel identifier as 0 .
  • the data reassembly link reorganizes the third data according to the link identification of the data.
  • the data reorganization link receives M/2 data with a channel identifier of 0, it sorts the M/2 data in the order of the link, and reorganizes the M/2 data.
  • the data reassembly link receives M/2 data with a channel identifier of 0, and the M/2 data includes M/4 data with a link identifier of 0 and M/4 data with a link identifier of 1. Data, sort the M/2 data according to the link identifier, and recombine the M/2 data.
  • the method further includes: performing TDM decoding on the data reorganized by the data reorganization link according to the channel identifier.
  • the method further includes: when the number of second data transmission channels corresponding to the same channel identifier of the chip is greater than the maximum value of the link identifier carried in the third data currently received, the chip According to the channel identification of the requested information, all data matching the channel identification in the third data are sent to the data reassembly link. In the case that the chip receives the request information of the channel identification again, the chip matches all the channel identification data in the third data, and the link number is greater than the maximum value of the link identification carried in the third data last time The data is sent to the data reassembly link.
  • the chip can configure the channel identifiers of the first data transmission channel and the second data transmission channel according to the link cross information of the printed circuit board, and/or the chip can be based on the printed circuit board
  • the link cross information configures the link identifier of the data transmission link.
  • the embodiment of the present application does not use a logical link, and thus does not introduce redundant clocks, and further does not increase the burden of selecting the clock tree at the back end of the chip.
  • the embodiment of the present application can configure the channel identifier of the first data transmission channel and the channel identifier of the second data transmission channel, and/or the internal data of the chip according to actual conditions
  • the link identification of the transmission link realizes the anti-printed circuit board link crossover of multiple channels and multiple link scenarios, and has strong scalability.
  • FIG. 11 shows a schematic diagram 1 of an optional structure of the sending end of a data processing device provided by the present application, which will be described according to each unit.
  • the chip 700 is configured to configure the channel identifier of the at least one first data transmission channel according to the link cross information of the printed circuit board; and/or configure the at least one data transmission link according to the link cross information of the printed circuit board The link ID.
  • the chip 700 configuring the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board includes: the link cross information of the printed circuit board is the mth In the case of a data transmission link corresponding to the n-th physical link port, the link identifier of the m-th data transmission link is configured to match the port identifier of the n-th physical link port, so that the m-th physical link port The data of each data transmission link can be transmitted to the nth link port; wherein, the m and n are both positive integers.
  • the TDM encoding unit 701 is configured to perform TDM encoding on data sent from all links in all channels of the chip, and send it to all data gating units 702 of the chip 700 in a broadcast manner.
  • the data gating unit 702 is configured to receive first data containing at least one second data obtained after performing TDM encoding on data sent from all links in all channels of the chip, and to transmit the at least one second data to the at least one first data.
  • the data gating unit 702 transmits the second data to the first data transmission channel matching the channel identifier of the second data.
  • the data distribution unit 703 is configured to send the data of the at least one first data transmission channel to the corresponding data transmission link according to the link cross information of the printed circuit board.
  • the data distribution unit sends the second data to a data transmission link matching the link identifier of the second data.
  • the shift unit 704 is configured to shift the data sent by the data distribution unit 703.
  • FIG. 12 shows a schematic diagram 1 of an optional structure of the receiving end of a data processing device provided by the present application, which will be described according to each unit.
  • the chip 800 is configured to configure the channel identification of at least one second data transmission channel that receives the at least one third data according to the channel identification of the third data.
  • the second receiving unit 804 is configured to respectively receive at least one piece of third data based on at least one port.
  • the data buffer unit 803 is configured to send the at least one piece of third data to the corresponding data reassembly link according to the channel identifier and the link identifier of the third data.
  • the TDM scheduling reorganization unit 802 is configured to send request information to the data buffer unit, where the request information carries a channel identifier.
  • the TDM scheduling reorganization unit 802 sends the request information to the data buffer unit in the order of channel identification.
  • the data buffer unit 803 is further configured to send data of at least one second data transmission channel matching the channel identifier of the request information to the TDM scheduler that issued the request information.
  • the TDM scheduling reorganization unit 802 is further configured to reorganize the third data according to the link identifier of the data.
  • the TDM decoding unit 801 is configured to perform TDM decoding on the third data reorganized by the TDM scheduling reorganization unit 802.
  • FIG. 13 shows a second schematic diagram of an optional structure of the sending end of a data processing device provided by the present application, which will be described according to each unit.
  • the first receiving unit 901 is configured to receive first data including at least one second data
  • the data gating unit 902 is configured to transmit the at least one second data to at least one first data transmission channel;
  • the data distribution unit 903 is configured to send the data of the at least one first data transmission channel to the corresponding data transmission link according to the link cross information of the printed circuit board.
  • the configuration unit 904 is configured to configure the channel identifier of the at least one first data transmission channel according to the link cross information of the printed circuit board.
  • the data gating unit 902 is further configured to transmit the second data to the first data transmission channel matching the channel identifier of the second data.
  • the configuration unit 904 is further configured to configure the link identifier of the at least one data transmission link according to the link cross information of the printed circuit board.
  • the method includes: when the m-th data transmission link corresponds to the n-th physical link port, configuring the link identifier of the m-th data transmission link as the link identifier of the n-th data transmission link; Wherein, the m and n are both positive integers.
  • the data distribution unit 903 is further configured to send the second data to a data transmission link matching the link identifier of the second data.
  • FIG. 14 shows the second schematic diagram of an optional structure of the receiving end of a data processing device provided by the present application, which will be described according to each unit.
  • the second receiving unit 1001 is configured to respectively receive at least one piece of third data based on at least one port.
  • the data buffer unit 1002 is configured to send the at least one third data to the corresponding data reassembly link according to the channel identifier of the request information.
  • the configuration unit 1003 is configured to configure, according to the channel identifier of the third data, the channel identifier of the at least one data buffer unit that receives the at least one third data according to the channel identifier of the third data.
  • the data buffer unit 1002 is further configured to send data of at least one data buffer unit that matches the channel identifier of the request information to the data reassembly link that sends the request information.
  • the foregoing program can be stored in a storage medium.
  • the program is executed, it is executed in the first application.
  • the first area on the screen of the electronic device responds to the notification message; wherein, the first area is smaller than the input method application loaded when the second application is run alone. Describe the corresponding area on the screen of the electronic device.
  • the aforementioned storage media include: removable storage devices, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disks or optical disks and other media that can store program codes.
  • the aforementioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium.
  • the computer software product is stored in a storage medium and includes several commands for A computer device (which may be a personal computer, a server, or a network device, etc.) executes all or part of the methods described in the various embodiments of the present invention.
  • the aforementioned storage media include: removable storage devices, ROM, RAM, magnetic disks, or optical disks and other media that can store program codes.

Abstract

一种数据处理方法、数据处理的装置及存储介质，其中，所述数据处理方法包括：接收包含至少一个第二数据的第一数据（S101）；将所述至少一个第二数据传输至至少一个第一数据传输通道（S102）；根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路（S103）；基于至少一个端口分别接收至少一个第三数据（S401）；根据请求信息的通道标识，将所述至少一个第三数据发送至对应的数据重组链路（S402）。所述数据处理方法使得在芯片的印刷电路板存在链路交叉的情况下，保证物理链路端口与数据传输链路一一对应。

Description

一种数据处理方法、装置及存储介质 技术领域
本发明涉及电子技术领域，尤其涉及一种数据处理方法、装置及存储介质。
背景技术
物理链路在芯片的印刷电路板(Printed Circuit Board ，PCB)上存在链路交叉的情况。因此。如何在交换芯片内部实现每个物理链路端口和数据传输链路之间的反交叉，保证物理链路端口与数据传输链路之间能够一一对应是需要解决的技术问题。
发明内容
本申请实施例提供一种数据处理方法、装置及存储介质，使得在芯片的印刷电路板上存在链路交叉的情况下，保证物理链路端口与芯片的数据传输链路之间仍然是一一对应的。
第一方面，本申请实施例提供一种数据处理方法，所述方法包括：
接收包含至少一个第二数据的第一数据；
将所述至少一个第二数据传输至至少一个第一数据传输通道；
根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
上述方案中，所述印刷电路板的链路交叉信息包括：
所述数据传输链路与物理链路端口的对应关系。
上述方案中，所述方法还包括：
根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输 通道的通道标识。
上述方案中，所述将所述至少一个第二数据传输至至少一个第一数据传输通道包括：
将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
上述方案中，所述方法还包括：
根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
上述方案中，所述根据所述印刷电路板的链路交叉信息，配置所述至少一个数据传输链路的链路标识包括：
在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个物理链路端口；
其中，所述m、n均为正整数。
上述方案中，所述将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路，包括：
将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
第二方面，本申请实施例提供一种数据处理方法，所述方法包括：
基于至少一个端口接收至少一个第三数据；
根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
上述方案中，所述方法还包括：
根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至 少一个第二数据传输通道的通道标识。
上述方案中，所述根据第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路包括：
根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
第三方面，本申请实施例提供一种数据处理装置，所述装置包括：
第一接收单元，配置为接收包含至少一个第二数据的第一数据；
数据选通单元，配置为将所述至少一个第二数据传输至至少一个第一数据传输通道；
数据分发单元，配置为根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
上述方案中，所述装置还包括：
配置单元，配置为根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
上述方案中，所述数据选通单元还配置为：
将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
上述方案中，所述配置单元还配置为：
根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
上述方案中，所述配置单元，配置为在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个链路端口；
其中，所述m、n均为正整数。
上述方案中，所述数据分发单元，配置为将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
第四方面，本申请实施例提供一种数据处理方法，所述装置包括：
第二接收单元，配置为基于至少一个端口分别接收至少一个第三数据；
数据缓存单元，配置为根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
上述方案中，所述装置还包括：配置单元，配置为根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识；
所述数据缓存单元，还配置为将所述第三数据传输至与所述第三数据的通道标识匹配的第二数据传输通道。
上述方案中，所述数据缓存单元，还配置为根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路；
所述装置还包括：数据重组单元，配置为向数据缓存单元发送所述请求信息；配置为根据至少一个第三数据的链路标识，重组所述至少一个第三数据。
本申请实施例还提供一种数据处理的装置，包括存储器、处理器及存储在存储器上并能够由所述处理器运行的可执行程序，所述处理器运行所述可执行程序时实现所述数据处理的方法的步骤。
本申请实施例提供一种数据处理的方法、装置及存储介质，通过接收包含至少一个第二数据的第一数据；将所述至少一个第二数据传输至至少一个第一数据传输通道；根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。使得在芯片的物 理链路在芯片的印刷电路板上存在链路交叉的情况下，芯片向印刷电路板上其他模块的物理链路端口传输数据时，仍然能够保证芯片内部的数据传输链路与印刷电路板上其他模块的物理链路端口一一对应。通过接收至少一个第三数据；根据请求信息的通道标识，将所述至少一条第二数据传输通道的数据发送至对应的数据重组链路。使得在芯片的物理链路在芯片的印刷电路板上存在链路交叉的情况下，芯片接收所述印刷电路板上其他模块的数据时，仍然能够保证芯片内部的数据传输链路与印刷电路板上其他模块的物理链路端口一一对应。本申请实施例提供的数据处理方法，扩展性高，在存在多个数据传输通道以及多个数据传输链路的芯片中同样适用；并且，本申请实施例提供的数据处理方法，没有引入数据逻辑链路，进而不会增加芯片数据选择模块的负担，也不会因为数据逻辑链路的时钟，增加芯片后端实时时钟树分析的复杂度。
附图说明
图1为以太网交换芯片和QSFP光模块在PCB上链路连接示意图一；
图2为以太网交换芯片和QSFP光模块在PCB上链路连接示意图二；
图3为以太网交换芯片和以太网接口芯片在背板上链路连接示意图；
图4为现有技术中实现PCB链路反交叉的芯片连接结构示意图；
图5为本申请实施例提供的数据处理方法的芯片发送数据的可选流程示意图；
图6为本申请实施例提供的芯片将至少一个第二数据传输至至少一个第一数据传输通道的可选流程示意图；
图7为本申请实施例中芯片将至少一条第一数据传输通道的数据发送至对应的数据传输链路的可选流程示意图；
图8为本申请实施例提供的数据处理方法的芯片接收数据的可选流程示意图；
图9为本申请实施例提供的芯片将至少一个第三数据传输至至少一条第二数据传输通道的可选流程示意图；
图10为本申请实施例提供的数据处理方法的可选流程示意图；
图11为本申请实施例提供的数据处理装置的芯片发送装置的可选结构示意图一；
图12为本申请实施例提供的数据处理装置的芯片接收装置的可选结构示意图一；
图13为本申请实施例提供的数据处理装置的芯片发送装置的可选结构示意图二；
图14为本申请实施例提供的数据处理装置的芯片接收装置的可选结构示意图二。
具体实施方式
以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
随着互联网对带宽的需求越来越高，交换芯片支持的带宽也随之增加。目前交换芯片可以提供12.8太字节(Terabyte，T)的输入/输出(In/Out，IO)交换带宽。所述可以提供12.8T带宽的交换芯片包括256根支持56吉字节(Gigabyte，G)交换带宽的物理链路，最大可以支持128个100G交换带宽的物理链路端口。
在实施过程中，无论盒式设备应用还是机架式设备应用，随着物理链路的增加，均可能出现交叉走线的情况，进而引起物理链路串扰，无法保证物理链路与物理链路端口一一对应。
相关技术中，一般采用在交换芯片内部，根据PCB交叉情况，增加逻辑链路，但随着数据传输链路数目增加，上述方案的扩展性不高，无法灵活支持随着数据传输链路增加带来的PCB交叉；同时，逻辑链路会导致芯 片内部时钟单元增加，进而导致芯片后端实时时钟树分析的复杂度。
图1示出了以太网交换芯片和四通道小尺寸可插拔(Quad Small Form-factor Pluggable，QSFP)光模块在PCB上链路连接示意图一。
在一些可选实施例中，所述QSFP的型号为QSFP28，包括4根支持25G交换带宽的物理链路。
如图1所示，所述QSFP28光模块包括4条物理介质依赖通道(Physical Medium Dependence Lane，PMDL)，分别是PMDL0_TX至PMDL3_TX。
在以太网交换芯片中的通道是支持100G交换带宽的通道(Port)的情况下，所述通道包括4条链路，与QSFP28的通道数相等。此时，所述交换芯片内部支持100G带宽的通道的物理编码子层(Physical Coding Sublayer，PCS)支持链路交叉后的链路重组，不会出现物理链路与物理链路端口不匹配的情况；即在以太网交换芯片中仅存在一个通道，且所述通道包含的链路数与设备面板口的物理链路端口数一致的情况下，不会出现链路交叉导致物理链路与物理链路端口无法一一对应的情况。
图2示出了以太网交换芯片和QSFP光模块在PCB上链路连接示意图二。
在一些可选实施例中，所述QSFP的型号为QSFP28，包括4根支持25G交换带宽的物理链路。
在以太网交换芯片中的通道是2个支持50G交换带宽的通道Port0和Port1的情况下，所述Port0和Port1均包含2个链路。所述Port0的两个链路连接的的是在设备面板口的PMDL0_TX物理链路端口和PMDL1_TX物理链路端口；所述Port1的两个链路连接的是在设备面板口的PMDL2_TX物理链路端口和PMDL3_TX物理链路端口。如果PCB链路存在交叉，就需要保证Port0的两个链路仍然连接设备面板口的PMDL0_TX物理链路端口和PMDL1_TX物理链路端口，以及Port1的两个链路仍然连接设备面板 口的PMDL2_TX物理链路端口和PMDL3_TX物理链路端口。
图3示出了以太网交换芯片和以太网接口芯片在背板上链路连接示意图。
如图3所示，以太网交换芯片中的通道是2个支持100G交换带宽的通道Port0和Port1，每个通道均包含4个链路。如果以太网交换芯片的8条链路和以太网接口芯片的8条链路不是一一对应连接，而是存在交叉连接的情况，为了避免交叉连接，需要在以太网交换芯片内增加额外的反交叉逻辑。
图4示出了现有技术中实现PCB链路反交叉的芯片连接结构示意图。
如图4所示，以太网交换芯片中的通道是2个支持50G交换带宽的通道Port0和Port1，每个通道均包含2个链路。
PCB上链路交叉信息为：以太网交换芯片的物理介质附着通道(Physical Medium Attachment Lane，PMAL)0连接QSFP28光模块的PMDL2_TX物理链路端口，PMAL1_TX连接QSFP28光模块的PMDL0_TX物理链路端口，PMAL2_TX连接QSFP28光模块的PMDL1_TX物理链路端口，PMAL3_TX连接QSFP28光模块的PMDL3_TX物理链路端口。为了使以太网交换芯片和QSFP28光模块连接时支持PCB上的链路交叉，保证以太网交换芯片内部每个50G带宽的两条链路分别与PMDL0_TX物理链路端口、PMDL1_TX物理链路端口、PMDL2_TX物理链路端口、PMDL3_TX物理链路端口连接，需要在以太网交换芯片内部，在变速箱(Gearbox)和PMAL之间，根据PCB上链路交叉的情况，在发送方向PMAL时钟域，增加数据的选择逻辑。所述数据的选择逻辑，不仅对数据进行选择，每个Gearbox使用的时钟也要选择与其相连接的PMAL链路的时钟，从而实现一个反交叉的过程。
但是，随着物理链路数量的增加，为实现反交叉链路，所述数据的选 择逻辑也更复杂；随之而来的，数据选择逻辑需要作出更多的数据选择，代价大大提升；同时，数据选择逻辑也会引入更多的时钟，增加以太网交换芯片后端实时时钟树分析的复杂度。
针对目前实现链路反交叉的方法中存在的问题，本申请提出一种数据处理方法,能够解决现有技术方案中无法解决的技术难题和缺点。
图5示出了本申请提供的一种数据处理方法的发送端可选流程示意图，将根据各个步骤进行说明。
步骤S101，接收包含至少一个第二数据的第一数据。
在一些实施例中，芯片接收包含至少一个第二数据的第一数据。所述第二数据为芯片内部通道包含的链路发送的数据，所述第一数据为所有第二数据的集合。
在另一些实施例中，所述芯片的每条第一数据传输通道均接收包含至少一个第二数据的第一数据，所述第一数据传输通道为芯片中用于传输数据的通道，所述第一数据传输通道对应至少一条数据传输链路，所述数据传输链路的数量为传输所述第一数据的所有芯片内部通道包含的总链路数。
在一些实施例中，芯片包含的第一数据传输通道对应的数据传输链路的数量均相等。
例如，芯片中有2个第一数据传输通道，第一个第一数据传输通道对应2个数据传输链路，则第二个第一数据传输通道也对应2个数据传输链路。
在一些实施例中，所述第一数据为芯片所有通道发送的总数据。所述第一数据通过广播的方式发送到所述芯片的所有第一数据传输通道上。
在一些实施例中，所述第一数据还包括：发送所述第一数据中每个数据的通道对应的通道信息；所述通道信息可以为通道标识。所述第二数据 携带发送所述第二数据的通道的通道标识。
在另一些实施例中，所述第一数据还包括：发送所述第一数据中每个数据的链路对应的链路信息；所述链路信息可以为链路标识。所述第二数据携带发送所述第二数据的链路的链路标识。
以图2为例，芯片内有2个50G PCS通道，每个50G PCS通道均发送M/2个数据，所述第一数据为2个50G PCS通道发出的总的M个数据，以及发送所述数据的通道的通道标识，和/或发送所述数据的链路的链路标识。所述芯片的第一数据传输通道数目为4条，且每条第一数据传输通道均接收M个数据，以及所述M个数据中每个数据对应的发送所述数据的通道标识和/或链路标识。
在一些可选实施例中，所述第一数据还可以为系统侧所有通道发送的数据，经过时分复用(Time Division Multiplexing，TDM)编码后的总数据。以图2为例，芯片内包含2个50G PCS通道，每个50G PCS通道均发送M/2个数据，，进一步每个50G PCS通道对应的2个链路均发送M/4个数据，对每条链路发送的M/4个数据进行TDM编码，形成第一数据。所述第二数据指每条链路发送的M/4个数据。
步骤S102，将所述至少一个第二数据传输至至少一个第一数据传输通道。
在一些实施例中，所述芯片将所述至少一个第二数据传输至至少一个第一数据传输通道包括步骤S201至步骤S202。图6示出了本申请实施例中所述芯片将所述至少一个第二数据传输至至少一个第一数据传输通道的可选流程示意图，将根据各个步骤进行说明。
步骤S201，根据印刷链路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
在一些实施例中，所述印刷电路板的链路交叉信息包括：数据传输 链路与物理链路端口的对应关系。如图4所示，所述印刷电路板的链路交叉信息为：以太网交换芯片的PMAL0_TX连接QSFP28光模块的PMDL2_TX物理链路端口，PMAL1_TX连接QSFP28光模块的PMDL0_TX物理链路端口，PMAL2_TX连接QSFP28光模块的PMDL1_TX物理链路端口，PMAL3_TX连接QSFP28光模块的PMDL3_TX物理链路端口。
在一些实施例中，所述芯片根据所述印刷链路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识，包括：所述芯片根据所述链路交叉信息，为每条第一数据传输通道配置对应的通道标识。
在一些实施例中，所述第一数据传输通道对应至少一条数据传输链路，且芯片包含的第一数据传输通道对应的数据传输链路数量均相等。
例如，芯片包含两个第一数据传输通道，第一个数据传输通道对应2个数据传输链路，则第二个数据传输通道也对应2个数据传输链路。
例如，为了使图4所示的以太网交换芯片的物理链路与QSFP28的物理链路端口一一对应，确保PCSL0_TX的数据发送到PMDL0_TX物理链路端口、PCSL1_TX的数据发送到PMDL1_TX物理链路端口、PCSL2_TX的数据发送到PMDL2_TX物理链路端口、PCSL3_TX的数据发送到PMDL3_TX物理链路端口。需要保证芯片的PCSL0_TX的数据发送到PMAL1_TX、芯片的PCSL1_TX的数据发送到PMAL2_TX、芯片的PCSL2_TX的数据发送到PMAL0_TX、芯片的PCSL3_TX的数据发送到PMAL3_TX。
也就是说，PMAL1_TX与PMAL2_TX接收通道标识为0的50G PSC通道发出的数据；PMAL0_TX与PMAL3_TX接收通道标识为1的50G PSC通道发出的数据。根据所述印刷电路板的链路交叉信息，配置芯片中的第一条第一数据传输通道至第四条第一数据传输通道的通道标识依次为1、0、0、1。
在另一些实施例中，所述芯片根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识包括：在所述印刷电路板的链路交叉信息为第m个数据传输通道对应第n个物理链路端口的情况下，配置所述第m个数据传输通道的通道标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输通道的数据能够传输至第n个物理链路端口；其中，所述m、n均为正整数。
如图4所示，芯片内部通道50G_0 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox0 TX和Gearbox1 TX发送数据；通道50G_1 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox2 TX和Gearbox3 TX发送数据，所述通道50G_0 PCS TX的通道标识为0，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为0，链路标识为0；通道50G_0 PCS TX的PCSL1链路发出的第二数据，携带的通道标识为0，链路标识为1。所述通道50G_1 PCS TX的通道标识为1，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_1 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为1，链路标识为0；通道50G_1 PCS TX的PCSL1链路发出的第二数据，携带的通道标识为1，链路标识为1。
在不存在芯片的印刷电路板链路交叉的情况下，所述通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带通道标识0，链路标识0，发送至芯片内部的Gearbox0 TX，再通过Gearbox0 TX发送至PMAL0 TX，再通过PMAL0 TX发送至QSFP28的第一个物理链路端口PMDL0 TX。
在芯片的印刷电路板存在如图4所示的链路交叉的情况下，所述PMAL0的数据将通过所述印刷电路板发送至QSFP28的第三个物理链路端口，即PMDL2 TX。
所述芯片根据印刷电路板的链路交叉信息配置所述至少一个数据传输 链路的链路标识包括：在所述芯片的印刷电路板不存在链路交叉的情况下，所述QSFP28的第三个物理链路端口PMDL2 TX接收PMAL2的数据，即通道标识为1链路标识为0的数据，为了实现链路反交叉，为所述PMAL0对应的物理链路设置通道标识1，链路标识0，保证所述QSFP28的第三个物理链路端口PMDL2 TX接收通道标识为1链路标识为0的数据。
步骤S202、将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
在一些实施例中，所述芯片将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道包括：在第二数据对应的通道标识与所述第一数据传输通道的通道标识匹配的情况下，所述芯片将所述第二数据传输至所述第一数据传输通道。
在一些实施例中，所述第二数据对应的通道标识与所述第一数据传输通道的通道标识匹配，是指第二数据对应的通道标识与所述第一数据传输通道的通道标识相等。
例如，第二数据对应的通道标识为1，第一数据传输通道的通道标识也为1，认为第二数据对应的通道标识与所述第一数据传输通道的通道标识匹配，芯片将通道标识为1的第二数据传输至通道标识为1的第一数据传输通道；如果第二数据对应的通道标识为1，第一数据传输通道的通道标识为0，认为第二数据对应的通道标识与所述第一数据传输通道的通道标识不匹配，芯片不会将通道标识为1的第二数据传输至通道标识为0的第一数据传输通道。
在另一实施例中，所述芯片根据所述第二数据对应的通道标识，将所述第二数据传输至于所述第二数据的通道标识匹配的第一数据传输通道。
例如，根据图4所示的印刷电路板的链路交叉信息，配置芯片中的第一条第一数据传输通道至第四条第一数据传输通道的通道标识依次为1、0、 0、1。芯片将接收的第一数据中，通道标识为0的第二数据，传输至第二个第一数据传输通道和第三个第一数据传输通道中；芯片将接收的第一数据中，通道标识为1的第二数据，传输至第一个第一数据传输通道和第四个第一数据传输通道中。
在一些实施例中，交换芯片的发送端只有一条第一数据传输通道，所述芯片将第一数据全部传输至所述第一数据传输通道。
步骤S103，根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
在一些实施例中，所述芯片根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路包括步骤S301至步骤S302。图7示出了本申请实施例中所述芯片将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路的可选流程示意图，将根据各个步骤进行说明。
步骤S301，根据印刷链路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
在一些实施例中，所述芯片根据印刷链路板的链路交叉信息配置所述至少一个数据传输链路的链路标识，包括：所述芯片根据所述链路交叉信息，为每条数据传输链路配置对应的链路标识。
在一些实施例中，所述印刷电路板的链路交叉信息包括：所述数据传输链路与物理链路端口的对应关系。如图4所示，所述印刷电路板的链路交叉信息为：以太网交换芯片的PMAL0_TX连接QSFP28光模块的PMDL2_TX物理链路端口，PMAL1_TX连接QSFP28光模块的PMDL0_TX物理链路端口，PMAL2_TX连接QSFP28光模块的PMDL1_TX物理链路端口，PMAL3_TX连接QSFP28光模块的PMDL3_TX物理链路端口。
例如，为了使图4所示对的芯片的链路与设备面板的端口一一对应， 确保PCSL0_TX的数据发送到PMDL0_TX物理链路端口、PCSL1_TX的数据发送到PMDL1_TX物理链路端口、PCSL2_TX的数据发送到PMDL2_TX物理链路端口、PCSL3_TX的数据发送到PMDL3_TX物理链路端口。需要保证芯片的PCSL0_TX的数据发送到PMAL1_TX、芯片的PCSL1_TX的数据发送到PMAL2_TX、芯片的PCSL2_TX的数据发送到PMAL0_TX、芯片的PCSL3_TX的数据发送到PMAL3_TX。
也就是说，PMAL0_TX接收通道标识为1，链路标识为0的数据传输链路发出的数据；PMAL1_TX接收通道标识为0，链路标识为0的数据传输链路发出的数据；PMAL2_TX接收通道标识为0，链路标识为1的数据传输链路发出的数据；PMAL0_TX接收通道标识为1，链路标识为1的数据传输链路发出的数据；根据所述印刷电路板的链路交叉信息，配置芯片中的第一条数据传输链路至第四条数据传输链路的链路标识依次为0、0、1、1。
在另一些实施例中，所述芯片根据印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识包括：在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个链路端口；其中，所述m、n均为正整数。
如图4所示，芯片内部通道50G_0 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox0 TX和Gearbox1 TX发送数据；通道50G_1 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox2 TX和Gearbox3 TX发送数据，所述通道50G_0 PCS TX的通道标识为0，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为0，链路标识为0；通道50G_0 PCS  TX的PCSL1链路发出的第二数据，携带的通道标识为0，链路标识为1。所述通道50G_1 PCS TX的通道标识为1，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_1 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为1，链路标识为0；通道50G_1 PCS TX的PCSL1链路发出的第二数据，携带的通道标识为1，链路标识为1。
在不存在芯片的印刷电路板链路交叉的情况下，所述通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带通道标识0，链路标识0，发送至芯片内部的Gearbox0 TX，再通过Gearbox0 TX发送至PMAL0 TX，再通过PMAL0 TX发送至QSFP28的第一个物理链路端口PMDL0 TX。
在芯片的印刷电路板存在如图4所示的链路交叉的情况下，所述PMAL0的数据将通过所述印刷电路板发送至QSFP28的第三个物理链路端口，即PMDL2 TX。
所述芯片根据印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识包括：在所述芯片的印刷电路板不存在链路交叉的情况下，所述QSFP28的第三个物理链路端口PMDL2 TX接收PMAL2的数据，即通道标识为1链路标识为0的数据，为了实现链路反交叉，为所述PMAL0对应的物理链路设置通道标识1，链路标识0，保证所述QSFP28的第三个物理链路端口PMDL2 TX接收通道标识为1链路标识为0的数据。
步骤S302，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
在一些实施例中，所述芯片将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路包括：芯片将第一数据传输通道的数据，发送至与所述数据的链路标识相同的数据传输链路中。
在另一些实施例中，所述芯片根据所述第二数据对应的链路标识，将所述第二数据发送至与所述第二数据的链路标识匹配的第一数据传输通 道。所述第二数据包含至少一个第四数据，所述第四数据的通道标识相同，链路标识不同。所述芯片根据所述第四数据的链路标识，将所述第四数据发送至所述第四数据的链路标识匹配的数据传输链路。
例如，第一数据传输通道对应2个数据传输链路，所述第一数据传输通道接收的N个数据中，第1个至第N/2个数据是链路标识为0的数据；第N/2+1个至第N个数据是链路标识为1的数据，所述芯片根据所述N个数据的链路标识，将第1个至第N/2个数据发送至链路标识为0的数据传输链路，将第N/2+1个至第N个数据发送至链路标识为1的数据传输链路。
或者，第一数据传输通道对应2个数据传输链路，所述第一数据传输通道接收的N个数据中，序号为奇数的数据是链路标识为0的数据；序号为偶数的数据是链路标识为1的数据，所述芯片根据所述N个数据的链路标识，将序号为奇数的数据发送至链路标识为0的数据传输链路，将序号为偶数的数据发送至链路标识为1的数据传输链路。
如此，根据上述实施例所述的发送端数据处理方法，芯片可以根据印刷电路板的链路交叉信息配置第一数据传输通道的通道标识，和/或，芯片根据印刷电路板的链路交叉信息配置数据传输链路的链路标识。在芯片存在多条第一数据传输通道，每条第一数据传输通道对应多条数据传输链路的情况下，所述芯片根据通道标识和链路标识发送数据，使得在发送数据时实现反印刷电路板链路交叉的效果。本申请实施例未使用逻辑链路，进而不会引入多余时钟，进一步不会增加芯片后端时钟树选择的负担。同时，随着发送通道以及发送链路增加，本申请实施例可以根据实际情况配置芯片内部第一数据传输通道的通道标识和/或芯片内部数据传输链路的链路标识，实现多条通道以及多条链路场景的反印刷电路板链路交叉，扩展性强。
图8示出了本申请提供的一种数据处理方法的发送端可选流程示意图，将根据各个步骤进行说明。
步骤S401，基于至少一个端口接收至少一个第三数据。
在一些实施例中，所述芯片基于至少一个端口至少一个第三数据；进一步，芯片的每条数据传输通道均接收一个第三数据。
在一些实施例中，所述第三数据携带发送所述第三数据的通道的通道标识，和/或，所述第三数据携带发送端发送所述第三数据的链路的链路标识。所述第三数据为芯片的数据传输链路发出的数据。
步骤S402，根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
在一些实施例中，所述芯片根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路包括步骤S501至步骤S502。图9示出了本申请实施例中芯片根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路的可选流程示意图，包括步骤S501至步骤S502，将根据各个步骤进行说明。
步骤S501，根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识。
在一些实施例中，所述第三数据携带传输所述第三数据的通道标识和链路标识。所述根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识包括：配置所述第二数据传输通道的通道标识为所述第二数据传输通道接收的第三数据的通道标识。
例如，为了使图4所示对的芯片的链路与设备面板的端口一一对应，确保PMDL0_RX物理链路端口的数据发送到PCSL0_RX、PMDL1_RX物理链路端口的数据发送到PCSL1_RX、PMDL2_RX物理链路端口的数据发送到PCSL2_RX、PMDL3_RX物理链路端口的数据发送到PCSL3_RX。需要保证设备面板的PMAL1_RX的数据发送到芯片的PCSL0_RX、设备面板 的PMAL2_RX的数据发送到芯片的PCSL1_RX、设备面板的PMAL0_RX的数据发送到芯片的PCSL2_RX、设备面板的PMAL3_RX的数据发送到芯片的PCSL3_RX。
也就是说，PMAL1_RX与PMAL2_RX接收通道标识为0的数据；PMAL0_RX与PMAL3_RX接收通道标识为1的数据。
根据所述接收数据的通道标准，配置芯片中的第一条第二数据传输通道至第四条第二数据传输通道的通道标识依次为1、0、0、1。
步骤S502，根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述请求信息为数据重组链路发出的，用于请求与所述请求信息的通道标识匹配的第三数据。
在一些实施例中，所述芯片接收请求信息，根据请求信息的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述通道标识匹配是指：请求信息的通道标识与第二数据传输通道的通道标识相等。
例如，所述芯片接收的请求信息的通道标识为0，芯片包含的第一条至第四条第二数据传输通道的通道标识依次为1、0、0、1；根据所述请求信息的通道标识，芯片将通道标识为0的第二传输通道的数据发送至发出所述请求信息的数据重组链路；对于通道标识为1的第二传输通道的数据，芯片暂时不做任何处理，在芯片接收的请求信息的通道标识为1的情况下，芯片根据所述请求信息的通道标识，将通道标识为1的第二传输通道的数据发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述数据重组链路用于重组通道标识一致的第三数 据。
例如，如图4所示的PCB链路交叉情况，数据重组链路向芯片发送请求信息，所述请求信息的通道标识为0，所述芯片将接收的通道标识为0的数据发送至所述数据重组链路；即所述芯片将第二条第二数据传输通道和第三条第二数据传输通道中的数据发送至所述数据重组链路。在所述第三数据为M/4个数据的情况下，所述数据重组链路接收M/2个通道标识为0的数据，并对所述M/2个通道标识为0的数据进行重组。
在一些实施例中，所述数据重组链路根据数据的链路标识重组所述第三数据。
在另一些实施例中，数据重组链路接收M/2个通道标识为0的数据后，将所述M/2个数据，按照链路顺序排序，并重组出M/2个数据。
例如，所述数据重组链路接收M/2个通道标识为0的数据，所述M/2个数据包括链路标识为0的M/4个数据和链路标识为1的M/4个数据，将所述M/2个数据按照链路标识排序，重组出M/2个数据。
在一些实施例中，所述方法还包括：对数据重组链路重组出去的数据，按照通道标识，进行TDM解码。
在一些实施例中，所述方法还包括：在芯片的相同通道标识对应的第二数据传输通道数目大于当前接收的所述第三数据携带的链路标识的最大值的情况下，所述芯片根据请求信息的通道标识，将第三数据中所有通道标识匹配的数据发送至数据重组链路。所述芯片再次接收所述通道标识的请求信息的情况下，所述芯片将第三数据中所有通道标识匹配的数据中，链路号大于上一次所述第三数据携带的链路标识最大值的数据，发送至所述数据重组链路。
例如，芯片中，通道标识为0的第二数据传输通道数目为Y，所述芯片当前接收的第三数据携带的通道标识为0的数据中，链路标识的最大值 为X，且所述Y>X。所述数据重组链路向芯片发送请求信息，请求通道标识为0的数据，芯片将所述X个数据发送至所述数据重组链路。当数据重组链路再一次向芯片发送请求信息，请求通道标识为0的数据，芯片将链路标识大于X的数据发送至数据重组链路；直到数据重组链路接收到链路标识为Y的数据。
如此，在芯片接收数据的链路标识小于芯片相应第二数据传输通道数目的情况下，芯片仍然可以根据多次请求信息向数据重组链路发送相应通道标识的全部数据，使数据重组链路能够对所述数据进行重组。
如此，根据上述实施例所述的接收端数据处理方法，所述芯片可以根据所述印刷电路板的链路交叉信息配置第二数据传输通道的通道标识。所述芯片通过根据通道标识接收数据，实现反印刷电路板链路交叉的效果。本申请实施例未使用逻辑链路，进而不会引入多余时钟，进一步不会增加芯片后端时钟树选择的负担。同时，随着发送通道以及发送链路增加，本申请实施例可以根据实际情况配置芯片内部第二数据传输通道的通道标识，实现多条通道以及多条链路场景的反印刷电路板链路交叉，扩展性强。
图10示出了本申请提供的一种数据处理方法的可选流程示意图，将根据各个步骤进行说明。
步骤S601，接收包含至少一个第二数据的第一数据。
在一些实施例中，芯片接收包含至少一个第二数据的第一数据。所述第二数据为芯片内部通道包含的链路发送的数据，所述第一数据为所有第二数据的集合。
在另一些实施例中，所述芯片的每条第一数据传输通道均接收包含至少一个第二数据的第一数据，所述第一数据传输通道为芯片中用于传输数据的通道，所述第一数据传输通道对应至少一条数据传输链路，所述数据传输链路的数量为传输所述第一数据的所有芯片内部通道包含的总链路 数。
在一些实施例中，芯片包含的第一数据传输通道对应的数据传输链路的数量均相等。
例如，芯片中有2个第一数据传输通道，第一个第一数据传输通道对应2个数据传输链路，则第二个第一数据传输通道也对应2个数据传输链路。
在一些实施例中，所述第一数据为芯片所有通道发送的总数据。所述第一数据通过广播的方式发送到所述芯片的所有第一数据传输通道上。
在一些实施例中，所述第一数据还包括：发送所述第一数据中每个数据的通道对应的通道信息；所述通道信息可以为通道标识。所述第二数据携带发送所述第二数据的通道的通道标识。
在另一些实施例中，所述第一数据还包括：发送所述第一数据中每个数据的链路对应的链路信息；所述链路信息可以为链路标识。所述第二数据携带发送所述第二数据的链路的链路标识。
步骤S602，根据印刷链路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
在一些实施例中，所述印刷电路板的链路交叉信息包括：数据传输链路与物理链路端口的对应关系。
在一些实施例中，所述芯片根据所述印刷链路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识，包括：所述芯片根据所述链路交叉信息，为每条第一数据传输通道配置对应的通道标识。
在一些实施例中，所述第一数据传输通道对应至少一条数据传输链路，且芯片中，每条第一数据传输通道对应的数据传输链路相等。
在另一些实施例中，所述芯片根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识包括：在第m个数据传 输链路对应第n个物理链路端口的情况下，将所述第m个数据传输链路的链路标识配置为第n个数据传输链路的链路标识；其中，所述m、n均为正整数。
如图4所示，发送端第一条第一数据传输通道对应的物理链路端口为PMDL2_TX，在不存在PCB链路交叉的情况下，所述PMDL2_TX物理链路端口对应的第一数据传输通道的通道标识为1，因此，配置所述第一条第一数据传输通道的通道标识为1。
在一些实施例中，所述PCB链路交叉包括：芯片的数据传输链路与芯片以外的其他模块的物理链路端口不一一对应。如图4所示，以太网交换芯片的PMAL0_TX连接QSFP28光模块的PMDL2_TX物理链路端口，PMAL1_TX连接QSFP28光模块的PMDL0_TX物理链路端口，PMAL2_TX连接QSFP28光模块的PMDL1_TX物理链路端口，PMAL3_TX连接QSFP28光模块的PMDL3_TX物理链路端口，以太网交换芯片的数据传输链路与QSFP光模块的炉里链路端口不一一对应，认为存在PCB链路交叉。
步骤S603、将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
在一些实施例中，所述芯片将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道包括：在第二数据对应的通道标识与所述第一数据传输通道的通道标识匹配的情况下，所述芯片将所述第二数据传输至所述第一数据传输通道。
在另一实施例中，所述芯片根据所述第二数据对应的通道标识，将所述第二数据传输至于所述第二数据的通道标识匹配的第一数据传输通道。
例如，根据图4所示的印刷电路板的链路交叉信息，配置芯片中的第一条第一数据传输通道至第四条第一数据传输通道的通道标识依次为1、0、0、1。芯片将接收的第一数据中，通道标识为0的第二数据，传输至第二 个第一数据传输通道和第三个第一数据传输通道中；芯片将接收的第一数据中，通道标识为1的第二数据，传输至第一个第一数据传输通道和第四个第一数据传输通道中。
在一些实施例中，交换芯片的发送端只有一条第一数据传输通道，所述芯片将第一数据全部传输至所述第一数据传输通道。
步骤S604，根据印刷链路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
在一些实施例中，所述芯片根据印刷链路板的链路交叉信息配置所述至少一个数据传输链路的链路标识，包括：所述芯片根据所述链路交叉信息，为每条数据传输链路配置对应的链路标识。
在一些实施例中，所述印刷电路板的链路交叉信息包括：数据传输链路与物理链路端口的对应关系。
在另一些实施例中，所述芯片根据印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识包括：在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个链路端口；其中，所述m、n均为正整数。
如图4所示，芯片内部通道50G_0 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox0 TX和Gearbox1 TX发送数据；通道50G_1 PCS TX通过PCSL0链路和PCSL1链路分别向Gearbox2 TX和Gearbox3 TX发送数据，所述通道50G_0 PCS TX的通道标识为0，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为0，链路标识为0；通道50G_0 PCS TX的PCSL1链路发出的第二数据，携带的通道标识为0，链路标识为1。 所述通道50G_1 PCS TX的通道标识为1，对应的PCSL0链路的链路标识为0，对应的PCSL1链路的链路标识为1；即通道50G_1 PCS TX的PCSL0链路发出的第二数据，携带的通道标识为1，链路标识为0；通道50G_1 PCS TX的PCSL1链路发出的第二数据，携带的通道标识为1，链路标识为1。
在不存在芯片的印刷电路板链路交叉的情况下，所述通道50G_0 PCS TX的PCSL0链路发出的第二数据，携带通道标识0，链路标识0，发送至芯片内部的Gearbox0 TX，再通过Gearbox0 TX发送至PMAL0 TX，再通过PMAL0 TX发送至QSFP28的第一个物理链路端口PMDL0 TX。
在芯片的印刷电路板存在如图4所示的链路交叉的情况下，所述PMAL0的数据将通过所述印刷电路板发送至QSFP28的第三个物理链路端口，即PMDL2 TX。
所述芯片根据印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识包括：在所述芯片的印刷电路板不存在链路交叉的情况下，所述QSFP28的第三个物理链路端口PMDL2 TX接收PMAL2的数据，即通道标识为1链路标识为0的数据，为了实现链路反交叉，为所述PMAL0对应的物理链路设置通道标识1，链路标识0，保证所述QSFP28的第三个物理链路端口PMDL2 TX接收通道标识为1链路标识为0的数据。
步骤S605，将所述至少一个第二数据传输至至少一个第一数据传输通道。
在一些实施例中，所述芯片将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道包括：在第二数据对应的通道标识与所述第一数据传输通道的通道标识匹配的情况下，所述芯片将所述第二数据传输至所述第一数据传输通道。
在另一实施例中，所述芯片根据所述第二数据对应的通道标识，将所 述第二数据传输至于所述第二数据的通道标识匹配的第一数据传输通道。
在一些实施例中，交换芯片内只有一条第一数据传输通道，所述芯片将第一数据全部传输至所述第一数据传输通道。
步骤S606，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
在一些实施例中，所述芯片将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路包括：芯片将第一数据传输通道的数据，发送至与所述数据的链路标识相同的数据传输链路中。
在另一些实施例中，所述芯片根据所述第二数据对应的链路标识，将所述第二数据发送至与所述第二数据的链路标识匹配的第一数据传输通道。所述第二数据包含至少一个第四数据，所述第四数据的通道标识相同，链路标识不同。所述芯片根据所述第四数据的链路标识，将所述第四数据发送至所述第四数据的链路标识匹配的数据传输链路。
步骤S607，基于至少一个端口接收至少一个第三数据。
在一些实施例中，所述芯片基于至少一个端口接收至少一个第三数据；进一步，芯片的每条数据传输通道均接收一个第三数据。
在一些实施例中，所述第三数据携带发送所述第三数据的通道的通道标识，和/或，所述第三数据携带发送端发送所述第三数据的链路的链路标识。所述第三数据为芯片的数据传输链路发出的数据。
步骤S608，根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识。
在一些实施例中，所述第三数据携带传输所述第三数据的通道标识和链路标识。所述根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识包括：配置所述第二数据传输通道的通道标识为所述第二数据传输通道接收的第三数据的 通道标识。
例如，为了使图4所示对的芯片的链路与设备面板的端口一一对应，确保PMDL0_RX物理链路端口的数据发送到PCSL0_RX、PMDL1_RX物理链路端口的数据发送到PCSL1_RX、PMDL2_RX物理链路端口的数据发送到PCSL2_RX、PMDL3_RX物理链路端口的数据发送到PCSL3_RX。需要保证设备面板的PMAL1_RX的数据发送到芯片的PCSL0_RX、设备面板的PMAL2_RX的数据发送到芯片的PCSL1_RX、设备面板的PMAL0_RX的数据发送到芯片的PCSL2_RX、设备面板的PMAL3_RX的数据发送到芯片的PCSL3_RX。
也就是说，PMAL1_RX与PMAL2_RX接收通道标识为0的数据；PMAL0_RX与PMAL3_RX接收通道标识为1的数据。
根据所述接收数据的通道标准，配置芯片中的第一条第二数据传输通道至第四条第二数据传输通道的通道标识依次为1、0、0、1。
步骤S609，根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述请求信息为数据重组链路发出的，用于请求与所述请求信息的通道标识匹配的第三数据。
在一些实施例中，所述芯片接收请求信息，根据请求信息的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述通道标识匹配是指：请求信息的通道标识与第二数据传输通道的通道标识相等。
例如，所述芯片接收的请求信息的通道标识为0，芯片包含的第一条至第四条第二数据传输通道的通道标识依次为1、0、0、1；根据所述请求信 息的通道标识，芯片将通道标识为0的第二传输通道的数据发送至发出所述请求信息的数据重组链路；对于通道标识为1的第二传输通道的数据，芯片暂时不做任何处理，在芯片接收的请求信息的通道标识为1的情况下，芯片根据所述请求信息的通道标识，将通道标识为1的第二传输通道的数据发送至发出所述请求信息的数据重组链路。
在一些实施例中，所述数据重组链路用于重组通道标识一致的第三数据。
例如，如图4所示的PCB链路交叉情况，数据重组链路向芯片发送请求信息，所述请求信息的通道标识为0，所述芯片将接收的通道标识为0的数据发送至所述数据重组链路；即所述芯片将第二条第二数据传输通道和第三条第二数据传输通道中的数据发送至所述数据重组链路。在所述第三数据为M/4个数据的情况下，所述数据重组链路接收M/2个通道标识为0的数据，并对所述M/2个通道标识为0的数据进行重组。
在一些实施例中，所述数据重组链路根据数据的链路标识重组所述第三数据。
在另一些实施例中，数据重组链路接收M/2个通道标识为0的数据后，将所述M/2个数据，按照链路顺序排序，并重组出M/2个数据。
例如，所述数据重组链路接收M/2个通道标识为0的数据，所述M/2个数据包括链路标识为0的M/4个数据和链路标识为1的M/4个数据，将所述M/2个数据按照链路标识排序，重组出M/2个数据。
在一些实施例中，所述方法还包括：对数据重组链路重组出去的数据，按照通道标识，进行TDM解码。
在一些实施例中，所述方法还包括：在芯片的相同通道标识对应的第二数据传输通道数目大于当前接收的所述第三数据携带的链路标识的最大值的情况下，所述芯片根据请求信息的通道标识，将第三数据中所有通道 标识匹配的数据发送至数据重组链路。所述芯片再次接收所述通道标识的请求信息的情况下，所述芯片将第三数据中所有通道标识匹配的数据中，链路号大于上一次所述第三数据携带的链路标识最大值的数据，发送至所述数据重组链路。
如此，根据上述实施例所述的数据处理方法，芯片可以根据印刷电路板的链路交叉信息配置第一数据传输通道和第二数据传输通道的通道标识，和/或，芯片可以根据印刷电路板的链路交叉信息配置数据传输链路的链路标识。在芯片存在多条第一数据传输通道，且每条第一数据传输通道对应多条数据传输链路的情况下，芯片通过根据通道标识和链路标识发送数据，使得在发送数据时实现反印刷电路板链路交叉的效果。芯片通过根据通道标识接收数据，使得在接收数据时实现反印刷电路板链路交叉的效果。本申请实施例未使用逻辑链路，进而不会引入多余时钟，进一步不会增加芯片后端时钟树选择的负担。同时，随着接收数据的通道标识以及链路标识数目的增加，本申请实施例可以根据实际情况配置第一数据传输通道的通道标识以及第二数据传输通道的通道标识，和/或芯片内部数据传输链路的链路标识，实现多条通道以及多条链路场景的反印刷电路板链路交叉，扩展性强。
图11示出了本申请提供的一种数据处理装置的发送端可选结构示意图一，将根据各个单元进行说明。
芯片700，配置为根据印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识；和/或，根据印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
在一些实施例中，所述芯片700根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识包括：在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况 下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个链路端口；其中，所述m、n均为正整数。
TDM编码单元701，配置为对芯片所有通道中所有链路发出的数据进行TDM编码，并通过广播的方式发送至所述芯片700的所有数据选通单元702中。
数据选通单元702，配置为接收芯片所有通道中所有链路发出的数据进行TDM编码后得到的包含至少一个第二数据的第一数据，并将所述至少一个第二数据传输至至少一个第一数据传输通道。
在一些实施例中，所述数据选通单元702将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
数据分发单元703，配置为根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
在一些实施例中，所述数据分发单元将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
变速单元704，配置为对数据分发单元703发出的数据进行变速。
图12示出了本申请提供的一种数据处理装置的接收端可选结构示意图一，将根据各个单元进行说明。
芯片800，配置为根据第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识。
第二接收单元804，配置为基于至少一个端口分别接收至少一个第三数据。
数据缓存单元803，配置为根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
TDM调度重组单元802，配置为向数据缓存单元发送请求信息，所述 请求信息携带通道标识。
在一些实施例中，所述TDM调度重组单元802按照通道标识顺序，向数据缓存单元发送请求信息。
在一些实施例中，所述数据缓存单元803，还配置为，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的所述TDM调度重组单元802。
在一些实施例中，所述TDM调度重组单元802还配置为，根据数据的链路标识重组所述第三数据。
TDM解码单元801，配置为对经过TDM调度重组单元802重组的第三数据进行TDM解码。
图13示出了本申请提供的一种数据处理装置的发送端可选结构示意图二，将根据各个单元进行说明。
第一接收单元901，配置为接收包含至少一个第二数据的第一数据；
数据选通单元902，配置为将所述至少一个第二数据传输至至少一个第一数据传输通道；
数据分发单元903，配置为根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
配置单元904，配置为根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
所述数据选通单元902还配置为：将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
所述配置单元904还配置为：根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。包括：在第m个数据传输链路对应第n个物理链路端口的情况下，将所述第m个数据传输链路的链路标识配置为第n个数据传输链路的链路标识；其中，所述m、n均为正整数。
所述数据分发单元903，还配置为将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
图14示出了本申请提供的一种数据处理装置的接收端可选结构示意图二，将根据各个单元进行说明。
第二接收单元1001，配置为基于至少一个端口分别接收至少一个第三数据。
数据缓存单元1002，配置为根据请求信息的通道标识，将所述至少一个第三数据发送至对应数据重组链路。
配置单元1003，配置为根据所述第三数据的通道标识，配置为根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个数据缓存单元的通道标识。
所述数据缓存单元1002，还配置为将与所述请求信息的通道标识匹配的至少一个数据缓存单元的数据，发送至发出所述请求信息的数据重组链路。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序命令相关的硬件来完成，前述的程序可以存储于一存储介质中，该程序在执行时，执行在第一应用运行过程中接收到基于第二应用的通知消息时，在电子设备屏幕上的第一区域响应所述通知消息；其中，所述第一区域小于单独运行第二应用时加载的输入法应用在所述电子设备屏幕上对应的区域。而前述的存储介质包括：移动存储设备、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
或者，本发明上述集成的单元如果以软件功能模块的形式实现并作为独立的产品销售或使用时，也可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明实施例的技术方案本质上或者说对现有技术做出 贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干命令用以使得一台计算机设备(可以是个人计算机、服务器、或者网络设备等)执行本发明各个实施例所述方法的全部或部分。而前述的存储介质包括：移动存储设备、ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种数据处理方法，所述方法包括：
    接收包含至少一个第二数据的第一数据；
    将所述至少一个第二数据传输至至少一个第一数据传输通道；
    根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
  2. 根据权利要求1所述的方法，其中，所述印刷电路板的链路交叉信息包括：
    所述数据传输链路与物理链路端口的对应关系。
  3. 根据权利要求1所述的方法，其中，所述方法还包括：
    根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
  4. 根据权利要求3所述的方法，其中，所述将所述至少一个第二数据传输至至少一个第一数据传输通道包括：
    将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
  5. 根据权利要求1所述的方法，其中，所述方法还包括：
    根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
  6. 根据权利要求5所述的方法，其中，所述根据所述印刷电路板的链路交叉信息，配置所述至少一个数据传输链路的链路标识包括：
    在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能 够传输至第n个物理链路端口；
    其中，所述m、n均为正整数。
  7. 根据权利要求5所述的方法，其中，所述将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路，包括：
    将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
  8. 一种数据处理方法，所述方法包括：
    基于至少一个端口接收至少一个第三数据；
    根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
  9. 根据权利要求8所述的方法，其中，所述方法还包括：
    根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识。
  10. 根据权利要求9所述的方法，其中，所述根据第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路包括：
    根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路。
  11. 一种数据处理装置，所述装置包括：
    第一接收单元，配置为接收包含至少一个第二数据的第一数据；
    数据选通单元，配置为将所述至少一个第二数据传输至至少一个第一数据传输通道；
    数据分发单元，配置为根据印刷电路板的链路交叉信息，将所述至少一条第一数据传输通道的数据发送至对应的数据传输链路。
  12. 根据权利要求11所述的装置，其中，所述装置还包括：
    配置单元，配置为根据所述印刷电路板的链路交叉信息配置所述至少一个第一数据传输通道的通道标识。
  13. 根据权利要求12所述的装置，其中，所述数据选通单元还配置为：
    将所述第二数据传输至与所述第二数据的通道标识匹配的第一数据传输通道。
  14. 根据权利要求11所述的装置，其中，所述配置单元还配置为：
    根据所述印刷电路板的链路交叉信息配置所述至少一个数据传输链路的链路标识。
  15. 根据权利要求14所述的装置，其中，
    所述配置单元，配置为在所述印刷电路板的链路交叉信息为第m个数据传输链路对应第n个物理链路端口的情况下，配置所述第m个数据传输链路的链路标识与第n个物理链路端口的端口标识匹配，以使所述第m个数据传输链路的数据能够传输至第n个链路端口；
    其中，所述m、n均为正整数。
  16. 根据权利要求14所述的装置，其中，
    所述数据分发单元，配置为将所述第二数据发送至与所述第二数据的链路标识匹配的数据传输链路。
  17. 一种数据处理装置，所述装置包括：
    第二接收单元，配置为基于至少一个端口分别接收至少一个第三数据；
    数据缓存单元，配置为根据所述第三数据的通道标识和链路标识，将所述至少一个第三数据发送至对应的数据重组链路。
  18. 根据权利要求17所述的装置，其中，
    所述装置还包括：配置单元，配置为根据所述第三数据的通道标识，配置接收所述至少一个第三数据的至少一个第二数据传输通道的通道标识；
    所述数据缓存单元，还配置为将所述第三数据传输至与所述第三数据的通道标识匹配的第二数据传输通道。
  19. 根据权利要求18所述的装置，其中，
    所述数据缓存单元，还配置为根据数据重组链路发送的请求信息携带的通道标识，将与所述请求信息的通道标识匹配的至少一个第二数据传输通道的数据，发送至发出所述请求信息的数据重组链路；
    所述装置还包括：数据重组单元，配置为向数据缓存单元发送所述请求信息；配置为根据至少一个第三数据的链路标识，重组所述至少一个第三数据。
  20. 一种存储介质，存储有可执行程序，所述可执行程序被处理器执行时，实现权利要求1至7任一项所述的数据处理方法，或者权利要求8至10任一项所述的数据处理方法。
  21. 一种数据处理装置，包括存储器、处理器及存储在存储器上并能够由所述处理器运行的可执行程序，所述处理器运行所述可执行程序时执行如权利要求1至7任一项所述的数据处理方法的，或者权利要求8至10任一项所述数据处理的方法的步骤。
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